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FIDO5200CBCZ

FIDO5200CBCZ

  • 厂商:

    AD(亚德诺)

  • 封装:

    CSPBGA144

  • 描述:

    FIDO5200CBCZ

  • 数据手册
  • 价格&库存
FIDO5200CBCZ 数据手册
Real-Time Ethernet Multiprotocol (REM) Switch fido5100/fido5200 Data Sheet FUNCTIONAL BLOCK DIAGRAM 144-lead CSP_BGA RoHS compliant package −40°C to +105°C industrial temperature range rating 3.3 V input/output buffers IEEE 802.3, 10 Mbps/100 Mbps, half and full duplex, IPv6 and IPv4 communication 2 independent Ethernet ports: 1 MII and 1 RMII interface per port Support for all industrial protocols PROFINET Class B and Class C with fast startup (Version 2.3) EtherNet/IP with QuickConnect, CIP Sync, and CIP Motion Modbus TCP EtherCAT Ethernet POWERLINK Host interface transfer rate: 32 bits per 28 ns Supports EtherCAT cycle times down to 12.5 μs and PROFINET cycle times down to 31.25 μs PI Net Load Class III capable DLR (supervisor and node, announce and beacon based), MRPD, HSR, PRP, shared device, controller redundancy IEEE 1588 Version 2 support: ordinary clock; both peer to peer and end to end transparent clocks, raw frames, and UDP 8 independent timer signals synchronized with an internal precision timer 4 independently programmable timer signals for timer capture events or timer output events 4 timer signals create programmable periodic waveforms synchronized to the internal precision timer DCP, LLDP, DHCP, RSTP, VLAN, IGMP snooping support Forwarding table with aging and learning Drive LEDs for link activity REM SWITCH TIMER CONTROL UNIT HOST INTERFACE BUFFER MEMORY INTERRUPT CONTROL PORT 1 PORT 2 15833-001 FEATURES Figure 1. GENERAL DESCRIPTION The fido5100 and fido5200 (REM switch) are programmable IEEE 802.3 10 Mbps/100 Mbps Ethernet Internet Protocol Version 6 (IPv6) and Internet Protocol Version 4 (IPv4) switches that support virtually any Layer 2 or Layer 3 protocol. The switches are personalized to support the desired protocol by firmware that is downloaded from a host processor. The firmware is contained in the real-time Ethernet multiprotocol (REM) switch driver and is downloaded at power-up. The REM switch can be ready for network data operation in less than 4 ms to support fast startup and quick connect type network functionality. The REM switch devices have the same signal assignments as defined in this data sheet. The fido5100 supports the following protocols: PROFINET real time (RT) and isochronous real time (IRT), EtherNet/IP with and without device level ring (DLR), Modbus TCP, and POWERLINK. The fido5200 supports the following protocols: EtherCAT and all protocols defined for the fido5100. APPLICATIONS Industrial automation Process control Managed Ethernet switch The REM switch is intended for use with a host processor. Network operation is handled using the functions and services provided in the REM switch driver. The host processor can implement any protocol stack by integrating it with the REM switch driver. An example application is shown in Figure 11. The REM switches are available in a 144-ball chip scale package ball grid array (CSP_BGA) package. Note that throughout this data sheet, multifunction pins, such as A02/ALE, are referred to either by the entire pin name or by a single function of the pin, for example, ALE, when only that function is relevant. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com fido5100/fido5200 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Device Interfaces ........................................................................ 12 Functional Block Diagram .............................................................. 1 Internal Precision Timer ........................................................... 12 General Description ......................................................................... 1 Host Interface.............................................................................. 12 Revision History ............................................................................... 2 Ethernet Interface ....................................................................... 15 Specifications..................................................................................... 3 Applications Information .............................................................. 17 REM Switch Characteristics ........................................................ 3 REM Switch Hardware .............................................................. 17 Timing Specifications—Nonmultiplexed Address Data Bus.. 3 Board Layout ............................................................................... 17 Timing Specifications—Multiplexed Address Data Bus ......... 5 Design Considerations .............................................................. 17 Absolute Maximum Ratings............................................................ 7 Outline Dimensions ....................................................................... 19 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 19 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 3/2020—Rev. D to Rev. E Deleted Table 13; Renumbered Sequentially .............................. 18 1/2020—Rev. C to Rev. D Change to Features Section ............................................................. 1 8/2019—Rev. B to Rev. C Change to Features Section, General Description Section, and Figure 1 .............................................................................................. 1 Changes to Figure 6 .......................................................................... 8 Change to Crystal Section and Figure 8 ...................................... 12 Change to Figure 9 and Figure 10 ................................................ 16 Changes to Figure 11, REM Switch Hardware Section, and Power Section .................................................................................. 17 Changes to Table 13 ........................................................................ 18 1/2019—Rev. A to Rev. B Change to tAH Parameter, Table 2 ....................................................3 Changes to Ordering Guide .......................................................... 19 8/2018—Rev. 0 to Rev. A Added Core Current Parameter and I/O Current Parameter, Table 1 .................................................................................................3 Changes to tAS Parameter and tAH Parameter, Table 2 ...................3 Added Note 2 and Note 3, Table 2; Renumbered Sequentially ...3 Change to Power Dissipation Parameter, Table 4 .........................7 10/2017—Revision 0: Initial Version Rev. E | Page 2 of 19 Data Sheet fido5100/fido5200 SPECIFICATIONS REM SWITCH CHARACTERISTICS Table 1. Parameter OPERATING CONDITIONS Core Voltage Core Current Input/Output (I/O) Buffers I/O Current PLL Analog Voltage Regulator Power Supply DC Input Voltage Output Voltage Operating Junction Temperature (Industrial) DC CHARACTERISTICS (I/O STANDARD) 3.3 V LVCMOS VCC+3V3 Input Voltage Low (VIL) High (VIH) Output Voltage Low (VOL) High (VOH) Output Current Low (IOL) High (IOH) LEAKAGE CURRENT Input Pin Tristated I/O Pin HOST INTERFACE TRANSFER RATE 1 1 Min Typ Max Unit 1.08 1.2 2.97 3.3 1.08 −0.5 −0.5 −40 1.2 1.32 48 3.63 0.035 1.32 +3.8 +3.8 +125 V mA V mA V V V °C 2.97 3.3 3.63 V +0.8 3.6 V V 0.4 V V 16.1 30.7 mA mA +10 +10 μA μA Bits −0.3 2.0 2.4 8.2 9.2 13.0 19.2 −10 −10 32 Test Conditions/Comments At TA = 85°C 3.3 V power supply At TA = 85°C Voltage level applied to the VCC+3V3 signal Input voltage (VIN) = 0 V to 3.3 V maximum Output voltage (VOUT) = 0 V to 3.3 V maximum Per 28 ns Supports EtherCAT cycle times down to 12.5 μs and PROFINET cycle times down to 31.25 μs. TIMING SPECIFICATIONS—NONMULTIPLEXED ADDRESS DATA BUS Table 2. Nonmultiplexed Address Data Bus—Read and Write Cycle Timing 1, 2, 3 Parameter tAS tAH tCDV tODV tOEL tCSH Min 2 370 Typ Max 20 20 20 8 Unit ps ps ns ns ns ns Description Address setup time Address hold time CS to data valid time Output enable to data valid time Output enable low time CS high time CS low time tCSL 20 ns tEOE 0 ns CS to output enable time tCOE 0 ns tDO tDHZ tCHZ 150 tWES 0 ns Output enable high to CS high Output enable to data drive time Output disable to high-Z time CS high to high-Z time CS to write enable tWEWC tWECS 16 0 ns ns 110 110 ps ps ps tDS 30 ps Write enable to write complete Write enable high to CS high Data setup to WE high tDH 30 ps Input data hold after WE high The MBS pin determines whether the host interfaced has multiplexed or separate address and data lines. When MBS = 0, the interface is nonmultiplexed. OE can be taken low before CS. Therefore, tEOE can be a negative value. In this case, a board designer must closely monitor tDO and tCDV to avoid bus contention and ensure proper data transfer. 3 The read bus cycle terminates when either CS or OE is taken high. Therefore, a negative value for tCOE is acceptable in some circumstances. 1 2 Rev. E | Page 3 of 19 fido5100/fido5200 Data Sheet Timing Diagrams, Nonmultiplexed REM Switch tAS ADDRESS tAH ADDRESS tCDV DATA DATA OUT tDO tDHZ tEOE OE tCHZ tODV tCOE tCSH tOEL 15833-002 CS tCSL Figure 2. REM Switch Nonmultiplexed Address and Data Bus Read Timing, MBS = 0 tAS ADDRESS tAH ADDRESS tDS DATA tDH DATA IN tWEWC WE tWES CS tCSH Figure 3. REM Switch Nonmultiplexed Address and Data Bus Write Timing, MBS = 0 Rev. E | Page 4 of 19 15833-003 tWECS Data Sheet fido5100/fido5200 TIMING SPECIFICATIONS—MULTIPLEXED ADDRESS DATA BUS Table 3. Multiplexed Address Data Bus—Read and Write Cycle Timing 1 Parameter tALEH tALEL tAS tAH tCDV tALOE tODV tDHZ tCHZ tCLLL tCSH tEOE tDO tCOE tWES tWEWC tWECS tWHLH tDS tDH 1 Min 8 16 170 170 Typ Max Unit ns ns ps ps ns ns ns ps ps ns ns ns ps ns ns ns ns ns ps ps 20 2 20 150 150 0 8 2 2 0 0 16 0 0 60 60 110 Description ALE high time ALE low time Address setup time Address hold time ALE to valid data ALE to output enable Output enable to data valid Output disable to high-Z time CS high to high-Z time CS low to ALE low CS high time CS to output enable Output enable to output drive time Output disable to CS high CS to write enable Write enable to write complete Write enable high to CS high WE high to next ALE high Data setup to WE high Input data hold after WE high The MBS pin determines whether the host interfaced has multiplexed or separate address and data lines. When MBS = 1, the interface is multiplexed. Timing Diagrams, Multiplexed REM Switch tCDV tAS ADDRESS BUS tAH ADDRESS DATA OUT tALEL ALE tALEH tALOE OE tDO tDHZ tCLLL tEOE tCHZ tCSH tODV 15833-004 tCOE CS Figure 4. REM Switch Multiplexed Address and Data Bus Read Timing, MBS = 1 Rev. E | Page 5 of 19 fido5100/fido5200 Data Sheet tAS ADDRESS BUS tAH tDS ADDRESS tDH DATA IN tALEL ALE tALEH tCLLL tWECS tCSH CS tWEWC tWHLH 15833-005 tWES WE Figure 5. REM Switch Multiplexed Address and Data Bus Write Timing, MBS = 1 Rev. E | Page 6 of 19 Data Sheet fido5100/fido5200 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Power Supply Core Voltage and Periphery Circuitry I/O (VCC+3V3) PLL Analog DC Input Voltage Operating Temperature Range Junction Ambient Storage Temperature (No Bias) Range Electrostatic Discharge (ESD) Voltage, Human Body Model Lead Temperature (Soldering) Power Dissipation 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rating 1.08 V to 1.32 V 2.97 V to 3.63 V 1.08 V to 1.32 V −0.5 V to +3.8 V −40°C to +125°C −40°C to +85°C −65°C to +150°C −2000 V to +2000 V ESD CAUTION J-STD-020C1 172.6 mW Compliant with JEDEC Standard J-STD-020C and restriction of hazardous substances (RoHS), Directive 2002/95/EU. Rev. E | Page 7 of 19 fido5100/fido5200 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REM SWITCH 1 2 3 4 5 6 7 8 9 10 11 12 A D02/AD02 D04/AD04 D07 D11 D15 D18 D19 D22 D25 D27 D30 D31 B D01 D03/AD03 D06 D10 D14 D17 D20 D23 D26 D29 OE WE C A04/UNUSED D00 D05/A05 D09 D13 D16 D21 D24 D28 INT2 INT1 INT0 D A02/ALE D08 D12 VCC+1V2 GND VCC+3V3 GND TIMER7 TIMER6 CS E RESET LE SIZE_32 GND VCC+1V2 GND VCC+1V2 GND VCC+3V3 TIMER5 TIMER4 TIMER3 F GND MBS GND VCC+3V3 GND VCC+1V2 GND GND GND TIMER2 TIMER1 TIMER0 G XTAL0 XTAL1 VCC+1V2A GND VCC+1V2 GND GND VCC+1V2 GND RMII_CLK CLKOUT P2_ACTIVITY H GND VCC+3V3 GND VCC+3V3 GND VCC+1V2 GND GND VCC+3V3 P2_CRS P2_COL P2_LINK_ STATUS J P1_TXEN P1_TXCLK NC GND VCC+3V3 GND VCC+1V2 NC NC NC P2_RXDV P2_RXCLK K P1_TXD0 NC NC NC NC P1_RXDV P1_LINK_ STATUS P2_TXD1 NC P2_RXD0 NC NC L P1_TXD1 P1_TXD2 P1_RXD0 P1_RXD3 NC P1_CRS P1_ACTIVITY P2_TXD0 P2_TXD3 NC P2_RXD2 NC M P1_TXD3 NC P1_RXD1 P1_RXD2 NC P1_RXCLK P1_COL P2_TXEN P2_TXD2 P2_TXCLK P2_RXD1 P2_RXD3 A03/UNUSED A05/UNUSED VCC+1V2 VCC+3V3 VCC+1V2 Figure 6. Pin Configuration Rev. E | Page 8 of 19 GND I/O 15833-006 TOP VIEW (Not to Scale) Data Sheet fido5100/fido5200 Table 5. Pin Function Descriptions Pin No. A1 Mnemonic D02/AD02 Direction 1 I/O A2 D04/AD04 I/O A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 D07 D11 D15 D18 D19 D22 D25 D27 D30 D31 D01 D03/AD03 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 D06 D10 D14 D17 D20 D23 D26 D29 OE WE I/O I/O I/O I/O I/O I/O I/O I/O I I C1 A04/UNUSED I C2 C3 D00 D05/A05 I/O I/O C4 C5 C6 D09 D13 D16 I/O I/O I/O Description Data Bus Bit 02 Nonmultiplexed/Data Bus Bit 02 Multiplexed. This is a multifunction pin. When MBS = 0, Pin A1 (D02) is Data Bus Bit 02 to and from the REM switch for the nonmultiplexed address data bus. When MBS = 1, Pin A1 (AD02) is for the multiplexed address data bus, Bit 02 of the address (LSB), and Bit 02 of the data. Data Bus Bit 04 Nonmultiplexed/Data Bus Bit 04 Multiplexed. This is a multifunction pin. When MBS = 0, Pin A2 (D04) is Data Bus Bit 04 to and from the REM switch for the nonmultiplexed address data bus. When MBS = 1, Pin A2 (AD04) is for the multiplexed address data bus, Bit 04 of the address, Bit 04 of the data. Data Bus Bit 07. Pin A3 is Data Bus Bit 07 to and from the REM switch. Data Bus Bit 11. Pin A4 is Data Bus Bit 11 to and from the REM switch. Data Bus Bit 15. Pin A5 is Data Bus Bit 15 to and from the REM switch. Data Bus Bit 18. Pin A6 is Data Bus Bit 18 to and from the REM switch. Data Bus Bit 19. Pin A7 is Data Bus Bit 19 to and from the REM switch. Data Bus Bit 22. Pin A8 is Data Bus Bit 22 to and from the REM switch. Data Bus Bit 25. Pin A9 is Data Bus Bit 25 to and from the REM switch. Data Bus Bit 27. Pin A10 is Data Bus Bit 27 to and from the REM switch. Data Bus Bit 30. Pin A11 is Data Bus Bit 30 to and from the REM switch. Data Bus Bit 31. Pin A12 is Data Bus Bit 31 to and from the REM switch. Data Bus Bit 01. Pin B1 is Data Bus Bit 01 to and from the REM switch. Data Bus Bit 03 Nonmultiplexed/Data Bus Bit 03 Multiplexed. This is a multifunction pin. When MBS = 0, Pin B2 (D03) is Data Bus Bit 03 to and from the REM switch for the nonmultiplexed address data bus. When MBS = 1, Pin B2 (AD03) is for the multiplexed address data bus, Bit 03 of the address, Bit 03 of the data. Data Bus Bit 06. Pin B3 is Data Bus Bit 06 to and from the REM switch. Data Bus Bit 10. Pin B4 is Data Bus Bit 10 to and from the REM switch. Data Bus Bit 14. Pin B5 is Data Bus Bit 14 to and from the REM switch. Data Bus Bit 17. Pin B6 is Data Bus Bit 17 to and from the REM switch. Data Bus Bit 20. Pin B7 is Data Bus Bit 20 to and from the REM switch. Data Bus Bit 23. Pin B8 is Data Bus Bit 23 to and from the REM switch. Data Bus Bit 26. Pin B9 is Data Bus Bit 26 to and from the REM switch. Data Bus Bit 29. Pin B10 is Data Bus Bit 29 to and from the REM switch. Output Enable. Setting Pin B11 low allows the REM switch to drive data lines. Write Enable. Setting Pin B12 low enables a write; setting Pin B12 high enables a read. Address Line 04/Multiplexed Address Bus (UNUSED). This is a multifunction pin. Pin C1 is Address Line 04 when MBS = 0 for the nonmultiplexed address data bus. When MBS = 1, Pin C1 is Bit 04 of the address bus. Line A04 is sampled on the falling edge of CS (Pin D12). Pin C1 is unused when MBS = 1 for the multiplexed address data bus. Data Bus Bit 00. C2 is Data Bus Bit 00 to and from the REM switch. Data Bus Bit 05 Nonmultiplexed/Data Bus Bit 05 Multiplexed. This is a multifunction pin. When MBS = 0, Pin C3 (D05) is Data Bus Bit 05 to and from the REM switch for the nonmultiplexed address data bus. When MBS = 1, Pin C3 (A05) is for the multiplexed address data bus, Bit 05 of the address, Bit 05 of the data. Data Bus Bit 09. Pin C4 is Data Bus Bit 09 to and from the REM switch. Data Bus Bit 13. Pin C5 is Data Bus Bit 13 to and from the REM switch. Data Bus Bit 16. Pin C6 is Data Bus Bit 16 to and from the REM switch. Rev. E | Page 9 of 19 fido5100/fido5200 Data Sheet Pin No. C7 C8 C9 C10 Mnemonic D21 D24 D28 INT2 Direction 1 I/O I/O I/O O C11 INT1 O C12 INT0 O D1 A02/ALE I N/A D2 A03/UNUSED I D3 A05/UNUSED I D4 D5 D6, E5, E7, F6, G5, G8, H6, J7 D7, D9, E4, E6, E8, F1, F3, F5, F7, F8, F9, G4, G6, G7, G9, H1, H3, H5, H7, H8, J4, J6 D8, E9, F4, H2, H4, H9, J5 D10 D11 D12 D08 D12 VCC+1V2 I/O I/O N/A Description Data Bus Bit 21. Pin C7 is Data Bus Bit 21 to and from the REM switch. Data Bus Bit 24. Pin C8 is Data Bus Bit 24 to and from the REM switch. Data Bus Bit 28. Pin C9 is Data Bus Bit 28 to and from the REM switch. Interrupt 2 Output to Host Processor. Pin C10 can be configured to respond to one or more internal events. Interrupt 1 Output to Host Processor. Pin C11 can be configured to respond to one or more internal events. Interrupt 0 Output to Host Processor. Pin C12 can be configured to respond to one or more internal events. Address Line 02/Address Latch Enable. This is a multifunction pin. Pin D1 is Address Line 02 when MBS = 0 for the nonmultiplexed address data bus. When MBS = 0, Pin D1 is Bit 02 of the address bus. Line A02 is sampled on the falling edge of CS (Pin D12). The addresses are 32-bit aligned/addressable. When MBS = 1, this pin is the address latch enable pin. Address Line 03/Multiplexed Address Bus. This is a multifunction pin. Pin D2 is Address Line 03 when MBS = 0 for the nonmultiplexed address data bus. When MBS = 0, Pin D2 is Bit 03 of the address bus. Line A03 is sampled on the falling edge of CS (Pin D12). The addresses are 32-bit aligned/addressable. Pin D2 is unused when MBS = 1 for the multiplexed address data bus. Address Line 05/Multiplexed Address Bus. This is a multifunction pin. Pin D3 is Address Line 05 when MBS = 0 for the nonmultiplexed address data bus. When MBS = 0, Pin D3 is Bit 05 of the address bus. Line A05 is sampled on the falling edge of CS (Pin D12). The addresses are 32-bit aligned/addressable. Pin D3 is unused when MBS = 1 for the multiplexed address data bus. Data Bus Bit 08. Pin D4 is Data Bus Bit 08 to and from the REM switch. Data Bus Bit 12. Pin D5 is Data Bus Bit 12 to and from the REM switch. 1.2 V Power Supply. GND N/A Ground. VCC+3V3 N/A 3.3 V Power Supply. TIMER7 TIMER6 CS O O I E1 RESET I E2 LE I E3 SIZE_32 I E10 TIMER5 O E11 TIMER4 O E12 TIMER3 I/O F2 MBS I F10 TIMER2 I/O Internal Precision Timer Clock 7 Synchronized. Pin D10 is a programmable output. Internal Precision Timer Clock 6 Synchronized. Pin D11 is a programmable output. Address Bus Chip Select. The address bus is sampled on the falling edge of CS. A rising edge on CS terminates the current read or write cycle. Reset. When Pin E1 is asserted low, all internal registers initialize and bus configuration pins enable for sampling. System Endianness. When Pin E2 is set high, the data format is little endian. When Pin E2 is set low, the data format is big endian. The value is captured on the rising edge of RESET. Data Bus Size. The data bus size is 32 bits when Pin E3 is set high and 16 bits when Pin E3 is set low. The value is captured on the rising edge of RESET. Internal Precision Timer Clock 5 Synchronized. Pin E10 is a programmable output. Internal Precision Timer Clock 4 Synchronized. Pin E11 is a programmable output. Internal Precision Timer 3 Clock Synchronized. Pin E12 is a programmable output or input. Multiplex Bus Select. When Pin F2 is set high, the host interface bus operates as a multiplexed bus. The host interface operates as a nonmultiplexed bus when Pin F2 is set low. The value is captured on the rising edge of Pin E1, RESET. Internal Precision Timer Clock 2 Synchronized. Pin F10 is a programmable output or input. Rev. E | Page 10 of 19 Data Sheet fido5100/fido5200 Pin No. F11 Mnemonic TIMER1 Direction 1 I/O F12 TIMER0 I/O G1 G2 G3 G10 XTAL0 XTAL1 VCC+1V2A RMII_CLK O G11 G12 H10 CLKOUT P2_ACTIVITY P2_CRS O O I H11 P2_COL I H12 P2_LINK_STATUS I J1 J2 J3, J8, J9, J10, K2, K3, K4, K5, K9, K11, K12, L5, L10, L12, M2, M5 J11 P1_TXEN P1_TXCLK NC O I N/A P2_RXDV I J12 K1 K6 P2_RXCLK P1_TXD0 P1_RXDV I O I K7 K8 K10 L1 L2 L3 L4 L6 P1_LINK_STATUS P2_TXD1 P2_RXD0 P1_TXD1 P1_TXD2 P1_RXD0 P1_RXD3 P1_CRS I O I I O I I I L7 L8 L9 L11 M1 M3 M4 M6 M7 M8 M9 M10 M11 M12 P1_ACTIVITY P2_TXD0 P2_TXD3 P2_RXD2 P1_TXD3 P1_RXD1 P1_RXD2 P1_RXCLK P1_COL P2_TXEN P2_TXD2 P2_TXCLK P2_RXD1 P2_RXD3 O O O I O I I I I O O I I I 1 Description Internal Precision Timer Clock 1 Synchronized. Pin F11 is a programmable output or input. Internal Precision Timer Clock 0 Synchronized. Pin F12 is a programmable output or input. Clock Input. This pin has a frequency of 25 MHz. Output Pair for XTAL0. Pin G2 is required for use with a crystal clock source. Analog 1.2 V Power Supply. This pin must be isolated from VCC+1V2. 50 MHz Reduced Media Independent Interface (RMII) Transmit and Receive Clock Reference for Port 1 and Port 2. Output Clock. Pin G11 has the same frequency as XTAL0 (25 MHz). Port 2 Activity LED Output Driver. The LED turns on when G12 is asserted low. Port 2 Carrier Sense. When H10 is asserted high, a carrier has been sensed on Port 2. Port 2 Media Independent Interface (MII) Collision. Pin H11 asserting high indicates a collision on Port 2. Port 2 Link Status from Physical Layer (PHY). When H12 is asserted low, the link on Port is active. Port 1 MII Transmit Enable. Setting Pin J1 high enables transmission on Port 1. Port 1 MII Transmit Clock from PHY. No Connection. Port 2 Received Data Valid. Data from the Port 2 PHY is valid when J11 is asserted high (used as CRS/RXDV in RMII mode). Port 2 MII Receive Clock from PHY. Transmit Data Output Bit 0 for Port 1 MII and RMII. Port I MII Received Data Valid. Asserting Pin K6 high indicates that data from the Port 1 PHY is valid (used as CRS/RXDV in RMII mode). Port 1 Link Status from PHY. Asserting Pin K7 low activates the Port 1 link. Transmit Data Output Bit 1 for Port 2 MII and RMII. Receive Data Input Bit 0 for Port 2 MII and RMII. Transmit Data Output Bit 1 for Port 1 MII and RMII. Transmit Data Output Bit 2 for Port 1 MII. Receive Data Input Bit 0 for Port 1 MII and RMII. Receive Data Input Bit 3 for Port 1 MII. Port 1 Carrier Sense. When L6 is asserted high, a carrier has been sensed on Port 1. Port 1 Activity LED Output Driver. The LED turns on when Pin L7 is asserted low. Transmit Data Output Bit 0 for Port 2 MII and RMII. Transmit Data Output Bit 3 for Port 2 MII. Receive Data Input Bit 2 for Port 2 MII. Transmit Data Output Bit 3 for Port 1 MII. Receive Data Input Bit 1 for Port 1 MII AND RMII. Receive Data Input Bit 2 for Port 1 MII. Port I MII Receive Clock from PHY. Port 1 MII Collision. Asserting Pin M7 high indicates a collision on Port 1. Port 2 MII Transmit Enable. Setting Pin M8 to high enables the Port 2 transmit. Transmit Data Output Bit 2 for Port 2 MII. Port 2 MII Transmit Clock from PHY. Receive Data Input Bit 1 for Port 2 MII and RMII. Receive Data Input Bit 3 for Port 2 MII. I is input, I/O is input/output, O is output, and N/A is not applicable. Rev. E | Page 11 of 19 fido5100/fido5200 Data Sheet THEORY OF OPERATION DEVICE INTERFACES TIMER0 to TIMER3 Inputs/Outputs Oscillator TIMER0 to TIMER3 inputs/outputs can be configured to either time stamp an input event or time trigger an output event. When configured to time stamp an input event, the value of the IPT is captured in a 64-bit register when the associated timer signal transitions from low to high. User software reads this register and uses the value to time stamp an associated event. For example, when the TIMER0 signal transitions from low to high, the value of the IPT is stored in the Timer 0, 64-bit register (consult the REM Switch Software Driver User Guide, available at www.analog.com/en/products/industrial-ethernet.html for more details). The same is true when configuring TIMER1, TIMER2, or TIMER3 to time stamp input events. User software uses the generated time stamp to associate the time stored in the 64-bit register with a particular event. The oscillator clock source is routed to an internal phase-locked loop (PLL) to create the following clock sources: • • 25 MHz for the CLKOUT reference clock 50 MHz for the RMII reference clock An oscillator used as a clock source requires a tighter tolerance. F12 TIMER0 F11 TIMER1 F10 TIMER2 E12 TIMER3 E11 TIMER4 E10 TIMER5 D11 TIMER6 D10 TIMER7 C12 INT0 C11 INT1 C10 INT2 6 VDD XTAL0 E2 F2 E3 LE MBS SIZE_32 C25 0.01µF GND GND ASEMPC– 25.000MHZ–LR–T _BGA GND When configured to time trigger an output event, the timer signal toggles when the IPT reaches the value stored in the Timer x, 64-bit register. The process of time triggering an output event is as follows using the Timer 0 register in the example: 4 OUT OE 1 R28 22Ω 15833-007 G1 G2 XTAL0 XTAL1 +3V3 U5 25MHz 3 GND TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 INT0 INT1 INT2 1. The host processor software stores a value in the Timer 0, 64-bit register. 2. The IPT reaches that value stored in the Timer 0, 64-bit register. 3. The TIMER0 pin toggles from high to low or low to high (depending on its state when the 64-bit register was loaded). The same process is followed when the TIMER1, TIMER2, and TIMER3 pins are configured to time trigger output events. Figure 7. Oscillator Clock Source Circuit Crystal When using the REM switch with a crystal, use an oscillator pad configuration, as shown Figure 8. XTAL0 CL 25MHz REM SWITCH RF TIMER4 to TIMER7 Outputs XTAL1 TIMER4 to TIMER7 outputs are configured to output independent, IPT clock synchronized, programmable, pulse-width modulated signals. Each of these timers has a resolution of 16 ns. Each timer can have its own pulse-width modulation program that allows an arbitrary number of rising and falling edges, depending on the protocols that repeat on a programmable interval. The software drivers for the REM switch provide the capability to define the rising and falling edges for each TIMERx output. 15833-008 CL Figure 8. Crystal Clock Source Circuit The values presented in the following list are typical for operation when using a 25 MHz crystal: • • • ESR = 40 Ω CL = 8 pF RF = 1 MΩ Reset Timing HOST INTERFACE The timing requirement for RESET is a minimum active low time of 16 ns. Multiplex Bus Select INTERNAL PRECISION TIMER The REM switch includes an internal precision timer (IPT). The IPT maintains a system time that has a resolution of 1 ns. Use the IPT to trigger timer output events or capture input event times on the TIMER0, TIMER1, TIMER2, and TIMER3 pins, or to create a complex pulse pattern on the TIMER4, TIMER5, TIMER6, and TIMER7 pins. The host interface supports a separate address bus and data bus or a multiplexed address and data bus. The selection between the two types of busses is provided by the MBS signal (Pin F2), which is sampled on the rising edge of RESET. See Table 5 for pin function descriptions for the MBS and RESET signals. Rev. E | Page 12 of 19 Data Sheet fido5100/fido5200 Data Bus Width initialization process. In the case of the number, 0x00003300, the value read from this register must be transferred across the bus, as shown in Table 6. When evaluated in the software on the host processor, the value of these 32 bits results in 0x00003300. The host interface supports either a 16-bit or 32-bit wide data bus. The data bus width is determined by the SIZE_32 (Pin E3) signal that is sampled on the rising edge of RESET. See Table 5 for pin function descriptions for the SIZE_32 and RESET signals. For queue accesses, the REM switch treats all data as byte arrays. Consider the following example of a stream of bytes received over an Ethernet cable into a REM switch port and then transferred to the host. The packet data in network order is as follows: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F. Endianness The host interface presents data on the data bus in either big endian or little endian format. The endianness of the data is determined by the LE signal (Pin E2), which is sampled on the rising edge of the RESET signal. See Table 5 for pin function descriptions for the LE and RESET signals. The data is read differently depending on the setting, as follows: • The REM switch data bus is defined as follows: • • • D0 = LSB D15 = MSB for 16-bit bus D31 = MSB for 32-bit bus • • For all control/status register accesses, there is no difference in operation based on the setting of the LE pin. The data representation in a host processor register must match the data that is transferred over the bus. • Big endian 16-bit host interface: 0x0001, 0x0203, 0x0405, 0x0607, 0x0809, 0x0A0B, 0x0C0D, 0x0E0F. Big endian 32-bit host interface: 0x00010203, 0x04050607, 0x08090A0B, 0x0C0D0E0F. Little endian 16-bit host interface: 0x0100, 0x0302, 0x0504, 0x0706, 0x0908, 0x0B0A, 0x0D0C, 0x0F0E. Little endian 32-bit host interface: 0x03020100, 0x07060504, 0x0B0A0908, 0x0F0E0D0C. Consult the REM Switch Software Driver User Guide, available at www.analog.com/en/products/industrial-ethernet.html for more details on how to handle endianness in an application of a device. All control/status registers are 16-bits wide. If using a 32-bit bus, transfer the data in the following order: D15 to D0 (D31 to D16 are ignored when using a 32-bit bus). For example, the REM switch driver reads the device number register early in the Table 6. Control/Status Registers Bit Map D31 0 D15 0 D30 0 D14 0 D29 0 D13 1 D28 0 D12 1 D27 0 D11 0 D26 0 D10 0 D25 0 D9 1 D24 0 D8 1 D23 0 D7 0 D22 0 D6 0 D21 0 D5 0 D20 0 D4 0 D19 0 D3 0 D18 0 D2 0 D17 0 D1 0 D16 0 D0 0 D23 0 D7 0 D22 0 D6 0 D21 0 D5 0 D20 0 D4 0 D19 0 D3 1 D18 0 D2 1 D17 0 D1 1 D16 0 D0 1 D22 0 D6 0 D21 0 D5 0 D20 0 D4 0 D19 1 D3 1 D18 1 D2 1 D17 0 D1 1 D16 1 D0 1 D22 0 D6 0 D21 0 D5 0 D20 0 D4 0 D19 0 D3 1 D18 0 D2 1 D17 0 D1 1 D16 0 D0 0 D21 0 D5 0 D20 0 D4 0 D19 1 D3 1 D18 1 D2 1 D17 1 D1 0 D16 0 D0 0 Table 7. Big Endian 16-Bit Data Bus Bit Map, 0x0E0F Hexadecimal D31 0 D15 0 D30 0 D14 0 D29 0 D13 0 D28 0 D12 0 D27 0 D11 1 D26 0 D10 1 D25 0 D9 1 D24 0 D8 0 Table 8. Big Endian 32-Bit Data Bus Bit Map, 0x0C0D0E0F Hexadecimal D31 0 D15 0 D30 0 D14 0 D29 0 D13 0 D28 0 D12 0 D27 1 D11 1 D26 1 D10 1 D25 0 D9 1 D24 0 D8 0 D23 0 D7 0 Table 9. Little Endian 16-Bit Data Bus Bit Map, 0x0E0F Hexadecimal D31 0 D15 0 D30 0 D14 0 D29 0 D13 0 D28 0 D12 0 D27 0 D11 1 D26 0 D10 1 D25 0 D9 1 D24 0 D8 1 D23 0 D7 0 Table 10. Little Endian 32-Bit Data Bus Bit Map, 0x0F0E0D0C Hexadecimal D31 0 D15 0 D30 0 D14 0 D29 0 D13 0 D28 0 D12 0 D27 1 D11 1 D26 1 D10 1 D25 1 D9 0 D24 1 D8 1 D23 0 D7 0 Rev. E | Page 13 of 19 D22 0 D6 0 fido5100/fido5200 Data Sheet Address/Data Bus Operation Register and Data Access The host interface address/data bus connects to the address/ data bus of the CPU. There are four bits of data for the address bus and either 16 bits or 32 bits of data for the data bus. Each REM switch address is 32-bit aligned, meaning that the addresses increment by four bytes (A05 to A02). Regardless of whether the data bus is 16 bits wide or 32 bits wide, the least significant address bit supplied to the REM switch is always the same. Four bits of address provide direct access to 16 registers. A read cycle or a write cycle obtains or sets the data in these registers. To access additional registers, use the host indirect address register. The direct address register definitions are provided in Table 11. In addition, all accesses to indirect registers return the register data in the lower 16 bits only (even if the interface is 32 bits wide). For wider registers, such as a 64-bit timer, use a repeated set of reads or writes to access the full content of the register. Nonmultiplexed Address Data Bus MBS = 0 selects the nonmultiplexed address data bus configuration. The read and write cycle timings are defined in Figure 2 and Figure 3. See Table 2 for the read and write cycle timing parameters. Multiplexed Address Data Bus MBS = 1 selects the multiplexed address data bus configuration. The read and write cycle timings are defined in Figure 4 and Figure 5. See Table 3 for the read and write cycle timing parameters. The REM switch software driver provides the necessary application programming interface (API) functions to access these registers and manage all aspects of the switch for a specific protocol. Ethernet packets are received and transmitted directly through the Queue 0, Queue 1, Queue 2, and Queue 3 read and write registers, depending on the protocol. Ethernet protocol control and switch management are performed by the software driver API through the host read/write queue data registers and the host direct/indirect registers (refer to the REM Switch Driver User Guide, available at www.analog.com/en/products/industrial-ethernet.html, for more information about these registers). Interrupt management is performed by the software driver API using the three interrupt lines in conjunction with the queue status register, timer status register, universal input/output controller (UIC) interrupt status register, and the composite interrupt status register. Table 11. Direct Address Register Definitions Register Name Queue 0 Read Queue 0 Write Queue 1 Read Queue 1 Write Queue 2 Read Queue 2 Write Queue 3 Read Queue 3 Write Reserved Host Read Queue 0 Data Host Read Queue 0 Data Head Host Read Queue 1 Data Host Read Queue 1 Data Head Queue Status Register Timer Status Register UIC Interrupt Status Composite Interrupt Status Host Indirect Address Host Indirect Read Data Host Indirect Write Data Host Write Queue 0 Completion Host Write Queue 1 Completion 1 2 Width 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 N/A 16/32 16/32 16/32 16/32 16 16 16 16 16 16 16 16 16 Address[5:0] 0x00 0x00 0x04 0x04 0x08 0x08 0x0C 0x0C 0x10 to 0x14 0x18 0x18 0x1C 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x34 0x38 0x3C R means read only, W means write only, and R/W means read/write. N/A means not applicable. Rev. E | Page 14 of 19 Read/Write 1 R W R W R W R W R W R W R/W R/W R/W R R/W R W R R Reset Value 2 0x00000000 N/A 0x00000000 N/A 0x00000000 N/A 0x00000000 N/A N/A 0x00000000 0x00000000 0x00000000 N/A 0x00000F00 0x00000000 0x0000 0x0000 0x0000 N/A N/A 0x0000 0x0000 Data Sheet fido5100/fido5200 Interrupts ETHERNET INTERFACE Three interrupt lines are outputs from the REM switch; these three lines are labeled INT0, INT1, and INT2. Each of these interrupt lines must be mapped according to the interrupt inputs of the host processor. To ensure the best protocol performance, give INT2 the highest priority in the processor priority scheme, and do not disable it. There are two Ethernet ports on the REM switch. Each port is capable of configuration to support RMII or MII. Each port also has an input for link status from the PHY and an output for a link activity LED. The interrupt lines are mapped to the events defined by the queue status register, timer status register, UIC interrupt status register, and composite interrupt status register for each protocol. It is the responsibility of the software driver API to provide the appropriate interrupt service routine for the mapped event. Refer to the REM Switch Driver User Guide, available at www.analog.com/en/products/industrial-ethernet.html, for technical details on handling REM switch interrupts for a specific industrial Ethernet protocol. When an interrupt event defined in the appropriate status registers occurs, the associated REM switch interrupt output line becomes active (Logic 1) and remains active until the register is cleared. If multiple events are mapped to the same REM switch interrupt output, and more than one becomes active, the associated interrupt line remains in the active (Logic 1) state until all active interrupt source registers are cleared. Note that although the interrupts, INT0, INT1, and INT2, are labeled as priorities of low, medium, and high, there is not any inherent priority on the lines themselves, and they can be mapped accordingly. Connections The pins associated specifically with the RMII and MII interfaces are listed in Table 12; their full descriptions are defined in Table 5. The RMII interface is a seven-signal interface for each port (see Figure 9). This interface uses a 50 MHz reference clock (RMII_ CLK) provided by the REM switch to the PHY. The MII interface is a 14-signal interface for each port (see Figure 10). The REM switch provides the base clock to the PHYs using the synchronized 25 MHz CLKOUT signal. The PHYs then provide a receive and transmit clock (RX_CLK and TX_CLK) for each port. Link Status and Activity The Px_LINK_STATUS signal is an input to the REM switch from the selected PHY, configured so that the Px_LINK_STATUS signal is asserted continuously (not blinking) and determines the link up or link down state. The Px_ACTIVITY signal is an output from the REM switch and is typically used to drive an LED to indicate a link is valid. Rev. E | Page 15 of 19 32 D00 TO D31 A02 TO A05 TIMER4 TO TIMER7 PORT 2 4 Brief Description 50 MHz RMII Transmit and Receive Clock for Port 1 and Port 2. Output Clock. Port 2 Activity LED Output Driver. Port 2 Carrier Sense. Port 2 MII Collision. Port 2 Link Status from PHY. Port 1 MII Transmit Enable. Port 1 MII Transmit Clock from PHY. Port 2 Received Data Valid. Port 2 MII Receive Clock from PHY. Transmit Data Output Bit 0 for Port 1 MII, RMII. Port I MII Received Data Valid. Port 1 Link Status from PHY. Transmit Data Output Bit 1 for Port 2 MII, RMII. Receive Data Input Bit 0 for Port 2 MII, RMII. Transmit Data Output Bit 1 for Port 1 MII, RMII. Transmit Data Output Bit 2 for Port 1 MII. Receive Data Input Bit 0 for Port 1 MII, RMII. Receive Data Input Bit 3 for Port 1 MII. Port 1 MII Carrier Sense. Port 1 Activity LED Output Driver. Transmit Data Output Bit 0 for Port 2 MII, RMII. Transmit Data Output Bit 3 for Port 2 MII. Receive Data Input Bit 2 for Port 2 MII. Transmit Data Output Bit 3 for Port 1 MII. Receive Data Input Bit 1 for Port 1 MII, RMII. Receive Data Input Bit 2 for Port 1 MII. Port 1 Receive Clock from PHY. Port 1 MII Collision. Port 2 MII Transmit Enable. Transmit Data Output Bit 2 for Port 2 MII. Port 2 MII Transmit Clock from PHY. Receive Data Input Bit 1 for Port 2 MII, RMII. Receive Data Input Bit 3 for Port 2 MII. Rev. E | Page 16 of 19 15833-010 P2_RXD0 TO P2_RXD3 4 P2_TXEN P2_RXDV P2_CRS P2_COL P2_TXD0 TO P2_TXD3 4 P1_RXCLK P1_TXCLK P2_RXCLK P2_TXCLK P2_LINK_STATUS P2_ACTIVITY Figure 10. REM Switch Configured for MII Interface Table 12. Brief Descriptions for MII and RMII Pins Mnemonic RMII_CLK CLKOUT P2_ACTIVITY P2_CRS P2_COL P2_LINK_STATUS P1_TXEN P1_TXCLK P2_RXDV P2_RXCLK P1_TXD0 P1_RXDV P1_LINK_STATUS P2_TXD1 P2_RXD0 P1_TXD1 P1_TXD2 P1_RXD0 P1_RXD3 P1_CRS P1_ACTIVITY P2_TXD0 P2_TXD3 P2_RXD2 P1_TXD3 P1_RXD1 P1_RXD2 P1_RXCLK P1_COL P2_TXEN P2_TXD2 P2_TXCLK P2_RXD1 P2_RXD3 REM SWITCH P1_TXD0 TO P1_TXD3 P1_RXD0 TO P1_RXD3 P1_CRS P1_COL P1_RXDV P1_TXEN 15833-009 P2_TXEN P2_RXD0/ P2_RXD1 2 PORT 1 P1_LINK_STATUS P1_ACTIVITY Figure 9. REM Switch Configured for RMII Interface Pin No. G10 G11 G12 H10 H11 H12 J1 J2 J11 J12 K1 K6 K7 K8 K10 L1 L2 L3 L4 L6 L7 L8 L9 L11 M1 M3 M4 M6 M7 M8 M9 M10 M11 M12 4 3 4 P2_LINK_STATUS P2_ACTIVITY RMII_CLK P1_RXD0/ P1_RXD1 2 2 P1_TXD0/ P1_TXD1 P1_LINK_STATUS P1_ACTIVITY 4 4 PORT 2 HOST INTERFACE CLKOUT RESET TIMER0 TO TIMER3 4 TIMER4 TO TIMER7 INT0 TO INT2 MBS LE SIZE_32 WE CS OE D00 TO D31 4 A02 TO A05 REM SWITCH P2_CRS/ P2_RXDV PORT 1 P2_TXD0/ P2_TXD1 CLKOUT RESET TIMER0 TO TIMER3 P1_CRS/ P1_RXDV P1_TXEN XTAL0 HOST INTERFACE 2 4 INT0 TO INT2 MBS LE SIZE_32 WE CS OE XTAL0 32 Data Sheet 3 fido5100/fido5200 Data Sheet fido5100/fido5200 APPLICATIONS INFORMATION CONFIGURABLE TO SUPPORT INDUSTRIAL ETHERNET PROTOCOLS INDUSTRIAL FIELD DEVICE OR CONTROLLER APPLICATION PRP FLASH PROFINET, EtherNet/IP, Modbus TCP, EtherCAT, ETHERNET POWERLINK CPU OR SoC RAM DLR MRPD REAL-TIME ETHERNET MULTIPROTOCOL (REM) SWITCH FAST CYCLE TIME, FAST STARTUP, AND LOW JITTER CONFIGURABLE TO SUPPORT TOPOLOGY MANAGEMENT PHY APPLICATION I/O LLDP PriorityChannel TECHNOLOGY HSR CONFIGURABLE TO SUPPORT NETWORK MANAGEMENT DCP PHY RSTP MRP VLAN DHCP IGMP LEARNING 15833-011 AGING INDUSTRIAL ETHERNET NETWORK Figure 11. Application for the REM Switch REM SWITCH HARDWARE BOARD LAYOUT The basic REM switch hardware is identified as the fido5100 or fido5200. For example, the fido5100 supports the following protocols: The following guidelines provide best practice for board layout with the REM switch: • • • • PROFINET RT and IRT, Class B and Class C with fast startup (Version 2.3) EtherNet/IP with and without DLR (supervisor and node, announce based and beacon based), QuickConnect, CIP Sync, and CIP Motion Modbus TCP POWERLINK • • • Use individual polygons for the power planes for each of the three supplies. Allow at least 0.2 mm of isolation between the power planes. Isolate clock signals from the other traces and make them as short as possible. A minimum clearance around the REM switch of 3 mm is required to facilitate heat dissipation. DESIGN CONSIDERATIONS The fido5200 supports the following protocols: Power • • The REM switch require 1.2 V and 3.3 V power supplies. Each power level requires its own power plane on the PCB. EtherCAT All protocols defined for the fido5100 The REM switches are PI Net Load Class III capable, and support media redundancy for planned duplication (MRPD), high availability seamless redundancy (HSR), and parallel redundancy protocol (PRP). They also support IEEE 1588 Version 2 for ordinary clock (both peer to peer and end to end transparent clocks), raw frames, and user datagram protocol (UDP), as well as discovery configuration protocol (DCP), link layer discovery protocol (LLDP), dynamic host configuration protocol (DHCP), rapid spanning tree protocol (RSTP), virtual local area network (VLAN), and Internet group management protocol (IGMP) snooping support. REM Switch Drivers The REM switch driver for each protocol is provided as portable C code. The REM Switch Software Driver User Guide describes the driver for each protocol and its integration into a host processor. Visit www.analog.com/en/products/industrialethernet.html to download the user guide. The REM switch uses 3.3 V LVCMOS logic levels for its I/O. This I/O requires a 3.3 V (±10%) power supply circuit. Ideally, this circuit uses a low noise switching power supply. The REM switch use a 1.2 V (±10%) supply for the core of the chip. The core power supply requires its own power plane on the PCB. Additional best practices include • • • • • Rev. E | Page 17 of 19 Use one 0.1 µF bypass capacitor for every 1.2 V power pin. Use a power supply IC rated to supply at least 100 mA. Supply 3.3 V power from its own layer on the PCB to the 3.3 V power input pins on the REM switch. Use one 0.1 µF bypass capacitor for every 3.3 V power pin. For the 1.2 V analog supply, the signal must be isolated using a 120 Ω, 500 mA ferrite bead and 10 µF, 1 µF, and 0.1 µF filtering capacitors. fido5100/fido5200 Data Sheet Reset The RESET signal is typically driven by the host microprocessor that is paired with the REM switch. RESET is an active low signal; therefore, pull RESET high as power becomes valid. Physical Layer (PHY) The REM switch is designed intentionally without PHYs because of the different requirements on PHY performance. EtherCAT and PROFINET IRT have much tighter latency and jitter requirements than standard Ethernet. Clocking Most PHYs allow the user to clock the PHY with a crystal oscillator or a separate clock source when using an MII interface. It is a requirement for EtherCAT designs (and recommended for other designs) to use the CLKOUT signal from the REM switch as the clock source for the PHYs. This approach minimizes jitter as much as possible. CLKOUT from the REM switch is a 25 MHz clock signal generated from the 25 MHz input clock to the REM switch using the internal PLL of the REM switch. The PHY uses the 25 MHz CLKOUT signal to generate the MII receive (Rx) and transmit (Tx) clock inputs (P1_RXCLK, P1_TXCLK, P2_RXCLK, and P2_TXCLK pins) to the REM switch. For RMII, the REM switch generates the required 50 MHz clock for the RMII interface. The clock is generated from the 25 MHz input clock to the REM switch using the internal PLL of the REM switch. As with all clock signals, take care when routing these signals to minimize noise and loading effects. Management Data Input/Output (MDIO) All PHYs require configuration and can provide some type of status information in return. Each PHY is different, but most PHYs use a management data input/output (MDIO) interface to communicate this configuration and status. The REM switch does not provide separate communication to the PHYs. The host processor paired with the REM switch is required to provide this PHY communication. Contact Analog Devices, Inc., technical support regarding questions about PHY settings or the MDIO interface. Rev. E | Page 18 of 19 Data Sheet fido5100/fido5200 OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 A1 BALL CORNER A1 BALL PAD CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ REF E F G H J 0.80 BSC K L M TOP VIEW BOTTOM VIEW DETAIL A SIDE VIEW DETAIL A 0.35 0.30 0.25 PKG-000000 SEATING PLANE 0.45 0.40 0.35 BALL DIAMETER 0.91 0.86 0.81 COPLANARITY 0.12 COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1 08-17-2017-A 1.24 MAX Figure 12. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 FIDO5100BBCZ FIDO5100CBCZ FIDO5110BBCZ FIDO5110CBCZ FIDO5200BBCZ FIDO5200CBCZ FIDO5210BBCZ FIDO5210CBCZ RAPID-NIEK-V0004 1 Temperature Range −40°C to +85°C −40°C to +105°C −40°C to +85°C −40°C to +105°C −40°C to +85°C −40°C to +105°C −40°C to +85°C −40°C to +105°C Package Description 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Kit Z = RoHS Compliant Part. ©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15833-3/20(E) Rev. E | Page 19 of 19 Package Option BC-144-12 BC-144-12 BC-144-12 BC-144-12 BC-144-12 BC-144-12 BC-144-12 BC-144-12
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