HMC1031MS8E

0.1 MHz to 500 MHz Clock Generator with Integer N PLL HMC1031 Data Sheet FUNCTIONAL BLOCK DIAGRAM Low current consumption: 1.95 mA typical High phase frequency detector rate: 140 MHz Hardware pin-programmable clock multiplication ratios: 1×/5×/10× Lock detect indicator Power-down mode (0.8 μA typical) 8-lead MSOP package: 4.9 mm × 3.0 mm APPLICATIONS VCC 1 REFIN 2 LKDOP 3 D0 4 HMC1031 PFD/CP LKD 1/N 8 GND 7 CP 6 VCOIN 5 D1 13353-001 FEATURES Figure 1. Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops (PLLs) Frequency translation Oven controlled crystal oscillator (OCXO) frequency multipliers Phase lock clean high frequency references to 10 MHz equipment GENERAL DESCRIPTION Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications. The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs. The HMC1031 features a low power integer N divider, supporting divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port. Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in powerdown mode. The HMC1031 is housed in an 8-lead MSOP package. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC1031 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Applications Information .............................................................. 10 Functional Block Diagram .............................................................. 1 Jitter Attenuation ........................................................................ 10 General Description ......................................................................... 1 Frequency Translation ............................................................... 10 Revision History ............................................................................... 2 Loop Bandwidths with HMC1031 ........................................... 10 Specifications..................................................................................... 3 Using VCOs/VCXOs with Negative Tuning Slope ................ 10 Electrical Specifications ............................................................... 3 Lock Detector ............................................................................. 10 Absolute Maximum Ratings ............................................................ 4 Printed Circuit Board (PCB) .................................................... 11 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 13 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 13 Interface Schematics..................................................................... 6 REVISION HISTORY 10/15—v02.0215 to Rev. C This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Changed MS8E to MSOP and VCO Input to VCOIN ...Throughout Changes to Features Section............................................................ 1 Changes to Figure 3, Figure 4, and Figure 6 ................................. 6 Deleted GND Interface Schematic; Renumbered Sequentially .. 7 Change to Figure 17 ......................................................................... 8 Changes to Lock Detector Section ............................................... 10 Changes to Figure 25 ...................................................................... 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 Rev. C | Page 2 of 13 Data Sheet HMC1031 SPECIFICATIONS ELECTRICAL SPECIFICATIONS TA = 25°C, VCC = 3.3 V, unless otherwise specified. Table 1. Parameter POWER SUPPLY VOLTAGE OPERATING TEMPERATURE FREQUENCY1 Reference Input2 VCO Input CHARGE PUMP Current Output Range3 INPUT Voltage Swing (Reference and VCOIN Inputs)1 REFIN, VCOIN DC Bias Duty Cycle Impedance at 50 MHz DIVIDE RATIOS FIGURE OF MERIT (FOM) 4 Floor Flicker PHASE AND FLICKER NOISE Flicker Noise (PNFLICK) Phase Noise Floor (PNFLOOR) CURRENT Supply5 Power-Down6 LOCK DETECT OUTPUT CURRENT Test Conditions/Comments Min 2.7 −40 Typ 3.3 +27 Max 3.5 +85 Unit V °C 140 500 MHz MHz 50 0.2 to VCC − 0.4 Externally ac-coupled to the chip2 0.1 0.5 × VCC approximately µA V 3.5 V p-p 60 V % Ω||pF −204 −248 dBc/Hz dBc/Hz 3 mA µA µA µA mA 1.65 40 Applicable to REFIN and VCOIN pins VCO/VCXO feedback divider Divide by 10 3600||4 1/5/10 −212 −254 PNFLICK = Flicker FOM + 20log(fVCXO) − 10log(fOFFSET), where fVCXO is the VCXO frequency and fOFFSET is the offset frequency PNFLOOR = Floor FOM + 10log(fPD) + 20log(fVCXO/fPD), where fPD is the phase detector frequency 100 MHz reference = VCXO, VCC = 3.3 V VCC = 3.0 V, 25°C, D0 = 0, D1 = 0 VCC = 3.3 V, 85°C VCC = 3.6 V, 85°C CMOS output level 1 −208 −252 Determined by formula Determined by formula 1.95 0.05 0.8 1 The REFIN and VCOIN inputs must be ac-coupled to the HMC1031. The peak input level must not exceed VCC + 0.4 V with respect to GND. The lower limit of operation, 0.1 MHz, is limited by off chip ac coupling. Select the size of the ac coupling capacitor such that the impedance, relative to the 3.6 kΩ input impedance of the device and any termination impedances on the evaluation board (50 Ω by default), is insignificant. 3 The PLL may lock in the voltage range of 0.2 V to VCC − 0.4 V. However, the charge pump gain may be reduced. See Figure 14 for charge pump compliance. 4 See Figure 20 and Figure 21 for additional flicker FOM and floor FOM data, respectively. 5 See Figure 17 for additional supply current data. Base frequency: 100 MHz; base VCC: 3.3 V, 0.8 mA/V to 1 mA/V; base phase frequency detector (PFD) current: 1.8 mA, 8 μA/MHz; base divider current: 1.15 mA, 15 μA/MHz. For example, the device current for a 10 MHz reference and 50 MHz VCO at 3.0 V VCC can be calculated as: ΔPFD current = (10 − 100) × (8 × 10−6) = −0.72 mA, ΔDIV current = (50 − 100) × (15 × 10−6) = −0.75 mA, device current = (1.8 − 0.72) + (1.15 − 0.75) = 1.48 mA at 3.3 V VCC. At 3 V, the VCC device current is approximately: 1.48 – (0.85 × 10−3) × (3.3 − 3.0) = 1.225 mA. 6 In power-down mode, the REFIN/VCOIN inputs and charge pump outputs are tristated. The power-down leakage current is measured without any signal applied to the HMC1031. 2 Rev. C | Page 3 of 13 HMC1031 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC to GND D0, D1 Pins to GND Maximum REFIN Input Voltage Maximum VCOIN Input Voltage Maximum Junction Temperature Maximum Peak Reflow Temperature (MSL1) Storage Temperature Range Operating Temperature Range Thermal Resistance Reflow Soldering Peak Temperature Time at Peak Temperature ESD Sensitivity (Human Body Model (HBM)) Rating −0.3 V to +3.6 V −0.3 V to +3.6 V VCC + 0.4 V VCC + 0.4 V 125°C 260°C −65°C to +150°C −40°C to +85°C 0.2°C/mW Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 260°C 40 sec Class 2 Rev. C | Page 4 of 13 Data Sheet HMC1031 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC 1 REFIN 2 8 GND HMC1031 7 CP TOP VIEW (Not to Scale) LKDOP 3 D0 4 5 D1 13353-002 6 VCOIN Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4, 5 Mnemonic VCC REFIN LKDOP D0, D1 6 7 8 VCOIN CP GND Description Supply Voltage (3.3 V Typical). Reference Input. REFIN is an externally ac-coupled reference frequency input. Lock Detect Output, CMOS Drive. Integer N Division Ratio Selection. D0 and D1 are the CMOS inputs used to specify the integer N division ratio. See Table 4. Voltage Controlled Oscillator Input. VCOIN is an ac-coupled VCO/VCXO input. Charge Pump Output. Ground. Table 4. Frequency Multiplication Truth Table D0 0 1 0 1 1 D1 0 0 1 1 PLL Feedback Division Ratio (N)1 Power-down mode Divide by 1 Divide by 5 Divide by 10 Set by SW1 in the evaluation PCB schematic (see Figure 24). Rev. C | Page 5 of 13 HMC1031 Data Sheet INTERFACE SCHEMATICS VCC VCC REFIN 13353-003 13353-006 VCOIN Figure 3. REFIN Interface Schematic Figure 6. VCOIN Interface Schematic VCC VCC VCC 13353-007 CP 13353-004 LKDOP Figure 7. CP Interface Schematic Figure 4. LKDOP Interface Schematic VCC 13353-005 D0, D1 Figure 5. D0, D1 Interface Schematic Rev. C | Page 6 of 13 Data Sheet HMC1031 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 3.3 V, unless otherwise specified. –40 –20 100MHz VCXO LOCKED WITH TINY PLL 10MHz NOISY REFERENCE 12kHz TO 20MHz INTEGRATED JITTER HMC1031/VCXO: 55fs 10MHz INPUT: 4ps PHASE NOISE (dBc/Hz) –100 –120 –140 –160 –100 –120 –140 10k 100k 1M –180 10 Figure 8. 10 MHz to 100 MHz with Noisy Reference Phase Noise; Loop Filter Value: C8 = 4.7 nF, R7 = 1.2 kΩ, C9 = 62 μF, Loop Filter BW = 8 Hz, VCXO = 100 MHz Crystek CVHD-950 100 1k 10k 100k 1M OFFSET (Hz) 13353-012 1k 13353-009 100 OFFSET (Hz) Figure 11. 10 MHz to 50 MHz with Noisy Reference Phase Noise; Loop Filter Value: C8 = 220 nF, R7 = 3.3 kΩ, C9 = 2.2 μF, Loop Filter BW = 50 Hz, VCXO = Bliley V105ACACB, 50 MHz –20 –20 OPEN-LOOP VCXO PHASE NOISE 10MHz VERY NOISY REFERENCE 100MHz VCXO LOCKED WITH TINY PLL –40 12kHz TO 20MHz INTEGRATED JITTER HMC1031/VCXO: 57.8fs 10MHz INPUT: 16.2ps –60 SIM MODEL SIM VCXO RESPONSE SIM PLL CONTRIBUTION SIM REFERENCE RESPONSE TOTAL MEASURED PHASE NOISE FREE RUNNING BLILEY 50MHz 10MHz NOISY REFERENCE 12kHz TO 20MHz INTEGRATED JITTER HMC1031/VCXO: 212fs –40 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –80 –160 –180 10 –80 –100 –120 –140 –160 –60 –80 –100 –120 –140 –160 1 10 100 1k 10k 100k 1M OFFSET (Hz) –180 13353-010 –180 12kHz TO 20MHz INTEGRATED JITTER HMC1031/VCXO: 190fs 10MHz INPUT: 4ps –60 Figure 9. 10 MHz to 100 MHz with Very Noisy Reference Phase Noise; Loop Filter Value: C8 = 4.7 nF, R7 = 1.2 kΩ, C9 = 62 μF; Loop Filter BW = 8 Hz; VCXO = 100 MHz Crystek CVHD-950 1 10 100 1k 10k 100k 1M 10M 100M OFFSET (Hz) 13353-013 PHASE NOISE (dBc/Hz) –60 –80 50MHz VCXO LOCKED WITH TINY PLL 10MHz NOISY REFERENCE OPEN LOOP VCXO PHASE NOISE –40 Figure 12. Typical Closed-Loop Phase Noise, HMC1031 as Jitter Attenuator, Loop BW = 100 Hz; Refer to Loop Filter Configuration 2 in Table 5 1000 200 FREQUENCY ERROR (Hz) PHASE ERROR (Degrees) 500 100 0 –100 0 –500 –1000 –1500 10 20 30 40 TIME (ms) 50 60 70 80 –2000 13353-011 0 Figure 10. Phase Error During Lock Time for Divide by 5; 10 MHz Input; 50 MHz Output; Loop BW = 100 Hz; Refer to Loop Filter Configuration 2 in Table 5 0 10 20 30 40 TIME (ms) 50 60 70 80 13353-014 –200 Figure 13. Frequency Error During Lock Time for Divide by 5; 10 MHz Input; 50 MHz Output; Loop Bandwidth = 100 Hz; Refer to Loop Filter Configuration 2 in Table 5 Rev. C | Page 7 of 13 HMC1031 Data Sheet 3.0 60 +85°C +27°C –40°C 40 30 ISOURCE = 3.0V, VCC ISINK 20 DIV 1, REF/VCXO = 122.88MHz 2.5 ISOURCE = 2.7V, VCC CURRENT (mA) SOURCE/SINK CURRENT (µA) 50 ISOURCE = 3.3V, VCC 10 DIV 10, REF = 10MHz, VCXO = 100MHz 2.0 1.5 ISOURCE = 3.5V, VCC 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 13353-015 0 1.0 4.0 CHARGE PUMP OUTPUT VOLTAGE (V) 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) Figure 14. Typical Source and Sink Current vs. Charge Pump Output Voltage 13353-018 DIV 5, REF = 10MHz, VCXO = 50MHz –10 Figure 17. Current vs. Supply Voltage, Different Configurations 10 RECOMMENDED REGION OF OPERATION –10 –30 50 100 150 200 INPUT FREQUENCY (MHz) RECOMMENDED REGION OF OPERATION 0.1 0.01 13353-016 –20 1 50 100 150 13353-019 0 INPUT VOLTAGE SWING (V p-p) INPUT POWER (dBm) 10 200 INPUT FREQUENCY (MHz) Figure 15. REFIN Input Power vs. Input Frequency Figure 18. REFIN Input Voltage Swing vs. Input Frequency 10 0 RECOMMENDED REGION OF OPERATION –10 –30 80 160 240 320 400 INPUT FREQUENCY (MHz) 480 560 13353-017 –20 1 RECOMMENDED REGION OF OPERATION 0.1 0.01 80 160 240 320 400 INPUT FREQUENCY (MHz) 480 560 13353-020 INPUT VOLTAGE SWING (V p-p) INPUT POWER (dBm) 10 Figure 19. VCOIN Input Voltage Swing vs. Input Frequency; Maximum Frequency Is Guaranteed in the Recommended Region of Operation Across Temperature and Process Variation Figure 16. VCOIN Input Power vs. Input Frequency, Maximum Frequency Is Guaranteed in the Recommended Region of Operation Across Temperature and Process Variation Rev. C | Page 8 of 13 Data Sheet HMC1031 –246 –200 –248 FLOOR FOM (dBc/Hz) –250 –252 –254 –256 –205 –210 –260 2.7 2.8 2.9 3.0 3.1 3.2 SUPPLY VOLTAGE (V) 3.3 3.4 3.5 Figure 20. Flicker FOM –215 2.7 2.8 2.9 3.0 3.1 3.2 SUPPLY VOLTAGE (V) Figure 21. Floor FOM Rev. C | Page 9 of 13 3.3 3.4 3.5 13353-022 –258 13353-021 FLICKER FOM (dBc/Hz) +85°C +27°C –40°C +85°C +27°C –40°C HMC1031 Data Sheet APPLICATIONS INFORMATION 1 REFIN 2 LKDOP 3 D0 4 HMC1031 8 GND PFD/CP LKD 1/N NARROW LOOP FILTER VCXO 7 CP UP TO 500MHz CLEAN CLOCK SIGNAL 6 VCOIN 5 D1 13353-023 UP TO 140MHz NOISY CLOCK REFERENCE VCC Figure 22. Typical Application Diagram JITTER ATTENUATION In some cases, reference clocks to the system may come from external noisy sources with high jitter. The HMC1031 can be used to attenuate this incoming jitter and distribute a clean clock in the system. In such a scheme, a narrow loop filter is selected for the HMC1031. The device frequency locks to the external VCXO, but the reference jitter is attenuated as defined by the set loop filter bandwidth. The final output frequency and phase noise characteristics outside the loop bandwidth is defined by the phase noise characteristics of the VCXO used. A low jitter clock reference yields better clocking performance and better LO performance of the RF PLL VCOs, and improves the SNR performance of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). FREQUENCY TRANSLATION The reference clock in a test and measurement system or a communications system is often a high accuracy OCXO with excellent long-term stability. In some applications, the OCXO frequency must be multiplied up to a higher rate to drive the primary clock inputs in a system. The HMC1031 offers a very low power, small package and high performance method to multiply its incoming frequency in 1×, 5×, and 10× rates. Such multiplication is required because the higher reference clocks improve phase noise, ADC/DAC signal-to-noise ratio (SNR), clock generator jitter, and PHY bit error rates (BERs). In this scheme, the HMC1031 can be connected to an external low cost VCXO (for example, at 50 MHz or 100 MHz), and lock this external VCXO to the excellent long-term stability of the OCXO. LOOP BANDWIDTHS WITH HMC1031 In typical jitter attenuation applications, an incoming reference clock is frequency locked with a narrow PLL loop bandwidth such that its incoming noise is filtered out by the PLL and VCXO combination. The out of band phase noise of the PLL follows the VCXO that it is locked to. A narrow PLL loop bandwidth ensures that the output jitter is determined by the VCXO (or any other type of high quality factor VCO) and not affected by the spectral noise of the incoming clock beyond the set loop bandwidth. To facilitate narrow bandwidth loop filter configurations, the HMC1031 is designed to have a low charge pump current of 50 µA. This architecture offers advantages in low power consumption and loop filter design. Typically, narrow loop filter bandwidths require large filter capacitors. Due to the low charge pump current design of the HMC1031, smaller loop filter capacitor sizes can be used to implement narrow loop filters. Note that the HMC1031 is designed to operate in loop bandwidths of only a few kilohertz in its widest loop bandwidth configuration. USING VCOs/VCXOs WITH NEGATIVE TUNING SLOPE In its typical configuration, the HMC1031 works with any VCO/VCXO that has a positive tuning slope. For any VCO/VCXO with negative tuning slope, that is, when the frequency decreases with increasing tuning voltage, connect the loop filter ac ground to VCC instead of GND. LOCK DETECTOR The lock detector measures the arrival times between the divided VCO edge and reference edge appearing at the phase detector. When this offset becomes greater than approximately 6 ns, the lock detector indicates an out of lock condition. Any leakage current on the CP output causes a phase offset between the two edges. Due to the relatively small 50 µA charge pump current, the HMC1031 is sensitive to leakage currents and may indicate a false out of lock condition if the leakage current from the charge pump (Pin 7) to ground is too high. Leakage currents include dc current through the loop filter capacitors and/or dc current into the VCO tuning voltage pin, VTUNE. It is recommended to use low leakage, loop filter multilayer ceramic capacitors (MLCCs) and careful VCO selection to maximize VTUNE resistance. The maximum acceptable leakage is dependent on the phase detector operating frequency and can be calculated as follows: I LEAKAGE 3 ns = I CP t PD where: ILEAKAGE is the total leakage current in µA. ICP is the charge pump current in µA (set to 50 µA). tPD is the reference frequency period in ns. Internal delays reduce the available lock detector range from 6 ns to 3 ns. Rev. C | Page 10 of 13 Data Sheet HMC1031 PRINTED CIRCUIT BOARD (PCB) For example, to guarantee correct lock detector operation with a 10 MHz reference (tPD = 100 ns) and no leakage into the VCO VTUNE pin, the total capacitor leakage must be less than 1.5 µA. A typical MLCC 33 nF, 25 V loop filter capacitor has approximately 0.5 nA of leakage (Murata GRM155R71E333KA88). Use a sufficient number of via holes to connect the top and bottom ground planes (see Figure 23). The evaluation circuit board design is available from Analog Devices upon request. U1 R1 R2 GND R3 Y1 J3 C5 EXT REF C3 J3 TP3 C12 J5 C2 C4 R6 TP4 C10 J6 U1 R21 C20 C22 R18 XTAL R22 U2 R26 R27 R28 R29 R25 D1 LD R31 D1 LDO J4 SW1 TP1 D0 TP2 R10 R11 R7 R9 R8 VTUNE C8 C9 C6 R5 C27 C11 C14 R16 J7 R17 VCO C13 +3V C16 C15 C18 C26 TP6 C7 R12 D0 R4 C21 C25 R30 C23 C24 GND TP7 TP8 J4 Y2 TP5 Y3 C19 J3 R23 R19 R24 GND J8 R20 C17 EXT VCO J8 13353-024 C1 Y4 +5.5V Figure 23. Evaluation PCB Rev. C | Page 11 of 13 HMC1031 Data Sheet C22 0.1µF R28 DEPOP C20 0.1µF R27 DEPOP R26 DEPOP C25 0.01µF GND TP5 4 GND 13 14 15 RD2 HV2 XTAL R18 0.2kΩ VR4 9 HV3 5 TP6 R21 DEPOP 1 C19 DEPOP HMC860LP3E NC R22 DEPOP C13 0.1µF C16 DEPOP VR3 10 REF C21 1µF 3V DEPOP 2 VR2 11 BAND GAP EN J6 1 HV4 3 RD4 2 R30 10kΩ 8 C24 4.7µF C10 DEPOP TP3 R25 0.2kΩ VR1 12 RD3 C23 0.1µF TP8 3V U2 VDD 7 1 6 TP7 +5.5V RD1 HV1 16 R29 DEPOP J5 XTAL 2 C12 0.1µF C15 DEPOP VCOVCC C11 DEPOP C26 0.1µF 1 C18 0.1µF J7 TP4 VCOVCC DEPOP 2 C14 0.1µF XTAL J3 FOUT C5 DEPOP GND 2 EXT_REF R6 51kΩ 3V C4 0.1µF C2 0.47µF PLL Y4 4 VDD 1 VC TCXO 122.88MHz Y1 DEPOP 4 VDD C1 3 1 DEPOP OUT EN GND 2 10.000MHz DEPOP TP2 DEPOP R11 DEPOP LOOP FILTER 1 2 3 TP1 LD DEPOP 3V R31 1.1kΩ 4 HMC1031 VCC REFIN PFD/CP LKDOP LKD R1 0kΩ NC NC NC NC D1 LED J9 2 4 6 8 10 12 1 3 5 7 9 11 D0 D1 LD NC NC SSW-106-01-T-D HEADER TO USB BOARD CP 8 1/N D1 5 3V 1 4 2 3 R3 100kΩ C8 0.022µF C7 0.0033µF C27 0.0033µF R4 100kΩ C6 DEPOP 50Ω CO-PLANAR TRACE R5 DEPOP R23 16Ω 3 D1 0 0 1 1 D0 0 1 0 1 VCXO J8 EXT_VCO VCOVCC R19 0Ω Y2 4 VDD VC 1 GND 2 FOUT DIVIDER CONTROL POWER-DOWN DIVIDE BY 1 DIVIDE BY 5 DIVIDE BY 10 R9 0Ω R24 16Ω ATTENUATOR J4 VTUNE R7 22kΩ C9 0.27µF R17 16Ω R16 DEPOP R12 51Ω TDA02H0SB1 R10 DEPOP R8 0Ω 7 VCOIN 6 D0 SW1 R2 0kΩ GND C17 0.1µF 50.000MHz DEPOP Y3 1 6 VCRTL VDD 4 OUT EN 2 5 NC GND 3 R20 0Ω NC 13353-025 3 C3 0.1µF Figure 24. Evaluation PCB Schematic Table 5. Loop Filter Configuration Configuration 1 2 3 fREF (MHz) 10 10 10 fVCO (MHz) 100 50 50 Divider 10 5 5 Bandwidth (Hz) 10 100 2000 Rev. C | Page 12 of 13 C8 220 nF 100 nF 300 pF R7 7.5 kΩ 5.6 kΩ 100 kΩ C9 4.7 µF 1 µF 3.9 nF Data Sheet HMC1031 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 0.80 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 25. 8-Lead Mini Small Outline Package [MSOP] (HRM-8-1) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC1031MS8E Temperature Range −40°C to +85°C Package Description 8-Lead Mini Small Outline Package [MSOP] Package Option HRM-8-1 HMC1031MS8ETR −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] HRM-8-1 EVAL01-HMC1031MS8E 1 2 HMC1031MS8E Evaluation PCB E = RoHS Compliant Part. XXXX is the four-digit lot number. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13353-0-10/15(C) Rev. C | Page 13 of 13 Branding2 H1031 XXXX H1031 XXXX