4 W, GaAs, pHEMT, MMIC
Power Amplifier, 5.5 GHz to 8.5 GHz
HMC1121
Data Sheet
31 NIC
33 NIC
32 VDD2
35 NIC
34 VGG2
36 VDD1
38 NIC
37 VGG1
30 NIC
NIC 1
NIC 2
HMC1121
NIC 3
29 NIC
28 NIC
27 NIC
NIC 4
26 RFOUT
RFIN 5
25 NIC
24 VDET
APPLICATIONS
NIC 6
Point to point radios
Point to multipoint radios
Very small aperture terminals (VSATs) and satellite
communications (SATCOMs)
Military electronic warfare (EW) and electronic counter
measures (ECM)
NIC 8
23 VREF
NIC 9
22 NIC
NIC 10
21 NIC
GENERAL DESCRIPTION
The HMC1121 is a three-stage, gallium arsenide (GaAs),
pseudomorphic high electron mobility transfer (pHEMT),
monolithic microwave integrated circuit (MMIC), 4 W power
amplifier with an integrated temperature compensated on-chip
power detector that operates between 5.5 GHz and 8.5 GHz.
The HMC1121 provides 28 dB of gain, 44 dBm output IP3, and
36.5 dBm of saturated output power at 30% PAE from a 7 V
power supply.
Rev. A
NIC 20
NIC 18
VDD4 19
VGG4 17
NIC 16
NIC 13
VGG3 14
VDD3 15
NIC 12
NIC 11
NIC 7
PACKAGE
BASE
13529-001
High saturated output power (PSAT): 36.5 dBm at 30% power
added efficiency (PAE)
High output third-order intercept (IP3): 44 dBm typical
High gain: 28 dB typical
High output power for 1 dB compression (P1dB): 36 dBm typical
Total supply current: 2200 mA at 7 V
40-lead, 6 mm × 6 mm LFCSP package: 36 mm2
40 NIC
FUNCTIONAL BLOCK DIAGRAM
39 NIC
FEATURES
Figure 1.
The HMC1121 exhibits excellent linearity and it is optimized
for high capacity, point to point and point to multipoint radio
systems. The amplifier configuration and high gain make it an
excellent candidate for last stage signal amplification preceding
the antenna.
Ideal for supporting higher volume applications, the HMC1121
is provided in a 40-lead LFCSP package.
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HMC1121
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 11
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Recommended Bias Sequence .................................................. 12
Revision History ............................................................................... 2
Typical Application Circuit ....................................................... 12
Specifications..................................................................................... 3
Evaluation Board ............................................................................ 13
Electrical Specifications ............................................................... 3
Bill of Materials ........................................................................... 13
Absolute Maximum Ratings ............................................................ 4
Evaluation Board Schematic ..................................................... 14
ESD Caution .................................................................................. 4
Outline Dimensions ....................................................................... 15
Pin Configuration and Function Descriptions ............................. 5
Ordering Guide .......................................................................... 15
Interface Schematics..................................................................... 6
REVISION HISTORY
10/2017—Rev. 0 to Rev. A
Changes to Figure 32 ...................................................................... 11
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
7/2016—Revision 0: Initial Version
Rev. A | Page 2 of 15
Data Sheet
HMC1121
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = 7 V, IDD = 2200 mA, frequency range = 5.5 GHz to 7.5 GHz.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation over Temperature
RETURN LOSS
Input
Output
OUTPUT POWER
For 1 dB Compression
Saturated
OUTPUT THIRD-ORDER INTERCEPT
SUPPLY
Voltage
Total Current
Symbol
Min
5.5
24
P1dB
PSAT
IP3
35
VDD
IDD
5
Typ
Max
7.5
27
0.01
Unit
GHz
dB
dB/°C
17
13
dB
dB
36
36.5
44
dBm
dBm
dBm
7.5
2200
V
mA
Test Conditions/Comments
36 dBm = 4 W
At 30% PAE
Measurement taken at POUT/tone = 28 dBm
Adjust the gate control voltage (VGG1 to VGG4) between
−2 V to 0 V to achieve an IDD = 2200 mA typical
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = 7 V, IDD = 2200 mA, frequency range = 7.5 GHz to 8.5 GHz.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation over Temperature
RETURN LOSS
Input
Output
OUTPUT POWER
For 1 dB Compression
Saturated
OUTPUT THIRD-ORDER INTERCEPT
SUPPLY
Voltage
Total Current
Symbol
Min
7.5
25
P1dB
PSAT
IP3
35
VDD
IDD
5
Typ
Max
8.5
28
0.009
Unit
GHz
dB
dB/°C
15
13
dB
dB
36
36.5
43
dBm
dBm
dBm
7.5
2200
V
mA
Rev. A | Page 3 of 15
Test Conditions/Comments
36 dBm = 4 W
At 30% PAE
Measurement taken at POUT/tone = 28 dBm
Adjust the gate control voltage (VGG1 to VGG4) between
−2 V to 0 V to achieve an IDD = 2200 mA typical
HMC1121
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
Drain Voltage Bias
RF Input Power (RFIN)1
Channel Temperature
Continuous Power Dissipation, PDISS (TA
= 85°C, Derate 227 mW/°C Above
85°C)
Thermal Resistance (RTH) Junction to
Ground Paddle
Maximum Peak Reflow Temperature
(MSL3)2
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
1
2
Rating
8V
24 dBm
175°C
20.5 W
4.4°C/W
ESD CAUTION
260°C
−65°C to +150°C
−40°C to +85°C
Class 1A, passed 250 V
The maximum input power (PIN) is limited to 24 dBm or to the thermal limits
constrained by the maximum power dissipation.
See the Ordering Guide section.
Rev. A | Page 4 of 15
Data Sheet
HMC1121
31 NIC
32 VDD2
33 NIC
35 NIC
34 VGG2
37 VGG1
36 VDD1
38 NIC
39 NIC
40 NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC 1
30 NIC
NIC 2
29 NIC
NIC 3
28 NIC
27 NIC
NIC 4
RFIN 5
HMC1121
26 RFOUT
NIC 6
TOP VIEW
(Not to Scale)
25 NIC
24 VDET
NIC 7
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND.
13529-002
NIC 20
NIC 18
VDD4 19
NIC 16
VGG4 17
VDD3 15
VGG3 14
21 NIC
NIC 13
NIC 10
NIC 12
23 VREF
22 NIC
NIC 11
NIC 8
NIC 9
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1 to 4, 6 to 13, 16, 18, 20
to 22, 25, 27 to 31, 33, 35,
38 to 40
5
Mnemonic
NC
Description
No Internal Connection. These pins and exposed ground pad must be connected to RF/dc
ground.
RFIN
RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 3 for the RFIN interface
schematic.
Gate Controls for the Amplifier. Adjust VGG1 through VGG4 to achieve the recommended bias
current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 5 for the
VGG1 to VGG4 interface schematic.
Drain Biases for the Amplifier. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required.
See Figure 8 for the VDD1 to VDD4 interface schematic.
Voltage Reference. This pin is the dc bias of the diode biased through the external resistor and is
used for the temperature compensation of VDET. See Figure 7 for the VREF interface schematic.
Voltage Detection. This pin is the dc voltage representing the RF output power rectified by the
diode that is biased through an external resistor. See Figure 4 for the VDET interface schematic.
RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface
schematic.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
14, 17, 34, 37
VGG3, VGG4,
VGG2, VGG1
15, 19, 32, 36
23
VDD3, VDD4,
VDD2, VDD1
VREF
24
VDET
26
RFOUT
EPAD
Rev. A | Page 5 of 15
HMC1121
Data Sheet
RFOUT
13529-004
Figure 6. RFOUT Interface Schematic
VDET
13529-007
RFIN
Figure 3. RFIN Interface Schematic
13529-006
13529-003
INTERFACE SCHEMATICS
VREF
Figure 4. VDET Interface Schematic
Figure 7. VREF Interface Schematic
13529-005
VGG1, VGG2,
VGG3, VGG4
13529-008
VDD1 , VDD2 ,
VDD3 , VDD4
Figure 5. VGG1 to VGG4 Interface Schematic
Figure 8. VDD1 to VDD4 Interface Schematic
Rev. A | Page 6 of 15
Data Sheet
HMC1121
TYPICAL PERFORMANCE CHARACTERISTICS
40
30
30
28
GAIN (dB)
RESPONSE (dB)
20
10
S11
S21
S22
0
26
24
–10
22
4
5
6
7
8
9
10
FREQUENCY (GHz)
20
13529-009
–30
5
8
9
Figure 12. Gain vs. Frequency at Various Temperatures
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–5
RETURN LOSS (dB)
–5
–10
–15
–20
–10
–15
5
6
7
8
9
FREQUENCY (GHz)
–25
13529-010
–25
Figure 10. Input Return Loss vs. Frequency at Various Temperatures
5
6
7
8
9
FREQUENCY (GHz)
13529-013
–20
Figure 13. Output Return Loss vs. Frequency at Various Temperatures
40
40
+85°C
+25°C
–40°C
38
P1dB (dBm)
38
36
34
32
36
34
6V
7V
30
5
6
7
8
FREQUENCY (GHz)
9
13529-011
32
Figure 11. P1dB vs. Frequency at Various Temperatures
30
5
6
7
8
FREQUENCY (GHz)
Figure 14. P1dB vs. Frequency at Various Supply Voltages
Rev. A | Page 7 of 15
9
13529-014
RETURN LOSS (dB)
7
FREQUENCY (GHz)
Figure 9. Response (Broadband Gain and Return Loss) vs. Frequency for S21,
S11, and S22
P1dB (dBm)
6
13529-012
+85°C
+25°C
–40°C
–20
Data Sheet
40
38
38
36
34
32
+85°C
+25°C
–40°C
30
5
6
7
8
9
FREQUENCY (GHz)
5
38
PSAT (dBm)
36
34
1800mA
2000mA
2200mA
2400mA
30
7
8
8
9
36
34
1800mA
2000mA
2200mA
2400mA
32
9
FREQUENCY (GHz)
30
13529-016
5
6
7
8
9
FREQUENCY (GHz)
Figure 16. P1dB vs. Frequency at Various Supply Currents (IDD)
Figure 19. PSAT vs. Frequency at Various Supply Currents (IDD)
48
46
46
44
44
IP3 (dBm)
48
42
40
42
40
+85°C
+25°C
–40°C
36
5
6
1800mA
2000mA
2200mA
2400mA
38
7
8
9
FREQUENCY (GHz)
13529-017
38
Figure 17. Output IP3 vs. Frequency at Various Temperatures,
POUT/Tone = 28 dBm
36
5
6
7
8
9
FREQUENCY (GHz)
Figure 20. Output IP3 vs. Frequency at Various Supply Currents,
POUT/Tone = 28 dBm
Rev. A | Page 8 of 15
13529-020
P1dB (dBm)
38
6
7
Figure 18. PSAT vs. Frequency at Various Supply Voltages
40
5
6
FREQUENCY (GHz)
40
32
6V
7V
30
Figure 15. PSAT vs. Frequency at Various Temperatures
IP3 (dBm)
34
13529-019
32
36
13529-018
PSAT (dBm)
40
13529-015
PSAT (dBm)
HMC1121
HMC1121
48
60
46
50
44
40
IM3 (dBc)
42
30
20
6V
7V
36
5
6
7
8
9
FREQUENCY (GHz)
0
16
50
50
40
40
IM3 (dBc)
22
24
26
28
30
32
34
30
30
20
5.5GHz
6.5GHz
7.5GHz
8.5GHz
18
20
22
24
26
28
30
32
34
POUT/TONE (dBm)
0
16
40
2800
2600
20
2500
2400
15
IDD (mA)
25
2300
10
2200
5
26
28
30
32
34
35
30
25
GAIN
P1dB
PSAT
2000
–2
2
6
10
14
INPUT POWER (dBm)
13529-023
2100
–6
24
2900
2700
–10
22
40
GAIN (dB), P1dB (dBm), PSAT (dBm)
30
20
Figure 25. Output IM3 vs. POUT/Tone at VDD = 8 V
3000
POUT
GAIN
PAE
IDD
18
POUT/TONE (dBm)
Figure 22. Output Third-Order Intermodulation (IM3) vs. POUT/Tone at VDD = 7 V
35
5.5GHz
6.5GHz
7.5GHz
8.5GHz
10
13529-022
10
13529-025
IM3 (dBc)
60
20
POUT (dBm), GAIN (dB), PAE (%)
20
Figure 24. Output IM3 vs. POUT/Tone at VDD = 6 V
60
0
–14
18
POUT/TONE (dBm)
Figure 21. Output IP3 vs. Frequency at Various Supply Voltages,
POUT/Tone = 28 dBm
0
16
5.5GHz
6.5GHz
7.5GHz
8.5GHz
10
13529-021
38
13529-024
40
Figure 23. POUT, Gain, PAE, and IDD vs. Input Power at 7 GHz
20
1800
2000
2200
2400
IDD (mA)
Figure 26. Gain, P1dB, and PSAT vs. Supply Current (IDD) at 7 GHz
Rev. A | Page 9 of 15
13529-026
IP3 (dBm)
Data Sheet
HMC1121
Data Sheet
10
5.5GHz
7.0GHz
8.5GHz
35
VREF – VDET (V)
1
30
25
0.1
0.01
20
6.0
6.5
7.0
7.5
8.0
VDD (V)
0.001
–10
20
30
40
Figure 30. Detector Voltage (VREF − VDET) vs. Output Power at
Various Frequencies
20
10
+85°C
+25°C
–40°C
18
VREF – VDET (V)
1
16
14
0.01
5.5GHz
6.5GHz
7.5GHz
8.5GHz
10
–14 –12 –10 –8
–6
–4
0
–2
2
4
6
8
10
12
INPUT POWER (dBm)
Figure 28. Power Dissipation vs. Input Power at TA = 85°C
0.001
–10
–20
–30
–40
–50
–60
–70
–90
7
8
9
FREQUENCY (GHz)
13529-029
–80
6
10
20
30
40
Figure 31. Detector Voltage (VREF − VDET) vs. Output Power at Various
Temperatures, at 7 GHz
+85°C
+25°C
–40°C
5
0
OUTPUT POWER (dBm)
0
–10
0.1
13529-031
12
13529-028
POWER DISSIPATION (W)
10
OUTPUT POWER (dBm)
Figure 27. Gain, P1dB, and PSAT vs. Supply Voltage (VDD) at 7 GHz
REVERSE ISOLATION (dB)
0
13529-030
GAIN
P1dB
PSAT
13529-027
GAIN (dB), P1dB (dBm), PSAT (dBm)
40
Figure 29. Reverse Isolation vs. Frequency at Various Temperatures
Rev. A | Page 10 of 15
Data Sheet
HMC1121
THEORY OF OPERATION
The HMC1121 is a three-stage, GaAs, pHEMT, MMIC, 4 W
power amplifier consisting of three gain stages in series. A
simplified block diagram is shown in Figure 32. The input
signal is divided evenly into two; each of these two paths are
amplified through three independent gain stages. The amplified
signals are then combined at the output.
VGG2
VGG1
VDD1
VDD2
VGG3
VDD3
VDD4
VGG4
Figure 32. Simplified Block Diagram
13529-032
RFOUT
RFIN
The HMC1121 has single-ended input and output ports whose
impedances are nominally matched to 50 Ω internally over the
5.5 GHz to 8.5 GHz frequency range. Consequently, it can directly
insert into a 50 Ω system without the need for impedance
matching circuitry. In addition, multiple HMC1121 amplifiers
can be cascaded back to back without the need of external
matching circuitry. Similarly, multiple HMC1121 amplifiers
can be used with power dividers at the input and power
combiners at the output to obtain higher output power levels.
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage that no impedance
matching compensation is required.
It is critical to supply very low inductance ground connections
to the ground pins as well as to the backside exposed pad to
ensure stable operation.
To ensure the best performance out of the HMC1121, do not
exceed the absolute maximum ratings.
Rev. A | Page 11 of 15
HMC1121
Data Sheet
APPLICATIONS INFORMATION
Figure 33 shows the basic connections for operating the
HMC1121 and also see the Theory of Operation section for
additional information. The RF input and RF output are accoupled by the internal dc block capacitors.
The bias conditions previously listed (VDDx = 7 V, IDD = 2200 mA),
are the recommended operating point to acheive optimum
performance. The data used in this datasheet is taken with the
recommended bias conditions. When using the HMC1121 with
different bias conditions, different performance may result than
what is shown in the Typical Performance Characteristics
section.
RECOMMENDED BIAS SEQUENCE
Follow the recommended bias sequencing to avoid damaging
the amplifier.
During Power-Up
The recommended bias sequence during power-up is the
following:
1.
2.
3.
4.
5.
The VDET and VREF pins are the output pins for the internal
power detector. The VDET pin is the dc voltage output pin that
represents the RF output power rectified by the internal diode,
which is biased through an external resistor.
Connect to ground.
Set VGGx to −2 V.
Set VDDx to 7 V.
Increase VGGx to achieve a typical IDD = 2200 mA.
Apply the RF signal.
The VREF pin is the dc voltage output pin that represents the
reference diode voltage, which is biased through an external
resistor. This voltage is then used to compensate for the
temperature variation effects on both diodes. A typical circuit
is shown in the Typical Application Circuit section that reads
out the output voltage and represents the RF output power is
shown in Figure 33.
During Power-Down
The recommended bias sequence during power-down is the
following:
1.
2.
Decrease VDDx to 0 V.
Increase VGGx to 0 V.
3.
4.
Turn the RF signal off.
Decrease VGGx to −2 V to achieve a typical IDD = 0 mA.
TYPICAL APPLICATION CIRCUIT
C2
100pF
25 NIC
24 VDET
23 VREF
C7
100pF
C22 + C13
4.7µF
10nF
R3
20Ω
C5
100pF
100kΩ
J2
RFOUT
10kΩ
VOUT = VREF – VDET
10kΩ
10kΩ
–5V
SUGGESTED CIRCUIT
C6
100pF
C13 +
10nF
C8
100pF
C16
10nF
VDD4
C22
4.7µF
VGG4
R4
20Ω
100kΩ
10kΩ
NIC 20
NIC 18
VDD4 19
NIC 16
VGG4 17
NIC 13
VGG3 14
VDD3 15
21 NIC
NIC 12
22 NIC
NIC 10
NIC 11
NIC 9
+5V
+5V
NIC 6
NIC 8
VDD3
28 NIC
27 NIC
26
C15
10nF
VDD2
29 NIC
NIC 4
5
NIC 7
+
C20
4.7µF
31 NIC
HMC1121
NIC 3
C21
4.7µF
C12 +
10nF
VGG2
+
C23
4.7µF
Figure 33. Typical Application Circuit
Rev. A | Page 12 of 15
13529-033
NIC 2
VGG3
+
C19
4.7µF
30 NIC
NIC 1
J1
RFIN
C10
10nF
C4
100pF
R1
20Ω
33 NIC
32 VDD2
+
C1
100pF
R2
20Ω
35 NIC
34 VGG2
C9
10nF
38 NIC
37 VGG1
36 VDD1
C17
4.7µF
C3
100pF
C11
10nF
40 NIC
VGG1
+
C18
4.7µF
39 NIC
VDD1
Data Sheet
HMC1121
EVALUATION BOARD
The HMC1121 evaluation printed circuit board (PCB) is a
2-layer board that was fabricated using a Rogers 4350 and best
practices for high frequency RF design. The RF input and RF
output traces have a 50 Ω characteristic impedance. The PCB is
attached to a heat sink by a SN96 solder, which provides a low
thermal resistance path. Components are mounted using SN63
solder, allowing rework of the surface-mount components
without compromising the circuit board to heat sink
attachment.
The evaluation PCB and populated components operate over
the −40°C to +85°C ambient temperature range. During operation,
attach the evaluation PCB to a temperature controlled plate to
control the temperature. For proper bias sequence, see the
Applications Information section.
13529-034
See Figure 35 for the HMC1121 evaluation board schematic. A
fully populated and tested evaluation board, which is shown in
Figure 34, is available from Analog Devices, Inc., upon request.
Figure 34. HMC1121 Evaluation Board
BILL OF MATERIALS
Table 5.
Item
J1, J2
J3, J4
J5, J6
C1 to C8
C9 to C16
C17 to C24
R1 to R4
R5, R6
U1
Heat sink
PCB
Description
PCB mount SMA RF connector, Johnson PN 142-07010851
DC pins
RF connectors for thru line; not populated
100 pF capacitors, 0402 package
10 nF capacitors, 0402 package
4.7 μF capacitor, Case A
20 Ω resistors, 0402 package
100 kΩ resistors, 0402 package
HMC1121LP6GE
Used for thermal transfer from the HMC1121LP6GE amplifier
600-01061-00 evaluation board; circuit board material: Rogers 4350
Rev. A | Page 13 of 15
HMC1121
Data Sheet
EVALUATION BOARD SCHEMATIC
C18
4.7µF
VG2
+
C11
10nF
C3
100pF
R2
20Ω
C2
100pF
C10
10nF
+
C19
4.7µF
VG1
C1
100pF
RFIN
4 NC
5 RFIN
35
NC
VG2 34
33
NC
VD2 32
31
NC
39
NC
2 NC
3 NC
38
NC
VG1 37
VD1 36
NC
1
J1
C4
100pF
R1
20Ω
40
+
C9
10nF
NC
C17
4.7µF
U1
6 NC
7 NC
VD3
+
C15
10nF
C22 + C13
10nF
4.7µF
C7
100pF
C5
100pF
J3
NC 30
NC 29
NC 28
27
NC
26
RFOUT
25
NC
24
VDET
23
VREF
22
NC
21
NC
VG1
VD1
VG2
VD2
RFOUT
C6
100pF
R3
20Ω
7
5
3
1
87759-0850
J2
VDET
R5
100kΩ
VREF
R6
100kΩ
C14 +
10nF
VD4
C8
100pF
C16
10nF
+
VD4
VG4
VD3
VG3
12
10
8
6
4
2
11
9 VD6
7
5
3
1
87759-1250
C23
4.7µF
Figure 35. HMC1121 Evaluation Board Schematic
Rev. A | Page 14 of 15
VD5
C24
4.7µF
VG4
R4
20Ω
8
6
4
2
J4
VG3
C21
4.7µF
C20
4.7µF
19 VD4
20 NC
16 NC
17 VG4
18 NC
11 NC
12 NC
10 NC
13 NC
14 VG3
15 VD3
8 NC
9 NC
VD2
C12 +
10nF
J6
DEPOP
THRUCAL
J5
DEPOP
13529-035
VD1
Data Sheet
HMC1121
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
0.30
0.25
0.20
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
31
40
1
30
0.50
BSC
4.75
4.70 SQ
4.65
EXPOSED
PAD
21
0.90
0.85
0.80
SIDE VIEW
PKG-004893
SEATING
PLANE
0.35
0.30
0.25
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
10
0.20 MIN
4.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
10-19-2017-A
TOP VIEW
Figure 36. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.85 mm Package Height
(HCP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
HMC1121LP6GE
HMC1121LP6GETR
EV1HMC1121LP6G
Temperature
−40°C to +85°C
−40°C to +85°C
MSL Rating 2
MSL3
MSL3
Package Description 3
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
The HMC1121LP6GE and the HMC1121LP6GETR are RoHS-Compliant Parts.
See the Absolute Maximum Ratings section for additional details.
3
The HMC1121LP6GE and the HMC1121LP6GETR are low stress injection molded plastic and their lead finish is 100% matte Sn.
1
2
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13529-0-10/17(A)
Rev. A | Page 15 of 15
Package Option
HCP-40-1
HCP-40-1
工商网监
湘ICP备2023018690号
