HMC1190LP6GE

HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Typical Applications Features The HMC1190LP6GE is Ideal for: Broadband Operation with no external matching High-side and Low-side LO injection Operation High Input IP3 of +24 dBm Power Conversion Gain of 8.9 dB Input P1dB of 11 dBm SSB Noise Figure of 9 dB 55 dBc Channel-to-Channel Isolation Enable/Disable Mixer and PLLVCO independently Single-ended RF input ports Maximum Phase Detector Rate: 100 MHz Low Phase Noise: -110 dBc/Hz in Band Typical PLL FOM: -230 dBc/Hz Integer Mode, -227 dBc/Hz Fractional Mode < 180 fs Integrated RMS Jitter (1 kHz to 20 MHz) LO Low Noise Floor: -165 dBc/Hz Mixer Low Noise Floor: -161 dBc/Hz Integrated VCO External VCO Input, differential LO output Exact Frequency Mode: 0 Hz Fractional Frequency Error Programmable RF Output Phase Output Phase Synchronous Frequency Changes Output Phase Synchronization LO Output Mute Function Compact Solution, 6x6 mm Leadless QFN Package • MIMO Infrastructure Receivers • Wideband Radio Receivers • Multiband Basestations & Repeaters LE Functional Diagram TE • GSM & 3G & LTE/WiMAX/4G B SO TRANSCEIVERS - Rx RFICs • M  ultiband/Multi-standard Cellular BTS Diversity Receivers General Description O The HMC1190LP6GE is a high linearity broadband dual channel downconverting mixer with integrated PLL and VCO optimized for multi-standard receiver applications that require a compact, low power design. Integrated wideband limiting LO amplifiers enable the HMC1190LP6GE to achieve an unprecedented RF bandwidth of 700 MHz to 3500 MHz for applications including Cellular/3G, LTE/WiMAX/4G. Unlike conventional narrow-band downconverters, the HMC1190LP6GE supports both high-side and low-side LO injection over all RF frequencies. The RF and LO input ports are internally matched to 50 Ohms. The HMC1190LP6GE features an integrated LO and RF baluns, enable control of IF and LO amplifiers and bias control interface to high linearity passive mixer cores. Balanced passive mixer combined with high-linearity IF amplifier architecture provides excellent LO-to-RF, LO-to-IF, and RF-to-IF isolations. Low noise figure of 9 dB, and high IIP3 of +24 dBm allow the HMC1190LP6GE to be used in most demanding applications. External bias control pins enable optimization of already low power dissipation of 2.34 W (typical). Fast enable control interface reduces power consumption further in TDD applications. External VCO input allows the HMC1190LP6GE to lock external VCOs, and enables cascaded LO architectures for MIMO applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase features can further phase adjust and synchronize multiple HMC1190LP6GE’s enabling scalable MIMO and beam-forming radio architectures. Additional features include configurable LO output mute function, Exact Frequency Mode that enables the HMC1190LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing phase of the output signal that increases efficiency of digital pre-distortion loops. The HMC1190LP6GE is housed in RoHS compliant compact 6x6 mm leadless QFN package. 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 Table 1. Electrical Specifications, (Unless Otherwise Specified, the Following Test Conditions Were Used) TA = +25°C, IF Frequency = 150 MHz, LO Power is set to ‘3’ [1], RF Input Power = -5 dBm (-5 dBm / tone for 2-tone IP3 tests, ∆f = 1MHz), LOVDD=3VRVDD=DVDD3V=CHIPEN= 3V, VDDCP=VCS1=VCS2=VBIASIF1=VBIASIF2=LOBIAS1=LOBIAS2=VCC1=VCC2=VGATE1=VGATE2=5V, VGATE = 4.8V. Typical Units Mixer Core RF Input Frequency Range 700 - 3500 MHz Mixer Core IF Output Frequency Range 50 - 350 RF=900 MHz[2] Conversion Gain 9.3 [5] IP3 (Input) 24.5 Noise Figure (SSB) 8.5 1 dB Compression (Input) 10.7 LO leakage @ RF port -67 MHz RF=1900 MHz[3] RF=2200 MHz [3] RF=2700 MHz [3] 8.4 [5] 8.1 [5] 7.1 [5] dB 24 23.5 23.5 dBm TE Parameter 9.2 9.5 10 dB 11.4 11.2 12 dBm -58 dBm -59 -58 40 46 45 52 dB 53 49 48 48 dBc 68 67 70 72 dBc 69 68 74 78 dBc LE RF to IF Isolation Channel to Channel Isolation [4] +2RF-2LO Response +3RF-3LO Response B SO [1] LO Power Level can be adjusted using Reg 16h. [2] High Side LO injection, VGATE1,2 = 5V [3] Low Side LO injection, VGATE1,2 = 4.8V [4] RF1 input power= -5 dBm, measurement taken from IF2 output. RF2 and IF1 ports are terminated with 50 Ohms. TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz [5] Balun losses at IF output ports are de-embedded. Table 2. DC Power Supply Specifications Min. Typ. Max. 5 V Supply Rails (VDDCP, VCS1, VCS2, VDDLS, VBIASIF1, VBIASIF2, LOBIAS1, LOBIAS2, VCC1, VCC2) +4.8 +5 +5.2 VGATE1, VGATE2 +4.5 +5 +5.2 +3.1 +3.3 +3.5 O Parameter 3.3 V Supply Voltage (LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF) Mixer Core Supply Currents when IF1EN and IF2EN are Enabled Units. V mA 348 [1] V V 198 mA VDDIF (5 V) 160 mA VCS1 + VCS2 (5 V) 3.3 4.2 mA VBIASIF1 + VBIASIF2 (5 V) 24 28 mA VGATE1, VGATE2 8 9.2 mA LOBIAS1 + LOBIAS2 (5 V) 4.6 5.6 mA LOVDD (3.3 V) 140 148 mA [1] LO Frequency=2400 MHz, LO_MIX Power and LO_OUT Power set to ‘3’, LO_MIX and LO_OUT is differential and LO_OUT is off. When LO_OUT enabled in differential mode the bias current increases by 34 mA (Typ.) Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 2 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 2. DC Power Supply Specifications Min. LO_OUT differential, LO_MIXER off [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 148 58 mA mA LO_OUT single-ended, LO_MIXER off [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 131 58 mA mA LO_OUT off, LO_MIXER differential [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 148 58 mA mA LO_OUT off, LO_MIXER single-ended [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 131 58 mA mA LO_OUT differential, LO_MIXER differential [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 182 58 mA mA LO_OUT single-ended, LO_MIXER single-ended [1] 5 V Supplies (VDDLS, VCC1, VCC2, VDDCP) 3.3 V Supplies (3VRVDD, DVDD3V, VCCHF, VCCPS, VCCPD) 150 58 mA mA VCCPD, VCCPS, VCCHF, DVDD3V, 3VRVDD (+3.3V) 58 VDDIF (5V) 0 VBIASIF1 + VBIASIF2 (5V) VGATE1 + VGATE2 (5V) LOBIAS1 + LOBIAS2 (5V) PLL/VCO Core Supply Currents when CHIPEN is Disabled Units. mA VCS1 + VCS2 (5V) Mixer Core Supply Currents when IF1EN and IF2EN are Disabled Max. 6 LE PLL/VCO Core Supply Currents when CHIPEN is Enabled Typ. TE Charge Pump (VDDCP, +5 V) +VCCLS B SO TRANSCEIVERS - Rx RFICs Parameter 64 mA mA 4 mA 3.5 mA 4 mA 5.5 mA LOVDD (3.3 V) 4 mA VDDCP, VCC1, VCC2, VDDLS (5V) [1] 3 mA 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF (3.3V) [1] 1 mA O [1] LO Frequency=2400 MHz, LO_MIX and LO_OUT outputs set to maximum gain. 3 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 3. PLL & VCO Specifications Conditions Min. Typ. Max. Units Logic High 1.2 V Logic Low Input Current LO Output Frequency VCO Frequency at PLL Input VCO Fundamental Frequency VCO Output Divider 19-Bit N Divider Range Phase Detector (PD) 1, 2, 4, ... 60, 62 pF 4100 MHz 2000 4100 MHz 2000 4100 MHz 1 62 Integer 16 524287 Fractional 20 524283 Fractional Mode DC 100 MHz Integer Mode DC 100 MHz B SO PD Frequency uA 50 LE VCO Output Divider Range +/- 1 2 LO Output Characteristics PLL RF Divider Characteristics V TE Input Capacitance 0.6 TRANSCEIVERS - Rx RFICs Parameter Logic Inputs Harmonics fo Mode at 4000 MHz 2nd / 3rd / 4th -30/-22/-32 dBc VCO Output Divider VCO RF Divider Range 1,2,4,6,8,... 62 1 62 Max = 219 - 1 16 524,287 Fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 PLL RF Divider Characteristics 19-Bit N-Divider Range (Integer) 19-Bit N-Divider Range (Fractional) REF Input Characteristics Max Ref Input Frequency O Ref Input Voltage AC Coupled 1 2 Ref Input Capacitance 14-\Bit R-Divider Range 1 350 MHz 3.3 Vpp 5 pF 16,383 VCO Open Loop Phase Noise at fo @ 4 GHz 10 kHz Offset -78 dBc/Hz 100 kHz Offset -108 dBc/Hz 1 MHz Offset -134.5 dBc/Hz 10 MHz Offset -156 dBc/Hz 100 MHz Offset -167 dBc/Hz Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 4 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 3. PLL & VCO Specifications Parameter Conditions Min. Typ. Max. Units 10 kHz Offset -83 dBc/Hz -113 dBc/Hz 1 MHz Offset -139.5 dBc/Hz 10 MHz Offset -165.5 dBc/Hz 100 MHz Offset -167 dBc/Hz TE 100 kHz Offset Figure of Merit Floor Integer Mode Normalized to 1 Hz Floor Fractional Mode Normalized to 1 Hz -227 dBc/Hz Flicker (Both Modes) Normalized to 1 Hz -268 dBc/Hz Measured at 2.5 V 15 MHz/V Measured at 2.5 V 14.5 MHz/V Measured at 2.5 V 16.2 MHz/V VCO Tuning Sensitivity at 3862 MHz VCO Tuning Sensitivity at 3643 MHz VCO Tuning Sensitivity at 3491 MHz VCO Tuning Sensitivity at 3044 MHz VCO Tuning Sensitivity at 2558 MHz VCO Tuning Sensitivity at 2129 MHz VCO Supply Pushing -230 LE VCO Characteristics dBc/Hz Measured at 2.5 V 14.6 MHz/V Measured at 2.5 V 15.4 MHz/V Measured at 2.5 V 14.8 MHz/V Measured at 2.5 V 2 MHz/V B SO TRANSCEIVERS - Rx RFICs VCO Open Loop Phase Noise at fo @ 3 GHz/2 = 1.5 GHz Table 4. Enable/Disable Settling Time Specifications Parameter Conditions Min. Typ. Max. Units Mixer Core Enabled 140 ns Disable Settling Time Mixer Core Disabled 110 ns O Enable Settling Time 5 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 1. Conversion Gain vs. VGATE [1] [2] Figure 2. Input IP3 vs. VGATE [1] 29 10 27 8 IIP3(dBm) 6 23 21 4 TE 19 2 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 4.9 V 4.8 V 5.0 V 100 2.3 2.7 3.1 3.5 4.7 V 4.9 V 4.8 V 5 .0V Figure 4. +3RF -3LO Response vs. VGATE[1] B SO 80 50 1.9 100 90 60 1.5 LE 4.7 V Figure 3. +2RF -2LO Response vs. VGATE[1] 70 1.1 FREQUENCY (GHz) FREQUENCY (GHz) +2RF-2LO RESPONSE (dBc) 25 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 90 80 70 60 50 40 0.7 3.5 TRANSCEIVERS - Rx RFICs 31 +3RF-3LO RESPONSE (dBc) CONVERSION GAIN (dB) 12 1.1 1.5 FREQUENCY (GHz) 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) 4.7V 4.9V 4.7V 4.9V 4.8V 5.0V 4.8V 5.0V 20 18 NOISE FIGURE (dB) O Figure 5. Noise Figure vs. VGATE [1] 16 14 12 10 8 6 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) 4.7V 4.9V 4.8V 5.0V [1] VGATE is bias voltage for passive mixer cores (VGATE1 and VGATE2 pins). Refer to pin description table. [2] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 6 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 6. Conversion Gain vs. High Side LO & Low Side LO @ VGATE=4.8V [1] Figure 7. Input IP3 vs. High Side LO & Low Side LO @ VGATE=4.8V 29 10 27 IIP3 (dBm) 8 6 4 25 23 21 TE 19 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 High Side LO 2.7 3.1 3.5 Low Side LO Figure 9. LO Leakage @ VGATE=4.8V -20 60 B SO 50 10 0.7 1.1 1.5 1.9 2.3 2.7 3.1 -40 -60 -80 0.7 3.5 1.1 1.5 +25C +85C O 2.3 2.7 @ RF PORT -40C Figure 10. Conversion Gain vs. LO Drive @ VGATE=4.8V [1] 1.9 3.1 3.5 FREQUENCY (GHz) FREQUENCY (GHz) @ IF PORT Figure 11. LO Drive @ VGATE=4.8V 12 31 29 10 27 8 IIP3(dBm) CONVERSION GAIN (dB) 2.3 LE 70 20 1.9 0 80 30 1.5 High Side LO Low Side LO Figure 8. RF/IF Isolation vs. Temperature @ VGATE=4.8V 40 1.1 FREQUENCY (GHz) FREQUENCY (GHz) LEAKAGE (dBm) CONVERSION GAIN (dB) 31 2 ISOLATION (dB) TRANSCEIVERS - Rx RFICs 12 6 4 25 23 21 19 2 0 0.7 17 1.1 1.5 1.9 2.3 2.7 3.1 3.5 15 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) FREQUENCY (GHz) LO Power Set to 0 LO Power Set to 2 LO Power Set to 0 LO Power Set to 2 LO Power Set to 1 LO Power Set to 3 LO Power Set to 1 LO Power Set to 3 [1] Balun losses at IF output ports are de-embedded. 7 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 13. +3RF -3LO Response vs. LO Drive @ VGATE=4.8V 90 90 +3RF-3LO RESPONSE (dBc) 100 80 70 50 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 70 60 50 40 0.7 3.5 FREQUENCY (GHz) 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) LO Power Set to 0 LO Power Set to 2 LO Power Set to 1 LO Power Set to 3 Figure 14. RF Input Return Loss @ VGATE=4.8V [1] LO Power Set to 0 LO Power Set to 2 LO Power Set to 1 LO Power Set to 3 LE Figure 15. IF Output Return Loss @ VGATE=4.8V [1] 0 0 -5 -10 -15 B SO RETURN LOSS (dB) 80 TE 60 -20 -25 RETURN LOSS (dB) +2RF-2LO RESPONSE (dBc) 100 -5 -10 TRANSCEIVERS - Rx RFICs Figure 12. +2RF -2LO Response vs. LO Drive @ VGATE=4.8V -15 -30 -35 0.1 0.7 1.2 1.8 2.3 2.9 3.4 4 -20 0.1 0.2 0.3 +25 C +85 C 0.4 0.5 0.6 0.7 0.8 0.9 1 FREQUENCY (GHz) FREQUENCY (GHz) +25 C -40 C +85 C -40 C 20 15 P1dB (dBm) O Figure 16. Input P1dB vs. Temperature @ VGATE=4.8V 10 5 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) +25C +85C -40C [1] LO input Frequency = 1700MHz, LO power = 0 dBm. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 8 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 17. Conversion Gain vs. Temperature @ VGATE=5.0V [1] Figure 18. Input IP3 vs. Temperature @ VGATE=5.0V 29 10 27 8 IIP3(dBm) 25 6 23 21 4 TE 19 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 +25C +85C 2.3 2.7 3.1 3.5 +85C -40C Figure 20. +3RF -3LO Response vs. Temperature @ VGATE=5.0V 100 90 B SO 80 50 1.9 LE 100 60 1.5 +25C -40C Figure 19. +2RF -2LO Response vs. Temperature @ VGATE=5.0V 70 1.1 FREQUENCY (GHz) FREQUENCY (GHz) 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 +3RF-3LO RESPONSE (dBc) CONVERSION GAIN (dB) 31 2 +2RF-2LO RESPONSE (dBc) TRANSCEIVERS - Rx RFICs 12 90 80 70 60 50 40 0.7 3.5 1.1 1.5 FREQUENCY (GHz) +25C +85C 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) -40C +25C +85C -40C 20 18 NOISE FIGURE (dB) O Figure 21. Noise Figure vs. Temperature @ VGATE=5.0V 16 14 12 10 8 6 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) +25C +85C -40C [1] Balun losses at IF output ports are de-embedded. 9 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 22. Conversion Gain vs. Temperature @ VGATE=4.9V [1] Figure 23. Input IP3 vs. Temperature @ VGATE=4.9V 29 10 27 8 IIP3(dBm) 6 23 21 4 TE 19 2 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 +25C +85C 2.3 2.7 3.1 3.5 +85C -40C Figure 25. +3RF -3LO Response vs. Temperature @ VGATE=4.9V 100 90 B SO 80 50 1.9 LE 100 60 1.5 +25C -40C Figure 24. +2RF -2LO Response vs. Temperature @ VGATE=4.9V 70 1.1 FREQUENCY (GHz) FREQUENCY (GHz) +2RF-2LO RESPONSE (dBc) 25 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 90 80 70 60 50 40 0.7 3.5 1.1 1.5 FREQUENCY (GHz) +25C +85C TRANSCEIVERS - Rx RFICs 31 +3RF-3LO RESPONSE (dBc) CONVERSION GAIN (dB) 12 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) -40C +25C +85C -40C 20 18 NOISE FIGURE (dB) O Figure 26. Noise Figure vs. Temperature @ VGATE=4.9V 16 14 12 10 8 6 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) +25C +85C -40C [1] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 10 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 27. Conversion Gain vs. Temperature @ VGATE=4.8V [1] Figure 28. Input IP3 vs. Temperature @ VGATE=4.8V 29 10 27 8 IIP3(dBm) 25 6 23 21 4 TE 19 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 +25C +85C 2.3 2.7 3.1 3.5 +85C -40C Figure 30. +3RF -3LO Response vs. Temperature @ VGATE=4.8V 100 90 B SO 80 50 1.9 LE 100 60 1.5 +25C -40C Figure 29. +2RF -2LO Response vs. Temperature @ VGATE=4.8V 70 1.1 FREQUENCY (GHz) FREQUENCY (GHz) 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 +3RF-3LO RESPONSE (dBc) CONVERSION GAIN (dB) 31 2 +2RF-2LO RESPONSE (dBc) TRANSCEIVERS - Rx RFICs 12 90 80 70 60 50 40 0.7 3.5 1.1 1.5 FREQUENCY (GHz) +25C +85C 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) -40C +25C +85C -40C 20 18 NOISE FIGURE (dB) O Figure 31. Noise Figure vs. Temperature @ VGATE=4.8V 16 14 12 10 8 6 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) +25C +85C -40C [1] Balun losses at IF output ports are de-embedded. 11 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 32. Conversion Gain vs. Temperature @ VGATE=4.7V [1] Figure 33. Input IP3 vs. Temperature @ VGATE=4.7V 29 10 27 8 IIP3(dBm) 6 23 21 4 TE 19 2 17 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 15 0.7 3.5 +25C +85C 2.3 2.7 3.1 3.5 +85C -40C Figure 35. +3RF -3LO Response vs. Temperature @ VGATE=4.7V 100 90 B SO 80 50 1.9 LE 100 60 1.5 +25C -40C Figure 34. +2RF -2LO Response vs. Temperature @ VGATE=4.7V 70 1.1 FREQUENCY (GHz) FREQUENCY (GHz) +2RF-2LO RESPONSE (dBc) 25 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 90 80 70 60 50 40 0.7 3.5 1.1 1.5 FREQUENCY (GHz) +25C +85C TRANSCEIVERS - Rx RFICs 31 +3RF-3LO RESPONSE (dBc) CONVERSION GAIN (dB) 12 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) -40C +25C +85C -40C 20 18 NOISE FIGURE (dB) O Figure 36. Noise Figure vs. Temperature @ VGATE=4.7V 16 14 12 10 8 6 4 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) +25C +85C -40C [1] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 12 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 60 65 55 ISOLATION (dB) 70 60 55 50 45 40 TE 50 35 40 0.7 1.1 1.5 1.9 2.3 2.7 3.1 30 0.7 3.5 FREQUENCY (GHz) 1.1 1.5 2.3 2.7 3.1 3.5 4.9 V 5.0 V IF=50MHz IF=100MHz IF=150MHz IF=200MHz IF=250MHz IF=300MHz IF=350MHz LE 4.7 V 4.8 V Figure 39. Conversion Gain, Channel Matching @ VGATE=4.8V [1] 12 Figure 40. Input IP3, Channel Matching @ VGATE=4.8V 31 29 10 6 4 B SO 27 8 2 0 0.7 1.1 1.5 1.9 2.3 2.7 3.1 25 23 21 19 17 15 0.7 3.5 1.1 1.5 CHANNEL 1 2.3 2.7 CHANNEL 1 CHANNEL 2 3.1 3.5 CHANNEL 2 Figure 42. Input IP3 vs. Vdd @ VGATE=4.8V O Figure 41. Conversion Gain vs. Vdd @ VGATE=4.8V [1] 1.9 FREQUENCY (GHz) FREQUENCY (GHz) 12 31 29 10 27 8 IIP3(dBm) CONVERSION GAIN (dB) 1.9 FREQUENCY (GHz) IIP3(dBm) ISOLATION (dB) Figure 38. Channel to Channel Isolation vs. IF Frequency 45 CONVERSION GAIN (dB) TRANSCEIVERS - Rx RFICs Figure 37. Channel to Channel Isolation vs. VGATE 6 4 25 23 21 19 2 0 0.7 17 1.1 1.5 1.9 2.3 2.7 FREQUENCY (GHz) VDD_IF=4.75V, VDD_LO=2.85V VDD_IF=5.00V, VDD_LO=3.00V VDD_IF=5.25V, VDD_LO=3.45V 3.1 3.5 15 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) VDD_IF=4.75V, VDD_LO=2.85V VDD_IF=5.00V, VDD_LO=3.00V VDD_IF=5.25V, VDD_LO=3.45V [1] Balun losses at IF output ports are de-embedded. 13 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 43. Conversion Gain vs. IF Frequency @ LO=850 MHz, VGATE=4.8V [1] Figure 44. IIP3 vs. IF Frequency @ LO=850 MHz, VGATE=4.8V 29 10 27 IIP3(dBm) 8 6 4 23 21 TE 19 2 17 15 0 0 100 200 300 400 500 600 700 100 200 300 400 500 600 700 +85C +25C -40C +85C -40C LE +25C 0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 45. Conversion Gain vs. IF Frequency @ LO=1800 MHz, VGATE=4.8V [1] 12 Figure 46. IIP3 vs. IF Frequency @ LO=1800 MHz, VGATE=4.8V 31 29 10 27 8 B SO CONVERSION GAIN (dB) 25 6 4 2 0 0 100 200 300 400 500 600 700 25 23 21 19 17 15 0 100 200 -40C 400 500 600 700 +25C +85C -40C O +85C 300 FREQUENCY (MHz) FREQUENCY (MHz) +25C TRANSCEIVERS - Rx RFICs 31 IIP3(dBm) CONVERSION GAIN (dB) 12 [1] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 14 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 48. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @3600 MHz with various divider ratios [1] Figure 47. Auxiliary LO Output, Open Loop Phase Noise @ 3600 MHz -80 -100 PHASE NOISE(dBc/Hz) PHASE NOISE(dBc/Hz) -60 -80 -120 -100 -120 -140 -140 TE -160 -160 -180 -180 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET (KHz) OFFSET (KHz) Div1 Div2 Div4 Div8 Div16 Div32 Div62 LE Figure 50. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @4100 MHz with various divider ratios [1] Figure 49. Auxiliary LO Output, Open Loop Phase Noise @ 4100 MHz -40 -80 -60 PHASE NOISE(dBc/Hz) -100 -80 -120 -100 -120 -140 -160 -180 1 B SO PHASE NOISE(dBc/Hz) TRANSCEIVERS - Rx RFICs -40 10 100 1000 10000 100000 -140 -160 -180 1 10 100 10000 100000 Div1 Div2 Div4 Div8 Div16 Div32 Div62 Figure 51. Auxiliary LO Output, Fractional Mode Closed Loop Phase Noise @ 3300 MHz with various divider ratios [2] -80 -100 PHASE NOISE(dBc/Hz) O 1000 OFFSET (KHz) OFFSET (KHz) -120 -140 -160 -180 1 10 100 1000 10000 100000 OFFSET (KHz) Div1 Div2 Div4 Div8 Div16 Div32 Div62 [1] Using 122.88 MHz clock input, 61.44 MHz PFD, 2.5 mA CP, 174 uA Leakage. [2] Using 100 MHz clock input, 50MHz PFD, 2.5 mA CP, 174 uA Leakage 15 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz -40 -100 -60 -110 PHASE NOISE (dBc/Hz) -80 -100 -120 -160 1 MHz Offset -140 -150 -160 -170 -180 100 MHz Offset -180 1 10 100 1000 10000 100000 30 3044 MHz 2558 MHz 2129.4 MHz 27 C Figure 54. Auxiliary LO Output Power vs Temperature [1] 10 100 85C 0.15 0.1 0.05 0 0 500 1000 2000 -40 C 2500 3000 3500 4000 27 C 85 C Figure 57. Reference Input Sensitivity, Square Wave, 50 Ω [3] O -220 -222 60 -224 50 FOM (dBc/Hz) KVCO (MHz/V) 1500 OUTPUT FREQUENCY (MHz) -40C Figure 56. Typical VCO Sensitivity 40 30 -226 -228 -230 20 -232 10 0 -40 C 0.2 1000 27C 70 85 C 0.25 OUTPUT FREQUENCY (MHz) 80 4000 Figure 55. Integrated RMS Jitter [2] B SO 5 -10 1000 0.3 15 -5 300 LE 3862.4 MHz 3643.33 MHz 3491.74 MHz 0 100 FREQUENCY (MHz) OFFSET (KHz) OUTPUT POWER (dBm) -130 TE -140 100 kHz Offset -120 TRANSCEIVERS - Rx RFICs Figure 53. Auxiliary LO Output, Open Loop Phase Noise vs. Temperature INTEGRATED JITTER (ps) PHASE NOISE(dBc/Hz) Figure 52. Auxiliary LO Output, Open Loop Phase Noise vs. Frequency 0 1 2 3 4 5 TUNING VOLTAGE (V) ML core, Tuning Cap 15 H core, Tuning Cap 7 MH core, Tuning Cap 7 CL core, Tuning Cap 15 L core, Tuning Cap 15 CH core, Tuning Cap 15 -234 -15 -12 -9 -6 -3 0 3 REFERENCE POWER (dBm) 14 MHz Square Wave 25 MHz Square Wave 50 MHz Square Wave 100 MHz Square Wave [1] Both Aux. LO and MOD LO Gain Set to ‘3’ (Max Level), both Aux. LO and MOD LO Buffer Enabled, measured from Auxiliary LO Port. [2] RMS Jitter data is measured in fractional mode using 50 MHz reference frequency, from 1 kHz to 100 MHz integration bandwidth. [3] Measured from a 50 Ω source with a 100 Ω external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 16 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 58. Reference Input Sensitivity, Sinusoid Wave, 50 Ω [1] Figure 59. Figure of Merit for PLL/VCO -200 NORMALIZED PHASE NOISE (dBc/Hz) -205 -215 -220 -230 -15 -10 -5 0 5 FOM Floor FOM 1/f Noise -230 10 10 4 10 5 10 6 50 MHz sin 100 MHz sin Figure 60. Fractional-N Spurious Performance @ 2646.96 MHz Exact Frequency Mode ON [2] -40 Figure 61. Fractional-N Spurious Performance @ 2646.96 MHz Exact Frequency Mode OFF [2] LE 14 MHz sin 25 MHz sin -40 -60 -60 -120 -140 -160 1 B SO -80 -100 10 100 1000 10000 100000 -80 -100 -120 -140 -160 -180 1 10 100 OFFSET (KHz) O Figure 62. Forward Transmission Gain [3] 10000 100000 Figure 63. Closed Loop Phase Noise With External VCO HMC384LP4E @ 2200 MHz -40 20 S21 EXT-IN LO OUT DIFFERENTIAL OUTPUT 15 1000 OFFSET (KHz) -60 PHASE NOISE(dBc/Hz) FORWARD TRANMISSION GAIN (dB) 3 OFFSET (Hz) REFERENCE POWER (dBm) -180 Typ FOM vs Offset -220 -240 2 10 -235 -20 -210 TE -225 PHASE NOISE(dBc/Hz) FOM (dBc/Hz) -210 PHASE NOISE(dBc/Hz) TRANSCEIVERS - Rx RFICs -200 -80 -100 10 -120 5 -140 0 S21 EXT-IN LO OUT SINGLE-ENDED OUTPUT -160 -180 -5 400 800 1200 1600 2000 OUTPUT FREQUENCY (MHz) 2400 2800 1 10 100 1000 10000 OFFSET (KHz) [1] Measured from a 50 Ω source with a 100 Ω external resistor termination. See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details. Full FOM performance up to maximum 3.3 Vpp input voltage. [2] 122.88 MHz clock input, PFD = 61.44 MHz, Channel Spacing = 240 KHz. [3] S21 from Ext_VCO (pin 43, 44) in and LO (pin32, 33) out. 17 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 0 0 -5 -5 -10 -15 -15 -20 TE -20 -10 -25 -25 -30 -30 100 1000 100 1000 OUTPUT FREQUENCY (MHz) B SO LE OUTPUT FREQUENCY (MHz) TRANSCEIVERS - Rx RFICs Figure 65. Auxiliary LO Single Ended Output Return Loss RETURN LOSS (dB) RETURN LOSS (dB) Figure 64. Auxiliary LO Differential Output Return Loss Table 5. Loop Filter Configuration C1 (pF) C2 (nF) O Loop Filter BW (kHz) 156 180 6.8 C3 (pF) C4 (pF) R2 (kΩ) R3 (kΩ) R4 (kΩ) 47 47 2.2 1 1 Loop Filter Design Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 18 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 6. Harmonics of LO Table 7. MxN Spurious @ IF Port nLO 1 2 3 4 mRF 0 1 2 3 4 0.7 -65 -45 -67 -63 0 xx -44 -52 -52 -55 1.1 -80 -55 -64 -67 1 -49 0 -44 -17 -52 1.5 -59 -58 -65 -62 2 -87 -45 -72 -50 -80 1.9 -59 -54 -72 -64 3 -88 -62 -88 -71 -87 2.3 -60 -59 -73 -63 4 -85 -85 -88 -88 -87 2.7 -59 -58 -82 -55 3.1 -60 -58 -77 -48 3.5 -53 -63 -73 -48 TE LO Freq. (GHz) RF Freq. = 0.9 GHz @-5 dBm LO Freq. = 0.8 GHz @ Max. level All values in dBc below IF power level (1RF - 1LO). Table 8. MxN Spurious @ IF Port nLO mRF 0 1 2 3 0 xxx -44 -49 -64 1 2 3 4 LE LO = Max. level All values in dBm measured at RF port. Table 9. MxN Spurious @ IF Port -54 0 -43 -83 -49 -87 -72 -83 -83 -85 mRF 0 1 2 3 4 -49 0 xxx -44 -47 -65 -53 1 -58 0 -46 -40 -68 -28 -65 -76 -57 -84 2 -80 -60 -75 -67 -85 -86 -88 -85 3 -82 -82 -86 -83 -85 -85 -87 4 -84 -82 -85 -85 -87 RF Freq. = 1.9 GHz @-5 dBm LO Freq. = 1.8 GHz @ Max. level All values in dBc below IF power level (1RF - 1LO). O nLO 4 B SO TRANSCEIVERS - Rx RFICs nLO Spur @ RF Port RF Freq. = 2.5 GHz @-5 dBm LO Freq. = 2.4 GHz @Max. level All values in dBc below IF power level (1RF - 1LO). Table 10. Truth Table [1] CHIPEN (V) PLL/VCO LOW OFF HIGH ON [1] IF and LO amplifiers can be disabled through SPI bus. See `Enabling/Disabling Mixer Features` application section. 19 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz +20 dBm VBIASIF1,2, LOVDD 6V VGATE1,2, VDDCP, VCS1, VCS2, LOVDD -0.3V to +5.5V 3VRVDD, DVDD3V -0.3V to +3.6V Max. Channel Temperature 150°C Thermal Resistance (channel to ground paddle) 3.3°C/W -65 to 150°C -40 to +85°C ESD Sensitivity (HBM) Class 1B 5.0 V LOVDD, 3VRVDD, DVDD3V, VCCPD, VCCPS, VCCHF +3.3 V Operating Temperature -40 to +85°C LE Storage Temperature Operating Temperature VDDCP, VCS1, VCS2, VBIASIF1, VBIASIF2,LOBIAS1,LOBIAS2,VCC1,VCC2,VGATE1,VGATE2,VDDLS B SO Outline Drawing TRANSCEIVERS - Rx RFICs RF Input Power (VBIASIF1,2= +5V, LOVDD=3.0V) Table 12. Recommended Operating Conditions TE Table 11. Absolute Maximum Ratings O NOTES: 1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. 2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. 3. LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN 4. DIMENSIONS ARE IN INCHES [MILLIMETERS]. 5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE. 6. CHARACTERS TO BE HELVETICA MEDIUM, .025 HIGH, WHITE INK, OR LASER MARK LOCATED APPROX. AS SHOWN. 7. P  AD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.05mm MAX. 8. PACKAGE WARP SHALL NOT EXCEED 0.05mm 9. A  LL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. 10. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. Package Information Part Number Package Body Material Lead Finish MSL Rating [2] Package Marking [1] HMC1190LP6GE RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn MSL1 H1190 XXX [1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260 °C Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 20 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Function 1 VDDCP Power Supply for charge pump analog section. 2 BIAS External bypass decoupling for precision bias circuits. 3,4 CP1,CP2 Charge Pump Outputs. 5 3VRVDD Reference supply, 3.3 V nominal. 6 XREFP Reference Input. DC bias is generated internally. Normally AC coupled externally. 7 DVDD3V DC Power Supply for Digital (CMOS) Circuitry, 3.3 V nominal. 8,23 VCS1, VCS2 Bias control pins for IF amplifiers. Connect to 5V supply through 590 Ohms resistors. Refer to application section for proper values of resistors to adjust IF amplifier current. 9 IF1_N 10 IF1_P 21 IF2_P 21 Description TE Pin Number Differential IF outputs. Connect to 5V supply through choke inductors. See application circuit. IF2_N 11, 20 VBIASIF1, VBIASIF2 12, 19 VGATE1, VGAET2 Bias pins for mixer cores. Set from 4.7V to 5.0V for operating frequency band. 13, 18 RF1, RF2 RF input pins of the mixer, internally matched to 50 Ohms. RF input pins require off chip DC blocking capacitors. See application circuit. 14, 17 LO_BIAS2, LO_BIAS1 Bias control pins for LO Amplifiers. Connect to 5V supply through 270 Ohms resistors. Refer to application section for proper values of resistors to adjust LO amplifier current. 15,24 RSV Reserved for internal use.Should be left floating. 16 LOVDD 3V bias supply for LO Drive stages. Refer to application circuit for appropriate filtering and bias generation information. LE 22 B SO Supply voltage pin for IF amplifier’s bias circuits. Connect to 5V supply through filtering. 25 CHIP_EN Chip Enable. Connect to logic high for normal operation. 26 LON Negative LO output used for single-ended, differential, or dual output mode. 27 LOP Positive LO output used for differential or dual outputs only. While it can drive a separate load from LO_N, it cannot be used when LO_N is disabled. 28 VCC1 VCO Analog supply1, 5.0V nominal. 29 VCC2 VCO Analog Supply 2, 5.0V nominal. 30 VTUNE VCO Varactor. Tuning Port Input. 31 SEN PLL Serial Port Enable (CMOS) Logic Input. 32 SDI PLL Serial Port Data (CMOS) Logic Input. O TRANSCEIVERS - Rx RFICs Table 13. Pin Descriptions 33 SCK PLL Serial Port Clock (CMOS) Logic Input. 34 LD/SDO Lock Detect, or Serial Data, or General Purpose (CMOS) Logic Output (GPO). 35 EXT_VC0_N External VCO negative input 36 EXT_VCO_P External VCO positive input. 37 VCCHF Analog supply, 3.3 V nominal 38 VCCPS Analog supply, Prescaler, 3.3 V nominal 39 VCCPD Analog supply, Phase Detector, 3.3 V nominal 40 VDDLS Analog supply, Charge Pump, 5.0 V nominal Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz TRANSCEIVERS - Rx RFICs B SO LE TE Evaluation PCB The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. Evaluation PCB Schematic O To view this Evaluation PCB Schematic please visit www.hittite.com and choose HMC1190LP6GE from the “Search by Part Number” pull down menu to view the product splash page. Table 14. Evaluation Order Information Item Contents Part Number Evaluation PCB Only HMC1190LP6GE Evaluation PCB Eval01-HMC1190LP6G [1] Evaluation Kit HMC1190LP6GE Evaluation PCB USB Interface Board 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software, Hittite PLL Design Software) EKIT01-HMC1190LP6G [2] [1] Reference this number when ordering Evaluation PCB Only [2] Reference this number when ordering an HMC1190LP6GE Evaluation KIt Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 22 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 1.0 Theory of Operation LE TE TRANSCEIVERS - Rx RFICs The block diagram of HMC1190LP6GE PLL with Integrated VCO is shown in Figure 66 1.1 B SO Figure 66. HMC1190LP6GE PLL VCO Block Diagram PLL Overview O The PLL divides down the VCO output to the desired comparison frequency via the N-divider (integer value set in Reg 03h, fractional value set in Reg 04h), compares the divided VCO signal to the divided reference signal (reference divider set in Reg 02h) in the Phase Detector (PD), and drives the VCO tuning voltage via the Charge Pump (CP) (configured in Reg 09h) to the VCO subsystem. Some of the additional PLL subsystem functions include: • Delta Sigma configuration (Reg 06h) • Exact Frequency Mode (Configured in Reg 0Ch, Reg 06h,Reg 03h, and Reg 04h) • Lock Detect (LD) Configuration (Reg 07h to configure LD, and Reg 0Fh to configure LD_SDO output pin) • External CEN pin used as hardware enable pin. Typically, only writes to the divider registers (integer part Reg 03h, fractional part Reg 04h,VCO Divide Ratio part Reg 04h) are required for HMC1190LP6GE output frequency changes. Divider registers of the PLL (Reg 03h, and Reg 04h), set the fundamental frequency (2050 MHz to 4100 MHz) of the VCO. Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the appropriate fundamental VCO frequency (2050 MHz to 4100 MHz) by programming N divider (Reg 03h, and Reg 04h), and programming the output divider (divide by 1/2/4/6.../60/62, programmed in Reg 16h) in the VCO register. For detailed frequency tuning information and example, please see “1.3.7 Frequency Tuning” section. 23 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz VCO Overview The VCO consists of a capacitor switched step tuned VCO and an output stage. In typical operation, the VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL AutoCal state machine if AutoCal is enabled (Reg 0Ah[11] = 0, see section “1.2.1 VCO Calibration” for more information). The VCO tunes to the fundamental frequency (2050 MHz to 4100 MHz), and is locked by the CP output from the PLL subsystem. The VCO controls the output stage of the HMC1190LP6GE enabling configuration of: 1.2.1 • Mute when unlock (Reg 17h[7]) VCO Calibration TE • • • VCO Output divider settings configured in Reg 16h (divide by 2/4/6...60/62 to generate frequencies from 33 MHz to 2050 MHz, or divide by 1 to generate fundamental frequencies between 2050 MHz and 4100 MHz) Output gain settings (Reg 16h[7:6], Reg 16h[9:8]) Single-ended or differential output operation (Reg 17h[9:8]) Always Mute (Reg 16h[5:0]) LE • 1.2.1.1 VCO Auto-Calibration (AutoCal) B SO The HMC1190LP6GE uses a step tuned type VCO. A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or ‘stepped’ by switching in/out VCO tank capacitors. A step tuned VCO allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the HMC1190LP6GE’s charge pump. This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). TRANSCEIVERS - Rx RFICs 1.2 The VCO switches are normally controlled automatically by the HMC1190LP6GE using the Auto-Calibration feature. The Auto-Calibration feature is implemented in the internal state machine. It manages the selection of the VCO sub-band (capacitor selection) when a new frequency is programmed. The VCO switches may also be controlled directly via register Reg 15h for testing or for other special purpose operation. O To use a step tuned VCO in a closed loop, the VCO must be calibrated such that the HMC1190LP6GE knows which switch position on the VCO is optimum for the desired output frequency. The HMC1190LP6GE supports Auto-Calibration (AutoCal) of the step tuned VCO. The AutoCal fixes the VCO tuning voltage at the optimum mid-point of the charge pump output, then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency. This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor. A typical tuning curve for a step tuned VCO is shown in Figure 67.Note how the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency hopping. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 24 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 3 2 1 fmin fmax 0 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 TE TUNE VOLTAGE AFTER CALIBRATION (V) 4 VCO FREQUENCY(MHz) Calibrated at 85C, Measured at 85C Calibrated at 85C, Measured at -40C Calibrated at -40C, Measured at -40C Calibrated at -40C, Measured at 85C Calibrated at 27C, Measured at 27C Figure 67.Typical VCO Tuning Voltage After Calibration LE The calibration is normally run automatically once for every change of frequency. This ensures optimum selection of VCO switch settings vs. time and temperature. The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine. The accuracy required in the calibration affects the amount of time required to tune the VCO. The calibration routine searches for the best step setting that locks the VCO at the current programmed frequency, and ensures that the VCO will stay locked and perform well over it’s full temperature range without additional calibration, regardless of the temperature that the VCO was calibrated at. Auto-Calibration can also be disabled allowing manual VCO tuning. Refer to section 1.2.1.5 for a description of manual tuning. B SO TRANSCEIVERS - Rx RFICs 5 1.2.1.2 Auto-reLock on Lock Detect Failure It is possible by setting Reg 0Ah[17] to have the VCO subsystem automatically re-run the calibration routine and re-lock itself if Lock Detect indicates an unlocked condition for any reason. With this option the system will attempt to re-Lock only once. 1.2.1.3 VCO AutoCal on Frequency Change O Assuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change is requested. If it is desired to rerun the AutoCal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency. 1.2.1.4 VCO AutoCal Time & Accuracy The VCO frequency is counted for Tmmt, the period of a single AutoCal measurement cycle. n Tmmt = Txtal · R · 2 (EQ 1) n is set by Reg 0Ah[2:0] and results in measurement periods which are multiples of the PD period, TxtalR. R is the reference path division ratio currently in use, Reg 02h Txtal is the period of the external reference (crystal) oscillator. The VCO AutoCal counter will, on average, expect to register N counts, rounded down (floor) to the nearest integer, every PD cycle. N 25 is the ratio of the target VCO frequency, fvco, to the frequency of the PD, fpd, where N can Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz be any rational number supported by the N divider. N is set by the integer (Nint = Reg 03h) and fractional (Nfrac = Reg 04h) register contents 24 (EQ 2) The AutoCal state machine runs at the rate of the FSM clock, TFSM, where the FSM clock frequency cannot be greater than 50 MHz. m TFSM = Txtal · 2 m (EQ 3) is 0, 2, 4 or 5 as determined by Reg 0Ah[14:13] TE The expected number of VCO counts, V, is given by n V = floor (N · 2 ) (EQ 4) The nominal VCO frequency measured, fvcom, is given by n fvcom = V · fxtal / (2 · R) LE where the worst case measurement error, ferr , is: n+1 B SO ferr ≈ ±fpd / 2 (EQ 5) (EQ 6) TRANSCEIVERS - Rx RFICs N = Nint + Nfrac / 2 Figure 68. VCO Calibration A 5-bit step tuned VCO, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 VSPI data transfers of 20 clock cycles each. Total calibration time, worst case, is given by: n Tcal = k128TFSM + 6TPD 2 + 7 · 20TFSM (EQ 7) O or equivalently n m Tcal = Txtal (6R · 2 + (140+(3 · 128)) · 2 ) (EQ 8) For guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8th the frequency step caused by a VCO sub-band switch change. Better resolution settings will show no improvement. 1.2.1.4.1 VCO AutoCal Example The HMC1190LP6GE must satisfy the maximum fpd limited by the two following conditions: a. N ≥ 16 (fint), N ≥ 20.0 (ffrac), where N = f VCO/ fpd b. fpd ≤ 100 MHz Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 26 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz TRANSCEIVERS - Rx RFICs Suppose the HMC1190LP6GE output frequency is to operate at 2.01 GHz. Our example crystal frequency is fxtal = 50 MHz, R=1, and m=0 (Figure 68), hence TFSM = 20 ns (50 MHz). Note, when using AutoCal, the maximum AutoCal Finite State Machine (FSM) clock cannot exceed 50 MHz (see Reg 0Ah[14:13]). The FSM clock does not affect the accuracy of the measurement, it only affects the time to produce the result. This same clock is used to clock the 16 bit VCO serial port. If time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. TE Using an input crystal of 50 MHz (R=1 and fpd=50 MHz) the times and accuracies for calibration using (EQ 6) and (EQ 8) are shown in Table 15 Where minimal tuning time is 1/8th of the VCO band spacing. Across all VCOs, a measurement resolution better than 800 kHz will produce correct results. Setting m = 0, n = 5, provides 781 kHz of resolution and adds 8.6 µs of AutoCal time to a normal frequency hop. Once the AutoCal sets the final switch value, 8.64 µs after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. Hence as shown in this example that AutoCal typically adds about 8.6 µs to the normal time to achieve frequency lock. Hence, AutoCal should be used for all but the most extreme frequency hopping requirements. Control Value Reg0Ah[2:0] n 0 0 1 2 3 3 4 5 6 7 2n Tmmt (µs) Tcal (µs) Ferr Max 1 0.02 4.92 ± 25 MHz 2 0.04 5.04 ± 12.5 MHz 4 0.08 5.28 ± 6.25 MHz 8 0.16 5.76 ± 3.125 MHz 5 32 0.64 8.64 ± 781 kHz 6 64 1.28 12.48 ± 390 kHz 7 128 2.56 20.16 ± 195 kHz 8 256 5.12 35.52 ± 98 kHz B SO 1 2 LE Table 15. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0 1.2.1.5 Manual VCO Calibration for Fast Frequency Hopping O If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host. This can be done by initially locking the HMC1190LP6GE on each desired frequency using AutoCal, then reading, and storing the selected VCO switch settings. The VCO switch settings are available in Reg 15h[8:1] after every AutoCal operation. The host must then program the VCO switch settings directly when changing frequencies. Manual writes to the VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled. Hence frequency changes with manual control and AutoCal disabled, requires a minimum of two serial port transfers to the HMC1190LP6GE, once to set the VCO switches, and once to set the PLL frequency. If AutoCal is disabled Reg 0Ah[11]=1, the VCO will update its registers with the value written via Reg 15h[8:1] immediately. 1.2.2 Registers required for Frequency Changes in Fractional Mode A large change of frequency, in fractional mode (Reg 06h[11]=1), may require Main Serial Port writes to: 1. The integer register intg, Reg 03h (only required if the integer part changes) 2. Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal disabled) 27 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 1.2.3 TE 3. VCO Divide Ratio and Gain Register • Reg 16h[5:0] is required to change the VCO Output Divider value if needed. • Reg 16h[10:6] is required to change the Output Gain if needed. 4. The fractional register, Reg 04h. The fractional register write triggers AutoCal if Reg 0Ah[11]=0, and is loaded into the Delta Sigma modulator automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the fractional frequency change is loaded into the Delta Sigma modulator immediately when the register is written with no adjustment to the VCO. Small steps in frequency in fractional mode, with AutoCal enabled (Reg 0Ah[11]=0), usually only require a single write to the fractional register. Worst case, 3 Main Serial Port transfers to the HMC1190LP6GE could be required to change frequencies in fractional mode. If the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. In all cases, in fractional mode, it is necessary to write to the fractional register Reg 04h for frequency changes. Registers Required for Frequency Changes in Integer Mode A change of frequency, in integer mode (Reg 06h[11]=0), requires Main Serial Port writes to: 1.2.4 B SO LE 1. VCO register • Reg 15h only required for manual control of VCO if Reg 0Ah[11]=1 (AutoCal disabled) • Reg 16h is required to change the VCO Output Divider value if needed 2. The integer register Reg 03h. • In integer mode, an integer register write triggers AutoCal if Reg 0Ah[11]=0, and is loaded into the prescaler automatically after AutoCal runs. If AutoCal is disabled, Reg 0Ah[11]=1, the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the VCO. Normally changes to the integer register cause large steps in the VCO frequency, hence the VCO switch settings must be adjusted. AutoCal enabled is the recommended method for integer mode frequency changes. If AutoCal is disabled (Reg 0Ah[11]=1), a prior knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change. TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz VCO Output Mute Function The HMC1190LP6GE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional. The mute function is automatically controlled by the HMC1190LP6GE, and provides a number of mute control options including: 1. Always mute (Reg 16h[5:0] = 0d). This mode is used for manual mute control. O 2. Automatically mute the outputs during VCO calibration (Reg 17h[7] = 1) that occurs during output frequency changes. This mode can be useful in eliminating any out of band emissions during freqeuncy changes, and ensuring that the system emits only desired frequencies. It is enabled by writing Reg 17h[7] = 1. Typical isolation when the HMC1190LP6GE is muted is always better than 60 dB, and is ~ 30 dB better than disabling the output buffers of the HMC1190LP6GE via Reg 17h[5:4]. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 28 HMC1190LP6GE v06.1113 2.1 PLL Overview 2.1.1 Charge Pump (CP) & Phase Detector (PD) The Phase detector (PD) has two inputs, one from the reference path divider and one from the RF path divider. When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other. We refer to the frequency of operation of the PD as fpd. Most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the PD, fpd. fpd is also referred to as the comparison frequency of the PD. TE The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. The output current varies linearly over a full ±2π radians (±360°) of input phase difference. 2.1.1.1 Charge Pump LE A simplified diagram of the charge pump is shown in Figure 69. The CP consists of 4 programmable current sources, two controlling the CP Gain (Up Gain Reg 09h[13:7], and Down Gain Reg 09h[6:0]) and two controlling the CP Offset, where the magnitude of the offset is set by Reg 09h [20:14], and the direction is selected by Reg 09h [21]=1 for up and Reg 09h [22]=1 for down offset. B SO CP Gain is used at all times, while CP Offset is only recommended for fractional mode of operation. Typically the CP Up and Down gain settings are set to the same value (Reg 09h[13:7] = Reg 09h[6:0]). O TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 69. Charge Pump Gain & Offset Control 2.1.1.1.1 Charge Pump Gain Charge pump Up and Down gains are set by Reg 09h[13:7] and Reg 09h[6:0] respectively. The current gain of the pump in Amps/radian is equal to the gain setting of this register divided by 2π. Typical CP gain setting is set to 2 to 2.5 mA, however lower values can also be used. Values < 1 mA may result in degraded Phase Noise performance. For example, if both Reg 09h[13:7] and Reg 09h[6:0] are set to ‘50d’ the output current of each pump will be 1 mA and the phase frequency detector gain kp = 1 mA/2π radians, or 159 µA/rad. 29 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz In Integer Mode, the phase detector operates with zero offset. The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time. Integer mode does not require any CP Offset current. When operating in Integer Mode simply disable CP offset in both directions (Up and down), by writing Reg 09h[22:21] = ‘00’b and set the CP Offset magnitude to zero by writing Reg 09h[20:14]= 0. In Fractional Mode CP linearity is of paramount importance. Any non-linearity degrades phase noise and spurious performance. TE In fractional mode, these non-linearities are eliminated by operating the PD with an average phase offset, either positive or negative (either the reference or the VCO edge always arrives first at the PD ie. leads). A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset. Positive current causes the VCO to lead, negative current causes the reference to lead. The CP offset is controlled via Reg 09h[20:14]. The phase offset is scaled from 0 degrees, that is the reference and the VCO path arrive in phase, to 360 degrees, where they arrive a full cycle late. LE The specific level of charge pump offset current Reg 09h[20:14] is provided in (EQ 9). It is also plotted in Figure 70 vs. PD frequency for typical CP Gain currents. ( ) (EQ 9) Required CP Offset = min  4.3 × 10−9 × FPD × ICP ,0.25 × ICP    B SO where: FPD: Comparison frequency of the Phase Detector (Hz) ICP: is the full scale current setting (A) of the switching charge pump (set in Reg 09h[6:0], [13:7] TRANSCEIVERS - Rx RFICs 2.1.1.1.2 Charge Pump Phase Offset O RECOMMENDED OFFSET CURRENT (uA) 700 CP Current = 2.5 mA 600 500 400 CP Current = 2 mA 300 200 CP Current = 1 mA 100 0 0 20 40 60 80 100 PHASE DETECTOR FREQUENCY (MHz) Recommended CP offset current CP gain currents. Calculated using (EQ 9) vs PD frequency for typical The required CP offset current should never exceed 25 % of the programmed CP current. It is recommended to enable the Up Offset and disable the Down Offset by writing Reg 09h[22:21] = ‘10’b. Operation with CP offset influences the required configuration of the Lock Detect function. Refer to the description of Lock Detect function in section 1.3.5. When operating with PD frequency >=80MHz, the CP Offset current should be disabled for the frequency change and then re-enabled after the PLL has settled. If the CP Offset current is enabled during a frequency change it may not lock. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 30 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 2.1.1.2 Phase Detector Functions Setting Reg 0Bh[5] = 0, masks the PD up output, which prevents the charge pump from pumping up.` Setting (Reg 0Bh[6]) = 0, masks the PD down output, which prevents the charge pump from pumping down. Clearing both Reg 0Bh[5] and Reg 0Bh[6] tri-states the charge pump while leaving all other functions operating internally. Reference Input Stage LE 2.1.2 TE PD Force UP Reg 0Bh[9] = 1 and PD Force DN Reg 0Bh[10] = 1 allows the charge pump to be forced up or down respectively. This will force the VCO to the ends of the tuning range which can be useful in VCO testing. B SO TRANSCEIVERS - Rx RFICs Phase detector register Reg 0Bhallows manual access to control special phase detector features. Figure 70. Reference Path Input Stage The reference buffer provides the path from an external reference source (generally crystal based) to the R divider, and eventually to the phase detector. The buffer has two modes of operation controlled by Reg 08h[21]. High Gain (Reg 08h[21] = 0), recommended below 200 MHz, and High frequency (Reg 08h[21] = 1), for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 Ω internal termination. For 50 Ω match, an external 100 Ω resistor to ground should be added, followed by an AC coupling capacitor (impedance < 1 Ω), then to the XREFP pin of the part. O At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher frequencies, a square or sinusoid can be used. The following table shows the recommended operating regions for different reference frequencies. If operating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. 31 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 16. Reference Sensitivity Table Reference Input Frequency (MHz) < 10 Slew > 0.5V/ns Sinusoidal Input Recommended Swing (Vpp) Recommended Power Range (dBm) Recommended Min Max Recommended Min Max YES 0.6 2.5 x x x YES 0.6 2.5 x x x YES 0.6 2.5 ok 8 15 TE 10 25 50 YES 0.6 2.5 YES 6 15 100 YES 0.6 2.5 YES 5 15 150 ok 0.9 2.5 YES 4 12 200 ok 1.2 2.5 YES 3 8 2.1.3 LE Input referred phase noise of the PLL when operating at 50 MHz is between -148 and -150 dBc/Hz at 10 kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better than this floor to avoid deg­radation of the PLL noise contribution. It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals. Reference Path ’R’ Divider 2.1.4 B SO The reference path “R” divider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled via Reg 02h. TRANSCEIVERS - Rx RFICs Square Input RF Path ’N’ Divider The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional mode, and 219-1 (524,287) to 16 in integer mode. 2.1.5 Lock Detect O The Lock Detect (LD) function indicates that the HMC1190LP6GE is indeed generating the desired frequency. It is enabled by writing Reg 07h[11]=1. The HMC1190LP6GE provides LD indicator in one of two ways: • As an output available on the LD_SDO pin of the HMC1190LP6GE, (Configuration is required to use the LD_SDO pin for LD purpose, for more information please see “1.8 Serial Port Open Mode” and “1.3.5.3 Configuring LD_SDO Pin for LD Output” section). • Or reading from Reg 12h[1], where Reg 12h[1] = 1 indicates locked and Reg 12h[1] = 0 indicates an unlocked condition. The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period (window), repeatedly. Either signal may arrive first, only the difference in arrival times is significant. The arrival of the two edges within the designated window increments an internal counter. Once the count reaches and exceeds a user specified value (Reg 07h[2:0]) the HMC1190LP6GE declares lock. Failure in registering the two edges in any one window resets the counter and immediately declares an un-locked condition. Lock is deemed to be reestablished once the counter reaches the user specified value (Reg 07h[2:0]) again. 2.1.5.1 Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section “1.3.1”. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 32 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz   ICP Offset ( A) 1   sec ) + 2.66 × 10−9 ( +  FPD () Hz × ICP ( A) FPD () Hz   LD Window ( seconds ) in Fractional Mode = 2 1 LD Window ( seconds ) in Integer Mode = 2 × FPD (EQ 10) TE where: FPD: is the comparison frequency of the Phase Detector ICP Offset : is the Charge Pump Offset Current Reg 09h[20:14] ICP: is the full scale current setting of the switching charge pump Reg 09h[6:0], or Reg 09h[13:7] If the result provided by (EQ 10) is equal to 10 ns Analog LD can be used (Reg 07h[6] = 0). Otherwise Digital LD is necessary Reg 07h[6] = 1. LE Table 17 provides the required Reg 07h settings to appropriately program the Digital LD window size. From Table 17, simply select the closest value in the “Digital LD Window Size” columns to the one calculated in (EQ 10) and program Reg 07h[9:8] and Reg 07h[7:5] accordingly. Table 17. Typical Digital Lock Detect Window LD Timer Speed Reg07[9:8] Digital Lock Detect Window Size Nominal Value (ns) Fastest 00 6.5 01 7 8 11 17 29 53 100 195 8.9 12.8 21 36 68 130 255 B SO TRANSCEIVERS - Rx RFICs These settings in Reg 09h impact the required LD window size in fractional mode of operation. To function, the required lock detect window size is provided by (EQ 10). 10 7.1 9.2 13.3 22 38 72 138 272 Slowest 11 7.6 10.2 15.4 26 47 88 172 338 LD Timer Divide Setting Reg07[7:5] 000 001 010 011 100 101 110 111 2.1.5.2 Digital Window Configuration Example Assuming, fractional mode, with a 50 MHz PD and • Charge Pump gain of 2 mA (Reg 09h[13:7] = 64h, Reg 09h[6:0] = 64h), • Down Offset (Reg 09h[22:21] = ‘10’b) • Offset current magnitude of +400 µA (Reg 09h[20:14] = 50h) O Applying (EQ 11), the required LD window size is:   0.4 x10−3 ( A) 1   + 2.66 × 10−9 ( + sec ) −3 6  50 × 106 ()  × × Hz 2 x 10 A 50 10 Hz () ()   13.33 nsec LD Window ( seconds ) = 2 (EQ 11) Locating the Table 17 value that is closest to the (EQ 11) result, in this case 13.3 ≈ 13.33. To set the Digital LD window size, simply program Reg 07h[9:8] = ‘10’b and Reg 07h[7:5] = ‘010’b according to Table 17. There is always a good solution for the lock detect window for a given operating point. The user should understand however that one solution does not fit all operating points. As observed from (EQ 11), If charge pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted. 33 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Setting Reg 0Fh[4:0]=1 will display the Lock Detect Flag on LD_SDO pin of the HMC1190LP6GE. If locked, LD_SDO will be high. As the name suggests, LD_SDO pin is multiplexed between LD and SDO (Serial Data Out) signals. Hence LD is available on the LD_SDO pin at all times except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data Out pin, and returns to the Lock Detect Flag after the read is completed. 2.1.6 Cycle Slip Prevention (CSP) TE LD can be made available on LD_SDO pin at all times by writing Reg 0Fh[6] = 1. In that case the HMC1190LP6GE will not provide any read-back functionality because the SDO signal is not available. LE When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than ±2π radians. Since the gain of the PD varies linearly with phase up to ±2π, the gain of a conventional PD will cycle from high gain, when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency. The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis. 2.1.7 B SO The HMC1190LP6GE PD features an ability to reduce cycle slipping during frequency tunning. The Cycle Slip Preven­tion (CSP) feature increases the PD gain during large phase errors. TRANSCEIVERS - Rx RFICs 2.1.5.3 Configuring LD_SDO Pin for LD Output Frequency Tuning HMC1190LP6GE VCO subsystem always operates in fundamental frequency of operation (2050 MHz to 4100 MHz). The HMC1190LP6GE generates frequencies below its fundamental frequency (33 MHz to 2050 MHz) by tuning to the appropriate fundamental frequency and selecting the appropriate Output Divider setting (divide by 2/4/6.../60/62) in Reg 16h[5:0]. The HMC1190LP6GE automatically controls frequency tuning in the fundamental band of operation, for more information see “1.2.1 VCO Calibration”. O To tune to frequencies below the fundamental frequency range ( fgcd 2 6 6 3 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 38 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz TRANSCEIVERS - Rx RFICs If (EQ 16) is satisfied for at least two of the equally spaced interval (channel) frequencies f VCO1,f VCO2 ,f VCO3 ,... f VCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies, and can be configured as follows: 1. Reg 03h = 2. Reg 0Ch = 6    VCO 1  floor  2800.2 × 10=  45 = = d 2Dh  fPD   61.44 × 106      f floor  61.44 × 106 61.44 × 106 d C00h = = = 3072 = 3 6 20000 gcd 100 × 10 ,61.44 × 10 gcd ( , fPD fVCOk +1 − fVCOk ) ( fPD ) ( ) TE where (f VCOk+1 - f VCOk) is the desired channel spacing (100 kHz in this example). 3. To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest channel VCO frequency f VCO1 must be calculated. fN = floor(f VCO1/fPD). Using the current example:  2800.2 × 106   =45 × 61.44 × 106 =2764.8 MHz  61.44 × 106    Then LE fN =fPD × floor   224 f  ( VCO1 − fN )   Reg 04h ceil = =   for channel 1 where fVCO1 2800.2 MHz f   PD    24 2800.2 × 106 − 2764.8 × 106  2 d 938000h = ceil  = =  9666560 61.44 × 106     ( ) B SO 4. To change from channel 1 (f VCO1 = 2800.2 MHz) to channel 2 (f VCO2 = 2800.3 MHz), only Reg 04h needs to be programmed, as long as all of the desired exact frequencies f VCOk (Figure 71) fall between the same integer-N boundaries (fN < f VCOk < fN+1). In that case ( )  24 2800.3 × 106 − 2764.8 × 106  2 = = d 93EAABh  9693867 61.44 × 106     Reg 04h = ceil  4.1.1 , and so on. Seed Register O The start phase of the fractional modulator digital phase accumulator (DPA) may be set to any desired phase relative to the reference frequency, The phase is programmed in Reg 1Ah, and Exact Frequency Mode is required. Phase = 2π x Reg1Ah/(224) via the seed register Reg 1Ah[23:0]. The HMC1190LP6GE will automatically reload the start phase (seed value) into the DPA every time a new fractional frequency is selected. Certain zero or binary seed values may cause spurious energy correlation at specific frequencies. For most cases a random, or non zero, non-binary start seed is recommended. 4.1 Soft Reset & Power-On Reset The HMC1190LP6GE features a hardware Power on Reset (POR). All chip registers will be reset to default states approximately 250 µs after power up. The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg 00h. 4.2 Power Down Mode Power down the HMC1190LP6GE by pulling CEN pin (pin 17) low (assuming no SPI overrides(Reg 01h[0]=1)). This will result in all analog functions and internal clocks disabled. Current consumption will typically drop below 10 µA in Power Down state. The serial port will still respond to normal communication in Power Down mode. It is possible to ignore the CEN pin, by setting Reg 01h[0]=0. Control of Power Down Mode then comes from the serial port register Reg 01h[1]. 39 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz a. Internal Bias Reference Sources Reg 01h[2] b. PD Block Reg 01h[3] c. CP Block Reg 01h[4] d. Reference Path Buffer Reg 01h[5] e. VCO Path buffer Reg 01h[6] f. Digital I/O Test pads Reg 01h[7] 4.3 General Purpose Output (GPO) Pin TE To mute the output but leave the PLL and VCO locked please refer to 1.2.4 section. LE The PLL shares the LD_SDO (Lock-Detect/Serial Data Out) pin to perform various functions. While the pin is most commonly used to read back registers from chip via the SPI, it is also capable of exporting a variety of signals and real time test waveforms (including Lock Detect). It is driven by a tri-state CMOS driver with ~200 Ω Rout. It has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. In its default configuration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus. The pin driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle = ‘000’b before the rising edge of SEN. If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the HMC1190LP6GE will start to drive the bus. B SO The BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER will naturally switch away from the GPO data and export the SDO during an SPI read. To prevent this automatic data selection, and always select the GPO signal, set “Prevent AutoMux of SDO” (Reg 0Fh[6] = 1). The phase noise performance at this output is poor and uncharacterized. The GPO output should not be toggling during normal operation because it may degrade the spectral performance. TRANSCEIVERS - Rx RFICs It is also possible to leave various blocks on when in Power Down (see Reg 01h), including: Note that there are additional controls available, which may be helpful if sharing the bus with other devices: • To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else). • To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 1 or Reg 0Fh[9] = 1 respectively. Example Scenarios: Drive SDO during reads, tri-state otherwise (to allow bus-sharing) • No action required. O • • Drive SDO during reads, Lock Detect otherwise • Set GPO Select Reg 0Fh [4:0] = ‘00001’b (which is default) • Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1) • Always drive Lock Detect • Set “ Prevent AutoMux of SDO” Reg 0Fh[6] = 1 • Set GPO Select Reg 0Fh[4:0]= 00001 (which is default) • Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)) The signals available on the GPO are selected in Reg 0Fh[4:0]. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 40 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Chip Identification The chip id information may be read by reading the content of read only register, chip_ID in Reg 00h. For HMC1190LP6GE, chip id is C7701Ah. 4.5 SERIAL PORT Overview The SPI protocol has the following general features: 4.5.1 Serial Port WRITE Operation AVDD = DVDD = 3V, AGND = DGND = 0V TE a. 3-bit chip address , enable the use of up to 8 devices connected to the serial bus b. Simultaneous Write/Read during the SPI cycle c. 5-bit address space d. 3 wire for Write Only capability, 4 wire for Read/Write capability Typical serial port operation can be run with SCLK at speeds up to 50 MHz. Parameter LE Table 18. SPI WRITE Timing Characteristics Conditions Min. Typ. Max Units t1 SDI setup time to SCLK Rising Edge 3 ns t2 SCLK Rising Edge to SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns t6 Recovery Time 10 ns B SO TRANSCEIVERS - Rx RFICs 4.4 Max Serial port Clock Speed 50 MHz A typical WRITE cycle is shown in Figure 72. O a. The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK. b. the slave (HMC1190LP6GE) shifts in data on SDI on the first 24 rising edges of SCLK c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK (25-29) d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29). e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32). Hittite reserves chip address a2:a0 = 000 for HMC1190LP6GE. f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32). g. Master asserts SEN after the 32nd rising edge of SCLK. h. Slave registers the SDI data on the rising edge of SEN. i. Master clears SEN to complete the WRITE cycle. 41 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 4.5.2 LE Figure 72. Serial Port Timing Diagram - WRITE Serial Port READ Operation A typical READ cycle is shown in Figure 73. B SO In general, the LD_SDO line is always active during the WRITE cycle. During any SPI cycle LD_SDO will contain the data from the current address written in Reg 00h[4:0]. If Reg 00h[4:0] is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress. If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the desired address to Reg 00h[4:0], then in the next SPI cycle the desired data will be available on LD_SDO. TRANSCEIVERS - Rx RFICs TE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz An example of the two cycle procedure to read from any address follows: O a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI as shown in Figure 73. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on the next cycle. b. the slave (HMC1190LP6GE) shifts in data on SDI on the first 24 rising edges of SCK c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5 falling edges of SCK (25-29). r4:r0=00000. d. Slave shifts the register bits on the next 5 rising edges of SCK (25-29). e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCK (30-32). Chip address is always ‘000’b. f. Slave shifts the chip address bits on the next 3 rising edges of SCK (30-32). g. Master asserts SEN after the 32nd rising edge of SCK. h. Slave registers the SDI data on the rising edge of SEN. i. Master clears SEN to complete the the address transfer of the two part READ cycle. j. If one does not wish to write data to the chip during the second cycle, then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle. k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK. l. Slave (HMC1190LP6GE) shifts the SDI data on the next 32 rising edges of SCK. On these same edges, the slave places the desired read data (ie. data from the address specified in Reg 00h[4:0] of the first cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the LD output. m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 42 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 19. SPI Read Timing Characteristics Conditions Min. Typ. Max Units t1 SDI setup time to SCK Rising Edge 3 ns t2 SCK Rising Edge to SDI hold time 3 ns t3 SEN low duration 10 ns t4 SEN high duration 10 ns SCK Rising Edge to SDO time Recovery TIme 10 8.2ns+0.2ns/pF ns t7 SCK 32 Rising Edge to SEN Rising Edge 10 ns ns B SO LE TE t5 t6 O TRANSCEIVERS - Rx RFICs Parameter 43 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 TRANSCEIVERS - Rx RFICs O B SO LE TE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Figure 73. Serial Port Timing Diagram - READ For more information on using the GPO pin while in SPI Mode please see section 1.8 Serial Port Overview Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 44 HMC1190LP6GE v06.1113 2.0 PLL Register Map 2.1 Reg 00h ID Register (Read Only) DEFAULT C7701A h Bit Type [23:0] RO Width Default 24 C7701A Reg 00h Open Mode Read Address/RST Strobe Register (Write Only) Bit Type [4:0] WO Name Read Address Width Default 5 - [5] WO Soft Reset 1 - [23:6] WO Not Defined 18 - Bit [0] [1] [2] [3] [4] [5] [6] [7] [9:8] Bit [13:0] 2.5 Bit (WRITE ONLY) Soft Reset - (set to 0 during operation) Not Defined (set to write 0h) Reg 01h Chip Enable Register DEFAULT 3h Type R/W R/W Name Chip Enable Pin Select SPI Chip Enable Width Default Description 1 = Chip enable via CHIP_EN pin, Reg 01h[0]=1 and CHIP_EN pin low places the HMC1190LP6GE in Power Down Mode 1 1 1 1 0 = Chip enable via SPI - Reg 01h[0] = 0, CHIP_EN pin ignored (see Power Down Mode description for more details) Controls Chip Enable (Power Down) if Reg 01h[0] =0 Reg 01h[0]=0 and Reg 01h[1]=1 - chip is enabled, CHIP_ EN pin don’t care Reg 01h[0]=0 and Reg 01h[1]=0 - chip disabled, CHIP_EN pin don’t care (see Power Down Mode description for more information) R/W Keep Bias On 1 0 keeps internal bias generators on, ignores Chip enable control R/W Keep PFD Pn 1 0 keeps PFD circuit on, ignores Chip enable control R/W Keep CP On 1 0 keeps Charge Pump on, ignores Chip enable control R/W Keep Reference Buffer ON 1 0 keeps Reference buffer block on, ignores Chip enable control R/W Keep VCO on 1 0 keeps VCO divider buffer on, ignores Chip enable control R/W Keep GPO Driver ON 1 0 keeps GPO output Driver ON, ignores Chip enable control R/W Reserved 2 0 reserved Reg 02h REFDIV Register DEFAULT 1h O 2.4 Description (WRITE ONLY) Read Address for next cycle LE 2.3 Description Chip ID Number TE 2.2 Name chip_ID B SO TRANSCEIVERS - Rx RFICs BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Type R/W Name rdiv Width 14 Default 1 Description Reference Divider ’R’ Value (EQ 8) min 1 max max 214-1 = 3FFFh = 16383d Reg 03h Frequency Register - Integer Part DEFAULT 19h Type Name Width Default Description Divider Integer part, used in all modes, see (EQ 10) [18:0] R/W Integer Setting 19 25d 19h Fractional Mode min 20d max 219 - 4 = 7FFFCh = 524,284d Integer Mode min 16d max 219-1 = 7FFFFh = 524,287d 45 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Bit [23:0] Reg 04h Frequency Register - Fractional Part DEFAULT 0h Type R/W Name Width Fractional Setting Default 24 Description Divider Fractional part (24 bit unsigned) see Fractional Frequency Tuning Fractional Division Value = Reg4[23:0]/2^24 Used in Fractional Mode only 0 Reg 05h Reserved Bit Type [23:0] R/W 2.8 Name Reserved Default 24 0 Description Reserved Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah BIT TYPE NAME [1:0] R/W Reserved R/W DSM Order Width Default 2 2 Reserved, Program to 0h 2 Select the Delta Sigma Modulator Type 0: 1st order 1: 2nd Order 2: 3rd Order - Recommended 3: Reserved 2 DESCRIPTION B SO [3:2] Width LE 2.7 TE min 0 max 224-1 = FFFFFFh = 16,777,215d 0: Normal SPI Load - all register load on rising edge of SEN TRANSCEIVERS - Rx RFICs 2.6 1: Synchronous SPI - registers Reg 03h, Reg 04h , Reg 1Ah wait to load synchronously on the next internal clock cycle. [4] [5] Synchronous SPI Mode 1 0 R/W Exact Frequency Mode Enable 1 0 1: Exact Frequency Mode Enabled 0: Exact Frequency Mode Disabled R/W Reserved 1 0 Reserved 0 0: Use Modulator, Required for Fractional Mode, 1: Bypass Modulator, Required for Integer Mode Note: When enabled fractional modulator output is ignored, but fractional modulator continues to be clocked if Reg 06h[11] =1. This feature can be used to test the isolation of the digital fractional modulator from the VCO output in integer mode. O [6] [7] Normally (When this bit is 0) SPI writes into the internal state machines/counters happen asynchronously relative to the internal clocks. This can create freq/phase disturbances if writing register 3, 4 or 1A. When this bit is enabled, the internal SPI registers are loaded synchronously with the internal clock. This means that the data in the SPI shifter should be held constant for at least 2 PFD clock periods after SEN is asserted to allow this retiming to happen cleanly. R/W R/W Fractional Bypass 1 1: loads the modulator seed (start phase) whenever the fractional [8] R/W [10:9] register (Reg 04h) is written Autoseed EN 1 1 R/W Reserved 2 3 Reserved [11] R/W Delta Sigma Modulator Enable 1 1 0: Disable DSM, used for Integer Mode 1: Enable DSM Core, required for Fractional Mode [23:12] R/W Reserved 12 48d 30h 0: when fractional register (Reg 04h) write changes frequency, modulator starts at previous value (phase) Reserved Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 46 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Type Name Default Description lock detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 R/W lkd_wincnt_max 3 4 [10:3] R/W Reserved 8 8 [11] R/W LD Enable 1 1 [19:12] R/W Reserved 8 0 [20] R/W Lock Detect Training [21] R/W CSP Enable [23:22] R/W Reserved Bit [4:0] Reserved 0: LD disable 1: LD enable Reserved 0 to 1 transition triggers the training. Lock Detect Training is only required after changing Phase Detector frequency. LE [2:0] 2.10 9 0 After changing PD frequency a toggle Reg 07h[20] from 0 to 1 retrains the Lock Detect. 1 1 Cycle Slip Prevention enable. When enabled, if the phase error becomes larger than approx 70% of the PFD period, the charge-pump gain is increased by approx 6mA for the duration of the cycle.. 2 0 Reserved Reg 08h Analog EN Register DEFAULT 1BFFF h Type R/W Name Reserved Width Default 5 31d Description Reserved 0 - Pin LD_SDO disabled 1 - and RegFh[7]=1 , Pin LD_SDO is always driven, this is required for use of GPO port GPO(General Purpose Output Pin Enable) 1 R/W Reserved 4 15d Reserved R/W VCO Buffer and Prescaler Bias Enable 1 1d 0: VCO Buffer and Prescaler Bias Disable 1: VCO Buffer and Prescaler Bias Enable Only applies to External VCO [20:11] R/W Reserved 10 55d [21] R/W High Frequency Reference 1 0 Program to 1 for XTAL > 200 MHz, 0 otherwise [22] R/W SDO Output Level 1 0d Output Logic Level on LD/SDO pin 0: 1.8 V Logic Levels 1: DVDD3V Logic Level [23] R/W Reserved 1 0d Reserved [5] [9:6] R/W O [10] 47 Width B SO TRANSCEIVERS - Rx RFICs Bit Reg 07h Lock Detect Register DEFAULT 200844 h TE 2.9 1d 1 - and RegFh[7]=0 LDO_SPI is off if chip address not equal to ‘000’b, allowing a shared SPI with other compatible parts Reserved Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz [13:7] [20:14] R/W R/W R/W Name CP DN Gain CP UP Gain Offset Magnitude R/W Offset UP enable R/W Offset DN enable [23] R/W HiK charge pump Mode 7 7 Default 100d 64h 100d 64h Description Charge Pump DN Gain Control 20 µA√step Affects fractional phase noise and lock detect settings 0d = 0 µA 1d = 20 µA 2d = 40 µA ... 127d = 2.54mA Default 2mA Charge Pump UP Gain Control 20 µA per step Affects fractional phase noise and lock detect settings 0d = 0 µA 1d = 20 µA 2d = 40 µA ... 127d = 2.54mA Default 2mA 81d Charge Pump Offset Control 5 µA/step Affects fractional phase noise and lock detect settings 0d = 0 µA 1d = 5 µA 2d = 10 µA ... 127d = 635 µA Default 405µA 7 1 0 Sets Direction of Reg 09h[20:14] Up, 0- UP Offset Off 1 1 Sets Direction of Reg 09h[20:14] Down, 0- DN Offset Off 1 0 Only recommended with external VCOs and Active Loop Filters. When enabled the HMC1190LP6GE increases CP current by 3 mA, thereby improving phase noise performance, and increasing loop bandwidth O B SO [21] [22] Width TRANSCEIVERS - Rx RFICs [6:0] Type TE Bit Reg 09h Charge Pump Register DEFAULT 547264 h LE 2.11 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 48 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 2.12 Type Name Width Default Description Used by internlan AutoCal state machine R Divider Cycles 0-1 1-2 2-4 3-8 4 - 32 5 - 64 6 - 128 7 - 256 div cycles for frequency measurement. Measurement should last > 4 µsec. Note: 1 does not work if R divider = 1. R/W Vtune Resolution 3 6d [10:3] R/W Reserved 8 16d [11] R/W AutoCal Disable 1 0 [12] R/W Reserved 1 0 Reserved 2 1 Set the AutoCal FSM and VSPI Clock (50 MHz maximum) 0: Input Crystal Reference 1: Input Crystal Reference/4 2: Input Crystal Reference/16 3: Input Crystal Reference/32 2 0 Reserved 1 0 0: Does not attempt to relock if lock is lost 1: Attempts to relock if Lock Detect fails for any reason. Only tries once. 5 0 Reserved R/W FSM/VSPI Clock Select [16:15] R/W Reserved [17] R/W Auto relock - one Try R/W Reserved 0 = AutoCal Enabled 1 = AutoCal disabled O [23:18] Reserved LE [14:13] TE [2:0] B SO TRANSCEIVERS - Rx RFICs Bit Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h 49 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Reg 0Bh PD/CP Register DEFAULT 78061 h BIT TYPE NAME Width Default [3:0] R/W Reserved 4 1 Reserved DESCRIPTION R/W PD Phase Select 1 0 [5] R/W PD Up Output Enable 1 1 Enables the PD UP output, see also Reg 0Bh[9] 0Bh[10] TE [4] Inverts the PD polarity (program to 0) 0- Use with a positive tuning slope VCO and Passive Loop Filter (default when using internal VCO) 1- Use with a Negative Slope VCO or with an inverting Active Loop Filter with a Positive Slope VCO (Only recommended when using an External VCO, and an active loop filter) [6] R/W PD Down Output Enable 1 1 Enables the PD DN output, see also Reg [8:7] R/W Reserved 2 0 Reserved, Program to 0d. R/W Force CP UP 1 0 Forces CP UP output on if CP is not forced down - Use for Test only R/W Force CP DN 1 0 Forces CP DN output on if CP is not forced up - Use for Test only [11] R/W Force CP Mid Rail 1 0 Force CP MId Rail - Use for Test only (if Force CP UP or Force CP DN are enabled they have precedence) [23:12] R/W Reserved 12 120d 78h BIT Reg 0Ch Exact Frequency Register TYPE R/W NAME Number of Channels per Fpd Width 24 Default DESCRIPTION 0 Comparison Frequency divided by the correction rate. Must be an integer. Frequencies at exactly the correction rate will have zero frequency error. Only works in modulator Mode B(3rd order recommended modulator type in Reg06[3:2]). Reg 0Ch must be 0 if using ohter DSM type 0: Disabled 1: Invalid ≥ 2 valid max 224-1 = FFFFFFh = 16,777,215d O [23:0] Reserved. B SO 2.14 LE [9] [10] TRANSCEIVERS - Rx RFICs 2.13 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 50 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 2.15 TYPE NAME Default DESCRIPTION Select signal to be output to SDO pin when enabled DEFAULT LOCK DETECT GPO 5 1 TE R/W 0: Data from Reg0F[5] 1: Lock Detect Output 2. Lock Detect Trigger 3: Lock Detect Window Output 4: Ring Osc Test 5. Pullup Hard from CSP 6. PullDN hard from CSP 7. Reserved 8: Reference Buffer Output 9: Ref Divider Output 10: VCO divider Output 11. Modulator Clock from VCO divider 12. Auxiliary Clock 13. Aux SPI Clock 14. Aux SPI Enable 15. Aux SPI Data Out 16. PD DN 17. PD UP 18. SD3 Clock Delay 19. SD3 Core Clock 20. AutoStrobe Integer Write 21. Autostrobe Frac Write 22. Autostrobe Aux SPI 23. SPI Latch Enable 24. VCO Divider Sync Reset 25. Seed Load Strobe 26.-29 Not Used 30. SPI Output Buffer En 31. Soft RSTB LE [4:0] [5] [6] [7] [8] R/W GPO Test Data 1 0 1 - GPO Test Data when GPO_Select = 0 R/W Prevent Automux SDO 1 0 1- Outputs GPO data only 0- Automuxes between SDO and GPO data R/W Reserved 1 0 [23:10] 2.16 Reserved R/W Disable PFET 1 0 Program to 1 if external pull-ups are used on the SDO line (Prevents conflicts on the SPI bus) R/W Disable NFET 1 0 Program to 1 if external pull-downs are used on the SDO line (Prevents conflicts on the SPI bus) R/W Reserved 14 0 Reserved O [9] 51 Width B SO TRANSCEIVERS - Rx RFICs BIT Reg 0Fh GPO Register Reg 10h Tuning Register DEFAULT 80 h BIT TYPE NAME Width Default [7:0] R VCO Tune Curve 8 16d 10h [8] R VCO Tuning Busy 1 0 DESCRIPTION VCO selection resulting from AutoCalibration. 0- maximum frequency ‘1111 1111’b- minimum frequency Indicates if the VCO tuning is in process 1- Busy 0- Not Busy Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz BIT Reg 11h SAR Register (Read Only) TYPE NAME Width Default DESCRIPTION [18:0] R SAR Error Magnitude Count 19 219 - 1d 7FFFFh [19] R SAR Error Sign 1 0 SAR Error Sign 0: positive 1: negative [23:20] R Reserved 4 0 Reserved TYPE [0] R [1] R [23:2] R Reserved 2.19 BIT Width Default DESCRIPTION GPO Out 1 0 GPO Output Lock Detect Out 1 0 Lock Detect Output 22 7h Reserved Reg 13h BIST Register (Read Only) TYPE R NAME Reserved Width Default 16 4697d 1259h DESCRIPTION Reserved O B SO [16:0] NAME TE Reg 12h GPO/LD Register (Read Only) BIT LE 2.18 SAR Error Magnitude Count TRANSCEIVERS - Rx RFICs 2.17 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 52 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 2.20 TYPE NAME Default DESCRIPTION [0] R/W Aux SPI Mode 1 0 1- Use the 3 outputs as an SPI port 0- Use the 3 outputs as a static GPO port along with Reg 14h[3:1] [3:1] R/W Aux GPO Values 3 0 3 Output values can be set indivually when Reg [4] R/W Aux GPO 3.3 V 1 0 [8:5] R/W Reserved 4 1 10h [0] = 1 0- 1.8 V output out of the Auxiliary GPO pins when Reg 1- 3.3 V output out of the Auxiliary GPO pins when Reg 10h [0] = 1 10h [0] = 1 TE Reserved When set, CHIP_EN pin is used as a trigger for phase synchronization. Can be used to synchronize multiple [11:10] [13:12] 2.21 BIT [0] [5:1] [8:6] R/W R/W Phase Sync Aux SPI GPO Output Aux SPI Outputs R/W Reserved 1 2 1 HMC1190LP6GE, or to along with the Reg 1Ah value to phase step the output. (Exact Frequency Mode must be enabled) 0 Option to send GPO multiplexed data (ex Lock Detect) to one of the auxiliary outputs 0- None 1 - to [0] 2 - to [1] 3 - to [2] 0 When disabled: 0 - Outputs Hi Z 1 - Outputs stay driven 2 - Outputs driven to high 3 - Outputs driven to low 2 10 0 Reserved Reg 15h Manual VCO Config Register Default F48A0 h TYPE NAME Width Default R/W Manual Calibration Mode 1 0 R/W Capacitor Switch Setting 5 16d 10h R/W Manual VCO Selection 3 2 selects the VCO core sub-band R/W Manual VCO Tune Enable 1 0 1- Manual VCO tuning enabled 0- Manual VCO tuning disabled O [9] R/W LE [9] [23:14] 53 Width B SO TRANSCEIVERS - Rx RFICs BIT Reg 14h Auxiliary SPI Register DESCRIPTION 1- VCO subsystem manual calibration enabled 0- VCO subsystem manual calibration disabled capacitor switch setting [15:10] R/W Reserved 6 18d 12h [16] R/W Enable Auto-Scale CP current 1 1 1 - Automatically scale CP current based on VCO frequency and capacitor setting 0- Don’t scale CP current [23:17] R/W Reserved 7 7d Reserved Reserved Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz R/W RF Divide Ratio [7:6] R/W LO Output Buffer Gain Control [9:8] R/W LO2 Output Buffer gain Control [10] R/W Divider Output Stage Gain Control [23:11] R/W Reserved Width 6 2 Default DESCRIPTION 1 0 - Mute, VCO and PLL buffer On, RF output stages Off 1 - Fo 2 - Fo/2 3 - invalid, defaults to 2 4 - Fo/2 5 - invalid, defaults to 4 6 - Fo/6 ... 60 - Fo/60 61 - invalid, defaults to 60 62 - Fo/62 > 62 - invalid, defaults to 62 3 3 - Max Gain 2 - Max Gain - 3 dB 1 - Max Gain - 6 dB 0 - Max Gain - 9 dB 2 2 3 - Max Gain 2 - Max Gain - 3 dB 1 - Max Gain - 6 dB 0 - Max Gain - 9 dB 1 1 1 - Max Gain 0 - Max Gain - 3 dB 13 0 Reserved O TRANSCEIVERS - Rx RFICs NAME B SO [5:0] TYPE TE BIT Reg 16h Gain Divider Register Default 6C1 h LE 2.22 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 54 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 2.23 TYPE NAME Default DESCRIPTION Master enable for the entire VCO Subsystem 1 - Enable 0 - Disable Chip Enable is also required to set as enable mode. R/W VCO SubSys Master Enable 1 1 [1] R/W VCO Enable 1 1 [2] R/W External VCO Buffer Enable 1 0 External VCO Buffer to output stage enable. Only used when locking an external VCO. [3] R/W PLL Buffer Enable 1 1 PLL Buffer Enable. Used when using an internal VCO. TE [0] [4] R/W LO1 Output Buffer Enable 1 0 Enables LO1 (LO_P & LO_N pins) output buffer. [5] R/W LO2 Output Buffer Enable 1 1 Enables the LO2 (LO2_N & LO2_P pins) output buffer [6] R/W External Input Enable 1 0 Enables External VCO input [7] R/W Pre Lock Mute Enable 1 1 Mute both output buffers until the PLL is locked R/W LO1 Output Single-Ended Enable R/W LO2 Output Single-Ended Enable [9] [11] [23:12] 2.24 BIT 0 Enables Single-Ended output mode for LO2 output 1- Single-ended mode, LO2_N pin is enabled, and LO2_P pin is disabled 0- Differential mode, both LO2_N and LO2_P pins enabled Please note that single-ended output is only available on LO2_N pin. 1 Reserved 1 0 Reserved R/W Charge Pump Output Select 1 0 Connects CP to CP1 or CP2 output. 0: CP1 1: CP2 R/W Reserved 12 0 Reserved Reg 18h Bias Register Default 54C1 h TYPE NAME Width Default R/W Reserved 19 21697d 54C1h 1 0 External Input buffer BIAS bit0 1 0 External Input buffer BIAS bit1 3 0 Reserved [19] R/W [20] R/W [23:21] R/W 2.25 1 R/W External Input buffer BIAS O [18:0] 1 Enables Single-Ended output mode for LO output 1- Single-ended mode, LO_N pin is enabled, and LO_P pin is disabled 0- Differential mode, both LO_N and LO_P pins enabled Please note that single-ended output is only available on LO_N pin. LE [8] [10] 55 Width B SO TRANSCEIVERS - Rx RFICs BIT Reg 17h Modes Register Default 1AB h bit0 External Input buffer BIAS bit1 Reserved DESCRIPTION Reserved Reg 19h Cals Register Default AAA h BIT TYPE NAME Width Default [23:0] R/W Reserved 2 2730d AAAh DESCRIPTION Reserved. Program to AB2h. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz BIT TYPE R/W NAME Delta Sigma Modulator Seed Width 24 Default DESCRIPTION 11705611d B29D0Bh Used to program output phase relative to the reference frequency. (Exact Frequency Mode required). When not using Exact Frequency Mode and Auto seed Enable Reg06h[8] =1, Reg1Ah sets the start phase of output signal. If AutoSeed disable Reg06h[8] =0, Reg1Ah is the start phase of the signal after every frequency changel. (LO Phase = 2π x Reg1Ah/(224) O B SO LE TE [23:0] Reg 1Ah Seed Register Default B29D0Bh TRANSCEIVERS - Rx RFICs 2.26 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 56 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Application Information The HMC1190LP6GE is a broadband dual channel, high dynamic range, high gain, low noise, highlinearity down converting mixer with integrated Fractional-N Integer-N PLL and VCO, designed to cover RF frequencies from 700 MHz to 3.5 GHz. The HMC1190LP6GE`s low noise and high linearity performance makes it suitable for a wide range of transmission standards, including TDD, FDD, LTE, WiMAX, CDMA,GSM, MC-GSM, W-CDMA, UMTS, TD-SCDMA applications. TE The HMC1190LP6GE offers an easy-to-use and complete frequency conversion solution for diversity and MIMO receiver applications in a highly compact 6x6 mm plastic QFN package. The HMC1190LP6GE greatly simplifies the design of diversity and MIMO receiver applications by increasing the integration level and reducing the number of required circuit elements thereby reducing cost, area, and power consumption. 3.1 Principle of Operation LE HMC1190LP6GE’s single-ended RF inputs are converted into differential through the on-chip integrated baluns. The single-ended RF inputs are internally broadband matched to 50 Ω and require only standard DC-blocking capacitors. HMC1190LP6GE’s RF inputs can be externally matched for narrow band application frequencies with a simple matching network including a series inductor, and a shunt capacitor to further improve the performance. Please refer to the application circuit for narrow band RF input matching for the detailed information. The HMC1190LP6GE’s IF amplifiers are designed for differential 200 Ω output load impedance. A few external components are required at these IF outputs for the broadband frequency response as recommended in the application circuit. B SO TRANSCEIVERS - Rx RFICs 3.0 Refer to the IF output interface section for detailed information. The HMC1190LP6GE requires 5V, 3.3V and 3V supply voltages and external bias voltages. Bias voltages generate reference currents for the IF and LO amplifiers. 3.3V supply voltage and the external bias voltages can be generated from 5V supply voltage to operate with a single supply. Please refer to the single supply operation section for more information. The reference currents to the IF and LO amplifiers can be disabled through SPI interface. See `Enabling / Disabling Mixer Features` section for details. 3.2 Supply Number Reduction O The LOVDD, VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1 and VGATE2 pins of HMC1190LP6GE requires different supply voltages. Except LOVDD, other pin voltages i.e. VGATE1, VGATE2, LOBIAS1, LOBIAS2, VCS1, VCS2 voltages are already generated from 5.5V supply voltage on evaluation board (see application circuit). These bias voltages can be optimized by external resistors (VCS1, VCS2, LOBIAS1, LOBIAS2, VGATE1, and VGATE2). The resistor values of VCS1, VCS2 on evaluation board are 590 Ohms. LOBIAS1 and LOBIAS2 series resistor values are 270 Ohms. Refer to the VCS Interface and LOBIAS Interface section for more information. On the evaluation board, VGATE1, VGATE2 pin voltages are 5V; however VGATE1, VGATE2 pin voltages can be tuned between 4.7V and 5V for optimization of Input IP3 and conversion gain performances. After VGATE1,VGATE2 pin voltages are optimized, these pin voltages can be generated from 5V supply by changing the values of series resistors, R14 and R15. Refer to the VGATE interface section for more information. The 3 V supply voltage for the LO amplifiers can be generated from 5 V or 3.3 V supply voltages by adding 57 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz a series resistor (R_LOVDD) between LOVDD pin and supply voltage in the configuration shown in Figure 74. TRANSCEIVERS - Rx RFICs If using a 5 V supply R_LOVDD = 14 Ω, and minimum power rating of R_LOVDD is 0.3 W LE TE If using a 3.3 V supply, R_LOVDD = 2.15 Ω, and minimum power of R_LOVDD is 0.05 W Figure 74. Interface to generate 3 V for LOVDD pin from 3.3V or 5V Supply. VGATE Interface B SO 3.3 The VGATE1, VGATE2 pins are bias pins for mixer cores. On evaluation board VGATE1, VGATE2 pin voltages are set to 5V. However voltage can be tuned between 4.7V and 5V for optimizing input IP3 and conversion gain performances for desired frequency band. Higher IIP3 values can be obtained by increasing the VGATE1, VGATE2 pin voltages but this will reduce HMC1190LP6GE`s conversion gain. Figure 77 shows the measured conversion gain and IIP3 for four values of VGATE1, VGATE2 pin voltages. Conversion Gain vs. VGATE [1] 10 8 6 4 29 27 25 23 21 19 2 0 0.7 31 IIP3(dBm) O CONVERSION GAIN (dB) 12 Input IP3 vs. VGATE 17 1.1 1.5 1.9 2.3 2.7 3.1 3.5 15 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 FREQUENCY (GHz) FREQUENCY (GHz) 4.7 V 4.9 V 4.7 V 4.9 V 4.8 V 5.0 V 4.8 V 5 .0V Figure 75. Conversion Gain & IIP3 vs. RF Frequency over VGATE Pin Voltage @25C, IF =150 MHz [1] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 58 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Table 20 shows the typical resistor values that need to be added in series with VGATE1, VGATE2 pins for different VGATE voltages.A fine tune for R54 and R56 resistors can be used if a better fit is required. Table 20. Resistor values for Different VGATE Pin Voltages 4.8 V 120 Ohms 4.9 V 56 Ohms 5.0 V 0 Ohm VCS Interface and LOBIAS Interface LE 3.4 R54=R56 174 Ohms TE VGATE1=VGATE2 4.7 V VCS1, VCS2 pins are bias pins for IF amplifiers on each channel and set the reference currents to these IF amplifiers.The VCS voltage is generated from the 5V supply by series resistors. Higher IIP3 values can be obtained by changing the values of these series resistors R61 and R73, which will change the total supply current of the IF amplifiers which can be seen on Table 21 a. LOBIAS1, LOBIAS2 pins are bias pins for LO amplifiers and set the reference currents to these LO amplifiers. The LOBIAS voltage is generated from the 5V supply by series resistors R71 and R57. Changing LOBIAS2 voltage, changes current consumed by LOVDD pin, which can be seen at Table 21 b. B SO TRANSCEIVERS - Rx RFICs After the VGATE voltage is tuned for optimized IIP3 and conversion gain performance, the VGATE pin voltage can be generated from 5V supply voltage by changing the value of series resistors, R54 and R56 from 0 Ohm to an appropriate value. HMC1190LP6GE`s flexible design allows users to choose best configuration for their needs. For higher power consumption, better OIP3 values can be achieved. 9 8 7 6 5 O 4 3.2 3.5 3.6 3.9 4 VCS (V) +3.35V +3.70V +4.05V 4.2 28 26 24 IIP3(dBm) CONVERSION GAIN (dB) 10 22 20 18 16 3.2 3.5 3.6 3.9 4 4.2 VCS (V) +4.40V +4.75V +3.35V +3.7V +4.05V +4.4V +4.75V Figure 76.Conversion Gain, IIP3 vs. VCS1, VCS2 and LOBIAS2 voltages at 1900 MHz RF Input. [1] Figure 76 shows the measured conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz. Conversion gain and IIP3 vs. VCS and LOBIAS2 voltages at 1900MHz. [1] Balun losses at IF output ports are de-embedded. 59 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz VCS Pin (V) 5.0 V IF Amp (mA) R61=R73 4.25 181 440 Ohms 4.0 159 590 Ohms 3.75 135 740 Ohms 3.5 110 880 Ohms 3.25 86 1 KOhms TE VCS Jumper, J13 (V) Table 21 b. LOBIAS2 voltage vs LO Amplifier Currents LOBIAS Jumper, J12 (V) LOBIAS2 Pin (V) 4.75 4.4 5.0 V 4.05 3.36 3.5 R71=R57 157 110 Ohms 150 270 Ohms 143 420 Ohms 135 580 Ohms 128 740 Ohms LE 3.7 LO Amp (mA) External RF Matching B SO The HMC1190LP6GE`s RF inputs are internally broadband matched to 50Ω. RF inputs can be externally matched for a specific RF frequency band of interest to further improve Input IP3 (IIP3). Matching RF inputs to a specific RF frequency band can be easily accomplished by adding a series inductor and a shunt capacitor. See Table 3 for values of the external matching components for corresponding RF frequency bands. Application circuit with the external components on RF input pins can be seen at Figure 80. TRANSCEIVERS - Rx RFICs Table 21 a. VCS voltage vs IF Amplifier Currents VGATE1, VGATE2 pin voltages can be optimized for a specific RF frequency band by changing the resistor values in series with these pins. Table-1 shows the resistor values (R54, R56) for corresponding VGATE pin voltage. Figure 77, Figure 78, and Figure 79 show the measured conversion gain, IIP3 and OIP3 for 900MHz, 1900MHz and 2500MHz RF frequency bands. 38 36 34 20 15 9 6 40 25 O 12 INPUT IP3 CONVERSION GAIN 10 IIP3 (dBm) CONVERSION GAIN (dB) 15 30 OIP3(dBm) 18 32 30 28 26 24 3 5 0 0 22 20 700 800 900 1000 1100 18 0.7 0.8 FREQUENCY (MHz) +25C +85C 0.9 1 1.1 FREQUENCY (GHz) -40C +25C +85C -40C Figure 77.Conversion gain, IIP3 and OIP3 for 900MHz RF frequency band. [1] [1] Balun losses at IF output ports are de-embedded. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 60 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 30 18 40 25 12 20 9 15 6 10 38 36 34 OIP3(dBm) 3 5 0 0 1800 30 28 26 24 CONVERSION GAIN 1700 32 1900 2000 2100 22 20 TE CONVERSION GAIN (dB) 15 IIP3 (dBm) 18 1.7 2200 FREQUENCY (MHz) +25C 1.8 1.9 2 2.1 2.2 FREQUENCY (GHz) +85C -40C +25C +85C -40C Figure 78.Conversion Gain, IIP3 and OIP3 for 1900MHz RF frequency band. [1] 30 LE 18 INPUT IP3 38 25 15 36 34 15 9 10 6 CONVERSION GAIN 3 OIP3(dBm) 20 12 B SO CONVERSION GAIN (dB) 40 IIP3 (dBm) TRANSCEIVERS - Rx RFICs INPUT IP3 5 0 0 2300 2400 2500 2600 2700 32 30 28 26 24 22 20 18 2.3 2.4 FREQUENCY (MHz) +25C +85C 2.5 2.6 2.7 FREQUENCY (GHz) -40C +25C +85C -40C Figure 79. Conversion Gain, IIP3 and OIP3 for 2500MHz RF frequency bands. [1] Table 22. Components for Selected Frequency Bands C82 O Tune Frequency C81 C80 R55 Recommended VGATE1,2 Voltages 900 MHz 2.7 pF 8.2 nH Open 0 Ohm 5.0V 1900 MHz 1 pF 2.7 nH Open 120 Ohms 4.8V 2500MHz Open 1 nH 1 pF 120 Ohms 4.8V [1] Balun losses at IF output ports are de-embedded. 61 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 Figure 80. Application Circuit for Narrowband RF Input Matching B SO It is recommended to use high side LO injection for RF frequencies below 1.2 GHz for better IIP3. For instance, higher IIP3 can be obtained if LO input is driven with high side at RF=900 MHz. Please refer to Figure 81. TRANSCEIVERS - Rx RFICs LE TE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz 31 29 IIP3 (dBm) 27 25 23 21 19 17 15 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 O FREQUENCY (GHz) High Side LO Low Side LO Figure 81. Input IP3 vs. High Side LO & Low Side LO @ VGATE=4.8V Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 62 HMC1190LP6GE v06.1113 BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz Input IP3 Dependence on RF Input Power The HMC1190LP6GE accepts a wide range of RF input power. Figure 82 shows the IIP3 vs. RF input power for 1900 MHz RF and 150 MHz IF. 31 29 25 TE IIP3 (dBm) 27 23 21 19 17 15 -10 -8 -6 -4 -2 0 LE RF POWER (dBm) 1900 MHz Figure 82. IIP3 vs. RF Input Power, RF= 1900 MHz, IF= 150 MHz, VGATE= 4.8V 3.7 Enabling / Disabling Mixer Features HMC1190LP6GE has a dual channel down converter core but it can also be configured as a single channel one. When single channel option is desired, HMC1190LP6GE`s unused IF amplifier can be disabled through SPI interface. B SO TRANSCEIVERS - Rx RFICs 3.6 HMC1190LP6GE can also be used as standalone PLL/VCO. In this case all IF and LO buffer amplifiers at mixer side can be disabled through SPI interface. Value of Reg14 should be changed in order to make necessary enable/disable changes. See Table 23 for details. O Table 23. Mixer Enable / Disable 3.8 REG14h value Function 3F4 IF2 disabled, IF1 and LO_Mixer enabled 3F2 IF1 disabled, IF2 and LO_Mixer enabled 3F6 IF1, IF2 and LO_Mixer disabled 3F0 IF1, IF2 and LO_Mixer enabled Using an External VCO In order to configure HMC1190LP6GE to use with an external VCO, Register 17 needs to be configured to disable the on chip VCO and VCO to PLL path. Enable External Buffer, second CP link and External I/O switch. To make these changes Reg 17 [0:11] should be configured as 3157d. Figure 83 shows HMC1190LP6GE configured as PLL alone used with External VCO HMC384LP4E. Loop Filter components are used as below. 63 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1190LP6GE v06.1113 Figure 83. Loop filter components for HMC1190LP6GE is configured as PLL alone used with external VCO HMC384LP4E LE -40 PHASE NOISE(dBc/Hz) -60 -80 -100 -120 B SO -140 TRANSCEIVERS - Rx RFICs TE BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz -160 -180 1 10 100 1000 10000 OFFSET (KHz) Figure 84. Closed Loop Phase Noise with External HMC384LP4E VCO @ 2200 MHz. O For detailed theory of operation of PLL/VCO, please refer to the “PLLs with Integrated VCOs - RF VCOs Operating Guide”. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 2delivery, and to placeChelmsford, orders: Analog MA Devices, Inc., For price, delivery and to place orders: Microwave Corporation, Elizabeth Drive, 01824 responsibility is assumed by Analog Devices for its use, nor for anyHittite infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 64