HMC625HFLP5E

HMC625HFLP5E v00.0311 Typical Applications Features The HMC625HFLP5E is ideal for: -13.5 to +18 Gain Control in 0.5 dB Steps • Cellular/3G Infrastructure Power-up State Selection • WiBro / WiMAX / 4G High Output IP3: +33 dBm • Microwave Radio & VSAT TTL/CMOS Compatible Serial, Parallel, or latched Parallel Control • Test Equipment and Sensors ±0.25 dB Typical Gain Step Error TE • IF & RF Applications Single +5V Supply 32 Lead 5 x 5 mm SMT Package: 25 mm2 Functional Diagram General Description B SO LE The HMC625HFLP5E is a digitally controlled variable gain amplifier which operates from 0.5 - 6 GHz, and can be programmed to provide anywhere from 13.5 dB attenuation, to 18 dB of gain, in 0.5 dB steps. The HMC625HFLP5E delivers noise figure of 6 dB in its maximum gain state, with output IP3 of up to +33 dBm in any state. The dual mode control interface is CMOS/ TTL compatible, and accepts either a three wire serial input or a 6 bit parallel word. The HMC625HFLP5E also features a user selectable power up state and a serial output port for cascading other Hittite serial controlled components. The HMC625HFLP5E is housed in a RoHS compliant 5 x 5 mm QFN leadless package, and requires no external matching components. Electrical Specifications, TA = +25 °C, 50 Ohm System Vdd = +5V, Vs = +5V O Variable Gain Amplifiers - Digital - SMT 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Parameter Min. Frequency Range Gain (Maximum Gain State) 13 Gain Control Range Max. Min. Typ. Max. Min. 2700 - 4000 18 11 14 5 Typ. Max. Units 4000 - 6000 MHz 10 dB 31.5 31.5 31.5 dB Input Return Loss 15 12 10 dB Output Return Loss 12 12 14 dB Gain Accuracy: (Referenced to Maximum Gain State) All Gain States ± (0.3 + 3% of relative gain setting) Max ± (0.3 + 3% of relative gain setting) Max ± (0.4 + 5% of relative gain setting) Max dB Output Power for 1 dB Compression Output Third Order Intercept Point (Two-Tone Output Power= 12 dBm Each Tone) Noise Figure (Max Gain State) 16 14 11 Switching Characteristics tRISE, tFall (10 / 90% RF) Supply Current (Amplifier) Supply Current (Controller) Idd 19 33 tON, tOFF (Latch Enable to 10 / 90% RF) 0-1 Typ. 500 - 2700 60 17 29 14 dBm 27 dBm 6 7 8 dB 30 60 30 60 30 60 ns ns 86 0.12 100 0.25 60 86 0.12 100 0.25 60 86 0.12 100 0.25 mA mA Information furnished by Analog Devices is believed to be accurate andMicrowave reliable. However, no For price,20 delivery, to place orders: Analog For price, delivery and to place orders: Hittite Corporation, Alphaand Road, Chelmsford, MADevices, 01824 Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order at www.hittite.com Phone:On-line 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarksApplication are the property of their respective Phone: owners. Support: 978-250-3343 or apps@hittite.com HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Normalized Attenuation Maximum Gain vs. Frequency (Only Major States are Shown) 25 15 +25 C +85 C -40 C 5 0 0.4 2.4 3.4 4.4 5.4 8dB -20 16dB 31.5dB -30 -40 1.4 6.4 FREQUENCY (GHz) 0.4 1.4 2.4 4.4 5.4 6.4 5.4 6.4 LE Output Return Loss (Only Major States are Shown) (Only Major States are Shown) 0 0 0dB -20 -30 B SO -10 -40 0.4 1.4 2.4 3.4 4.4 5.4 -10 -20 -30 -40 0.4 6.4 1.4 2.4 FREQUENCY (GHz) Bit Error vs. Frequency O 2 1 3.4 4.4 FREQUENCY (GHz) Bit Error vs. Attenuation State (Only Major States are Shown) 1.5 1 31.5dB 16dB BIT ERROR (dB) BIT ERROR (dB) 3.4 FREQUENCY (GHz) Input Return Loss RETURN LOSS (dB) -10 TE 10 RETURN LOSS (dB) GAIN (dB) 20 0 0.5 GHz 0.5 0.7 GHz Variable Gain Amplifiers - Digital - SMT NORMAILIZED ATTENUATION (dB) 0 5.0 GHz 0 2.0 GHz -0.5 4.0 GHz -1 -1 -2 0.4 1.4 2.4 3.4 4.4 FREQUENCY (GHz) 5.4 6.4 -1.5 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, andRoad, to place orders: Analog Devices, For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Chelmsford, MA 01824Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Phone: Order781-329-4700 On-line at www.hittite.com • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 0-2 HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Normal Relative Phase vs. Frequency Step Attenuation vs. Attenuation State, 0.5 - 3.5 GHz (Only Major States are Shown) 1.5 16dB 30 20 8dB 10 0 -10 -20 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) 0.5 0 -0.5 0 4 8 16 20 24 28 32 LE Step Attenuation vs. Attenuation State, 4.0 - 6.0 GHz 1.5 Output P1dB vs. Temperature 25 20 0.5 0 B SO 1 0 4 8 12 16 20 24 28 15 +25 C +85 C -40 C 10 4.0 GHz 5.0 GHz 6.0 GHz -0.5 5 0.4 32 1.4 ATTENUATION STATE (dB) O Output IP3 vs. Temperature 12 35 10 20 +25 C +85 C -40 C 15 10 0.4 1.4 2.4 3.4 3.4 4.4 FREQUENCY (GHz) 5.4 6.4 6.4 8 6 4 +25 C +85 C -40 C 2 4.4 5.4 Noise Figure 40 25 2.4 FREQUENCY (GHz) NOISE FIGURE (dB) IP3 (dBm) 12 ATTENUATION STATE (dB) 30 0-3 0.5 GHz 0.7 GHz 2.0 GHz 2.7 GHz 3.5 GHz 1 TE STEP ATTENUATION (dB) 31.5dB 40 P1dB (dBm) RELATIVE PHASE (DEG) 50 STEP ATTENUATION (dB) Variable Gain Amplifiers - Digital - SMT 60 0 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, 20 delivery, and to place orders: Analog For price, delivery and to place orders: Hittite Microwave Corporation, Alpha Road, Chelmsford, MADevices, 01824Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz The HMC625HFLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. TE When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (D0 - D5). When LE is high, 6-bit parallel data is transferred to the attenuator. B SO LE For all modes of operations, the DVGA state will stay constant while LE is kept low. Typ. Min. serial period, tSCK 100 ns Control set-up time, tCS 20 ns Control hold-time, tCH 20 ns LE setup-time, tLN 10 ns Min. LE pulse width, tLEW 10 ns Min LE pulse spacing, tLES 630 ns Serial clock hold-time from LE, tCKN 10 ns Hold Time tPH 0 ns Latch Enable Minimum width, tLEN 10 ns Setup Time, tPS 2 ns O Parameter Timing Diagram (Latched Parallel Mode) Variable Gain Amplifiers - Digital - SMT Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, andRoad, to place orders: Analog Devices, For price, delivery and to for place Hittite Microwave Corporation, 20 Alpha Chelmsford, MA 01824Inc., responsibility is assumed by Analog Devices its use,orders: nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax:rights 978-250-3373 Order 781-329-4700 On-line at www.hittite.com Phone: • Order online at www.analog.com license is granted by implication or otherwise under any patent or patent of Analog Devices. Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 978-250-3343 or apps@hittite.com 0-4 HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz PUP Truth Table If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. PUP1 PUP2 Gain Relative to Maximum Gain 0 0 0 -31.5 0 1 0 -24 0 0 1 -16 0 1 1 Insertion Loss 1 X X 0 to -31.5 dB Note: The logic state of D0 - D5 determines the powerup state per truth table shown below when LE is high at power-up. LE The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND LE TE Power-On Sequence Truth Table Absolute Maximum Ratings 11.5 dBm (T = 85 °C) Digital Inputs (LE, SERIN, CLK, P/S, DO-D5, PUP1, PUP2) -0.5 to Vdd +0.5V Controller Bias Voltage (Vdd) 5.6V Amplifier Bias Voltage (Vcc) 5.5V Channel Temperature 150 °C Continuous Pdiss (T = 85 °C) (derate 15.1 mW/°C above 85 °C) [1] 0.98 W Control Voltage Input D5 B SO RF Input Power [1] Thermal Resistance 66.3 °C/W Storage Temperature -65 to +150 °C Operating Temperature -40 to +85 °C ESD Sensitivity (HBM) Class 1A [1] At max gain settling D4 D3 D2 D1 D0 Gain Relative to Maximum Gain High High High High High High 0 dB High High High High High Low -0.5 dB High High High High Low High -1 dB High High High Low High High -2 dB High High Low High High High -4 dB High Low High High High High -8 dB Low High High High High High -16 dB Low Low Low Low Low Low -31.5 dB Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Control Voltage Table Bias Voltage O Variable Gain Amplifiers - Digital - SMT Power-Up States Vdd (V) Idd (Typ.) (mA) State Vdd = +3V Vdd = +5V 5V 0.12 Low 0 to 0.5V @