HMC6301BG46

Millimeterwave Receiver, 57 GHz to 64 GHz HMC6301 Data Sheet FEATURES GENERAL DESCRIPTION Frequency band: 57 GHz to 64 GHz Radio frequency (RF) signal modulation bandwidth: up to 1.8 GHz Noise figure (NF): 8 dB typical Receiver gain: 0 dB to 69 dB Digital and analog RF and intermediate frequency (IF) gain control Programmable baseband gain and filter bandwidth Integrated frequency synthesizer Integrated image reject filter Partially external loop filter Support for external local oscillator (LO) On-chip temperature sensor Support for 256 quadrature amplitude modulation (QAM) Integrated AM and FM detectors Universal analog I/Q baseband interface 3-wire serial digital interface 75-ball, RoHS compliant, wafer level ball grid array The HMC6301 is a complete millimeterwave receiver integrated circuit in a 6 mm × 4 mm, RoHS compliant, wafer level ball grid array (WLBGA) that includes a low noise amplifier (LNA), an image reject filter, an RF to IF downconverter, an IF filter, an I/Q downconverter, and a frequency synthesizer. The receiver operates from 57 GHz to 64 GHz with up to 1.8 GHz of doublesided modulation bandwidth. An integrated synthesizer provides tuning in 250 MHz, 500 MHz, or 540 MHz steps with excellent phase noise to support up to 64 QAM modulation. Optionally, an external LO can be injected allowing for user selectable LO characteristics or phase coherent transmit and receive operation, as well as modulation up to 256 QAM. Support for a wide variety of modulation formats is provided through a universal analog baseband I/Q interface. The receiver device also contains AM and FM detectors to demodulate on-off keying (OOK), frequency-shift keying (FSK), or minimum-shift keying (MSK) modulation formats for lower cost and lower power serial data links without the need for high speed data converters. APPLICATIONS Small cell backhaul 60 GHz industrial, scientific, and medical (ISM) band data transfer Multiple Gbps data communication WiGig/802.11ad radio High definition video transmission Radar/high resolution imaging Gain control is provided in the RF, IF, and baseband stages and a low 8 dB typical noise figure is supported at maximum gain. Together with the HMC6300 transmitter, a complete 60 GHz transmit/receive chipset is provided for multiple Gbps operation in the unlicensed 60 GHz ISM band. VOUT_IP VOUT_IM VOUT_QP VOUT_QM FUNCTIONAL BLOCK DIAGRAM SCANOUT DATA HMC6301 INTERFACE SERIAL BBVGA CLK MUX PFD MUX REFCLK_M REFCLK_P ÷2 DIV DISCR FM 90° 0° CP AMDET RFIN LNA AMP IF ×3 MUX EXTLO_N EXTLO_P 14424-001 LPF Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC6301 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................6  Applications ....................................................................................... 1  Pin Configuration and Function Descriptions..............................7  General Description ......................................................................... 1  Typical Performance Characteristics ..............................................9  Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 12  Revision History ............................................................................... 2  Register Array Assignment and Serial Interface .................... 12  Specifications..................................................................................... 3  Receiver Register Array Assignments...................................... 13  Electrical Specifications ............................................................... 3  Applications Information .............................................................. 21  Recommended Operating Conditions ...................................... 4  Outline Dimensions ....................................................................... 24  Power Consumption .................................................................... 5  Ordering Guide .......................................................................... 24  Absolute Maximum Ratings............................................................ 6  REVISION HISTORY 9/2016—v00.0716 to Rev. A Updated Format .................................................................. Universal Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Parameter and Symbols Columns, Table 3 ............... 5 Changes to Figure 17 ...................................................................... 17 Added Ordering Guide .................................................................. 24 7/2016—Revision v00.0716: Initial Version Rev. A | Page 2 of 24 Data Sheet HMC6301 SPECIFICATIONS TA = 25°C, reference frequency = 71.4286 MHz, gain settings = maximum, IF bandwidth = maximum, input impedance = 50 Ω single ended, output impedance = 100 Ω differential, unless otherwise noted. ELECTRICAL SPECIFICATIONS Table 1. Parameter FREQUENCY RANGE FREQUENCY STEP SIZE MODULATION BANDWIDTH GAIN Maximum Receiver Gain Minimum Receiver Gain Baseband Gain Control IF Gain Control (Analog/Digital) LNA Gain Control (Analog/Digital) NOISE FIGURE INPUT For 1 dB Compression (P1dB) Third-Order Intercept (IP3) TEMPERATURE SENSOR RANGE SUPPRESSION AND REJECTION Image Rejection (3 × LO − IF) Sideband Suppression (I/Q Balance) PHASE Phase Noise @ 100 kHz Offset @1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset Phase-Locked Loop (PLL) Bandwidth POWER DISSIPATION Single-Ended External LO Test Conditions/Comments Min 57 With 71.4286 MHz reference clock With 142.857 MHz reference clock With 154.2857 MHz reference clock Maximum bandwidth setting 3 dB bandwidth 5 dB bandwidth 63 High and low gain settings At maximum gain Minimum LNA gain Typ Max 64 250 500 540 Unit GHz MHz MHz MHz 1.4 1.8 GHz GHz 69 0 41 12/15 20/20 8 13.5 dB dB dB dB dB dB +85 dBm dBm °C −19 −9 Four levels −40 20 Using internal filter Rev. A | Page 3 of 24 >35 23 dBc dBc −75 −93 −114 −122 300 dBc/Hz dBc/Hz dBc/Hz dBc/Hz kHz 0.82 0.57 W W HMC6301 Data Sheet RECOMMENDED OPERATING CONDITIONS Table 2. Parameter POWER SUPPLY Buffer Low Noise Amplifier (LNA) Tripler Divider Voltage Controlled Oscillator (VCO) Intermediate Frequency Mixer Synthesizer Digital Circuit INPUT VOLTAGE RANGE Serial Digital Interface Logic High Logic Low REFERENCE CLOCK Reference Clock, Positive LVPECL/LVDS CMOS Reference Clock, Negative LVPECL/LVDS CMOS BASEBAND I/Q In-Phase Baseband Input Negative (Minus) Positive Quadrature Baseband Input Negative (Minus) Positive BASEBAND I/Q, COMMON MODE In-Phase Baseband Input Negative (Minus) Positive Quadrature Baseband Input Negative (Minus) Positive ANALOG GAIN CONTROL Low Noise Amplifier IF Variable Gain Amplifier EXTERNAL LO Positive Negative DRAIN CURRENT 1.35 V 2.7 V Symbol Min Typ Max Unit VCCBUF VDDLNA VCCTRIP VCCDIV VCCVCO VCCIF VCCMIX VCCSYN VDDD 2.565 2.565 2.565 2.565 2.565 2.565 2.565 1.3 1.3 2.7 2.7 2.7 2.7 2.7 2.7 2.7 1.35 1.35 2.835 2.835 2.835 2.835 2.835 2.835 2.835 1.48 1.48 V dc V dc V dc V dc V dc V dc V dc V dc V dc 0.9 −0.05 1.2 +0.1 1.4 +0.3 V V DATA, ENABLE, CLK, RESET REFCLKP 3.3/2.5 1.2 V V V REFCLKN 3.3/2.5 1.2 V VOUT_IM VOUT_IP 10 10 50 50 200 200 mV p-p mV p-p VOUT_QM VOUT_QP 10 10 50 50 200 200 mV p-p mV p-p VOUT_IM VOUT_IP 1.3 1.3 V V VOUT_QM VOUT_QP 1.3 1.3 V V ANACTRLLNA ACTLIFVGA 0.1 0.1 EXTLO_P EXTLO_N 0 0 3 3