FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
APPLICATIONS
GND
VGG2
NIC
GND
RFIN
GND
NIC
GND
GND
NIC
NIC
NIC
VGG1
NIC
ACG3
GND
Military and space
Test instrumentation
GND
NIC
GND
RFOUT/VDD
GND
NIC
NIC
GND
PACKAGE
BASE
GND
16273-001
P1dB output power: 28 dBm typical
Gain: 15.5 dB typical
Output IP3: 39 dBm typical
Self biased at VDD = 12 V at 345 mA typical
Optional bias control on VGG1 for IDQ adjustment
Optional bias control on VGG2 for IP2 and IP3 optimization
50 Ω matched input/output
32-lead, 5 mm × 5 mm LFCSP package: 25 mm2
GND
NIC
ACG1
ACG2
NIC
NIC
NIC
GND
FEATURES
32
31
30
29
28
27
26
25
Data Sheet
GaAs, pHEMT, MMIC, Single Positive
Supply, DC to 7.5 GHz, 1 W Power Amplifier
HMC637BPM5E
Figure 1.
GENERAL DESCRIPTION
The HMC637BPM5E is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), cascode distributed
power amplifier. The device is self biased in normal operation
and features optional bias control for quiescent current (IDQ)
adjustment and for second-order intercept (IP2) and third-order
intercept (IP3) optimization. The amplifier operates from dc to
7.5 GHz, providing 15.5 dB of small signal gain, 28 dBm output
power at 1 dB gain compression, a typical output IP3 of 39 dBm,
Rev. A
and a 3.5 dB noise figure, while requiring 345 mA from a 12 V
supply voltage (VDD). Gain flatness is excellent from dc to 7.5 GHz
at ±0.5 dB typical, making the HMC637BPM5E ideal for military,
space, and test equipment applications. The HMC637BPM5E
also features inputs/outputs (I/Os) that are internally matched to
50 Ω, housed in a RoHS-compliant, 5 mm × 5 mm, premolded
cavity, lead frame chip scale package (LFCSP), making the device
compatible with high volume, surface-mount technology (SMT)
assembly equipment.
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HMC637BPM5E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Applications ...................................................................................... 1
Typical Performance Characteristic ...............................................7
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 17
General Description ......................................................................... 1
Applications Information ............................................................. 18
Revision History ............................................................................... 2
Typical Application Circuit ...................................................... 19
Specifications .................................................................................... 3
Evaluation PCB ............................................................................... 20
Frequency Range = DC to 7.5 GHz ........................................... 3
Bill of Materials .......................................................................... 20
Absolute Maximum Ratings ........................................................... 4
Outline Dimensions ....................................................................... 21
Thermal Resistance ...................................................................... 4
Ordering Guide .......................................................................... 21
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions ............................ 5
REVISION HISTORY
8/2020—Rev. 0 to Rev. A
Changes to Figure 17 Caption ........................................................ 8
Added Figure 68; Renumbered Sequentially .............................. 16
5/2018—Revision 0: Initial Version
Rev. A | Page 2 of 21
Data Sheet
HMC637BPM5E
SPECIFICATIONS
FREQUENCY RANGE = DC TO 7.5 GHz
TA = 25°C, VDD = 12 V, IDQ = 345 mA, VGG1 = GND, VGG2 = open, for nominal self biased operation, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Flatness
Gain Variation over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
P1dB
PSAT
IP3
SUPPLY
Current
IDQ
Voltage
Symbol
VDD
Min
DC
12.5
25
8
Typ
15.5
±0.5
±0.015
3.5
Unit
GHz
dB
dB
dB/°C
dB
15
15
dB
dB
28
30.5
39
dBm
dBm
dBm
345
mA
12
Max
7.5
13
Rev. A | Page 3 of 21
V
Test Conditions/Comments
Measurement taken at output power (POUT)/
tone = 10 dBm
For the external bias condition, adjust the gate
bias voltage (VGG1) between −2 V up to +0.5 V to
achieve the desired quiescent current (IDQ)
HMC637BPM5E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter1
Drain Bias Voltage (VDD)
Gate 1 Voltage (VGG1)
Gate 2 Voltage (VGG2)
Radio Frequency (RF) Input Power (RFIN)
Continuous Power Dissipation (PDISS),
T = 85°C (Derate 63.29 mW/°C
Above 85°C)
Output Load Voltage Standing Wave
Ratio (VSWR)
Storage Temperature Range
Operating Temperature Range
Maximum Peak Reflow Temperature
ESD Sensitivity
Human Body Model (HBM)
Junction Temperature to Maintain
1 Million Hour Mean Time to Failure
(MTTF)
Nominal Junction Temperature
(T = 85°C, VDD = 12 V)
1
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
14 V
−2 V to +1 V
3.5 V to 7 V
25 dBm
5.7 W
θJC is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package
CG-32-21
7:1
1
−65°C to +150°C
−55°C to +85°C
260°C
θJC
15.8
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with 36 thermal vias. See JEDEC JESD51.
ESD CAUTION
Class 1C
175°C
148.52°C
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed.
For full pin names of the multifunction pins, refer to the Pin Configuration
and Function Descriptions section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. A | Page 4 of 21
Data Sheet
HMC637BPM5E
32
31
30
29
28
27
26
25
GND
NIC
ACG1
ACG2
NIC
NIC
NIC
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC637BPM5E
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
NIC
GND
RFOUT/VDD
GND
NIC
NIC
GND
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
2. NIC = NOT INTERNALLY CONNECTED.
16273-002
GND
NIC
NIC
NIC
VGG1
NIC
ACG3
GND
9
10
11
12
13
14
15
16
GND
VGG2
NIC
GND
RFIN
GND
NIC
GND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 4, 6, 8, 9, 16, 17,
20, 22, 24, 25,
32
2
Mnemonic
GND
Description
Ground. These pins and the exposed pad must be connected to RF/dc ground.
VGG2
3, 7, 10 to 12, 14,
18, 19, 23, 26
to 28, 31
5
13
NIC
Gate Control 2 for the Amplifier. VGG2 is left open for self biased mode. Adjusting the voltage controls
the gain response. External capacitors are required (see Figure 70). See Figure 7 for the interface schematic.
Not Internally Connected. These pins must be connected to RF/dc ground.
15, 29, 30
ACG1, ACG2,
ACG3
RFOUT/VDD
21
RFIN
VGG1
EPAD
RF Input. This pin is dc-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
Optional Gate Control for the Amplifier. If this pin is grounded, the amplifier runs in self biased mode
at the standard current of 345 mA. Adjusting the voltage above or below the ground potential controls the
drain current. External capacitors are required (see Figure 70). See Figure 8 for the interface schematic.
Low Frequency Termination. External bypass capacitors are required on these pins (see Figure 70). See
Figure 4 and Figure 5 for the interface schematics.
RF Output for the Amplifier (RFOUT).
Drain Bias Voltage (VDD). Connect the dc bias (VDD) network to provide the drain current, IDD (see Figure 70).
See Figure 5 for the interface schematic.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
Rev. A | Page 5 of 21
HMC637BPM5E
Data Sheet
RFIN
Figure 3. GND Interface Schematic
Figure 6. RFIN Interface Schematic
VDD
ACG3
RFOUT/VDD
16273-007
ACG2
16273-004
RFIN
16273-006
GND
16273-003
INTERFACE SCHEMATICS
RFOUT/VDD
16273-005
ACG1
ACG2
VGG1
Figure 5. RFOUT/VDD, ACG1, ACG2 Interface Schematic
16273-008
Figure 7. VGG2 Interface Schematic
Figure 4. ACG3 Interface Schematic
Figure 8. VGG1 Interface Schematic
Rev. A | Page 6 of 21
Data Sheet
HMC637BPM5E
TYPICAL PERFORMANCE CHARACTERISTIC
20
18
15
17
16
5
15
S11
S21
S22
0
GAIN (dB)
–5
–10
12
10
1
3
2
4
5
6
8
7
9
10
8
16273-009
0
FREQUENCY (GHz)
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
Figure 9. Gain and Return Loss Response vs. Frequency, Self Biased Mode,
VDD = 12 V, VGG1 = GND, VGG2 = Open
Figure 12. Gain vs. Frequency for Various Temperatures, Self Biased Mode,
VDD = 12 V, VGG1 = GND, VGG2 = Open
18
18
17
16
16
15
15
14
14
GAIN (dB)
17
13
12
11
13
12
11
8V
9V
10V
11V
12V
13V
9
0
1
9
2
3
4
5
6
7
8
FREQUENCY (GHz)
8
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
Figure 10. Gain vs. Frequency for Various Supply Voltages (VDD), Self Biased
Mode, VGG1 = GND, VGG2 = Open
Figure 13. Gain vs. Frequency for Various Supply Currents (IDD), Externally
Biased Mode, VDD = 12 V, VGG2 = Open, Controlled VGG1
18
0
4V
5V (SELF BIASED)
6V
17
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
10
16273-010
10
8
–55°C
+25°C
+85°C
9
16273-012
–20
GAIN (dB)
13
11
–15
–25
14
16273-013
RESPONSE (dB)
10
–55°C
+25°C
+85°C
16
–5
RETURN LOSS (dB)
GAIN (dB)
15
14
13
12
11
–10
–15
10
0
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
–20
0
1
2
3
4
5
FREQUENCY (GHz)
Figure 11. Gain vs. Frequency for Various VGG2 Values, VDD = 12 V, VGG1 = GND
Rev. A | Page 7 of 21
6
7
8
16273-014
8
16273-011
9
Figure 14. Input Return Loss vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG1 = GND, VGG2 = Open
HMC637BPM5E
0
0
8V
9V
10V
11V
12V
13V
–10
–15
1
3
2
4
5
6
7
8
–20
0
4V
5V (SELF BIASED)
6V
–5
3
4
5
6
7
8
–55°C
+25°C
+85°C
–5
RETURN LOSS (dB)
–10
–15
–10
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
–20
2
3
4
5
6
7
8
Figure 19. Output Return Loss vs. Frequency for Various Temperatures,
Self Biased Mode, VDD =12 V, VGG2 = Open, VGG1 = GND
0
8V
9V
10V
11V
12V
13V
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
–5
RETURN LOSS (dB)
–5
1
FREQUENCY (GHz)
Figure 16. Input Return Loss vs. Frequency for Various VGG2 Values,
VDD = 12 V, VGG1= GND
0
0
16273-019
0
16273-016
–15
–10
–15
–10
–15
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
–20
16273-017
0
0
1
2
3
4
5
FREQUENCY (GHz)
Figure 17. Output Return Loss vs. Frequency for Various Supply Voltages
(VDD), Self Biased Mode, VGG2 = Open, VGG1 = GND
6
7
8
16273-020
RETURN LOSS (dB)
2
Figure 18. Input Return Loss vs. Frequency for Various Supply Currents (IDD),
Externally Biased Mode, VDD = 12 V, VGG2 = Open, Controlled VGG1
0
RETURN LOSS (dB)
1
FREQUENCY (GHz)
Figure 15. Input Return Loss vs. Frequency for Various Supply Voltages (VDD),
Self Biased Mode, VGG2 = Open, VGG1 = GND
–20
0
16273-018
0
FREQUENCY (GHz)
–20
–10
–15
16273-015
–20
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
–5
RETURN LOSS (dB)
–5
RETURN LOSS (dB)
Data Sheet
Figure 20. Output Return Loss vs. Frequency for Various Supply Currents (IDD),
External Biased condition, VDD = 12 V, VGG2 = Open, Controlled VGG1
Rev. A | Page 8 of 21
Data Sheet
0
HMC637BPM5E
0
4V
5V (SELF BIASED)
6V
–20
ISOLATION (dB)
–5
RETURN LOSS (dB)
–55°C
+25°C
+85°C
–10
–10
–15
–30
–40
–50
–60
–70
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
–90
16273-021
–20
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
16273-024
–80
Figure 24. Reverse Isolation vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG2 = Open, VGG1 = GND
Figure 21. Output Return Loss vs. Frequency for Various VGG2 Values,
VDD = 12 V, VGG1 = GND
10
16
–55°C
+25°C
+85°C
14
–55°C
+25°C
+85°C
9
8
NOISE FIGURE (dB)
NOISE FIGURE (dB)
12
10
8
6
7
6
5
4
3
4
2
2
0.04
0.06
0.10
0.08
FREQUENCY (GHz)
0
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
16273-025
0.02
0
16273-022
0
1
Figure 25. Noise Figure vs. Frequency for Various Temperatures, Self Biased
Mode, VDD = 12 V, VGG2 = Open, VGG1 = GND
Figure 22. Noise Figure vs. Low Frequency for Various Temperatures,
Self Biased Mode, VDD =12 V, VGG2 = Open, VGG1 = GND
32
32
–55°C
+25°C
+85°C
28
28
P1dB (dBm)
P1dB (dBm)
24
24
20
20
16
0
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
8
16273-023
12
8V
9V
10V
11V
12V
13V
12
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
Figure 23. P1dB vs. Frequency for Various Temperatures, Self Biased Mode,
VDD = 12 V, VGG2 = Open, VGG1 = GND
Rev. A | Page 9 of 21
Figure 26. P1dB vs. Frequency for Various Supply Voltages (VDD),
VGG2 = Open, VGG1 = GND
16273-026
16
Data Sheet
32
32
28
28
24
24
P1dB (dBm)
20
16
16
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
2
3
4
5
6
7
8
FREQUENCY (GHz)
8
PSAT (dBm)
28
26
24
20
20
3
4
5
6
7
8
FREQUENCY (GHz)
18
32
30
30
28
28
PSAT (dBm)
32
26
24
0
1
2
3
8V
9V
10V
11V
12V
13V
0
1
2
3
4
5
6
7
8
26
24
22
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
4V
5V (SELF BIASED)
6V
20
4
5
FREQUENCY (GHz)
6
7
8
18
16273-029
PSAT (dBm)
34
18
8
Figure 31. PSAT vs. Frequency for Various Supply Voltages (VDD), VGG2 = Open,
VGG1 = GND
34
20
7
FREQUENCY (GHz)
Figure 28. PSAT vs. Frequency for Various Temperatures, Self Biased Mode,
VDD = 12 V, VGG2 = Open, VGG1 = GND
22
6
24
22
2
5
26
22
16273-028
PSAT (dBm)
28
1
4
32
30
0
3
34
30
18
2
Figure 30. P1dB vs. Frequency for Various VGG2 Values, VDD = 12 V, VGG1 = GND
–55°C
+25°C
+85°C
32
1
FREQUENCY (GHz)
Figure 27. P1dB vs. Frequency for Various Supply Currents (IDD),
Externally Biased Mode, VDD = 12 V, VGG2 = Open, Controlled VGG1
34
0
16273-030
1
4V
5V (SELF-BIASED)
6V
16273-031
0
12
16273-027
12
8
20
Figure 29. PSAT vs. Frequency for Various Supply Currents (IDD), VDD = 12 V,
VGG2 = Open, Controlled VGG1
0
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
16273-032
P1dB (dBm)
HMC637BPM5E
Figure 32. PSAT vs. Frequency for Various VGG2 Values, VDD = 12 V, VGG1 = GND
Rev. A | Page 10 of 21
Data Sheet
HMC637BPM5E
30
30
–55°C
+25°C
+85°C
25
25
20
10
10
5
5
1
0
2
5
4
3
6
7
8
FREQUENCY (GHz)
0
30
25
25
20
20
PAE (%)
15
8
7
4V
5V (SELF BIASED)
6V
10
3
2
4
5
6
7
8
0
420
30
390
15
375
10
360
5
345
2
4
6
8
10
12
14
16
18
IDD (mA)
20
POUT (dBm), GAIN (dB), PAE (%)
35
405
5
6
7
8
Figure 37. PAE vs. Frequency for Various VGG2 Values, VDD =12 V,
VGG1 = GND, PAE Measured at PSAT
435
25
4
3
2
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 35. POUT, Gain, PAE, and IDD vs. Input Power, 1 GHz, VDD = 12 V,
VGG1= GND, VGG2 = Open
420
405
20
390
15
375
10
360
5
345
0
330
20
435
POUT
GAIN
PAE
IDD
25
16273-035
POUT
GAIN
PAE
IDD
1
0
16273-037
1
16273-034
0
5
Figure 34. PAE vs. Frequency for Various Supply Currents (IDD),
VDD = 12 V, VGG2 = Open, Controlled VGG1, PAE Measured at PSAT
POUT (dBm), GAIN (dB), PAE (%)
6
15
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
FREQUENCY (GHz)
0
5
0
2
4
6
8
10
12
14
16
18
IDD (mA)
PAE (%)
30
5
0
4
3
2
Figure 36. PAE vs. Frequency for Various Supply Voltages (VDD),
VGG2 = Open, VGG1 = GND, PAE Measured at PSAT
10
30
1
0
FREQUENCY (GHz)
Figure 33. Power Added Efficiency (PAE) vs. Frequency for Various Temperatures,
Self Biased Mode, VDD = 12 V, VGG2 = Open, VGG1 = GND, PAE Measured at PSAT
0
8V
9V
10V
11V
12V
13V
330
20
INPUT POWER (dBm)
Figure 38. POUT, Gain, PAE, and IDD vs. Input Power, 3 GHz, VDD = 12 V,
VGG1 = GND, VGG2 = Open
Rev. A | Page 11 of 21
16273-038
0
35
15
16273-036
PAE (%)
15
16273-033
PAE (%)
20
HMC637BPM5E
6
4
390
15
375
10
360
5
345
1
330
20
0
0
2
4
6
8
10
12
14
16
18
16273-039
0
IDD (mA)
20
INPUT POWER (dBm)
45
45
40
40
35
35
30
25
1
2
3
4
5
6
7
8
16273-040
0
40
35
35
OUTPUT IP3 (dBm)
40
30
25
8V
9V
10V
11V
12V
13V
3
0
1
2
3
4
5
6
7
8
30
25
15
4
5
FREQUENCY (GHz)
6
7
8
10
16273-041
2
20
20
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
1
16
Figure 43. Output IP3 vs. Frequency for Various Supply Voltages (VDD),
VGG2 = Open, VGG1 = GND, POUT/Tone = 10 dBm
45
0
12
FREQUENCY (GHz)
45
15
8
25
10
Figure 40. Output IP3 vs. Frequency for Various Temperatures, POUT/Tone =
10 dBm, Self Biased Mode, VDD = 12 V, VGG2 = Open, VGG1 = GND
20
4
30
15
–55°C
+25°C
+85°C
FREQUENCY (GHz)
10
0
20
15
10
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
Figure 42. Power Dissipation vs. Input Power at TA = 85°C, VDD = 12 V,
VGG1 = GND, VGG2 = Open
20
OUTPUT IP3 (dBm)
2
INPUT POWER (dBm)
OUTPUT IP3 (dBm)
OUTPUT IP3 (dBm)
Figure 39. POUT, Gain, PAE, and IDD vs. Input Power, 6 GHz, VDD = 12 V,
VGG1= GND, VGG2 = Open
3
16273-043
405
25
MAXIMUM PDISS
5
16273-042
420
Figure 41. Output IP3 vs. Frequency for Various Supply Current (IDD),
VDD = 12 V, VGG2 = Open, Controlled VGG1, POUT/Tone = 10 dBm
4V
5V (SELF BIASED)
6V
0
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
16273-044
30
POUT (dBm), GAIN (dB), PAE (%)
435
POUT
GAIN
PAE
IDD
POWER DISSIPATION (W)
35
Data Sheet
Figure 44. Output IP3 vs. Frequency for Various VGG2 Values, VDD = 12 V,
VGG1 = GND, POUT/Tone = 10 dBm
Rev. A | Page 12 of 21
Data Sheet
HMC637BPM5E
45
100
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
90
40
70
IM3 (dBc)
OUTPUT IP3 (dBm)
80
35
30
25
60
50
40
30
20
20
2
3
4
5
6
7
8
FREQUENCY (GHz)
0
80
80
70
IM3 (dBc)
50
40
50
40
30
20
20
10
10
5
10
15
20
POUT/TONE (dBm)
0
70
70
IM3 (dBc)
40
60
50
40
30
20
20
10
10
10
15
20
POUT/TONE (dBm)
16273-047
30
5
20
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
80
50
0
15
90
60
0
10
100
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
80
5
Figure 49. IM3 vs. POUT/Tone, VDD = 10 V, VGG2 = Open, VGG1 = GND
100
90
0
POUT/TONE (dBm)
Figure 46. Third-Order Intermodulation Distortion Relative to Carrier (IM3) vs.
POUT/Tone, VDD = 9 V, VGG2 = Open, VGG1 = GND
IM3 (dBc)
60
30
0
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
90
60
0
20
15
100
16273-046
IM3 (dBc)
70
10
Figure 48. IM3 vs. POUT/Tone, VDD = 8 V, VGG2 = Open, VGG1 = GND
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
90
5
POUT/TONE (dBm)
Figure 45. Output IP3 vs. Frequency for Various POUT/Tone, VDD = 12 V,
VGG2 = Open, VGG1 = GND
100
0
16273-048
1
16273-049
0
10
16273-045
10
0dBm
10dBm
20dBm
Figure 47. IM3 vs. POUT/Tone, VDD = 11 V, VGG2 = Open, VGG1 = GND
0
0
5
10
POUT/TONE (dBm)
15
20
16273-050
15
Figure 50. IM3 vs. POUT/Tone, VDD = 12 V, VGG2 = Open, VGG1 = GND
Rev. A | Page 13 of 21
HMC637BPM5E
Data Sheet
60
100
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
80
IM3 (dBc)
70
–55°C
+25°C
+85°C
50
OUTPUT IP2 (dBm)
90
60
50
40
30
20
40
30
20
10
0
15
10
5
0
16273-051
20
POUT/TONE (dBm)
2
3
4
5
6
7
8
FREQUENCY (GHz)
70
60
60
OUTPUT IP2 (dBm)
50
40
30
20
50
40
30
20
8V
9V
10V
11V
12V
13V
10
0
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
10
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
0
16273-052
OUTPUT IP2 (dBm)
1
Figure 54. Output IP2 vs. Frequency for Various Temperatures, POUT/Tone =
10 dBm, VDD =12 V, VGG2 = Open, VGG1 = GND (Self Biased)
Figure 51. IM3 vs. POUT/Tone, VDD = 13 V, VGG2 = Open, VGG1 = GND
0
0
Figure 52. Output IP2 vs. Frequency for Various Supply Voltages (VDD),
VGG2 = Open, VGG1 = GND, POUT/Tone = 10 dBm
0
1
2
3
4
5
6
0dBm
10dBm
20dBm
4V
5V (SELF BIASED)
6V
55
8
Figure 55. Output IP2 vs. Frequency for Various Supply Currents (IDD),
VDD = 12 V, VGG2 = Open, Controlled VGG1, POUT/Tone = 10 dBm
60
60
7
FREQUENCY (GHz)
16273-055
0
16273-054
10
50
45
OUTPUT IP2 (dBm)
OUTPUT IP2 (dBm)
50
40
35
30
40
30
20
25
20
10
0
1
2
3
4
5
FREQUENCY (GHz)
6
7
8
0
16273-053
10
0
1
2
3
4
5
FREQUENCY (GHz)
Figure 53. Output IP2 vs. Frequency for Various VGG2 Values, VDD =12 V,
VGG1 = GND, POUT/Tone = 10 dBm
6
7
8
16273-056
15
Figure 56. Output IP2 vs. Frequency for Various POUT/Tone Values, VDD = 12 V,
VGG2 = Open, VGG1 = GND
Rev. A | Page 14 of 21
Data Sheet
60
HMC637BPM5E
60
–55°C
+25°C
+85°C
50
40
30
20
10
20
2
3
4
5
6
7
8
0
50
50
SECOND HARMONIC (dBc)
60
40
30
20
345mA (SELF BIASED)
250mA
300mA
350mA
400mA
450mA
2
3
4
5
6
7
8
FREQUENCY (GHz)
4
5
6
7
8
4V
5V (SELF BIASED)
6V
40
30
20
0
1
2
3
4
5
6
7
8
FREQUENCY (GHz)
Figure 58. Second Harmonic vs. Frequency for Various Supply Currents (IDD),
VDD = 12 V, VGG2 = Open, Controlled VGG1, POUT = 10 dBm
Figure 61. Second Harmonic vs. Frequency for Various VGG2 Values,
VDD = 12 V, VGG1 = GND, POUT = 10 dBm
60
500
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
475
50
450
40
IDD (mA)
425
30
0
1
2
350
325
3
4
5
FREQUENCY (GHz)
6
7
8
300
0
4
8
12
16
20
INPUT POWER (dBm)
Figure 59. Second Harmonic vs. Frequency for Various POUT Values,
VDD = 12 V, VGG2 = Open, VGG1 = GND (Self Biased)
Figure 62. IDD vs. Input Power for Various Frequencies, VDD = 12 V,
VGG2 = Open, VGG1 = GND
Rev. A | Page 15 of 21
16273-062
10
400
375
10dBm
12dBm
14dBm
16dBm
18dBm
20dBm
22dBm
24dBm
20
16273-059
SECOND HARMONIC (dBc)
3
10
16273-058
1
2
Figure 60. Second Harmonic vs. Frequency for Various Supply Voltages (VDD),
POUT = 10 dBm, VGG2 = Open, VGG1 = GND
60
10
1
FREQUENCY (GHz)
Figure 57. Second Harmonic vs. Frequency for Various Temperatures,
POUT = 10 dBm, VDD = 12 V, VGG2 = Open, VGG1 = GND (Self Biased)
0
8V
9V
10V
11V
12V
13V
16273-061
1
FREQUENCY (GHz)
SECOND HARMONIC (dBc)
30
10
16273-057
0
40
16273-060
SECOND HARMONIC (dBc)
SECOND HARMONIC (dBc)
50
HMC637BPM5E
Data Sheet
4.0
0.20
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
0.16
0.12
3.0
2.5
2.0
0.04
IGG2 (mA)
IGG1 (mA)
0.08
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
3.5
0
–0.04
1.5
1.0
0.5
0
–0.08
–0.5
–0.12
–1.0
–0.16
0
4
8
12
16
20
INPUT POWER (dBm)
–2.0
Figure 63. Gate 1 Current (IGG1) vs. Input Power for Various Frequencies,
VDD = 12 V, VGG2 = Open, VGG1 = GND
0
4
8
12
16
20
INPUT POWER (dBm)
16273-066
–1.5
16273-063
–0.20
Figure 66. Gate 2 Current (IGG2) vs. Input Power for Various Frequencies,
VDD = 12 V, VGG2 = 5 V, VGG1 = GND
525
400
450
390
380
375
370
IDD (mA)
IDD (mA)
300
225
360
350
340
150
330
75
320
0
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
VGG1 (V)
300
8
–90
380
–100
PHASE NOISE (dBc/Hz)
–80
390
360
350
340
330
–130
–140
–150
310
–170
5.00
5.25
5.50
5.75
VGG2 (V)
Figure 65. IDD vs. VGG2, VDD = 12 V, VGG1 = GND
13
–120
–160
4.75
12
–110
320
6.00
–180
100
16273-065
IDD (mA)
370
4.50
11
Figure 67. IDD vs. VDD, VGG2 = Open, VGG1 = GND
400
4.25
10
VDD (V)
Figure 64. IDD vs. VGG1, VDD = 12 V, VGG2 = Open
300
4.00
9
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
16273-168
–1.25
16273-067
310
16273-064
–75
–1.50
Figure 68. Additive Phase Noise vs. Offset Frequency, RF Frequency =
6 GHz, RF Input Power = 1 dBm (P1dB)
Rev. A | Page 16 of 21
Data Sheet
HMC637BPM5E
THEORY OF OPERATION
The HMC637BPM5E is a GaAs, MMIC, pHEMT, cascode distributed power amplifier. The cascode distributed architecture of
the HMC637BPM5E uses a fundamental cell consisting of a
stack of two field effect transistors (FETs) with the source of the
upper FET connected to the drain of the lower FET. The
fundamental cell is then duplicated several times with an RFIN
transmission line interconnecting the gates of the lower FETs
and an RFOUT transmission line interconnecting the drains of
the upper FETs.
ACG1 ACG2
T-LINE
RFOUT/
VDD
VDD
For simplified biasing without the need for a negative voltage
rail, VGG1 can be connected directly to GND. With VDD = 12 V
and VGG1 grounded, a quiescent drain current of 345 mA (typical)
results. An externally generated VGG1 voltage can optionally be
applied, allowing adjustment of the quiescent drain current
above and below the 345 mA nominal value. As an example,
Figure 64 shows that by adjusting VGG1 from −0.3 V to +0.3 V
(approximately), quiescent drain currents from 250 mA to
450 mA can be obtained.
The HMC637BPM5E has single-ended input and output ports
with impedances nominally equal to 50 Ω over the dc to 7.5 GHz
frequency range. Therefore, the device can be directly inserted
into a 50 Ω system with no required impedance matching circuitry.
Similarly, the input and output impedances are sufficiently stable
across variations in temperature and supply voltage so that no
impedance matching compensation is required. The RF output
port additionally functions as the VDD bias pin, requiring an RF
choke through which dc bias is applied.
VGG2
T-LINE
16273-068
RFIN
VGG1 ACG3
adjustment on performance is more apparent at lower operating
frequencies.
Figure 69. Simplified Schematic of the Cascode Distributed Amplifier
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth, output power, and noise
figure. The major benefit of this architecture is that a high
output level is maintained across a bandwidth far greater than
what a single instance of the fundamental cell provides. A
simplified schematic of this architecture is shown in Figure 69.
The gate bias voltages of the upper FETs are set internally by a
resistive voltage divider tapped off at VDD, resulting in a 5 V
bias for the nominal VDD value of 12 V. However, the VGG2 pin
is provided to allow the application of an externally generated
bias voltage within the range of 4 V up to 6 V. Application of
such a voltage allows adjustment of IP3 and IP2 by as much as
3 dB and 1.5 dB, respectively, while minimally affecting the gain,
noise figure, P1dB, PSAT, and PAE. The effect of this bias
Though the device technically operates down to dc, blocking
capacitors are recommended at the RF input and output ports
to prevent the stages with which they interface from loading the
dc bias supplies and suffering damage. The RF choke and blocking
capacitor at the RF output together constitute a bias tee. In
practice, the external RF choke and dc blocking capacitor
selections limit the lowest frequency of operation.
ACG1 through ACG3 are nodes at which ac terminations
(capacitors) to ground can be provided. The use of such
terminations serves to roll off the gain at frequencies below
200 MHz, allowing the flattest possible gain response to be
obtained over various frequencies.
It is critical to supply very low inductance ground connections
to the GND pins and to the package base exposed pad to ensure
stable operation. To achieve optimal performance from the
HMC637BPM5E and to prevent damage to the device, do not
exceed the absolute maximum ratings.
Rev. A | Page 17 of 21
HMC637BPM5E
Data Sheet
APPLICATIONS INFORMATION
Capacitive bypassing is required for VDD and VGG1, as shown in
the typical application circuit in Figure 70. Both the RFIN and
RFOUT/VDD pins are dc-coupled. Use of an external dc blocking
capacitor at RFIN is recommended. Use of an external RF
choke plus a dc blocking capacitor (for example, a bias tee) at
RFOUT/
VDD is required. For wideband applications, ensure that the
frequency responses of the external biasing and blocking
components are adequate for use across the entire frequency
range of the application.
The HMC637BPM5E operates in either self biased or externally
biased mode. To operate in self biased mode, ground the VGG1 pin
and leave VGG2 open. For the externally biased configuration,
adjust VGG1 within −2 V to +0.5 V to set the target drain current
and adjust VGG2 from 4 V to 6 V for IP2 and IP3 control.
The recommended bias sequence during power-up for self
biased operation is as follows:
1.
2.
3.
Turn off the RFIN signal.
Set VDD to 0 V.
1.
2.
3.
4.
5.
6.
Connect GND.
Set VGG1 to −2 V.
Set VDD to 12 V.
Increase VGG1 to achieve the desired quiescent current (IDQ).
Apply the RF signal.
When using the IP2/IP3 control function, apply a voltage
from 4 V to 6 V until the desired performance is obtained.
The recommended bias sequence during power-down for
externally biased operation is as follows:
1.
2.
3.
4.
5.
Turn off the RFIN signal.
Remove the VGG2 voltage.
Decrease VGG1 to −2 V to achieve a typical IDQ of 0 mA.
Set VDD to 0 V.
Set VGG1 to 0 V.
Adhere to the values shown in the Absolute Maximum Ratings
section.
Connect GND.
Set VDD to 12 V.
Apply the RF signal.
The recommended bias sequence during power-down for self
biased operation is as follows :
1.
2.
The recommended bias sequence during power-up for
externally biased operation is as follows:
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 70), and
biased per the conditions in this section. The bias conditions
described in this section are the operating points recommended
to optimize the overall device performance. Operation using
other bias conditions may result in performance that differs
from what is shown in the Typical Performance Characteristic
section. To obtain the best performance while avoiding damage
to the device, follow the recommended biasing sequences
described in this section.
Rev. A | Page 18 of 21
Data Sheet
HMC637BPM5E
connected to an external dc block at RFIN. Optional capacitors
can be used if the device is to be operated below 200 MHz.
TYPICAL APPLICATION CIRCUIT
In Figure 70, the drain bias (VDD) must be applied through an
external broadband bias tee connected at RFOUT/VDD and
NOTE 2
C1
1000pF
C9
4.7µF
VDD
32
31
30
29
28
27
26
25
C5
0.01µF
RFOUT
NOTE 1
9
10
11
12
13
14
15
16
NOTE 1
C2
1000pF
24
23
22
21
20
19
18
17
ACG3
RFIN
C6
0.01µF
1
2
3
4
5
6
7
8
ACG1
ACG2
VGG2
NOTE 2
C3
1000pF
C4
1000pF
C8
0.01µF
C10
4.7µF
C7
0.01µF
C11
4.7µF
Figure 70. Typical Application Circuit
Rev. A | Page 19 of 21
16273-069
VGG1
NOTES
1. DRAIN BIAS (VDD) MUST BE APPLIED THROUGH AN ETERNAL BIAS TEE CONNECTED
AT THE RFOUT/VDD PIN AND AN EXTERNAL DC BLOCK MUST BE CONNECTED AT THE RFIN PIN.
2. OPTIONAL CAPACITORS MUST BE USED IF THE DEVICE IS OPERATED BELOW 200MHz.
HMC637BPM5E
Data Sheet
EVALUATION PCB
to the ground plane, similar to what is shown in Figure 71. Use
a sufficient number of via holes to connect the top and bottom
ground planes, including the grounds directly beneath the ground
pad to provide adequate electrical and thermal conduction. Use
of a heat sink on the bottom side of the PCB is recommended.
The evaluation PCB shown in Figure 71 is available from
Analog Devices, Inc., upon request.
The EV1HMC637BPM5 (600-01711-00) evaluation PCB is
shown in Figure 71.
BILL OF MATERIALS
Use RF circuit design techniques for the circuit board used in
the application. Provide 50 Ω impedance for the signal lines
and directly connect the package ground leads and exposed pad
THRU
CAL
C1
C5
J3
C6
C2
J2
U1
C3
C7
+ C10
C11
R1
C4
C8
J1
RFOUT
+
RFIN
C9
600-01711-00-1
GND CTNL
+
J4
16273-070
GND VGG
Figure 71. Evaluation PCB
Table 5. Bill of Materials for the Evaluation PCB EV1HMC637BPM5 (600-01711-00)
Item
J1, J2
J3, J4
C1, C2, C3, C4
C5, C6, C7, C8
C9, C10, C11
R1
U1
PCB
Description
PCB Mount K connectors
DC pins
1000 pF capacitors, 0402 package
10000 pF capacitors, 0402 package
4.7 µF capacitors, tantalum, 1206 package
0 Ω resistor, 0402 package
HMC637BPM5E
600-01711-00 evaluation PCB; circuit board material: Rogers 4350 or Arlon 25FR
Rev. A | Page 20 of 21
Data Sheet
HMC637BPM5E
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
25
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
8
17
0.45
0.40
0.35
TOP VIEW
PKG-005068
1.35
1.25
1.15
0.60 REF SIDE VIEW
9
16
BOTTOM VIEW
0.40
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
24
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-19-2017-A
PIN 1
INDICATOR
0.30
0.25
0.20
Figure 72. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeter
ORDERING GUIDE
Model 1, 2
HMC637BPM5E
Temperature
−55°C to +85°C
MSL Rating 3
3
HMC637BPM5ETR
−55°C to +85°C
3
EV1HMC637BPM5
Description 4
32-Lead Lead Frame Chip Scale Package, Premolded
Cavity [LFCSP_CAV]
32-Lead Lead Frame Chip Scale Package, Premolded
Cavity [LFCSP_CAV]
Evaluation Board
All parts are RoHS Compliant.
When ordering the evaluation board only, reference the model number, EV1HMC637BPM5.
See the Absolute Maximum Ratings section for additional information.
4
The lead finish of the HMC637BPM5E and the HMC637BPM5ETR is nickel palladium gold (NiPdAu).
1
2
3
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16273-8/20(A)
Rev. A | Page 21 of 21
Package Option
CG-32-2
CG-32-2
