0.1 GHz to 18 GHz, GaAs SP4T Switch
HMC641A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RF2
RF1
HMC641A
50Ω
RFC
50Ω
50Ω
RF3
RF4
GND
CTRLA
CTRLB
VSS
15148-001
50Ω
2 TO 4 LINE DECODER
Broadband frequency range: 0.1 GHz to 18 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.1 dB to 12 GHz
High isolation: 42 dB to 12 GHz
High input linearity
P1dB: 25 dBm typical at VSS = −5 V
IP3: 41 dBm typical
High power handling at VSS = −5 V
24 dBm through path
23 dBm terminated path
Integrated 2 to 4 line decoder
8-pad, 1.92 mm × 1.60 mm × 0.102 mm, CHIP
Figure 1.
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The HMC641A is a nonreflective, single-pole, four-throw
(SP4T) switch, manufactured using a gallium arsenide (GaAs)
process. This switch typically provides low insertion loss of
2.1 dB and high isolation of 42 dB in broadband frequency
range from 0.1 GHz to 18 GHz.
The switch operates with a negative supply voltage of −5 V to
−3 V and requires two negative logic control voltages.
All electrical performance data is acquired with the HMC641A
that all RFx pads are connected to by the 50 Ω transmission
lines via one 3.0 mil × 0.5 mil ribbon bond of minimal length.
The HMC641A includes an on-chip, binary 2 to 4 line decoder
that provides control from two logic input lines.
Rev. D
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©2018 Analog Devices, Inc. All rights reserved.
Technical Support
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HMC641A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications ....................................................................................... 1
Insertion Loss, Return Loss, and Isolation ................................6
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Input Power Compression (P1dB) and Third-Order Intercept
(IP3) ................................................................................................7
Revision History ............................................................................... 2
Theory of Operation .........................................................................8
Specifications..................................................................................... 3
Applications Information .................................................................9
Absolute Maximum Ratings ............................................................ 4
Mounting and Bonding Techniques ...........................................9
Power Derating Curve ................................................................. 4
Assembly Diagram ........................................................................9
ESD Caution .................................................................................. 4
Outline Dimensions ....................................................................... 10
Pin Configuration and Function Descriptions ............................. 5
Ordering Guide .......................................................................... 10
Interface Schematics..................................................................... 5
REVISION HISTORY
10/2018—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 10
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
3/2017—Rev. 02.0316 to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................ 1
Changed VSS = −5 V to VSS = −5 V to −3 V, Table 1 ..................... 3
Changes to Table 1 ............................................................................ 3
Deleted Bias Voltage & Current Table, TTL/CMOS Control
Voltage Table, and Truth Table ....................................................... 3
Changes to Table 2 ............................................................................ 4
Added Power Derating Curve Section and Figure 2;
Renumbered Sequentially ................................................................4
Added Figure 4 ..................................................................................5
Deleted GND Interface Schematic Figure and TTL Interface
Circuit Figure .....................................................................................5
Changes to Table 3 and Figure 5......................................................5
Added Table 4; Renumbered Sequentially .....................................8
Added Theory of Operation Section ..............................................8
Added Applications Information Section, Figure 14, Figure 15,
and Assembly Diagram Section.......................................................9
Updated Outline Dimensions ....................................................... 10
Updated Ordering Guide .............................................................. 10
Rev. D | Page 2 of 10
Data Sheet
HMC641A
SPECIFICATIONS
VSS = −5 V to −3 V, VCTL = 0 V or VSS, TDIE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
BROADBAND FREQUENCY RANGE
INSERTION LOSS
Symbol
f
Third-Order Intercept
SUPPLY
Voltage
Current
DIGITAL CONTROL INPUTS
Voltage
Low
1
Min
0.1
0.1 GHz to 12 GHz
0.1 GHz to 18 GHz
ISOLATION
Between RFC and RF1 to RF4
RETURN LOSS
RFC
RF1 to RF4
On State
Off State
SWITCHING CHARACTERISTICS
Rise and Fall Time
On and Off Time
INPUT LINEARITY1
1 dB Compression
Test Conditions/Comments
0.1 GHz to 12 GHz
0.1 GHz to 18 GHz
tRISE, tFALL
tON, tOFF
P1dB
IP3
Typ
2.1
2.3
Unit
GHz
dB
dB
42
38
dB
dB
0.1 GHz to 18 GHz
15
dB
0.1 GHz to 18 GHz
0.1 GHz to 18 GHz
15
15
dB
dB
10% to 90% of RF output
50% VCTL to 90% of RF output
250 MHz to 18 GHz
VSS = −5 V
VSS = −3 V
10 dBm per tone, 1 MHz spacing
VSS = −5 V
VSS = −3 V
VSS pin
15
95
ns
ns
22
25
22
dBm
dBm
38
41
41
dBm
dBm
VSS
ISS
39
36
Max
18
2.4
3.0
−5
1.9
−3
6
V
mA
0
0
−4.2
−2.2
V
V
V
V
CTRLA and CTRLB pins
VCTL
VINL
High
VINH
Current
Low
High
ICTL
IINL
IINH
VSS = −5 V
VSS = −3 V
VSS = −5 V
VSS = −3 V
−3
−1
−5
−3
50
0.2
Input linearity performance degrades at frequencies less than 250 MHz; see Figure 10, Figure 11, Figure 12, and Figure 13.
Rev. D | Page 3 of 10
µA
µA
HMC641A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
POWER DERATING CURVE
Table 2.
1
2
Rating
−7 V
VSS − 0.5 V to +1 V
0
POWER DERATING (dB)
24 dBm
23 dBm
20 dBm
–2
–4
–6
–8
21 dBm
20 dBm
17 dBm
–10
0.01
0.1
1
FREQUENCY (GHz)
Figure 2. Power Derating at Frequencies Less Than 250 MHz
150°C
−55°C to +85°C
−65°C to +150°C
ESD CAUTION
201°C/W
322°C/W
250 V (Class 1A)
For power derating at frequencies less than 250 MHz, see Figure 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 4 of 10
15148-002
Parameter
Supply Voltage
Digital Control Input Voltage
RF Input Power1
(f = 250 MHz to 18 GHz, TDIE = 85°C)
VSS = −5 V
Through Path
Terminated Path
Hot Switching
VSS = −3 V
Through Path
Terminated Path
Hot Switching
Temperature
Junction Temperature, TJ
Die Bottom Temperature Range, TDIE
Storage Temperature Range
Junction to Die Bottom Thermal Resistance
Through Path
Terminated Path
ESD Sensitivity
Human Body Model (HBM)
Data Sheet
HMC641A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RF1
RF2
2
3
4
CTRLA
5
CTRLB
6
VSS
HMC641A
TOP VIEW
(Not to Scale)
8
7
RF4
15148-003
1
RFC
RF3
Figure 3. Pin Configuration
Table 3. Pad Function Descriptions1
Pad No.
1
Mnemonic
RFC
2
RF1
3
RF2
4
5
6
7
CTRLA
CTRLB
VSS
RF3
8
RF4
Die Bottom
GND
1
Description
RF Common Pad. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
RF Throw Pad 1. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
RF Throw Pad 2. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
Control Input A; see Table 4. See Figure 5 for the interface schematic.
Control Input B; see Table 4. See Figure 5 for the interface schematic.
Negative Supply Voltage.
RF Throw Pad 3. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
RF Throw Pad 4. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
Ground. Die bottom must be attached directly to the ground plane eutectically or with conductive epoxy.
No connection is required for the unlabeled grounds.
CTRLA,
CTRLB
500Ω
100kΩ
VSS
Figure 4. RFC to RF4 Interface Schematic
15148-005
RFC,
RF1,
RF2,
RF3,
RF4
15148-004
INTERFACE SCHEMATICS
Figure 5. CTRLA and CTRLB Interface Schematic
Rev. D | Page 5 of 10
HMC641A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
0
0
TDIE = +85°C
TDIE = +25°C
TDIE = –55°C
–1
INSERTION LOSS (dB)
–2
–3
–2
–3
–4
–4
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
–5
15148-006
–5
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
Figure 6. Insertion Loss Between RFC and RF1 vs. Frequency over
Temperature
15148-008
INSERTION LOSS (dB)
–1
RF1
RF2
RF3
RF4
Figure 8. Insertion Loss Between RFC and RF1 to RF4 vs. Frequency
0
0
RFC
RF1 TO RF4 ON
RF1 TO RF4 OFF
–5
RF1
RF2
RF3
RF4
–10
–20
ISOLATION (dB)
–30
–15
–20
–25
–40
–50
–60
–70
–30
–80
–35
–40
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
–100
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
Figure 7. Return Loss for RFC, RF1 to RF4 On and RF1 to RF4 Off vs.
Frequency
Figure 9. Isolation Between RFC and RF1 to RF4 vs. Frequency
Rev. D | Page 6 of 10
15148-009
–90
15148-007
RETURN LOSS (dB)
–10
Data Sheet
HMC641A
INPUT POWER COMPRESSION (P1dB) AND THIRD-ORDER INTERCEPT (IP3)
30
28
26
26
24
24
22
20
18
16
14
22
20
18
16
12
10
4
6
8
10
12
14
16
18
FREQUENCY (GHz)
0
45
45
40
40
INPUT IP3 (dBm)
50
35
30
4
6
8
10
12
14
16
18
FREQUENCY (GHz)
10
12
14
16
18
30
TDIE = +85°C
TDIE = +25°C
TDIE = –55°C
20
15148-011
2
8
35
25
TDIE = +85°C
TDIE = +25°C
TDIE = –55°C
0
6
Figure 12. Input P1dB vs. Frequency over Temperature, VSS = −3 V
50
20
4
FREQUENCY (GHz)
Figure 10. Input P1dB vs. Frequency over Temperature, VSS = −5 V
25
2
0
2
4
6
8
10
12
14
16
18
FREQUENCY (GHz)
Figure 11. Input IP3 vs. Frequency over Temperature, VSS = −5 V
Figure 13. Input IP3 vs. Frequency over Temperature, VSS = −3 V
Rev. D | Page 7 of 10
15148-013
2
15148-010
12
10
15148-012
14
0
INPUT IP3 (dBm)
TDIE = +85°C
TDIE = +25°C
TDIE = –55°C
28
INPUT P1dB (dBm)
INPUT P1dB (dBm)
30
TDIE = +85°C
TDIE = +25°C
TDIE = –55°C
HMC641A
Data Sheet
THEORY OF OPERATION
The HMC641A requires a negative supply voltage at the VSS pad
and two logic control inputs at the CTRLA and CTRLB pads to
control the state of the RF paths.
Depending on the logic level applied to the CTRLA and CTRLB
pads, one RF path is in the insertion loss state while the other
three paths are in an isolation state (see Table 4). The insertion loss
path conducts the RF signal between the RF throw pad and RF
common pad while the isolation paths provide high loss between
RF throw pads terminated to internal 50 Ω resistors and the
insertion loss path.
The ideal power-up sequence is as follows:
1.
2.
3.
4.
Ground to the die bottom.
Power up VSS.
Power up the digital control inputs. The relative order of the
logic control inputs is not important. However, powering the
digital control inputs before the VSS supply can inadvertently
become forward-biased and damage the internal electrostatic
discharge (ESD) protection structures.
Apply an RF input signal. The design is bidirectional; the
RF input signal can be applied to the RFC pad while the RF
throw pads are the outputs or the RF input signal can be
applied to the RF throw pads while the RFC pad is the
output. All of the RF pads are dc-coupled to 0 V, and no dc
blocking is required at the RF pads when the RF line
potential is equal to 0 V.
The power-down sequence is the reverse of the power-up
sequence.
Table 4. Control Voltage Truth Table
Digital Control Input
CTRLA
CTRLB
High
High
Low
High
High
Low
Low
Low
RF1 to RFC
Insertion loss (on)
Isolation (off )
Isolation (off )
Isolation (off )
RF2 to RFC
Isolation (off )
Insertion loss (on)
Isolation (off )
Isolation (off )
Rev. D | Page 8 of 10
RF Paths
RF3 to RFC
Isolation (off )
Isolation (off )
Insertion loss (on)
Isolation (off )
RF4 to RFC
Isolation (off )
Isolation (off )
Isolation (off )
Insertion loss (on)
Data Sheet
HMC641A
APPLICATIONS INFORMATION
MOUNTING AND BONDING TECHNIQUES
The HMC641A is back metallized and must be attached directly
to the ground plane with gold tin (AuSn) eutectic preforms or
with electrically conductive epoxy.
The die thickness is 0.102 mm (4 mil). The 50 Ω microstrip
transmission lines on 0.127 mm (5 mil) thick alumina thin film
substrates are recommended for bringing RF to and from the
HMC641A (see Figure 14).
When using 0.254 mm (10 mil) thick alumina thin film substrates,
the HMC641A must be raised 0.150 mm (6 mil) so the surface of
the HMC641A is coplanar with the surface of the substrate. One
way to accomplish this is by attaching the 0.102 mm (4 mil) thick
die to a 0.150 mm (6 mil) thick molybdenum heat spreader (moly
tab), which is then attached to the ground plane (see Figure 15).
0.102mm (0.004") THICK GaAs MMIC
RIBBON BOND
0.076mm
(0.003")
0.102mm (0.004") THICK GaAs MMIC
RIBBON BOND
0.076mm
(0.003")
0.150mm
(0.006”) THICK
MOLY TAB
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
RF GROUND PLANE
15148-015
RF GROUND PLANE
Microstrip substrates are placed as close to the HMC641A as
possible to minimize bond length. Typical die to substrate
spacing is 0.076 mm (3 mil).
RF bonds made with 3 mil × 5 mil ribbon are recommended.
DC bonds made with 1 mil diameter wire are recommended.
All bonds must be as short as possible.
ASSEMBLY DIAGRAM
An assembly diagram of the HMC641A is shown in Figure 16.
15148-016
Figure 14. Bonding RF Pads to 5 mil Substrate
15148-014
Figure 15. Bonding RF Pads to 10 mil Substrate
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
Figure 16. Die Assembly Diagram
Rev. D | Page 9 of 10
HMC641A
Data Sheet
OUTLINE DIMENSIONS
1.920
0.102
0.198 × 0.100
(Pads 2-3 and 7-8)
2
0.455
0.074 × 0.074
3
(Pads 4-6)
0.125
K6101
2015
4
0.206
1.600
0.100 × 0.198
0.548
1
0.203
5
6
0.457
7
TOP VIEW
0.127
0.100
0.140
(CIRCUIT SIDE)
0.200
0.200
0.661
0.200
0.200
0.114
SIDE VIEW
09-24-2018-B
8
0.122
0.266
Figure 17. 8-Pad Bare Die [CHIP]
(C-8-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
HMC641A
HMC641A-SX
1
2
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
8-Pad Bare Die [CHIP]
8-Pad Bare Die [CHIP]
The HMC641A is a RoHS compliant part.
The HMC641A-SX is a sample order model.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15148-0-10/18(D)
Rev. D | Page 10 of 10
Package Option
C-8-9
C-8-9
