0.1 GHz to 20 GHz
GaAs, Nonreflective, SP4T Switch
HMC641ALP4E
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
4
NIC
5
NIC
6
RF1
GND
GND
RF2
GND
19
18 NIC
50Ω
50Ω
17 GND
16 CTRLA
15 CTRLB
14 VSS
13 NIC
7
8
9
10
11
12
NIC = NOT INTERNALLY CONNECTED
PACKAGE
BASE
GND
16094-001
GND
20
2:4 DECODER
3
21
GND
RFC
22
RF3
2
23
GND
1
24
GND
NIC
GND
GND
HMC641ALP4E
RF4
Broadband frequency range: 0.1 GHz to 20 GHz
Nonreflective 50 Ω design
Low insertion loss: 3.0 dB at 20 GHz
High isolation: 40 dB at 20 GHz
High input linearity at 250 MHz to 20 GHz
P1dB: 24 dBm typical
IP3: 41 dBm typical
High power handling
26.5 dBm through path
23 dBm terminated path
Integrated 2 to 4 line decoder
24-lead, 4 mm × 4 mm LFCSP package
ESD rating: 250 V (Class 1A)
GND
FEATURES
Figure 1.
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The HMC641ALP4E is a general-purpose, nonreflective, singlepole, four-throw (SP4T) switch manufactured using a gallium
arsenide (GaAs) process. This switch offers high isolation, low
insertion loss, and on-chip termination of the isolated ports.
The HMC641ALP4E includes an on-chip, binary 2 to 4 line
decoder that provides logic control from two logic input lines.
The HMC641ALP4E comes in a 4 mm × 4 mm, 24-lead LFCSP
package and operates from 0.1 GHz to 20 GHz.
The switch operates with a negative supply voltage range of −5 V to
−3 V and requires two negative logic control voltages.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC641ALP4E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................5
Applications ....................................................................................... 1
Typical Performance Charcteristics ................................................6
Functional Block Diagram .............................................................. 1
Insertion Loss, Return Loss, and Isolation ................................6
General Description ......................................................................... 1
Input Power Compression and IP3 .............................................7
Revision History ............................................................................... 2
Theory of Operation .........................................................................8
Specifications..................................................................................... 3
Application Information ...................................................................9
Absolute Maximum Ratings............................................................ 4
Evaluation Board ...........................................................................9
Power Derating Curves ................................................................ 4
Outline Dimensions ....................................................................... 11
ESD Caution .................................................................................. 4
Ordering Guide .......................................................................... 11
Pin Configuration and Function Descriptions ............................. 5
REVISION HISTORY
8/2018—Rev. A to Rev. B
Changes to Insertion Loss, Between RFC and RF1 to RF4 (On)
Parameter, Table 1............................................................................. 3
Changed Reflow (MSL1 Rating) to Reflow, Table 2 ..................... 4
Deleted Note 2, Table 2; Renumbered Sequentially ..................... 4
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
7/2017—Rev. 00.1013 to Rev. A
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changes to Features Section, Applications Section, General
Description Section, and Figure 1 .................................................. 1
Deleted Truth Table, Bias Voltage and Current Table, and
TTL/CMOS Control Voltages Table .............................................. 3
Changes to Table 1 ............................................................................ 3
Added Power Derating Curves Section and Figure 2;
Renumbered Sequentially ................................................................4
Changes to Table 2.............................................................................4
Added Figure 4...................................................................................5
Changes to Figure 3, Table 3, and Figure 5 ....................................5
Deleted GND Interface Schematic ..................................................5
Changes to Typical Performance Characteristics Section ...........6
Added Theory of Operation Section and Table 4; Renumbered
Sequentially ........................................................................................8
Added Applications Information Section and Figure 14 .............9
Changes to Table 5.............................................................................9
Added Figure 16 ............................................................................. 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
Rev. B | Page 2 of 11
Data Sheet
HMC641ALP4E
SPECIFICATIONS
VSS = −3 V or −5 V, VCTRL = 0 V or VSS, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
INSERTION LOSS
Between RFC and RF1 to RF4 (On)
Symbol
f
0.1 GHz to 12 GHz
12 GHz to 20 GHz
RETURN LOSS
RFC and RF1 to RF4 (On)
On and Off Time
INPUT LINEARITY 1
1 dB Power Compression
Third-Order Intercept
SUPPLY
Voltage
Current
DIGITAL CONTROL INPUTS
Voltage
Low
High
Current
Low
High
1
Min
0.1
0.1 GHz to 12 GHz
12 GHz to 20 GHz
ISOLATION
Between RFC and RF1 to RF4 (Off )
RF1 to RF4 (Off )
SWITCHING
Rise and Fall Time
Test Conditions/Comments
tRISE, tFALL
tON, tOFF
P1dB
IP3
Max
20
Unit
GHz
2.0
3.0
3.2
4.2
dB
dB
42
40
dB
dB
0.1 GHz to 12 GHz
12 GHz to 20 GHz
0.1 GHz to 20 GHz
18
17
13
dB
10% to 90% of radio frequency (RF)
output
50% VCTL to 90% of RF output
250 MHz to 20 GHz
VSS = −5 V
VSS = −3 V
10 dBm per tone, 1 MHz spacing
VSS = −5 V
VSS = −3 V
VSS pin
30
ns
100
ns
24
22
dBm
dBm
41
41
dBm
dBm
VSS
ISS
30
30
Typ
20
−5
1.7
dB
−3
5
V
mA
0
0
−4.2
−2.2
V
V
V
V
CTRLA and CTRLB pins
VCTL
VINL
VINH
VSS = −5 V
VSS = −3 V
VSS = −5 V
VSS = −3 V
ICTL
IINL
IINH
−3
−1
−5
−3
30
0.5
Input linearity performance degrades at frequencies less than 250 MHz.
Rev. B | Page 3 of 11
µA
µA
HMC641ALP4E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
1
Rating
−7 V
VSS − 0.5 V to + 1 V
21 dBm
20 dBm
17 dBm
150°C
−65°C to +150°C
260°C
POWER DERATING CURVES
2
0
For power derating at frequencies less than 250 MHz, see Figure 2.
–4
–6
–8
201°C/W
321°C/W
250 V (Class 1A)
–2
–10
0.01
0.1
FREQUENCY (GHz)
1
16094-002
26.5 dBm
23 dBm
20 dBm
POWER DERATING (dB)
Parameter
Negative Supply Voltage (VSS)
Digital Control Input Voltage
RF Input Power1
(f = 250 MHz to 20 GHz, TCASE = 85°C)
VSS = −5 V
Through Path
Terminated Path
Hot Switching
VSS = −3 V
Through Path
Terminated Path
Hot Switching
Temperature
Junction, TJ
Storage
Reflow
Junction to Case Thermal Resistance, θJC
Through Path
Terminated Path
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Figure 2. Power Derating at Frequencies Less than 250 MHz
ESD CAUTION
Rev. B | Page 4 of 11
Data Sheet
HMC641ALP4E
GND
RF1
GND
GND
RF2
GND
24
23
22
21
20
19
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC 1
18
NIC
GND 2
17
GND
16
CTRLA
15
CTRLB
NIC 5
14
VSS
NIC 6
13
NIC
HMC641ALP4E
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THE PINS ARE
NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA
SHOWN IN THIS DATA SHEET IS MEASURED WITH
THESE PINS CONNECTED TO RF/DC GROUND
EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND OF THE PCB.
16094-002
9
RF4
GND 12
7
8
GND
RF3 11
TOP VIEW
(Not to Scale)
GND 4
GND 10
RFC 3
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 5, 6, 13, 18
Mnemonic
NIC
2, 4, 7, 9, 10, 12, 17,
19, 21, 22, 24
3
GND
8
RF4
11
RF3
14
15
16
20
VSS
CTRLB
CTRLA
RF2
23
RF1
RFC
EPAD
Description
Not Internally Connected. The pins are not connected internally; however, all data shown in this data sheet
is measured with these pins connected to RF/dc ground externally.
Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
Negative Supply Voltage Pin.
Control Input 2 Pin. See Table 4 for the control voltage truth table.
Control Input 1 Pin. See Table 4 for the control voltage truth table.
RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
500Ω
100kΩ
VSS
Figure 4. RFC to RF4 Interface Schematic
16094-004
CTRLA,
CTRLB
16094-003
RFC,
RF1,
RF2,
RF3,
RF4
Figure 5. CTRLA and CTRLB Interface Schematic
Rev. B | Page 5 of 11
HMC641ALP4E
Data Sheet
TYPICAL PERFORMANCE CHARCTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
0
0
+85°C
+25°C
–40°C
–1
INSERTION LOSS (dB)
–2
–3
RF1
RF2
RF3
RF4
–2
–3
0
4
12
8
16
20
24
FREQUENCY (GHz)
–5
16094-005
–5
0
4
8
12
16
20
24
FREQUENCY (GHz)
Figure 6. Insertion Loss Between RFC and RF1 vs. Frequency at Various
Temperatures
16094-007
–4
–4
Figure 8. Insertion Loss Between RFC to RFx vs. Frequency
0
0
RFC
RF1 TO RF4 ON
RF1 TO RF4 OFF
–5
RFC TO
RFC TO
RFC TO
RFC TO
–10
RF1
RF2
RF3
RF4
–20
ISOLATION (dB)
–10
–15
–20
–25
–30
–40
–50
–60
–30
–35
0
4
8
12
16
20
24
FREQUENCY (GHz)
16094-006
–70
Figure 7. Return Loss for RFC, RF1 to RF4 On, and RF1 to RF4 Off vs.
Frequency
–80
0
4
8
12
16
20
FREQUENCY (GHz)
Figure 9. Isolation Between RFC and RFx vs. Frequency
Rev. B | Page 6 of 11
24
16094-008
INSERTION LOSS (dB)
–1
RETURN LOSS (dB)
RFC TO
RFC TO
RFC TO
RFC TO
Data Sheet
HMC641ALP4E
INPUT POWER COMPRESSION AND IP3
30
20
15
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (GHz)
15
10
0
45
45
40
40
INPUT IP3 (dBm)
50
35
30
20
20
12
16
20
FREQUENCY (GHz)
10
12
14
16
18
20
22
15
16094-011
8
8
30
25
4
6
35
25
0
4
Figure 12. Input Compression vs. Frequency at Room Temperature,
VSS = −3 V
50
15
2
FREQUENCY (GHz)
Figure 10. Input Compression vs. Frequency at Room Temperature,
VSS = −5 V
INPUT IP3 (dBm)
20
0
4
8
12
16
FREQUENCY (GHz)
Figure 11. Input IP3 vs. Frequency at Room Temperature,
VSS = −5 V
Figure 13. Input IP3 vs. Frequency at Room Temperature,
VSS = −3 V
Rev. B | Page 7 of 11
20
16094-012
10
25
16094-010
INPUT COMPRESSION (dBm)
25
16094-009
INPUT COMPRESSION (dBm)
30
HMC641ALP4E
Data Sheet
THEORY OF OPERATION
The HMC641ALP4E requires a negative supply voltage at the
VSS pin and two logic control inputs at the CTRLA and CTRLB
pins to control the state of the RF paths.
Depending on the logic level applied to the CTRLA pin and the
CTRLB pin, one RF path is in the insertion loss state while the
other three paths are in an isolation state (see Table 4). The
insertion loss path conducts the RF signal between the RF throw
pin and RF common pin while the isolation paths provide high loss
between RF throw pins terminated to internal 50 Ω resistors and
the insertion loss path.
The ideal power-up sequence is as follows:
1.
2.
3.
4.
Ground to the die bottom.
Power up VSS.
Power up the digital control inputs. The relative order of the
logic control inputs is not important. However, powering the
digital control inputs before the VSS supply can inadvertently
become forward-biased and damage the internal ESD
protection structures.
Apply an RF input signal. The design is bidirectional; the RF
input signal can be applied to the RFC pin while the RF throw
pins are the outputs, or the RF input signal can be applied to
the RF throw pins while the RFC pin is the output. All of the
RF pins are dc-coupled to 0 V, and no dc blocking is required
at the RF pins when the RF line potential is equal to 0 V.
The power-down sequence is the reverse of the power-up
sequence.
Table 4. Control Voltage Truth Table
Digital Control Input
CTRLA
CTRLB
High
High
Low
High
High
Low
Low
Low
RFC to RF1
Insertion loss (on)
Isolation (off )
Isolation (off )
Isolation (off )
RFC to RF2
Isolation (off )
Insertion loss (on)
Isolation (off )
Isolation (off )
Rev. B | Page 8 of 11
RF Paths
RFC to RF3
Isolation (off )
Isolation (off )
Insertion loss (on)
Isolation (off )
RFC to RF4
Isolation (off )
Isolation (off )
Isolation (off )
Insertion loss (on)
Data Sheet
HMC641ALP4E
APPLICATION INFORMATION
Figure 15 shows the layout of the EV1HMC641ALP4 evaluation
board with component placement. Power supply port is connected
to the VSS test point, J8, and control voltages, CTRLA and CTRLB,
are connected to the A and B test points, J6 and J7, and the ground
reference is connected to the GND test point, J9. On the supply
trace, VSS, use a 1000 pF bypass capacitor to filter high
frequency noise.
EVALUATION BOARD
The EV1HMC641ALP4 is a 4-layer evaluation board. Each
copper layer is 0.5 oz (0.7 mil) and separated by dielectric
materials. Figure 14 shows the stack up for this
evaluation board.
W = 16mil
0.5oz Cu (0.7mil)
TOTAL THICKNESS
~62mil
RO4350
0.5oz Cu (0.7mil)
The RF input and output ports (RFC, RF1, RF2, RF3, and RF4)
are connected through 50 Ω transmission lines to the SMA
launchers, J1 to J5. These SMA launchers are soldered onto the
board. A through calibration line connects the unpopulated J10
and J11 launchers; this transmission line estimates the loss of
the PCB over the environmental conditions being evaluated, as
shown in Figure 16.
T = 0.7mil
H = 10mil
0.5oz Cu (0.7mil)
FR4-08
Table 5 shows the evaluation board components.
0.5oz Cu (0.7mil)
RO4350
0.5oz Cu (0.7mil)
16094-013
0.5oz Cu (0.7mil)
G = 13mil
Figure 14. The EV1HMC641ALP4 Evaluation Board (Cross Sectional View)
All RF and dc traces are routed on the top copper layer whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. Top dielectric
material is a 10 mil Rogers RO4350. The middle and bottom
dielectric materials provide mechanical strength. The overall
board thickness is approximately 62 mil, allowing the
subminiature version A (SMA) launchers to be connected at the
board edges.
Table 5. Evaluation Board Components
Component
J1 to J5
J6 to J9
J10, J11
C1
U1
PCB
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with trace width of 16 mil and
ground clearance of 13 mil for a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, arrange as many
plated through vias as possible around transmission lines and
under the exposed pad of the package.
Rev. B | Page 9 of 11
Default Value
Do not insert
1000 pF
600-00782-00-1
Description
PCB mount SMA connector
DC pin
PCB mount SMA connector
Capacitor, C0402 package
HMC641ALP4E SP4T switch
Evaluation PCB
Data Sheet
16094-014
HMC641ALP4E
Figure 15. The EV1HMC641ALP4 Evaluation Board Component Placement
J2
25
1
2
3
4
5
6
NIC
GND
RFC
GND
NIC
NIC
HMC641A
CTRLA
NIC
GND
CTRLA
CTRLB
VSS
NIC
18
17
16
15
14
13
CTRLB
VSS
GND
RF4
GND
GND
RF3
GND
J5
EPAD
GND
RF1
GND
GND
RF2
GND
24
23
22
21
20
19
J1
7
8
9
10
11
12
C1
1000pF
J4
J3
DNI
J11
DNI
Figure 16. The EV1HMC641ALP4 Evaluation Board Schematic
Rev. B | Page 10 of 11
16094-015
J10
Data Sheet
HMC641ALP4E
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
0.30
0.25
0.18
1
0.50
BSC
2.85
2.70 SQ
2.55
EXPOSED
PAD
13
TOP VIEW
0.95
0.85
0.75
SIDE VIEW
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PKG-04940
SEATING
PLANE
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
12-08-2017-C
4.10
4.00 SQ
3.90
Figure 17. 24-Terminal Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.90 mm Package Height
(HCP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC641ALP4E
HMC641ALP4ETR
EV1HMC641ALP4
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Terminal Lead Frame Chip Scale Package [LFCSP]
24-Terminal Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
All models are RoHS compliant.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16094-0-8/18(B)
Rev. B | Page 11 of 11
Package Option
HCP-24-3
HCP-24-3