HMC703LP4ETR

HMC703LP4E v02.0813 8 GHz fractional synthesizer Typical Applications The HMC703LP4E is ideal for: • Microwave Point-to-Point Radios • Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Features Wide band: DC - 8 GHz RF Input Best Phase Noise and Spurious in the Industry: -112 dBc/Hz @ 8 GHz Fractional, 50 kHz Offset Figure of Merit • Wireless LANs, WiMAX -230 dBc/Hz Fractional Mode • Communications Test Equipment -233 dBc/Hz Integer Mode • CATV Equipment High PFD rate: 100 MHz • Automotive Sensors < 50 fs RMS jitter • AESA - Phased Arrays Frequency and Phase Modulation • FMCW Radar Systems Integrated Frequency Sweeper Triggered Frequency Hopping External Triggering PLLs - SMT 24 Lead 4x4 mm SMT Package: 16 mm2 Functional Diagram General Description The HMC703LP4E fractional synthesizer is built upon the high performance PLL platform also contained in the HMC704LP4E and Hittite’s latest generation of PLL+VCO products. This platform has the best phasenoise and spurious performance in the industry enabling higher order modulation schemes while minimizing blocker effects in high performance radios. In addition, the HMC703LP4E offers frequency sweep and modulation features, external triggering, doublebuffering, exact frequency control, phase modulation and more - while maintaining pin compatibility with the HMC700LP4E PLL. Exact frequency mode with a 24-bit fractional mod­ ulator provides the ability to generate fractional frequencies with zero frequency error and very low channel spurious, an important feature for Digital PreDistortion systems. The serial interface offers read back capability and is compatible with a wide variety of protocols. 6-1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Table 1. Electrical Specifications Unless otherwise specified, data is collected at 3.3 V, and 5.0 V (on charge-pump), 100 MHz reference, 50 MHz fPD. Min and Max are specified across temperature range from -40 °C to 85 °C ambient. Parameter RF INPUT CHARACTERISTICS Conditions Min. Typ. Max. Units [6][7] RF Input Frequency Range [1] DC 8000 MHz Prescaler Input Freq Range [1] DC 4000 MHz Power Range [13] -15 -10 -3 dBm Return Loss [15] -18 -12 -7 dB Frequency Range (3.3V) [1][8] DC 50 350 MHz Power from 50 Ω Source [12] with 100 Ω termination off chip Return Loss [15] REF INPUT CHARACTERISTICS dBm -16 -8 1 16,383 dB [1] Integer Mode DC 50 115 MHz Fractional Mode B DC 50 100 MHz Fractional Mode A DC 50 80 MHz 2.5 mA 3.5 6 mA 2.7 3.3 3.5 V 2.7 5.0 5.2 V CHARGE PUMP CP Output Current 20 µA Steps, Charge Pump Gain = CP Current/2π Amps/rad CP HiK see “Charge Pump Gain” section 0.02 plls - SMT Ref Divider Range (14 bit) PHASE DETECTOR RATE 6 POWER SUPPLIES RVDD, AVDD, VCCPS, VCCHF, VCCPD, DVDD, VDDIO VDDLS, VPPCP Charge Pump VDDLS, VPPCP must be equal 3.3V - Current consumption [9] 100 kHz PD 50 MHz PD 100 MHz PD 34 54 74 45 70 95 mA mA mA 5V - Current consumption All Modes 100 kHz PD 50 MHz PD w/ CP HiK 100 MHz PD w/ CP HiK 3 7 13 5 12 16 mA mA mA Power Down Current [10] 100 uA BIAS Reference Voltage Pin 12. Measured with 10 GΩ Meter 1.960 V 1.880 1.920 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6-2 HMC703LP4E v02.0813 8 GHz fractional synthesizer Table 34. Electrical Specifications (Continued) Parameter Conditions Min. Typ. Max. Units PHASE NOISE [14] Flicker Figure of Merit (FOM)[2] dBc/Hz Floor Figure of Merit [11] Integer HiK Mode Integer Normal Mode Fractional HiK Mode [3] Fractional Normal Mode [3] Flicker Noise at foffset PNflick = Flicker FOM +20log(f vco) -10log(foffset) dBc/Hz Phase Noise Floor at f vco with fpd PNfloor = Floor FOM + 10log(fpd) +20log(f vco/fpd) dBc/Hz VCO referred Phase Noise Contribution PN = 10log(10(PNflick /10) + 10(PNfloor /10) ) dBc/Hz of the PLL vs foffset, f vco, fpd Jitter SSB 100Hz to 100MHz with HMC508LP5E VCO SPURIOUS [4][5] Integer Boundary Spurs @~8GHz PLLs - SMT -270 -236 -232 -232 -228 -233 -230 -230 -227 -231 -228 -227 -225 50 offsets less than loop bandwidth, fpd = 50MHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz fs -60 -52 dBc 47 54 % VDDIO LOGIC INPUTS Switching Theshold (Vsw) VIH/VIL within 50 mV of Vsw 38 LOGIC OUTPUT VOH Output High Voltage VDDIO V VOL Output Low Voltage 0 V Output impedance : Pull Up VDDIO=3.3 V 115 150 180 Ohm Output impedance : Pull Dn VDDIO=3.3 V 130 135 210 Ohm 1.5 mA DC load Digital Output Driver Delay SCK to Digital Output Delay 0.5ns+0.2ns/pF 8.2ns+0.2ns/pF 1.7nsec with a 3 pF load ns ns RF Divider Range >4GHz Integer Mode 16 bit , Even values only 32 131,070 < 4GHz Integer Mode 16 bit , All values 16 65,535 > 4GHz Fractional Mode 16 bit 40.0 131,065.0 < 4GHz Fractional Mode 16 bit 20.0 65,531.0 [1] Frequency is guaranteed across process, voltage and temperature from -400C to 850C. [2] With high charge-pump current, +12dBm 100MHz sine reference [3] Fractional FOM degrades about 3dB/octave for prescaler input frequencies below 2GHz [4] Using 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger offsets produce better results. See the “Spurious Performance” section for more information. [5] Measured with the HMC703LP4E evaluation board. Board design and isolation will affect performance. [6] Internal divide-by-2 should be enabled for frequencies >4GHz [7] At low RF Frequency, Rise and fall times should be less than 1ns to maintain performance [8] Slew rate of greater or equal to 0.5 V/ns [9] Current consumption depends upon operating mode and frequency of the VCO. Typical values are for fractional mode. [10] Reference input disconnected [11] Min/Max versus temperature and supply, under typical reference & RF frequencies and power levels [12] Slew > 0.5V/ns is recommended , see Table 7, Figure 5, Figure 6 for more information. [13] Operable with reduced spectral performance outside of this range. [14] This section specifies the Phase Noise contribution of the PLL, solution phase noise with a given VCO, loop filter and reference requires a closed loop calculation using Hittite PLL Design Tool. [15] As measured on HMC703LP4E Evaluation board, with 100Ohm external termination. 6-3 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, plots are measured with a 50 MHz PD rate, VCO near 8 GHz, RF power ≈ -10 dBm, and a Wenzel 100 MHz sinusoid reference. The operating modes in the following plots refer to Integer (int), Fractional Modes A and B, HiKcp (HiK). Figure 1. Floor FOM vs. Mode and Temp, 2.5 mA CP Current Figure 2. Flicker FOM vs. Mode and Temp, 2.5 mA CP Current -226 -266 Frac Mode A -267 Frac Mode A FLICKER FOM (dBc/Hz) FLOOR FOM (dBc/Hz) -228 -230 Integer Mode -232 HiK Frac Mode A HiK Integer -268 HiK Frac Mode A -269 -270 Integer Mode HiK Integer -271 -234 -272 0 40 TEMPERATURE (C) -273 -40 80 -20 20 40 60 80 TEMPERATURE (C) Figure 3. Floor FOM vs. Output Frequency and Mode, 2.5 mA CP Current Figure 4. Flicker FOM vs. Output Frequency and Mode, 2.5 mA CP Current -220 -265 -222 FLICKER FOM (dBc/Hz) Mode B -224 -226 -228 -230 Mode A Mode A HIK Mode B HIK Integer Frac Mode B Frac Mode A -266 FLOOR FOM (dBc/Hz) 0 -267 plls - SMT -236 -40 HiK Frac Mode B -268 HiK Frac Mode A -269 Int -232 Integer HIK -234 -270 1 2 4 1 8 2 Figure 5. Floor FOM vs. Reference Power and Mode, 2.5 mA CP Current [1] 0.40 -226 0.50 REFERENCE POWER (Vpp) 0.63 0.80 1 1.26 4 8 FREQUENCY (GHz) FREQUENCY (GHz) 1.59 2 Figure 6. Flicker FOM vs. Reference Power and Mode, 2.5 mA CP Current [1] 2.52 -268 0.40 0.50 REFERENCE POWER (Vpp) 0.63 0.80 1 1.26 1.59 2 2.52 8 10 12 Frac Mode B FLICKER FOM (dBc/Hz) FLOOR FOM (dBc/Hz) Frac Mode B -228 Integer Mode -230 HiK Frac Mode B -269 HiK Frac Mode B -270 Integer Mode -271 -232 HiK Integer Mode HiK Integer -272 -234 -4 -2 0 2 4 6 REFERENCE POWER (dBm) 8 10 12 -4 -2 0 2 4 6 REFERENCE POWER (dBm) [1] 100 MHz Sinusoidal Wenzel reference. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6-4 HMC703LP4E v02.0813 8 GHz fractional synthesizer Figure 7. Flicker FOM vs. CP Current, Fractional Mode B, 2.5 mA CP Current Figure 8. Floor FOM vs. CP Current, Fractional Mode B, 2.5 mA CP Current -260 -216 -218 FLOOR FOM (dBc/Hz) FLICKER FOM (dBc/Hz) -262 -264 -266 -220 -222 -224 -226 -268 -228 -270 0.5 1 1.5 2 2.5 -230 0.5 3 1 2 2.5 3 Figure 10. Floor FOM vs. CP Voltage, CP Current = 2.5 mA [1] -222 -260 -262 Integer Fractional FLOOR FOM (dBc/Hz) -224 -264 -266 -268 -226 -228 -230 -270 -232 -272 0 1 2 3 CP VOLTAGE (V) 4 0 5 1 2 3 CP VOLTAGE (V) 4 5 Figure 12. Floor FOM vs. CP Voltage, HiKcp + CP Current = 6 mA [2] Figure 11. Flicker FOM vs. CP Voltage, HiKcp + CP Current = 6 mA [2] -266 -222 -268 -224 FLOOR FOM (dBc/Hz) FLOOR FOM (dBc/Hz) 1.5 CP CURRENT (mA) Figure 9. Flicker FOM vs. CP Voltage, CP Current = 2.5 mA [1] FLICKER FOM (dBc/Hz) PLLs - SMT CP CURRENT (mA) -270 -272 Floor Int FOM Floor Frac FOM -226 -228 -230 -274 -232 -276 -234 0 1 2 3 CP VOLTAGE (V) 4 5 0 1 2 3 CP VOLTAGE (V) 4 5 [2] Active Loop Filter, with DC bias point on -ve leg of op-amp swept. 6-5 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Figure 14. Fractional Performance, Exact Frequency Mode On at 8013.6 MHz [4] Figure 13. Typical Phase Noise & Spur Performance at 8 GHz + 200 kHz[3] -80 -60 -100 PHASE NOISE (dBc/Hz) -100 -120 -140 -120 -140 -160 -160 -180 -180 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 2 10 3 10 4 10 Figure 15. Integer Boundary Spur at 8 GHz + 20 kHz vs. Charge Pump Offset[5] 6 10 7 10 8 30 20 kHz Offset Spur 10 kHz Offset Spur -30 20 Recommended Operating Range -40 INPUT POWER (dBm) SPUR MAGNITUDE (dBc) 10 Figure 16. RF Input Limits [6] -20 -50 -60 -70 -80 10 0 No Divider Divide By 2 RECOMMENDED OPERATING RANGE -10 -20 -30 -90 -800 -600 -400 -200 0 200 400 CP OFFSET CURRENT (uA) 600 -40 0 800 4000 6000 8000 10000 Figure 18. Modelled vs. Measured Phase Noise, Fractional Mode B, HiK at ~ 8 GHz [8] -80 -80 Total Noise Simulated Using Hittite PLL Design Software Total Noise Simulated Using Hittite PLL Design Software -100 -100 PHASE NOISE (dBc/Hz) Modelled PLL Floor -120 Measured Total Noise -140 INTEGRATED RMS JITTER = 36.1 fs 100 Hz to 100 MHz -160 Modelled PLL Floor -120 Measured Total Noise -140 INTEGRATED RMS JITTER = 44.2 fs 100 Hz to 100 MHz -160 -180 10 2000 RF INPUT FREQUENCY AT PRESCALAR (MHz) Figure 17. Modelled vs. Measured Phase Noise, Integer Mode HiK at 8 GHz [7] PHASE NOISE (dBc/Hz) 5 OFFSET (Hz) OFFSET(Hz) plls - SMT PHASE NOISE (dBc/Hz) -80 -180 2 10 3 10 4 10 5 OFFSET (Hz) 10 6 10 7 10 8 10 2 10 3 10 4 5 10 OFFSET (Hz) 10 6 10 7 10 8 [3] Output frequency = 8 GHz + 200 kHz using HMC508LP5E VCO, Reference Input = 100 MHz, PD frequency = 100 MHz, CP current = 2.5 mA, Fractional Mode B, 20 kHz bandwidth Loop Filter. Spur at 200kHz due to RF signal at 8GHz + 200kHz, spur at 100kHz due to prescaler input at 4GHz+100kHz. Reference feedthrough spur at 100 MHz offset. [4] Exact Frequency Mode channel spacing 100 kHz, Fractional N, Rfout = 8013.6 MHz using HMC508LP5E VCO, Reference Input = 100 MHz, PD frequency = 100 MHz, Prescaler divide-by-2 selected. 20 kHz Loop Filter bandwidth, reference feedthrough spur at 100 MHz offset. [5] Tuned to 8 GHz + 20 kHz, Prescaler at 4 GHz + 10 kHz, Loop bandwidth >> 20 kHz, Reference Frequency 50 MHz. Offset polarity should be positive for inverting configurations and negative otherwise. [6] Low frequency minimum power levels not characterized. Low frequency limitation is only a function of external AC coupling capacitance signal slew rate. [7] HiK integer mode measured at 8 GHz, Prescalar at 4 GHz, 50 MHz reference frequency. [8] Active Fractional B Mode (Prescalar @ 4 GHz + 2.5 kHz), Reference Frequency 50 MHz. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6-6 HMC703LP4E v02.0813 8 GHz fractional synthesizer Figure 19. Floor FOM Near 8 GHz vs RF Input Power and Mode Figure 20. Flicker FOM Near 8 GHz vs. RF Input Power and Mode -267 -224 Frac Mode A -267.5 Frac Mode B -268 FLICKER FOM (dBc/Hz) FLOOR FOM (dBc/Hz) -226 Frac Mode A HiK Mode B -230 HiK Mode A -269 -269.5 -232 Integer -270 HiK Mode A -270.5 HiK Integer HiK Integer -271 -234 -25 -20 -15 -10 -5 0 5 -25 -20 RF POWER (dBm) Figure 21. Reference Input Sensitivity, Square Wave, 50 Ω [9] -15 -10 -5 RF POWER (dBm) 0 5 Figure 22. Reference Input Sensitivity Sinusoid Wave, 50 Ω [9] -215 -200 50 MHz -205 14 MHz sq 25 MHz sq 50 MHz sq 100 MHz sq 25 MHz FLOOR FOM (dBc/Hz) -220 FLOOR FOM (dBc/Hz) PLLs - SMT Frac Mode B HiK Mode B -268.5 -228 -225 14 MHz -230 -210 25 MHz -215 14 MHz -220 50 MHz -225 -230 100 MHz 100 MHz -235 -15 -235 -10 -5 0 5 10 -20 -15 REFERENCE POWER (dBm) -5 0 5 Figure 24. RF Input Return Loss [11] 0 0 -5 -5 RETURN LOSS (dB) RETURN LOSS (dB) Figure 23. Reference Input Return Loss [10] -10 -10 -15 -15 -20 0 -10 REFERENCE POWER (dBm) -20 50 100 150 200 250 REFERENCE INPUT FREQUENCY (MHz) 300 350 0 2000 4000 6000 8000 10000 RF INPUT FREQUENCY (MHz) [9] Measured with a 100 Ω external resistor termination, resulting in 50Ohm effective input impedance.. See “Reference Input Stage” for more details. Full FOM performance up to maximum 3.3 Vpp input voltage. [10] Measured with a 100 Ω external termination AC coupled on HMC703LP4E evaluation board, as in Figure 35. [11] Measured with a 100 Ω external termination AC coupled on HMC703LP4E evaluation board, as in Figure 37. 6-7 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Figure 25. 2-Way Auto Sweep 3750 OUTPUT FREQUENCY (MHz) 3700 3650 3600 3550 3500 3450 3400 3350 0 5 10 15 20 plls - SMT TIME (milliseconds) Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6-8 HMC703LP4E v02.0813 8 GHz fractional synthesizer PLLs - SMT Table 2. Pin Descriptions 6-9 Pin Number Function Description 1 SCK CMOS Input: Serial port clock 2 SDI CMOS Input: Serial port data 3 DVDD Power Supply for digital - Nominal 3.3 V MAX 25 mA, fPD dependent 4 VDDIO Power Supply for Digital IO - 3.3 V, 8 mA MAX (only when driving LD_SDO) CMOS Output: General Purpose Output - Lock Detect, Serial Data Out, others, Selectable 5 LD_SDO 6 TRIG 7 N/C 8 VDDPS 9 N/C 10 VCOIP 11 VCOIN Differential RF Inputs. Normally AC Coupled, 2 V DC bias generated internally. For Single Ended operation, RFN must be AC coupled to the ground plane, typically 100 pF ceramic. DC Bias of 2.3 V is generated internally 12 VDDHF Power Supply for RF Buffer, Nominal 3.3 V, 6 mA MAX 13 VDDLS Power Supply for PFD to CP Level Shifters, Nominal 5 V, 5 mA MAX, fPD dependent. CMOS Input : External Trigger pin. No Connect Power Supply for RF Divider, Nominal 3.3 V 35 mA MAX No Connect 14 VDDCPA 15 CP Power Supply for charge pump, Nominal 5 V, 10 mA MAX 16 AVDD Power supply for analog bias generation, Nominal 3.3 V, 2 mA MAX 17 BIAS External bypass decoupling for precision bias circuits, 1.920 V +/-2 mV NOTE: BIAS ref voltage cannot drive an external load. Must be measured with 10 GΩ meter such as Agilent 34410A, normal 10 MΩ DVM will read erroneously. 18 RVDD Power Supply for Reference path, Nominal 3.3 V. 15 mA MAX reference dependent Charge pump output 19 N/C 20 XREFP No Connect Reference Input. DC bias is generated internally. Normally AC coupled externally. 21 VDDPD Power Supply for phase detector. Nominally 3.3 V. Decoupling for this supply is critical. 5 mA MAX, fPD dependent 22 N/C No Connect 23 CEN CMOS Input: Hardware Chip Enable 24 SEN CMOS Input: Serial port latch enable Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Table 3. Absolute Maximum Ratings Rating Max Vdc to paddle on supply pins 3,4,8,12,16,18,21 -0.3 V to +3.6 V VDDLS, VPPCP -0.3 V to +5.5 V VCOIN, VCOIP Single Ended DC VCCHF -0.2 V VCOIN, VCOIP Differential DC 5.2 V VCOIN, VCOIP Single Ended AC 50Ohm +7 dBm VCOIN, VCOIP Differential AC 50Ohm +13 dBm Digital Load 1 kΩ min Digital Input 1.4 V to 1.7 V min rise time 20 nsec Digital Input Voltage Range -0.25 to VDDIO+0,5 V Thermal Resistance (Jxn to Gnd Paddle) 25 0C/W Operating Temperature Range -40 OC to +85 OC Storage Temperature Range -65 OC to + 125 OC Maximum Junction Temperature +150 OC Reflow Soldering Peak Temperature Time at Peak Temperature ESD Sensitivity HBM 260 OC 40 sec Class 1B Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended plls - SMT Parameter periods may affect device reliability. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 10 HMC703LP4E v02.0813 8 GHz fractional synthesizer PLLs - SMT Outline Drawing NOTES: [1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. [2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. [3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN. [4] DIMENSIONS ARE IN INCHES [MILLIMETERS]. [5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE. [6] PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.05mm MAX. [7] PACKAGE WARP SHALL NOT EXCEED 0.05mm [8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. [9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. Table 4. Package Information Part Number Package Body Material Lead Finish MSL Rating Package Marking [1] HMC703LP4E RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn MSL1[2] H703 XXXX [1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260°C 6 - 11 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. plls - SMT Evaluation PCB Table 5. Evaluation Order Information Item Contents Part Number Evaluation Kit HMC703LP4E Evaluation PCB USB Interface Board 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software, Hittite PLL Design Software) EKIT01-HMC703LP4E Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 12 HMC703LP4E v02.0813 8 GHz fractional synthesizer PLLs - SMT Evaluation PCB Block Diagram Evaluation PCB Schematic To view Evaluation PCB Schematic please visit www.hittite.com and choose HMC703LP4E from “Search by Part Number” pull down menu to view the product splash page. 6 - 13 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Theory Of Operation PLL Basics Figure 26. Typical PLL In integer synthesizers, N can only take on discrete values (eg. 200, 201, etc.). In fractional synthesizers, such as the HMC703LP4E and others, N can also take on fractional levels, eg. N=20.4. In theory, the fractional divider normally permits higher phase-detector frequencies for a given output frequency, with associated improvements in signal quality (phase-noise). Unfortunately, fractional synthesizers suffer from imperfections which do not effect integer synthesizers. These problems can effect the phase noise, but more seriously they tend to manifest as spurious emissions - and these spurs are the most serious drawback of fractional synthesis. plls - SMT In its most trivial form, a synthesizer IC, such as the HMC703LP4E forms the heart of the control loop to multiply a low frequency reference source up to a higher frequency. The phase detector (PD) and charge-pump (CP) drive the tuning signal of a voltage-controlled oscillator in an attempt to bring the phases, at the phase-detector input, into alignment. If the loop can manage this, it means that the phase detector inputs (reference and DIV) must also be at the same frequency. Since the frequency of the DIV signal = fvco / N, this means the control loop must have forced the frequency of the VCO output must be locked to N x fpd. Hittite’s fractional synthesizer family (including the HMC703LP4E) offer drastic performance advantages over other fractional synthesizers in the industry. The HMC703LP4E synthesizer consists of the following functional blocks: 1. 2. 3. 4. 5. 6. 7. Reference Path Input Buffer and ’R’ Divider VCO Path Input Buffer, RF Divide-by-2 and Multi-Modulus ’N’ Divider Δ � Fractional Modulator Phase Detector Charge Pump Main Serial Port Lock Detect and Register Control 8. Power On Reset Circuit Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 14 HMC703LP4E v02.0813 8 GHz fractional synthesizer High Performance Low Spurious Operation The HMC703LP4E has been designed for the best phase noise and low spurious content possible in an integrated synthesizer. Spurious signals in a synthesizer can occur in any mode of operation and can come from a number of sources. Figure of Merit, Noise Floor, and Flicker Noise Models The phase noise of an ideal phase locked oscillator is dependent upon a number of factors: a. b. c. d. Frequency of the VCO, and the Phase detector VCO Sensitivity, kvco, VCO and Reference Oscillator phase noise profiles Charge Pump current, Loop Filter and Loop Bandwidth Mode of Operation: Integer, Fractional modulator style PLLs - SMT The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit (FOM) for both the PLL noise floor and the PLL flicker (1/f) noise regions, as follows: where: Ф p2 fo fpd fm Fpo Phase Noise Contribution of the PLL (rads2/Hz) Frequency of the VCO (Hz) Frequency of the Phase Detector (Hz) Frequency offset from the carrier (Hz) Figure of Merit (FOM) for the phase noise floor Fp1 Figure of Merit (FOM) for the flicker noise region PLL Phase Noise Contribution ( F f2 ) pf1 0 � 2p f0 , fm , fpd = m + Fp0 f02 (EQ 1) fpd Figure 27. Figure of Merit Noise Models for the PLL If the free running phase noise of the VCO is known, it may also be represented by a figure of merit for both 1/f2 , Fv2, and the 1/f3, Fv3, regions. 6 - 15 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer 2 F f 2 Fn f0 � n2 ( f0 , fm ) = n 22 0 + 33 fm fm VCO Phase Noise Contribution (EQ 2) The Figures of Merit are essentially normalized noise parameters for both the PLL and VCO that can allow quick estimates of the performance levels of the PLL at the required VCO, offset and phase detector fre­quency. Normally, the PLL IC noise dominates inside the closed loop bandwidth of the synthesizer, and the VCO dominates outside the loop bandwidth at offsets far from the carrier. Hence a quick estimate of the closed loop performance of the PLL can be made by setting the loop bandwidth equal to the frequency where the PLL and free running phase noise are equal. The Figure of Merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as Hittite PLL Design, which can give a much more accurate estimate of the closed loop phase noise and PLL loop filter component values. Given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the PLL and VCO noise contributions. ( ) � 2 = min � 2p , � n2 (EQ 3) An example of the use of the FOM values to make a quick estimate of PLL performance: Estimate the phase noise of an 8 GHz closed loop PLL with a 100 MHz reference operating in Fractional Mode B with the VCO operating at 8 GHz and the VCO divide by 2 port driving the PLL at 4 GHz. Assume an HMC509 VCO has free running phase noise in the 1/f2 region at 1 MHz offset of -135 dBc/Hz and phase noise in the 1/f3 region at 1 kHz offset of -60 dBc/Hz. Fv1_dB = -135 Free Running VCO PN at 1MHz offset +20*log10(1e6) PNoise normalized to 1Hz offset -20*log10(8e9) Pnoise normalized to 1Hz carrier = -213.1 dBc/Hz at 1Hz VCO FOM Fv3_dB = -60 Free Running VCO PN at 1kHz offset +30*log10(1e3) PNoise normalized to 1Hz offset -20*log10(8e9) Pnoise normalized to 1Hz carrier = -168 dBc/Hz at 1Hz VCO Flicker FOM plls - SMT PLL-VCO Noise We can see from Figure 3 and Figure 4 respectively that the PLL FOM floor and FOM flicker parameters in fractional Mode A: Fpo_dB = -227 dBc/Hz at 1Hz Fp1_dB = -266 dBc/Hz at 1Hz Each of the Figure of Merit equations result in straight lines on a log-frequency plot. We can see in the example below the resulting PLL floor at 8 GHz = Fpo_dB +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dBc/Hz PLL Flicker at 1 kHz = Fp1_dB+20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dBc/Hz VCO at 1 MHz = Fv1_dB+20log10(fvco)-20log10(fm)= -213 +198-120 = -135 dBc/Hz VCO flicker at 1 kHz = Fv3_dB+20log10(fvco)-30log10(fm)= -168 +198-90 = -60 dBc/Hz These four values help to visualize the main contributors to phase noise in the closed loop PLL. Each falls on a linear line on the log-frequency phase noise plot shown in Figure 27. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 16 HMC703LP4E v02.0813 8 GHz fractional synthesizer -20 PHASE NOISE (dBc/Hz) -40 VCO at 1 kHz -60 -80 -100 PLL Floor -120 PLL at 1 kHz -140 VCO at 1 MHz -160 PLLs - SMT -180 100 1000 4 5 6 10 10 10 FREQUENCY OFFSET (Hz) 10 7 10 8 Figure 28. Figure of Merit Example It should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parameters and one should use a more complete design tool such as Hittite PLL Design for better esti­mates of the phase noise performance. Noise models for each of the components in Hittite PLL Design can be derived from the FOM equations or can be provided by Hittite applications engineering. Spurious Performance Integer Operation The VCO always operates at an integer multiple of the PD frequency in an integer synthesizer. In general, spurious signals originating from an integer synthesizer can only occur at multiples of the PD frequency. These unwanted outputs are often simply referred to as reference sidebands. Spurs unrelated to the reference frequency must originate from outside sources. External spurious sources can modulate the VCO indirectly through power supplies, ground, or output ports, or bypass the loop filter due to poor isolation of the filter. It can also simply add to the output of the synthesizer. The HMC703LP4E has been designed and tested for ultra-low spurious performance. Reference spuri­ous levels are typically below -100 dBc with a well designed board layout. A regulator with low noise and high power supply rejection, such as the HMC860LP3E, is recommended to minimize external spurious sources. Reference spurious levels of below -100 dBc require superb board isolation of power supplies, isolation of the VCO from the digital switching of the synthesizer and isolation of the VCO load from the synthesizer. Typical board layout, regulator design, demo boards and application information are available for very low spurious operation. Operation with lower levels of isolation in the application circuit board, from those rec­ommended by Hittite, can result in higher spurious levels. Of course, if the application environment contains other interfering frequencies unrelated to the PD fre­quency, and if the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurs. The level of these spurs is dependant upon isolation and supply regulation or rejection (PSRR). 6 - 17 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Fractional Operation Unlike an integer synthesizer, spurious signals in a fractional synthesizer can occur due to the fact that the VCO operates at frequencies unrelated to the PD frequency. Hence intermodulation of the VCO and the PD harmonics can cause spurious sidebands. Spurious emissions are largest when the VCO operates very close to an integer multiple of the PD. When the VCO operates exactly at a harmonic of the PD then, no in-close mixing products are present. Interference is always present at multiples of the PD frequency, fpd, and the VCO frequency, fvco. If the fractional mode of operation is used, the difference, Δ, between the VCO frequency and the nearest har­monic of the reference, will create what are referred to as integer boundary spurs. Depending upon the mode of operation of the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the PD frequency. That is, fractional VCO frequencies which are near nfpd + fpdd/m, where n, d and m are all integers and d≤m (mathematicians refer to d/m as a rational num­ber). We will refer to fpdd/m as an integer fraction. The denominator, m, is the order of the spurious product. Higher values of m produce smaller amplitude spurious at offsets of mΔ and usually when m>4 spurs are very small or unmeasurable. plls - SMT The worst case, in fractional mode, is when d=1, and the VCO frequency is offset from nfpd by less than the loop bandwidth. This is the “in-band fractional boundary” case. Figure 29. Fractional Spurious Example Characterization of the levels and orders of these products is not unlike a mixer spur chart. Exact levels of the products are dependent upon isolation of the various synthesizer parts. Hittite can offer guidance about expected levels of spurious with our PLL and VCO application boards. Regulators with high power supply rejection ratios (PSRR) are recommended, especially in noisy applications. When operating in fractional mode, charge pump and phase detector linearity is of paramount importance. Any nonlinearity degrades phase noise and spurious performance. Phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and VCO lead. To mitigate these non-linearities in fractional mode it is critical to operate the phase detector with some finite phase offset such that either the reference or VCO always leads. To provide a finite phase error, extra current sources can be enabled which provide a constant DC current path to VDD (VCO leads always) or ground (reference leads always). These current sources are called charge pump offset and they are controlled via Reg 09h. The time offset at the phase detector should be ~2.5 ns + 4 Tps, where Tps is the RF period at the fractional prescaler input in nanoseconds (ie. after the optional fixed divide by 2). The specific level of charge pump offset current is determined by this time offset, the comparison frequency and the charge pump current and can be calculated from: Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 18 HMC703LP4E v02.0813 8 GHz fractional synthesizer Required CP Offset = (2.5 ∙ 10 -9+ 4TPS) ∙ (Fcomparison) ∙ ICP where: : is the RF period at the fractional prescaler input TPS (EQ 4) ICP: is the full scale current setting of the switching charge pump Note that this calculation can be performed for the center frequency of the VCO, and does not need refinement for small differences ( 10 x the loop bandwidth. 6 - 27 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 Figure 34. Single Step Ramp Mode The user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. If the loop bandwidth in use is much wider than the rate of the steps then the locking will be fast and the ramp will have a staircase shape. If the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. Hence the swept output will have a small lag and will sweep in a near continuous fashion. Detailed Sweeper Configuration plls - SMT 8 GHz fractional synthesizer The Following procedure is recommended to configure the frequency sweep in HMC703LP4E: 1. Lock in fractional mode (Reg 06h[7:5] = 0) to the start frequency (f0). 2. Program frequency step Reg 0Ah and stop N (Reg 0Ch,Reg 0Dh). Note that stop N must be exactly equal to start N plus an integer number of steps (Reg 0Ah). If it is not, the sweeper function will not terminate properly. This normally means rounding the stop N up or down slightly to ensure it falls on a step boundary. 3. Change Mode to Reg 06h[7:5] = 5,6, or 7 - depending on the desired profile. Note that the ramp step Reg 0Ah is signed two’s complement. If negative, the first ramp has a negative slope, and vice-versa. Setting autoseed (Reg 06h[8] = 1) ensures that different sweeps have identical phase profile. This is achieved by loading the seed (Reg 05h) into the phase accumulator at the beginning of each ramp Setting Reg 06h[22] = 1 ensures identical phase AND quantization noise performance on each sweep by resetting the entire delta-sigma modulator at the beginning of each ramp. Note that, while the HMC703LP4E can enforce phase coherence between different frequency sweeps, there will be a phase discontinuity if the start phase that is programmed in SEED (Reg 05h) is different from the phase state that the PLL finds itself in at the end of the ramp. This discontinuity can be prevented by tailoring the sweep profile such that the phase of the PLL at the start of the ramp is equal to phase at the end of the ramp. Example: Configure a sweep from f0 = 3000 MHz to ff = 3105 MHz in Tramp ≈ 2 ms, with fPD = 50 MHz: 1. Start in fractional mode (Program Reg 06h[7:5] = 0) 1. Calculate Start N and Stop N, Program Start N (Reg 03h,Reg 04h) Start N = 3000.0 MHz / 50.0 MHz = 60.0 Stop N = 3105.0 MHz / 50.0 MHz = 62.1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 28 HMC703LP4E v02.0813 8 GHz fractional synthesizer Program Reg 03h = 60, Reg 04h = 0 2. Calculate how many reference cycles will occur in 2 ms. Given that Tref = 1 / fPD = 20ns, 3. Calculate the desired N step size, given Start N, Stop N and Nbr of Steps Nbr of Steps = Tramp/Tref = 2ms/20ns = 100,000 N_Step_Size_desired = (62.1 - 60.0) / 100,000 = 21u [fractions of N] 4. Quantize the fractional N step into the 24 bit step size Program Reg 0Ah = 21u x 224 = round(352.32) = 352 5. Readjust the stop frequency slightly to ensure it falls exactly on a step boundary Due to step quantization,there will be some finite error in either the sweep time or sweep span. We have 3 choices: PLLs - SMT a) Target an accurate sweep time, sacrifice resolution on stop frequency Sweep time = 100k cycles = 2 ms Stop N = Start N + 100,000 x 352/224 (Keep 100k cycles) Stop N = 60.000 + 35,200,000 / 224 ≈ 62.09808 Program Reg 0Ch= 62, Reg 0Dh = 35,200,000 MOD 224 = 1,645,568 ≈ 0.09808 ff ≈ 3104.904 (96 kHz lower stop frequency then desired) b) Target an accurate stop frequency, at the expense of sweep time accuracy Given step size of 352/224 , how many cycles to get from 60.0 to 62.1 Nbr of Steps = (62.1 - 60.0) / (352/224) = 100,091.345 Must round to 100,091 steps. Sweep time = Tref * 100,091 = 2.00182ms (1.82 us longer than desired) Stop N = 60.0 + 100,091 x 352/224 ≈ 62.0999927 Program Reg 0Ch= 62, Reg 0Dh = 35,232,032 MOD 224 = 1,677,600 ≈ 0.0999927 ff = 3104.99964 MHz (362 Hz lower stop frequency then desired) c) A combination of situation a and b 6. Program SD_Mode based on desired trigger and ramp/hop profile (Reg 06h[7:5] = 5,6, or 7) 7. Trigger via either the external pin or SPI TRIG bit. Continue to issue triggers to advance the ramp profile to the next stage... Sweeper Configuration for Ultra Fine Step Sizes In cases where finer step size resolution is desired, it is possible to reduce the fPD, along with performance implications it has, or use a single-step mode (Reg 06h[23] = 1) and provide a lower frequency clock on the external trigger pin to reduce the update rate. The HMC703LP4E can generate a lower frequency clock by programming the R divider appropriately, and not using it for the PD (Reg 06h[21] = 1), but rather routing it out of the HMC703LP4E via the GPO. The R divider output can then be looped back to the TRIG pin of the HMC703LP4E to use as a low rate trigger. See “Ref Path ’R’ Divider” for more details. 6 - 29 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer Reference Input Stage The reference buffer provides the path from an external reference source (generally crystal based) to the R divider, and eventually to the phase detector. The buffer has two modes of operation. High Gain (recommended below 200 MHz), and High frequency, for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 Ω internal termination. For 50 Ω match, an external 100 Ω resistance to AC ground should be added, followed by an AC coupling capacitance (impedance < 1 Ohm), then to the XREFP pin of the part. At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher frequencies, a square or sinusoid can be used. The following table shows the recommended operating regions for different reference frequencies. If operating outside these regions the part will normally still operate, but with degraded performance. Minimum pulse width at the reference buffer input is 2.5 ns. For best spur performance when R = 1, the pulse width should be > (2.5 ns + 8 Tps), where Tps is the period of the VCO at the prescaler input. When R > 1 minimum pulse plls - SMT Figure 35. Reference Path Input Stage width is 2.5 ns. Table 7. Reference Sensitivity Table Square Input Sinusoidal Input Frequency Slew > 0.5V/ns (MHz) Recommended Recommended Swing (Vpp) Min Max Recommended Recommended Power Range (dBm) Min Max < 10 YES 0.6 2.5 x x x 10 YES 0.6 2.5 x x x 25 YES 0.6 2.5 ok 8 15 50 YES 0.6 2.5 YES 6 15 100 YES 0.6 2.5 YES 5 15 150 ok 0.9 2.5 YES 4 12 200 ok 1.2 2.5 YES 3 8 x YES1 5 10 200 to 350 x x Note: For greater than 200 MHz operation, use buffer in High Frequency Mode. Reg 08h[18] = 1 Input referred phase noise of the PLL when operating at 50 MHz is between -150 and -156 dBc/Hz at 10 kHz offset depending upon the mode of operation. The input reference signal should be 10dB better than this floor to avoid deg­ radation of the PLL noise contribution. It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 30 HMC703LP4E v02.0813 8 GHz fractional synthesizer Ref Path ’R’ Divider The reference path “R” divider is based on a 14 bit counter and can divide input signals of up to 350 MHz input by values from 1 to 16,383 and is controlled by Reg 02h[13:0]. The reference divider output may be viewed in test mode on the LD_SDO pin, by setting Reg 0Fh[4:0] = 9d. The HMC703LP4E can use the undivided reference, while exporting a divided version for auxiliary purposes (eg. ramp triggers, FPGAs etc.) on the GPO, if Reg 06h[21] = 1. RF Path PLLs - SMT The RF path is shown in Figure 36. This path features a low noise 8 GHz RF input buffer followed by an 8 GHz RF divide-by-2 with a selectable bypass. If the VCO input is below 4 GHz the RF divide-by-2 should be by-passed for improved performance in fractional mode. The RF divide-by-2 is followed by the N divider, a 16 bit divider that can operate in either integer or fractional mode with up to 4 GHz inputs. Finally the N divider is followed by the Phase Detector (PD), which has two inputs, the RF path from the VCO (V) and the reference path (R) from the crystal. The PD can operate at speeds up to 100 MHz in fractional Mode B (recommended ), 80 MHz in fractional Mode A and 115 MHz in integer mode. Figure 36. RF Path RF Input Stage The RF input stage provides the path from the external VCO to the phase detector via the RF or ’N’ divider. The RF input path is rated to operate up to 8 GHz across all conditions. The RF input stage is a differential common emitter stage with internal DC bias, and is protected by ESD diodes as shown in Figure 37. This input is not matched to 50 Ω. A 100 Ω resistor placed across the inputs can be used for a better match to 50 Ω. In most applications the input is used single-ended into either the VCOIP or VCOIN pin with the other input connected to ground through a DC blocking capacitor. The preferred input level for best spectral performance is -10 dBm nominally. 6 - 31 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 Figure 37. RF Input Stage- shown with single ended device RF Path ’N’ Divider The main RF path ’N’ divider is capable of divide ratios anywhere between 216-1 (524,287) and 16 . This divider for example could divide a 4 GHz input to a PD frequency anywhere between its maximum output limit of 115 MHz to as low as 7.6 kHz. The ’N’ divider output may be viewed in test mode on LD_SDO by set­ting Reg 0Fh[4:0] = 10d. When operating in fractional mode the N divider can change by up to +/-4 from the average value. Hence the selected divide ratio in fractional mode is restricted to values between 216-5 (65,531) and 20. plls - SMT 8 GHz fractional synthesizer If the VCO input is above 4 GHz then the 8 GHz fixed RF divide-by-2 should be used, Reg 08h[17] = 1. In this case the integer division range is restricted to even numbers over the range 2*(216-5) (131,062) down to 40. PLL Jitter The standard deviation of the arrival time of the VCO signal, or the jitter, may be estimated with a simple approximation f0 ) if we assume that the locked VCO has a constant phase noise, � 2 ( , at offsets less than the loop 3dB bandwidth and a 20dB per decade roll off at greater offsets. The simple locked VCO phase noise approximation is shown on the left of Figure 38. Figure 38. PLL Phase Noise and Jitter Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and Drive, to placeChelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth 01824 responsibility assumed by Analog for its use, nor for any infringements of patents orCorporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any• patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of theirApplication respective owners. Support: pll@hittite.com 6 - 32 HMC703LP4E v02.0813 8 GHz fractional synthesizer With this simplification the total integrated VCO phase noise, Ф2v, in rads2 is given by (EQ 10) Ф2v = Ф2(f0) Вπ where Ф2 is the single sideband phase noise in rads2/Hz inside the loop bandwidth, and В is the 3 dB corner frequency of the closed loop PLL The integrated phase noise at the phase detector, Ф2pd, is just scaled by N2 ie. Ф2pd = Ф2v/N2 The rms phase jitter of the VCO (Фv) in rads, is just the square root of the phase noise integral. PLLs - SMT Since the simple integral of (EQ 10) is just a product of constants, we can easily do the integral in the log domain. For example if the phase noise inside the loop is -110 dBc/Hz at 10 kHz offset and the loop band­width is 100 kHz, and the division ratio is 100, then the integrated phase noise at the phase detector, in dB, is given by; Ф2pd = 10log(Ф2(f0) Вπ/N2) = -110 + 5 + 50 - 40 = -95 dBrads, or equivalently � = 10 rms. �95 20 = 18 µrads = 1 milli-degrees While the phase noise reduces by a factor of 20logN after division to the reference, due to the increased period of the PD reference signal, the jitter is constant. The rms jitter from the phase noise is then given by Tjpn=Tpd Ф2pd/2π In this example if the PD reference was 50 MHz, Tpd = 20 nsec, and hence Tjpn = 56 femto-sec. Charge Pump and Phase Detector The Phase Detector or PD has two inputs, one from the reference path divider and one from the RF path divider. When in lock these two inputs are at the same average frequency and are fixed at a constant aver­age phase offset with respect to each other. We refer to the frequency of operation of the PD as fpd. Most formula related to step size, deltasigma modulation, timers etc., are functions of the operating frequency of the PD, fpd is sometimes referred to as the comparison frequency of the PD. The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. The out­put current varies in a linear fashion over nearly ±2π radians (±360) of input phase difference. Charge Pump and Phase Detector Functions Phase detector register Reg 0Bh allows manual access to control special phase detector features. Reg 0Bh[2:0] allows fine tuning of the PD reset path delay. This adjustment can be used to improve perfor­mance at very high PD rates. Most often this register is set to the recommended value only. Reg 0Bh[5] and [6] enables the PD UP and DN outputs respectively. Disabling prevents the charge pump from pumping up or down respectively and effectively tri-states the charge pump while leaving all other functions operating internally. CP Force UP Reg 0Bh[7] and CP Force DN Reg 0Bh[8] allows the charge pump to be forced up or down respectively. This will force the VCO to the ends of the tuning range which can be useful for testing of the VCO. 6 - 33 Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price,2delivery, and to place Chelmsford, orders: Analog MA Devices, Inc., For price,is delivery and Devices to place orders: Hittite Microwave Elizabeth Drive, 01824 responsibility assumed by Analog for its use, nor for any infringements of patents or Corporation, other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No 978-250-3343 978-250-3373 fax Devices. • Order On-line at www.hittite.com Phone: 781-329-4700 • Order online at www.analog.com license is granted by implication or otherwise under any•patent or patent rights of Analog Application Support: Phone: 1-800-ANALOG-D Trademarks and registered trademarks are the property of their Application respective owners. Support: pll@hittite.com HMC703LP4E v02.0813 8 GHz fractional synthesizer PD Force Mid Reg 0Bh[9] will disable the charge pump current sources and place a voltage source on the loop filter at approximately VPPCP/2. If a passive filter is used this will set the VCO to the mid-voltage tun­ing point which can be useful for testing of the VCO. Lock Detect Each PD (Phase Detector) cycle, the HMC703LP4E measures phase error at the PD. The measured phase error must be: • < ~220 degrees if 40 MHz