HMC7044LP10BE

High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B HMC7044 Data Sheet FEATURES APPLICATIONS Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz Noise floor: −156 dBc/Hz at 2457.6 MHz Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2 Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz JESD204B-compatible system reference (SYSREF) pulses 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels SPI-programmable phase noise vs. power consumption SYSREF valid interrupt to simplify JESD204B synchronization Narrow-band, dual core VCOs Up to 2 buffered voltage controlled oscillator (VCXO) outputs Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes Frequency holdover mode to maintain output frequency Loss of signal (LOS) detection and hitless reference switching 4× GPIOs alarms/status indicators to determine the health of the system External VCO input to support up to 6000 MHz On-board regulators for excellent PSRR 68-lead, 10 mm × 10 mm LFCSP_VQ JESD204B clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Microwave baseband cards Phase array reference distribution GENERAL DESCRIPTION The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs). The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses. FUNCTIONAL BLOCK DIAGRAM OSCIN OSCIN CPOUT1 PLL1 ÷ CLKOUT12 CLKOUT12 SCLKOUT13 SCLKOUT13 PLL2 SYSREF CONTROL SYNC SDATA ÷ CLKOUT0 CLKOUT0 SCLKOUT1 SCLKOUT1 CLKOUT2 CLKOUT2 SCLKOUT3 SCLKOUT3 14-CLOCK DISTRIBUTION SPI CONTROL INTERFACE SLEN 13033-001 CLKIN0/RFSYNCIN CLKIN0/RFSYNCIN CLKIN1/FIN CLKIN1/FIN CLKIN2/OSCOUT0 CLKIN2/OSCOUT0 CLKIN3 CLKIN3 CPOUT2 OSCOUT1 OSCOUT1 SCLK Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC7044 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 23  Applications ...................................................................................... 1  Detailed Block Diagram ............................................................ 24  General Description ......................................................................... 1  Dual PLL Overview .................................................................... 25  Functional Block Diagram .............................................................. 1  Component Blocks—Input PLL (PLL1) ................................. 25  Table of Contents ............................................................................. 2  Component Blocks—Output PLL (PLL2) .............................. 30  Revision History ............................................................................... 2  Clock Output Network .............................................................. 31  Specifications .................................................................................... 3  Reference Buffer Details ............................................................ 38  Conditions ..................................................................................... 3  Typical Programming Sequence .............................................. 38  Supply Current ............................................................................. 3  Power Supply Considerations .................................................. 39  Digital Input/Output (I/O) Electrical Specifications .............. 4  SeriaL Control Port ........................................................................ 42  PLL1 Characteristics .................................................................... 5  Serial Port Interface (SPI) Control .......................................... 42  PLL2 Characteristics .................................................................... 7  Applications Information ............................................................. 43  VCO Characteristics .................................................................... 8  PLL1 Noise Calculations ........................................................... 43  Clock Output Distribution Characteristics .............................. 9  PLL2 Noise Calculations ........................................................... 43  Spur Characteristics ................................................................... 10  Phase Noise Floor and Jitter ..................................................... 43  Noise and Jitter Characteristics ................................................ 10  Control Registers ............................................................................ 44  Clock Output Driver Characteristics....................................... 11  Control Register Map ................................................................ 44  Absolute Maximum Ratings ......................................................... 13  Control Register Map Bit Descriptions................................... 52  ESD Caution................................................................................ 13  Evaluation PCB Schematic............................................................ 69  Pin Configuration and Function Descriptions .......................... 14  Evaluation PCB........................................................................... 69  Typical Performance Characteristics ........................................... 17  Outline Dimensions ....................................................................... 71  Typical Application Circuits ......................................................... 21  Ordering Guide .......................................................................... 71  Terminology .................................................................................... 22  REVISION HISTORY 9/2021—Rev. B to Rev. C Change to Bit 5, Register 0x0001, Table 25................................. 44 Change to Bit 5, Register 0x0001, Table 27................................. 52 11/2016—Rev. A to Rev. B Changes to Table 1 and Endnote 4, Table 2 ................................. 3 Changes to Reliable Signal Swing Parameter, Table 4 ................ 5 Change to PLL2 VCXO Input Parameter, Table 5 ...................... 7 Changes to Table 7 ........................................................................... 9 Added Figure 13; Renumbered Sequentially .............................. 18 Added Figure 20 ............................................................................. 19 Added Figure 21, Figure 22, and Figure 23 ................................ 20 Changes to Figure 34 ..................................................................... 21 Changes to Table 15 and Table 17 ............................................... 34 Changes to Figure 47 ..................................................................... 37 Changes to Table 23 ....................................................................... 41 Changes to Table 25 ....................................................................... 46 Changes to Table 49 ....................................................................... 57 Change to Table 75 ........................................................................ 68 5/2016—Rev. 0 to Rev. A Changes to Table 3 ............................................................................4 Changes to Current Range (ICP2) Parameter, Table 5 ...................8 Changes to Table 9 ......................................................................... 11 Changes to Table 10 ....................................................................... 13 Changes to LDOBYP5 Pin Description ...................................... 15 Changes to Figure 13 ..................................................................... 19 Changes to Figure 30 ..................................................................... 25 Changes to Evaluation PCB Section ............................................ 69 Added Figure 46; Renumbered Sequentially .............................. 69 Added Figure 50 ............................................................................. 71 Updated Outline Dimensions ...................................................... 71 9/2015—Revision 0: Initial Version Rev. C | Page 2 of 71 Data Sheet HMC7044 SPECIFICATIONS Unless otherwise noted, fVCXO = 122.88 MHz single-ended; CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, and CLKIN3/CLKIN3 differential at 122.88 MHz; fVCO = 2949.12 MHz; doubler is on; typical value is given for VCC = 3.3 V; and TA = 25°C. Minimum and maximum values are given over the full VCC and TA (−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as CLKIN0/ RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only that function is relevant. CONDITIONS Table 1. Parameter SUPPLY VOLTAGE, VCC VCC1_VCO VCC2_OUT Min Typ Max Unit Test Conditions/Comments 3.135 3.135 3.3 3.3 3.465 3.465 V V VCC3_SYSREF VCC4_OUT 3.135 3.135 3.3 3.3 3.465 3.465 V V VCC5_PLL1 VCC6_OSCOUT VCC7_PLL2 VCC8_OUT 3.135 3.135 3.135 3.135 3.3 3.3 3.3 3.3 3.465 3.465 3.465 3.465 V V V V VCC9_OUT 3.135 3.3 3.465 V 3.3 V ± 5%, supply voltage for VCO and VCO distribution 3.3 V ± 5%, supply voltage for Output Channel 2 and Output Channel 3 3.3 V ± 5%, supply voltage for common SYSREF divider 3.3 V ± 5%, supply voltage for Output Channel 4, Output Channel 5, Output Channel 6, Output Channel 7 3.3 V ± 5%, supply voltage for the LDO used in PLL1 3.3 V ± 5%, supply voltage for oscillator output path 3.3 V ± 5%, supply voltage for the LDO used in PLL2 3.3 V ± 5%, supply voltage for Output Channel 8, Output Channel 9, Output Channel 10, and Output Channel 11 3.3 V ± 5%, supply voltage for Output Channel 0, Output Channel 1, Output Channel 12, and Output Channel 13 −40 +25 +85 °C TEMPERATURE Ambient Temperature Range, TA SUPPLY CURRENT For detailed test conditions, see Table 22 and Table 23. Table 2. Parameter 1, 2 CURRENT CONSUMPTION 3 VCC1_VCO VCC2_OUT 4 VCC3_SYSREF VCC4_OUT4 Min Typ Max Unit 157 65 12 78 225 250 37 500 mA mA mA mA VCC5_PLL1 VCC6_OSCOUT VCC7_PLL2 VCC8_OUT4 39 0 46 124 125 80 80 500 mA mA mA mA VCC9_OUT4 65 500 mA Total Current 586 Test Conditions/Comments Typical value is given at TA = 25°C with two LVDS clocks at divide by 8 Typical value is given at 25°C with two LVPECL high performance clocks, fundamental frequency of internal VCO (fO), 2 SYSREF clocks (off) Typical value is given at 25°C with two LVPECL high performance clocks at divide by 2, 2 SYSREF clocks (off) Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF clocks (off) mA Maximum values are guaranteed by design and characterization. Currents include LVPECL termination currents. Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary synchronization events. 4 Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column. 1 2 3 Rev. C | Page 3 of 71 HMC7044 Data Sheet DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS Table 3. Parameter DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK) Safe Input Voltage Range 1 Input Load Input Voltage Input Logic High (VIH) Input Logic Low (VIL) SPI Bus Frequency DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1) Safe Input Voltage Range1 Input Capacitance Input Resistance Input Voltage Input Logic High (VIH) Input Logic Low (VIL) Input Hysteresis GPIO1 TO GPIO4 ALARM MUXING/DELAY Delay from Internal Alarm/Signal to General-Purpose Output (GPO) Driver DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1) CMOS MODE Logic 1 Level Logic 0 Level Output Drive Resistance (RDRIVE) Output Driver Delay (tDGPO) Min Typ Max Unit +3.6 V pF VCC 0.5 10 V V MHz +3.6 V pF Ω VCC 0.24 0.2 V V V Occurs around 0.85 V 2 ns Does not include tDGPO −0.1 0.3 1.2 0 −0.1 0.4 50G 1.22 0 1.6 1.9 0 50 1.5 + 42 × CLOAD Maximum Supported DC Current1 OPEN-DRAIN MODE1 Logic 1 Level 1 Logic 0 Level 0.13 Pull-Down Impedance Maximum Supported Sink Current 60 Guaranteed by design and characterization. Rev. C | Page 4 of 71 2.2 0.1 V V Ω ns 0.6 mA 3.6 V 0.28 V 5 Ω mA Test Conditions/Comments Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD (CLOAD in nF) External 1 kΩ pull-up resistor 3.6 V maximum permitted; specifications set by external supply Against a 1 kΩ external pull-up resistor to 3.3 V Data Sheet HMC7044 PLL1 CHARACTERISTICS Table 4. Parameter PLL1 REFERENCE INPUTS (CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, CLKIN3/CLKIN3) Reliable Signal Swing Differential Single-Ended 1 Common-Mode Range Input Impedance Return Loss PLL1 REFERENCE DIVIDER 8-Bit Lowest Common Multiple (LCM) Dividers 16-Bit R Divider (R1) PLL1 FEEDBACK DIVIDER 16-Bit N Divider (N1) PLL1 FREQUENCY LIMITATIONS PLL1 REF Input Frequency (fREF) Digital LOS/LCM Frequency (fLCM) PD1 Frequency (fPD1) Min Typ Max Unit Test Conditions/Comments 0.375 1.4 V p-p 0.375 1.4 V p-p 0.4 2.4 V Differential, keep signal at reference input pin ~4ns? TRISTATE LOCKDET MAINTAIN HOLDOVER RST DOWN CP1 LOOP FILTER ÷N1 VCXO 122.88MHz TO PLL2 13033-033 CYCLE SLIP DETECTED (TO PLL1 FSM) Figure 36. PLL1 Architecture with a Typical Frequency Configuration Lock Detect The lock detect circuit in both PLL1 and PLL2 function the same way. They count the number of consecutive clock cycles in which the phase error at the PFD is below a threshold. Any phase error above this threshold resets the counter, and the count is restarted. When the count reaches its programmed limit, the lock detect signal is issued and the clock of the counter is gated off to reduce power/coupling until a large phase error restarts the process. Although the PLL2 loop BW is relatively well defined, the PLL1 loop BW can vary widely in any given application. The SPI word, PLL1 Lock Detect Timer[4:0] in Register 0x0028, configures the PLL1 lock detect timer and looks for 2PLL1 Lock Detect Timer[4:0] consecutive LCM clock cycles with a phase-error