21 GHz to 24 GHz,
GaAs, MMIC, I/Q Upconverter
HMC7912
Data Sheet
FEATURES
GENERAL DESCRIPTION
Conversion gain: 15 dB typical
Sideband rejection: 22 dBc typical
Input power for 1 dB compression (P1dB): 4 dBm typical
Output third-order intercept (OIP3): 33 dBm typical
2× local oscillator (LO) leakage at RFOUT: 5 dBm typical
2× LO leakage at the intermediate frequency (IF) input:
−35 dBm typical
RF return loss: 15 dB typical
LO return loss: 15 dB typical
32-lead, 5 mm × 5 mm LFCSP package
The HMC7912 is a compact, gallium arsenide (GaAs), pseudomorphic (pHEMT), monolithic microwave integrated circuit
(MMIC) upconverter in a RoHS compliant, low stress, injection
molded plastic LFCSP package that operates from 21 GHz to
24 GHz. This device provides a small signal conversion gain of
15 dB with 22 dBc of sideband rejection. The HMC7912 uses a
variable gain amplifier preceded by an in-phase/quadrature (I/Q)
mixer that is driven by an active 2× LO multiplier. IF1 and IF2
mixer inputs are provided, and an external 90° hybrid is needed to
select the required sideband. The I/Q mixer topology reduces
the need for filtering of the unwanted sideband. The HMC7912
is a much smaller alternative to hybrid style single sideband (SSB)
upconverter assemblies, and it eliminates the need for wire
bonding by allowing the use of surface-mount manufacturing
techniques.
APPLICATIONS
Point to point and point to multipoint radios
Military radars, electronic warfare (EW), and electronic
intelligence (ELINT)
Satellite communications
Sensors
NIC
IF1
30
29
28
27
26
VDRF1
IF2
31
VGRF
NIC
32
VESD
NIC
FUNCTIONAL BLOCK DIAGRAM
25
VGMIX 1
24 NIC
NIC 2
23 NIC
NIC 3
22 VDRF2
NIC 4
21 VCTL1
HMC7912
GND 6
20 VCTL2
19 VDRF3
2×
13
14
15
16
NIC
12
GND
11
RFOUT
10
GND
9
VDET
17 NIC
VREF
GND 8
VDLO2
18 VDRF4
VDLO1
LOIN 7
EPAD
13735-001
NIC 5
Figure 1.
Rev. B
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HMC7912
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Leakage Performance ................................................................. 16
Applications ....................................................................................... 1
Return Loss Performance .......................................................... 17
General Description ......................................................................... 1
Power Detector Performance .................................................... 18
Functional Block Diagram .............................................................. 1
Spurious Performance ............................................................... 19
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 20
Specifications..................................................................................... 3
Applications Information .............................................................. 21
Absolute Maximum Ratings ............................................................ 4
Biasing Sequence ........................................................................ 21
Thermal Resistance ...................................................................... 4
Local Oscillator Nulling ............................................................ 21
ESD Caution .................................................................................. 4
Evaluation Printed Circuit Board............................................. 23
Pin Configuration and Function Descriptions ............................. 5
Outline Dimensions ....................................................................... 24
Interface Schematics..................................................................... 6
Ordering Guide .......................................................................... 24
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
4/2018—Rev. A to Rev. B
Changes to Biasing Sequence Section .......................................... 21
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
6/2016—Rev. 0 to Rev. A
Change to the Local Oscillator (LO) Parameter and Output
Third-Order Intercept (OIP3) at Maximum Gain Parameter,
Table 1 ................................................................................................ 3
Changes to Figure 76, Figure 77, Figure 78, Figure 79, Figure 80,
and Figure 81 ................................................................................... 18
4/2016—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
HMC7912
SPECIFICATIONS
TA = 25°C, IF = 1 GHz, VDLOx = 5 V, VDRFx = 5 V, VCTLx = −5 V, VESD = −5 V, VGMIX = −0.5 V, LO = 4 dBm. Measurements performed with upper
sideband selected and external 90° hybrid at the IF ports, unless otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
Frequency Range
Radio Frequency (RF)
Local Oscillator (LO)
Intermediate Frequency (IF)
LO Drive Range
PERFORMANCE
Conversion Gain
Conversion Gain Dynamic Range
Sideband Rejection
Input Power for 1 dB Compression (P1dB)
Output Third-Order Intercept (OIP3) at Maximum Gain
2× LO Leakage at RFOUT1
2× LO Leakage at IFx2
Noise Figure
Return Loss
RF
LO
IFx2
POWER SUPPLY
Total Supply Current
LO Amplifier
RF Amplifier3
Min
Typ
21
8.75
DC
2
10
31
13
22.5
2
Rev. B | Page 3 of 24
Unit
24
12
3.5
8
GHz
GHz
GHz
dBm
15
33
22
4
33
5
−35
14
dB
dB
dBc
dBm
dBm
dBm
dBm
dB
15
15
20
dB
dB
dB
100
220
mA
mA
The LO signal level at the RF output port is not calibrated.
Measurements taken without the 90° hybrid at the IF ports.
3
Adjust VGRF between −2 V and 0 V to achieve a total variable gain amplifier quiescent drain current = 220 mA.
1
Max
HMC7912
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Drain Bias Voltage
VDRFx, VDLOx, VREF, VDET
Gate Bias Voltage
VGRF
VCTLx, VESD
VGMIX
LO Input Power
IF Input Power
Maximum Junction Temperature
Storage Temperature Range
Operating Temperature Range
Reflow Temperature
ESD Sensitivity (HBM)
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages. The θJA
values in Table 3 assume a 4-layer JEDEC standard board with
zero airflow.
Rating
5.5 V
−3 V to 0 V
−7 V to 0 V
−2 V to 0 V
10 dBm
10 dBm
175°C
−65°C to +150°C
−40°C to +85°C
260°C
250 V (Class 1A)
Table 3. Thermal Resistance
Package Type
32-Lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 4 of 24
θJA
31.66
θJC
37.6
Unit
°C/W
Data Sheet
HMC7912
VDRF1
VESD
VGRF
IF1
NIC
NIC
IF2
NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
VGMIX 1
24 NIC
NIC 2
23 NIC
22 VDRF2
NIC 3
NIC 4
HMC7912
21 VCTL1
NIC 5
TOP VIEW
(Not to Scale)
20 VCTL2
GND 6
19 VDRF3
14
15
16
EPAD
NOTES
1. NIC = NOT INTERNALLY CONNECTED. NO CONNECTION IS REQUIRED.
THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA
SHOWN HEREIN WERE MEASURED WITH THESE PINS CONNECTED
EXTERNALLY TO RF/DC GROUND.
2. EXPOSED PAD. CONNECT TO A LOW IMPEDANCE THERMAL AND
ELECTRICAL GROUND PLANE.
13735-002
13
NIC
12
VDET
11
VREF
10
VDLO2
VDLO1
9
GND
17 NIC
GND
18 VDRF4
GND 8
RFOUT
LOIN 7
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VGMIX
2 to 5, 16, 17,
23, 24, 29, 31, 32
6, 8, 13, 15
7
9, 10
NIC
GND
LOIN
VDLO1, VDLO2
11
VREF
12
VDET
14
18, 19, 22, 25
RFOUT
VDRF4, VDRF3,
VDRF2, VDRF1
20, 21
VCTL2, VCTL1
26
VGRF
27
VESD
DC Voltage for ESD Protection. See Figure 13. Refer to the typical application circuit for the required
external components (see Figure 83).
28, 30
IF1, IF2
Quadrature IF Inputs. See Figure 14. For applications not requiring operation to dc, use an off chip dc
blocking capacitor. For operation to dc, these pins must not source/sink more than ±3 mA of current or
device malfunction and failure may result.
Exposed Pad. Connect to a low impedance thermal and electrical ground plane.
EPAD
Description
Gate Voltage for the FET Mixer. See Figure 3. Refer to the typical application circuit for the required external
components (see Figure 83).
Not Internally Connected. No connection is required. These pins are not connected internally. However, all
data shown herein were measured with these pins connected externally to RF/dc ground.
Ground Connect. See Figure 4. These pins and package bottom must be connected to RF/dc ground.
Local Oscillator Input. See Figure 5. This pin is dc-coupled and matched to 50 Ω.
Power Supply Voltage for the LO Amplifier. See Figure 6. Refer to the typical application circuit for the
required external components (see Figure 83).
Reference Voltage for the Power Detector. See Figure 8. VREF is the dc bias of the diode biased through the
external resistor used for temperature compensation of VDET. Refer to the typical application circuit for the
required external components (see Figure 83).
Detector Voltage for the Power Detector. See Figure 8. VDET is the dc voltage representing the RF output
power rectified by the diode, which is biased through an external resistor. Refer to the typical application
circuit for the required external components (see Figure 83).
Radio Frequency Output. See Figure 9. This pin is dc-coupled and matched to 50 Ω.
Power Supply Voltage for the Variable Gain Amplifier. See Figure 10. Refer to the typical application circuit
for the required external components (see Figure 83).
Gain Control Voltage for the Variable Gain Amplifier. See Figure 11. Refer to the typical application circuit
for the required external components (see Figure 83).
Gate Voltage for the Variable Gain Amplifier. See Figure 12. Refer to the typical application circuit for the
required external components (see Figure 83).
Rev. B | Page 5 of 24
HMC7912
Data Sheet
INTERFACE SCHEMATICS
13735-003
13735-009
RFOUT
VGMIX
Figure 9. RFOUT Interface
Figure 3. VGMIX Interface
13735-004
Figure 4. GND Interface
13735-005
LOIN
Figure 10. VDRF1, VDRF2, VDRF3, VDRF4 Interface
13735-011
GND
13735-010
VDRF1 , VDRF2 , VDRF3 , VDRF4
VCTL1, VCTL2
Figure 5. LOIN Interface
Figure 11. VCTL1, VCTL2 Interface
VGRF
13735-008
VESD
IF1, IF2
13735-014
VDET
Figure 13. VESD Interface
13735-007
Figure 7. VREF Interface
13735-013
Figure 12. VGRF Interface
Figure 6. VDLO1, VDLO2 Interface
VREF
13735-012
13735-006
VDLO1, VDLO2
Figure 14. IF1, IF2 Interface
Figure 8. VDET Interface
Rev. B | Page 6 of 24
Data Sheet
HMC7912
TYPICAL PERFORMANCE CHARACTERISTICS
20
18
18
16
14
12
10
8
6
21.0
TA = +85°C
TA = +25°C
TA = –40°C
21.5
22.0
16
14
12
10
8
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
6
21.0
LO
LO
LO
LO
= 0dBm
= 2dBm
= 4dBm
= 6dBm
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 15. Conversion Gain vs. RF Frequency at Various Temperatures,
LO = 4 dBm
13735-018
CONVERSION GAIN (dB)
20
13735-015
CONVERSION GAIN (dB)
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 1 GHz.
Figure 18. Conversion Gain vs. RF Frequency at Various LO Powers
20
20
16
15
4
0
–4
–8
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
10
5
0
–5
–10
–12
–15
–16
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 16. Conversion Gain vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
35
35
SIDEBAND REJECTION (dBc)
40
25
20
15
10
5
0
21.0
TA = +85°C
TA = +25°C
TA = –40°C
21.5
22.0
23.0
RF FREQUENCY (GHz)
23.5
24.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
30
25
20
15
10
5
22.5
–4.0
Figure 19. Conversion Gain vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
40
30
–4.5
= 21GHz
= 22GHz
= 23GHz
= 24GHz
CONTROL VOLTAGE (V)
13735-017
SIDEBAND REJECTION (dBc)
–20
–5.0
13735-016
–20
21.0
RF
RF
RF
RF
Figure 17. Sideband Rejection vs. RF Frequency at Various Temperatures,
LO = 4 dBm
Rev. B | Page 7 of 24
0
21.0
LO
LO
LO
LO
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
RF FREQUENCY (GHz)
23.5
24.0
13735-020
8
13735-019
CONVERSION GAIN (dB)
CONVERSION GAIN (dB)
12
Figure 20. Sideband Rejection vs. RF Frequency at Various LO Powers
HMC7912
Data Sheet
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 1 GHz.
40
36
34
17
32
IP3 (dBm)
19
15
13
9
24
7
22
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
20
21.0
38
21
36
19
34
17
32
IP3 (dBm)
15
13
11
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
20
21.0
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
Figure 25. Output IP3 vs. RF Frequency at Various LO Powers
48
28
44
26
40
24
36
22
32
IP3 (dBm)
20
18
16
14
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
28
24
20
16
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
21.5
22.0
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
22.5
23.0
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
23.5
12
8
4
24.0
RF FREQUENCY (GHz)
13735-023
6
21.0
LO
LO
LO
LO
RF FREQUENCY (GHz)
30
8
24.0
28
22
Figure 22. Input IP3 vs. RF Frequency at Various LO Powers
10
23.5
30
24
RF FREQUENCY (GHz)
12
23.0
26
LO
LO
LO
LO
13735-022
5
21.0
22.5
13735-025
IP3 (dBm)
40
23
7
22.0
Figure 24. Output IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
25
9
21.5
RF FREQUENCY (GHz)
Figure 21. Input IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
IP3 (dBm)
28
26
5
21.0
TA = +85°C
TA = +25°C
TA = –40°C
30
11
13735-021
IP3 (dBm)
21
38
Figure 23. Input IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
0
21.0
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 26. Output IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
Rev. B | Page 8 of 24
13735-026
23
TA = +85°C
TA = +25°C
TA = –40°C
13735-024
25
Data Sheet
HMC7912
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 1 GHz.
40
35
30
RF
RF
RF
RF
= 21GHz
= 22GHz
= 23GHz
= 24GHz
35
30
25
IP3 (dBm)
IP3 (dBm)
25
20
15
20
15
10
10
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
CONTROL VOLTAGE (V)
0
–5.0
13735-027
Figure 27. Input IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
P1dB (dBm)
20
0
–2.5
–1.5
–2.0
–1.0
–4
12
21.5
22.0
22.5
23.0
23.5
24.0
TA = +85°C
TA = +25°C
TA = –40°C
16
14
RF FREQUENCY (GHz)
10
21.0
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 28. Input P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
Figure 31. Output P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
25
25
TA = +85°C
TA = +25°C
TA = –40°C
23
21
NOISE FIGURE (dB)
19
17
15
13
11
17
15
13
11
9
7
7
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
TA = +85°C
TA = +25°C
TA = –40°C
19
9
5
1.0
13735-029
NOISE FIGURE (dB)
–3.0
18
–2
5
21.0
–3.5
13735-031
2
13735-028
P1dB (dBm)
24
4
21
–4.0
26
TA = +85°C
TA = +25°C
TA = –40°C
22
23
–4.5
Figure 30. Output IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
6
–6
21.0
= 21GHz
= 22GHz
= 23GHz
= 24GHz
CONTROL VOLTAGE (V)
10
8
RF
RF
RF
RF
1.5
2.0
2.5
3.0
3.5
IF FREQUENCY (GHz)
Figure 29. Noise Figure vs. RF Frequency at Various Temperatures,
LO = 6 dBm
Figure 32. Noise Figure vs. IF Frequency at Various Temperatures,
LO = 6 dBm, LO Frequency = 19 GHz
Rev. B | Page 9 of 24
13735-032
0
–5.0
5
13735-030
5
HMC7912
Data Sheet
20
18
18
16
14
12
10
8
6
21.0
TA = +85°C
TA = +25°C
TA = –40°C
21.5
22.0
16
14
12
10
8
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
6
21.0
LO
LO
LO
LO
= 0dBm
= 2dBm
= 4dBm
= 6dBm
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 33. Conversion Gain vs. RF Frequency at Various Temperatures,
LO = 4 dBm
13735-036
CONVERSION GAIN (dB)
20
13735-033
CONVERSION GAIN (dB)
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 2 GHz.
Figure 36. Conversion Gain vs. RF Frequency at Various LO Powers
20
20
16
15
8
0
–4
–8
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
5
0
–5
–10
–12
–15
–16
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
–20
–5.0
13735-034
–20
21.0
Figure 34. Conversion Gain vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
40
35
SIDEBAND REJECTION (dBc)
SIDEBAND REJECTION (dBc)
–4.0
Figure 37. Conversion Gain vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
TA = +85°C
TA = +25°C
TA = –40°C
30
25
20
15
10
30
25
20
15
10
5
5
21.5
22.0
22.5
23.0
RF FREQUENCY (GHz)
23.5
24.0
0
21.0
13735-035
0
21.0
–4.5
= 21GHz
= 22GHz
= 23GHz
= 24GHz
CONTROL VOLTAGE (V)
40
35
RF
RF
RF
RF
Figure 35. Sideband Rejection vs. RF Frequency at Various Temperatures,
LO = 4 dBm
LO
LO
LO
LO
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
RF FREQUENCY (GHz)
23.5
24.0
13735-038
4
10
13735-037
CONVERSION GAIN (dB)
CONVERSION GAIN (dB)
12
Figure 38. Sideband Rejection vs. RF Frequency at Various LO Powers
Rev. B | Page 10 of 24
Data Sheet
HMC7912
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 2 GHz.
40
36
34
17
32
IP3 (dBm)
19
15
13
9
24
7
22
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
20
21.0
38
21
36
19
34
17
32
IP3 (dBm)
40
23
15
13
11
5
21.0
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
20
21.0
24.0
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
LO
LO
LO
LO
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 43. Output IP3 vs. RF Frequency at Various LO Powers
48
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
44
40
26
36
24
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
VCTLx = –2.3V
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
32
IP3 (dBm)
22
20
18
28
24
20
16
16
12
14
10
21.0
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
21.5
22.0
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
22.5
23.0
8
VCTLx = –1.3V
VCTLx = –1.0V
23.5
4
24.0
RF FREQUENCY (GHz)
Figure 41. Input IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
0
21.0
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 44. Output IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
Rev. B | Page 11 of 24
13735-044
12
13735-041
IP3 (dBm)
23.5
28
22
Figure 40. Input IP3 vs. RF Frequency at Various LO Powers
28
23.0
30
24
RF FREQUENCY (GHz)
30
22.5
26
LO
LO
LO
LO
13735-040
7
22.0
Figure 42. Output IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
25
9
21.5
RF FREQUENCY (GHz)
Figure 39. Input IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
IP3 (dBm)
28
26
5
21.0
TA = +85°C
TA = +25°C
TA = –40°C
30
11
13735-039
IP3 (dBm)
21
38
13735-043
23
TA = +85°C
TA = +25°C
TA = –40°C
13735-042
25
HMC7912
Data Sheet
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 2 GHz.
40
35
30
RF
RF
RF
RF
= 21GHz
= 22GHz
= 23GHz
= 24GHz
35
30
25
IP3 (dBm)
IP3 (dBm)
25
20
15
20
15
10
10
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
CONTROL VOLTAGE (V)
0
–5.0
13735-045
Figure 45. Input IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
P1dB (dBm)
2
0
–2.0
–1.5
–1.0
14
–4
12
21.5
22.0
22.5
23.0
23.5
24.0
Figure 46. Input P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
10
21.0
19
17
15
13
11
9
22.5
23.0
23.5
24.0
13735-047
7
RF FREQUENCY (GHz)
22.0
22.5
23.0
23.5
24.0
Figure 49. Output P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
TA = +85°C
TA = +25°C
TA = –40°C
22.0
21.5
RF FREQUENCY (GHz)
25
21.5
TA = +85°C
TA = +25°C
TA = –40°C
16
–2
RF FREQUENCY (GHz)
NOISE FIGURE (dB)
–2.5
18
13735-046
P1dB (dBm)
20
5
21.0
–3.0
24
4
21
–3.5
26
TA = +85°C
TA = +25°C
TA = –40°C
22
23
–4.0
Figure 48. Output IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
6
–6
21.0
–4.5
= 21GHz
= 22GHz
= 23GHz
= 24GHz
CONTROL VOLTAGE (V)
10
8
RF
RF
RF
RF
Figure 47. Noise Figure vs. RF Frequency at Various Temperatures,
LO = 6 dBm
Rev. B | Page 12 of 24
13735-049
0
–5.0
5
13735-048
5
Data Sheet
HMC7912
20
18
18
16
14
12
10
21.5
22.0
22.5
23.0
23.5
24.0
6
21.0
CONVERSION GAIN (dB)
20
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
8
4
0
–4
–8
–12
23.5
24.0
RF FREQUENCY (GHz)
–5
–10
35
35
SIDEBAND REJECTION (dBc)
40
30
25
20
15
10
TA = +85°C
TA = +25°C
TA = –40°C
21.5
22.0
23.0
RF FREQUENCY (GHz)
23.5
24.0
Figure 52. Sideband Rejection vs. RF Frequency at Various Temperatures,
LO = 4 dBm
–4.5
= 21GHz
= 22GHz
= 23GHz
= 24GHz
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
30
25
20
15
10
5
22.5
RF
RF
RF
RF
Figure 54. Conversion Gain vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
40
0
21.0
24.0
CONTROL VOLTAGE (V)
0
21.0
13735-052
SIDEBAND REJECTION (dBc)
Figure 51. Conversion Gain vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
5
23.5
0
–20
–5.0
13735-051
23.0
23.0
5
–16
22.5
22.5
10
–15
22.0
22.0
15
12
21.5
21.5
20
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
16
–20
21.0
= 0dBm
= 2dBm
= 4dBm
= 6dBm
Figure 53. Conversion Gain vs. RF Frequency at Various LO Powers
CONVERSION GAIN (dB)
24
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
LO
LO
LO
LO
RF FREQUENCY (GHz)
Figure 50. Conversion Gain vs. RF Frequency at Various Temperatures,
LO = 4 dBm
28
10
8
RF FREQUENCY (GHz)
32
12
13735-054
6
21.0
TA = +85°C
TA = +25°C
TA = –40°C
14
LO
LO
LO
LO
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
RF FREQUENCY (GHz)
23.5
24.0
13735-055
8
16
13735-053
CONVERSION GAIN (dB)
20
13735-050
CONVERSION GAIN (dB)
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 3 GHz.
Figure 55. Sideband Rejection vs. RF Frequency at Various LO Powers
Rev. B | Page 13 of 24
HMC7912
Data Sheet
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 3 GHz.
40
36
34
17
32
IP3 (dBm)
19
15
13
9
24
7
22
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
20
21.0
38
21
36
19
34
17
32
IP3 (dBm)
15
13
11
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
20
21.0
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
21.5
= 0dBm
= 2dBm
= 4dBm
= 6dBm
22.0
22.5
23.0
23.5
24.0
Figure 60. Output IP3 vs. RF Frequency at Various LO Powers
52
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
LO
LO
LO
LO
RF FREQUENCY (GHz)
30
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
48
44
26
40
24
VCTLx = –5.0V
VCTLx = –4.8V
VCTLx = –4.5V
VCTLx = –4.3V
VCTLx = –4.0V
VCTLx = –3.8V
VCTLx = –3.5V
VCTLx = –3.3V
VCTLx = –3.0V
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
VCTLx = –1.3V
VCTLx = –1.0V
36
IP3 (dBm)
22
20
18
32
28
24
20
16
16
12
14
VCTLx = –2.8V
VCTLx = –2.5V
VCTLx = –2.3V
21.5
22.0
VCTLx = –2.0V
VCTLx = –1.8V
VCTLx = –1.5V
22.5
23.0
8
VCTLx = –1.3V
VCTLx = –1.0V
23.5
24.0
RF FREQUENCY (GHz)
4
13735-058
10
21.0
24.0
28
22
Figure 57. Input IP3 vs. RF Frequency at Various LO Powers
12
23.5
30
24
RF FREQUENCY (GHz)
28
23.0
26
LO
LO
LO
LO
13735-057
5
21.0
22.5
13735-060
IP3 (dBm)
40
23
7
22.0
Figure 59. Output IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
25
9
21.5
RF FREQUENCY (GHz)
Figure 56. Input IP3 vs. RF Frequency at Various Temperatures,
LO = 4 dBm
IP3 (dBm)
28
26
5
21.0
TA = +85°C
TA = +25°C
TA = –40°C
30
11
13735-056
IP3 (dBm)
21
38
Figure 58. Input IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
0
21.0
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 61. Output IP3 vs. RF Frequency at Various Control Voltages,
LO = 4 dBm
Rev. B | Page 14 of 24
13735-061
23
TA = +85°C
TA = +25°C
TA = –40°C
13735-059
25
Data Sheet
HMC7912
Data taken as SSB upconverter with external IF 90° hybrid at the IF ports, IF = 3 GHz.
40
35
30
RF
RF
RF
RF
= 21GHz
= 22GHz
= 23GHz
= 24GHz
35
30
25
IP3 (dBm)
IP3 (dBm)
25
20
15
20
15
10
10
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
CONTROL VOLTAGE (V)
0
–5.0
13735-062
Figure 62. Input IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
P1dB (dBm)
20
2
0
14
–4
12
21.5
22.0
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
Figure 63. Input P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
10
21.0
–2.0
–1.5
–1.0
19
17
15
13
11
9
22.5
23.0
23.5
24.0
RF FREQUENCY (GHz)
13735-064
7
22.0
21.5
22.0
22.5
23.0
23.5
24.0
Figure 66. Output P1dB vs. RF Frequency at Various Temperatures,
LO = 4 dBm
TA = +85°C
TA = +25°C
TA = –40°C
21.5
TA = +85°C
TA = +25°C
TA = –40°C
RF FREQUENCY (GHz)
25
NOISE FIGURE (dB)
–2.5
16
–2
5
21.0
–3.0
18
13735-063
P1dB (dBm)
24
4
21
–3.5
26
TA = +85°C
TA = +25°C
TA = –40°C
22
23
–4.0
Figure 65. Output IP3 vs. Control Voltage at Various RF Frequencies,
LO = 4 dBm
6
–6
21.0
–4.5
= 21GHz
= 22GHz
= 23GHz
= 24GHz
CONTROL VOLTAGE (V)
10
8
RF
RF
RF
RF
Figure 64. Noise Figure vs. RF Frequency at Various Temperatures,
LO = 6 dBm
Rev. B | Page 15 of 24
13735-066
0
–5.0
5
13735-065
5
HMC7912
Data Sheet
LEAKAGE PERFORMANCE
20
–10
TA = +85°C
TA = +25°C
TA = –40°C
15
TA = +85°C
TA = +25°C
TA = –40°C
–15
LEAKAGE (dBm)
LEAKAGE (dBm)
–20
10
5
0
–25
–30
–35
–40
–5
18
19
20
21
22
23
24
LO FREQUENCY (GHz)
–50
17
13735-067
–10
17
18
19
20
21
22
23
24
LO FREQUENCY (GHz)
Figure 67. 2× LO Leakage at RFOUT vs. LO Frequency at
Various Temperatures, LO = 4 dBm
13735-070
–45
Figure 70. 2× LO Leakage at IF1 vs. LO Frequency at
Various Temperatures, LO = 4 dBm
–10
–10
–15
–15
–20
–20
LEAKAGE (dBm)
LEAKAGE (dBm)
–25
–25
–30
–35
–30
–35
–40
–45
–40
–50
18
19
20
21
22
23
24
LO FREQUENCY (GHz)
13735-068
–50
17
Figure 68. 2× LO Leakage at IF2 vs. LO Frequency at
Various Temperatures, LO = 4 dBm
TA = +85°C
TA = +25°C
TA = –40°C
–20
–30
–35
–40
–45
–50
–55
–60
–65
–70
0.5
1.0
1.5
2.0
2.5
3.0
IF FREQUENCY (GHz)
3.5
13735-069
LEAKAGE (dBm)
–25
0
–60
0
0.5
1.0
1.5
2.0
2.5
3.0
IF FREQUENCY (GHz)
Figure 71. IF1 Leakage at RFOUT vs. IF Frequency at
Various Temperatures
–10
–15
TA = +85°C
TA = +25°C
TA = –40°C
–55
Figure 69. IF2 Leakage at RFOUT vs. IF Frequency at
Various Temperatures
Rev. B | Page 16 of 24
3.5
13735-071
TA = +85°C
TA = +25°C
TA = –40°C
–45
Data Sheet
HMC7912
RETURN LOSS PERFORMANCE
0
–10
–15
–20
–10
–15
–20
–25
21.5
22.0
22.5
23.0
23.5
24.0
–30
8.0
RF FREQUENCY (GHz)
Figure 72. RF Return Loss vs. RF Frequency at Various Temperatures,
LO = 4 dBm at LO Frequency = 20 GHz
10.0
10.5
11.0
11.5
12.0
0
TA = +85°C
TA = +25°C
TA = –40°C
–5
TA = +85°C
TA = +25°C
TA = –40°C
–15
–20
–25
–15
–20
–25
–30
–30
–35
–35
1.0
1.5
2.0
2.5
3.0
3.5
IF FREQUENCY (GHz)
Figure 73. IF1 Return Loss vs. IF Frequency at Various Temperatures,
LO = 4 dBm at LO Frequency = 20 GHz
–40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IF FREQUENCY (GHz)
Figure 75. IF2 Return Loss vs. IF Frequency at Various Temperatures,
LO = 4 dBm at LO Frequency = 20 GHz
Rev. B | Page 17 of 24
13735-075
RETURN LOSS (dB)
–10
13735-073
RETURN LOSS (dB)
9.5
Figure 74. LO Return Loss vs. LO Frequency at Various Temperatures,
LO = 4 dBm
–10
–40
0.5
9.0
LO FREQUENCY (GHz)
0
–5
8.5
13735-074
–25
13735-072
–30
21.0
TA = +85°C
TA = +25°C
TA = –40°C
–5
RETURN LOSS (dB)
RETURN LOSS (dB)
–5
0
TA = +85°C
TA = +25°C
TA = –40°C
HMC7912
Data Sheet
POWER DETECTOR PERFORMANCE
0.1
0.1
0.01
–16 –14 –12 –10 –8
TA = +85°C
TA = +25°C
TA = –40°C
–6
–4
–2
0
2
4
6
8
10
OUTPUT POWER (dBm)
Figure 76. Detector Output Voltage (VREF − VDET) vs. Output Power at Various
Temperatures, LO = 17.5 GHz
0.001
–16 –14 –12 –10 –8
–6
–4
–2
0
2
4
6
8
10
Figure 79. Detector Sensitivity vs. Output Power at Various Temperatures,
LO = 17.5 GHz
0.1
0.1
0.01
–16 –14 –12 –10 –8
TA = +85°C
TA = +25°C
TA = –40°C
–6
–4
–2
0
2
4
6
8
10
OUTPUT POWER (dBm)
Figure 77. Detector Output Voltage (VREF − VDET) vs. Output Power at Various
Temperatures, LO = 19 GHz
0.01
0.001
–16 –14 –12 –10 –8
TA = +85°C
TA = +25°C
TA = –40°C
–6
–4
–2
0
2
4
6
8
10
OUTPUT POWER (dBm)
13735-080
SENSITIVITY (V/dB)
1
13735-077
Figure 80. Detector Sensitivity vs. Output Power at Various Temperatures,
LO = 19 GHz
0.1
SENSITIVITY (V/dB)
10
1
0.1
–6
–4
–2
0
2
OUTPUT POWER (dBm)
4
6
8
10
0.001
–16 –14 –12 –10 –8
13735-078
0.01
–16 –14 –12 –10 –8
TA = +85°C
TA = +25°C
TA = –40°C
Figure 78. Detector Output Voltage (VREF − VDET) vs. Output Power at Various
Temperatures, LO = 20.5 GHz
0.01
TA = +85°C
TA = +25°C
TA = –40°C
–6
–4
–2
0
2
OUTPUT POWER (dBm)
4
6
8
10
13735-081
OUTPUT VOLTAGE (V)
TA = +85°C
TA = +25°C
TA = –40°C
OUTPUT POWER (dBm)
10
OUTPUT VOLTAGE (V)
0.01
13735-079
SENSITIVITY (V/dB)
1
13735-076
OUTPUT VOLTAGE (V)
10
Figure 81. Detector Sensitivity vs. Output Power at Various Temperatures,
LO = 20.5 GHz
Rev. B | Page 18 of 24
Data Sheet
HMC7912
SPURIOUS PERFORMANCE
M × N Spurious Output, RF = 24 GHz
TA = 25°C, IF = 1 GHz, VDLOx = 5 V, VDRFx = 5 V, VCTLx = −5 V,
VESD = −5 V, VGMIX = −0.5 V.
IF = 1 GHz at IF input power = −6 dBm, LO frequency =
23 GHz at LO input = +4 dBm.
Mixer spurious products are measured in dBc from the RF
output power level. Spur values are (M × IF) + (N × LO). N/A
means not applicable.
M × N Spurious Outputs, RF = 21 GHz
IF = 1 GHz at IF input power = −6 dBm, LO frequency =
20 GHz at LO input power = +4 dBm.
M × IF
0
1
2
3
4
5
0
N/A
53
73
90
101
114
1
5
0
37
66
77
102
N × LO
2
3
66
N/A
52
N/A
52
N/A
85
N/A
95
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
N/A
N/A
IF = 2 GHz at IF input power = −6 dBm, LO frequency =
19 GHz at LO input power = +4 dBm.
M × IF
0
1
2
3
4
5
0
N/A
61
63
79
115
114
1
11
N/A
44
60
81
91
N × LO
2
3
73
N/A
66
N/A
51
N/A
74
N/A
N/A
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
N/A
N/A
IF = 3 GHz at IF input power = −6 dBm, LO frequency =
18 GHz at LO input = +4 dBm.
M × IF
0
1
2
3
4
5
0
N/A
50
57
59
64
25
1
3
0
43
34
51
56
N × LO
2
3
62
N/A
64
N/A
51
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
M × IF
0
1
2
3
4
5
0
N/A
59
74
91
90
113
1
4
0
39
58
70
80
N × LO
2
N/A
N/A
N/A
N/A
N/A
N/A
3
N/A
N/A
N/A
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
N/A
N/A
IF = 2 GHz at IF input power = −6 dBm, LO frequency =
22 GHz at LO input power = +4 dBm.
M × IF
0
1
2
3
4
5
0
N/A
60
61
73
93
113
1
5
0
44
61
74
86
N × LO
2
64
N/A
N/A
N/A
N/A
N/A
3
N/A
N/A
N/A
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
N/A
N/A
IF = 3 GHz at IF input power = −6 dBm, LO frequency =
21 GHz at LO input power = +4 dBm.
M × IF
5
N/A
N/A
N/A
N/A
N/A
N/A
Rev. B | Page 19 of 24
0
1
2
3
4
5
0
N/A
56
57
81
88
47
1
4
0
49
69
84
76
N × LO
2
3
N/A
58
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
47
4
N/A
N/A
N/A
N/A
N/A
N/A
5
N/A
N/A
N/A
N/A
N/A
N/A
HMC7912
Data Sheet
THEORY OF OPERATION
an on-chip Wilkinson power combiner and relatively matched
to provide a single-ended 50 Ω output signal that is amplified
by the RF amplifiers to produce a dc-coupled and 50 Ω matched
RF output signal at the RFOUT port. A voltage attenuator precedes
the RF amplifiers for desired gain control.
The HMC7912 is a GaAs, pHEMT, MMIC I/Q upconverter with
an integrated LO buffer that upconverts intermediate frequencies
between dc and 3.5 GHz to radio frequencies between 21 GHz
and 24 GHz. LO buffer amplifiers are included on chip to allow
a typical LO drive level of only 4 dBm for full performance. The
LO path feeds a quadrature splitter followed by on-chip baluns
that drive the I and Q singly balanced cores of the passive mixers.
The RF output of the I and Q mixers are then summed through
ESD
ESD
ESD
I
VDLO2
VDLO1
ESD
VDRF1
ESD
VDRF2
ESD
ESD
VDRF3
VDRF4
2×
VGMIX
RFOUT
VDET
VREF
Q
VCTL1
ESD
ESD
VGRF VCTL2
ESD
ESD
Figure 82. Upconverter Circuit Architecture
Rev. B | Page 20 of 24
ESD
ESD
13735-082
LOIN
The power detector feature provides a LO cancellation capability
to the level of −10 dBm. See Figure 82 for a functional block
diagram of the upconverter circuit architecture.
Data Sheet
HMC7912
APPLICATIONS INFORMATION
A typical lower sideband upconversion circuit is shown in
Figure 83. The lower sideband input signal is connected to the
input port of the 90° hybrid coupler. The isolated port is loaded
to 50 Ω. The external 90° hybrid splits the IF signal into I and Q
phase terms. The I and Q input signals enter the HMC7912 on
the IF1 and IF2 inputs. IF1 of the device is connected to the 0°
port of the hybrid coupler. IF2 is connected to the 90° port of
the hybrid coupler. The LO to RF leakage can be improved by
applying small dc offsets to the I/Q mixer cores via the VDC_IF1
and VDC_IF2 inputs. However, it is important to limit the applied
dc bias to avoid sourcing or sinking more than ±3 mA of bias
current. Depending on the bias sources used, it may be prudent to
add series resistance to ensure that the applied bias current does
not exceed ±3 mA.
Biasing the power detector circuitry may degrade the IP3
performance. Therefore, to achieve optimum IP3 performance
it is recommended that the power detector of the HMC7912 be
kept in off mode.
BIASING SEQUENCE
The HMC7912 uses buffer amplifiers in the LO and RF paths.
These active stages all use depletion mode pHEMTs. To ensure
transistor damage does not occur, use the following power-up
bias sequence:
1.
2.
3.
4.
5.
6.
7.
Apply 5 V to Pin 9 (VDLO1) and Pin 10 (VDLO2).
Apply −5 V to Pin 20 (VCTL2) and Pin 21 (VCTL1). Adjust
VCTL1 and VCTL2 between −5 V and 0 V depending on the
amount of attenuation desired.
Apply 5 V to Pin 18, Pin 19, Pin 22, and Pin 25 (VDRF4,
VDRF3, VDRF2, and VDRF1).
Adjust Pin 26 (VGRF) between −2 V and 0 V to achieve a
total amplifier quiescent drain current of 220 mA.
LOCAL OSCILLATOR NULLING
Broad LO nulling may be required to achieve optimum IP3 and
LO to RF isolation performance. This nulling is achieved by
applying dc voltages between −0.2 V and +0.2 V to the I and Q
ports to suppress the LO signal across the RF frequency band by
approximately 5 dBc to 10 dBc. To suppress the LO signal at the
RF port, use the following nulling sequence:
1.
2.
3.
Apply a −5 V bias to Pin 27 (VESD).
Apply a −2 V bias to Pin 26 (VGRF), which is a pinched
off state.
Apply a −0.5 V bias to Pin 1 (VGMIX). This bias can be
adjusted from −0.5 V to −1 V depending on the LO power
used to provide the optimum IP3 response of the mixer.
Rev. B | Page 21 of 24
Adjust VDC_IF1 between −0.2 V and +0.2 V and monitor the
LO leakage on the RF port. When the desired or maximum
level of suppression is achieved, proceed to Step 2.
Adjust VDC_IF2 between −0.2 V and +0.2 V and monitor the
LO leakage on the RF port until either the desired or the
maximum level of suppression is achieved.
If the desired level of the LO signal on the RF port has still
not been achieved, further tune each VDC_IF1 and VDC_IF2
independently to achieve the desired LO leakage. The
resolution of the voltage changed on the voltage of the
VDC_IF1 and VDC_IF2 inputs must be in the millivolt range.
HMC7912
Data Sheet
IF1
IFIN
IF2
HYBRID
COUPLER
VDC_IF2
100nF
100pF
100pF
33nH
100pF
VDC_IF1
33nH
100pF
100nF
VESD
100pF
100nF
4.7µF
+
VGRF
100pF
100nF
4.7µF
+
100pF
100nF
4.7µF
100pF
100nF
4.7µF
100pF
100nF
4.7µF
100pF
100nF
4.7µF
100pF
100nF
4.7µF
100pF
100nF
4.7µF
+
VDRF1
32 31 30 29 28 27 26 25
VGMIX
100pF
100nF
4.7µF
+
1
24
2
23
3
22
4
LOIN
20
6
19
7
18
8
17
VDRF2
VCTL1
21
HMC7912
5
+
+
VCTL2
+
9 10 11 12 13 14 15 16
GND
4.7µF
VDLO2
4.7µF
+
+
100pF
100nF
100pF
100nF
VREF
+
VDRF3
VDRF4
RFOUT
VDET
VDET
VREF
VREF
VDET
100nF
100pF
+5V
100kΩ
10kΩ
10kΩ
33kΩ
VD_5V
100kΩ
33kΩ
10kΩ
–5V
10kΩ
VOUT = VREF – VDET
+5V
ALTERNATE SUGGESTED CIRCUIT
Figure 83. Typical Application Circuit
Rev. B | Page 22 of 24
13735-083
VDLO1
+
Data Sheet
HMC7912
EVALUATION PRINTED CIRCUIT BOARD
Use a sufficient number of via holes to connect the top and
bottom ground planes. The evaluation circuit board shown in
Figure 84 is available from Analog Devices, Inc., upon request.
The circuit board used in this application must use RF circuit
design techniques. Signal lines must have 50 Ω impedance and
the package ground leads and exposed pad must be connected
directly to the ground plane similar to that shown in Figure 84.
J3
L1
+
U1
VDLO2 C32
VDREF
VD_5V
C6
C77
R2
+
C50
C25
VDD3 +
VDD4
C65
+
J7
C57
RFOUT
J4
600-01346-00-2
13735-084
+
C9
R1
C26
VDOUT + C27
C78
C51
+
GN D
C5
J8
C5
6
C2
C4
VDLO1
+
C3
C3
1
LOIN
C1
C29
C28
+
J1
VGRF
C61
C49 VDLNA +
VDD2
C47
C45
C18
C44
C17
C15
C16
C13
C10 C11
VCTL1
C7
+C8VCTL2
C12
C4 C
6 48
C30
-5ESD
+
GN D
C62
+
+
C64
J5
C75
J6
VI
GN D
C70
VQ
VADJUST
GN D
I
GN D
C76
Q
C71
C72
L2
C69
C74
C73
J2
Figure 84. Evaluation Board Top Layer
Rev. B | Page 23 of 24
HMC7912
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
1
24
0.50
BSC
3.80
3.70 SQ
3.60
EXPOSED
PAD
17
0.45
0.40
0.35
TOP VIEW
0.90
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004898
8
16
9
BOTTOM VIEW
3.50 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4.
03-09-2017-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.85 mm Package Height
(HCP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC7912LP5E
HMC7912LP5ETR
EV1HMC7912LP5
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
MSL Rating2
MSL3
MSL3
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Assembly Board
HMC7912LP5E and HMC7912LP5ETR are RoHS compliant parts.
The peak reflow temperature is 260°C. See the Absolute Maximum Ratings section, Table 2.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13735-0-4/18(B)
Rev. B | Page 24 of 24
Package Option
HCP-32-1
HCP-32-1
工商网监
湘ICP备2023018690号
