9 GHz to 10 GHz,
X-Band, GaAs, MMIC, Low Noise Converter
HMC8108
Data Sheet
25 NIC
24
NIC
2
23
BUFF_VD
LNA_VG1
3
22
NIC
NIC
4
21
NIC
RFIN
5
20
LOIN
NIC
6
19
NIC
VCTRL
7
18
NIC
NIC
8
17
NIC
MIX_VG 15
BUFF_VG 16
NIC 14
IF_I 13
NIC 11
NIC
NIC 12
HMC8108
EPAD
15133-001
26 GND
27 NIC
28 IF_Q
29 NIC
30 LNA_VD2
1
NIC
9
Point to point and point to multipoint radios
Military radar
Satellite communications
NIC
LNA_VG2 10
APPLICATIONS
31 NIC
FUNCTIONAL BLOCK DIAGRAM
Conversion gain: 13 dB typical
Image rejection: 20 dBc typical
Noise figure: 2 dB typical
Input power for 1 dB compression: −4 dBm typical
Input third-order intercept: 6 dBm typical
Output saturated power: 10 dBm typical
LO leakage at the IF port: −20 dBm typical
LO leakage at the RF port: −37 dBm typical
32-terminal, 5 mm × 5 mm, ceramic leadless chip carrier (LCC)
32 LNA_VD1
FEATURES
Figure 1.
GENERAL DESCRIPTION
The HMC8108 is a compact, X-band, gallium arsenide (GaAs),
monolithic microwave integrated circuit (MMIC) in-phase/
quadrature (I/Q), low noise converter in a ceramic, leadless chip
carrier, RoHS compliant package. The HMC8108 converts radio
frequency (RF) input signals ranging from 9 GHz to 10 GHz to a
typical single-ended intermediate frequency (IF) signal of 60 MHz
at its output. This device provides a small signal conversion gain
of 13 dB with a noise figure of 2 dB and image rejection of 20 dBc.
Rev. 0
The HMC8108 uses a low noise amplifier followed by an image
reject mixer that is driven by an active LO buffer amplifier. The
image reject mixer eliminates the need for a filter following the
low noise amplifier and removes thermal noise at the image
frequency. I/Q mixer outputs are provided, and an external 90°
hybrid is needed to select the required sideband. The HMC8108
is a much smaller alternative to hybrid style, image reject mixer,
downconverter assemblies and is compatible with surface-mount
manufacturing techniques.
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Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC8108
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................7
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 14
General Description ......................................................................... 1
Applications Information .............................................................. 15
Revision History ............................................................................... 2
Biasing Sequence ........................................................................ 15
Specifications..................................................................................... 3
Results .......................................................................................... 15
Absolute Maximum Ratings............................................................ 4
Evaluation Board Information ................................................. 17
Thermal Resistance ...................................................................... 4
Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 4
Ordering Guide .......................................................................... 18
Pin Configuration and Function Descriptions ............................. 5
REVISION HISTORY
2/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 18
Data Sheet
HMC8108
SPECIFICATIONS
TA = −25°C, IF = 60 MHz, LNA_VD1/LNA_VD2 = +3 V, BUFF_VD = +3 V, VCTRL = −1 V, MIX_VG = −1.4 V, LO power= −5 dBm,
downconverter mode with lower side selected and external 90° hybrid at the IF ports, unless otherwise noted.
Table 1.
Parameter
OPERATING CONDITIONS
Frequency Range
Radio Frequency
Local Oscillator
Intermediate Frequency
LO Input Level
PERFORMANCE
Conversion Gain
Gain Variation Range
Noise Figure
Image Rejection
Input Power for 1 dB Compression
Input Third-Order Intercept
Input Second-Order Intercept
Output Saturated Power
LO Leakage at the IF Port 1
LO Leakage at the RF Port
RF Leakage at the IF Port1
Amplitude Balance1
Phase Balance1
Return Loss
RF Port
LO Port
IF Port1
POWER SUPPLY
LNA_VD1
LNA_VD2
BUFF_VD
1
Symbol
Min
RF
LO
IF
9
9
0.02
−10
10
10
NF
15
P1dB
IP3
IP2
PSAT
Measurements performed without external 90° hybrid at the IF ports.
Rev. 0 | Page 3 of 18
2
Typ
13
15
2
20
−4
6
12
10
−20
−37
−27
3
4
Max
Unit
10
10
1
0
GHz
GHz
GHz
dBm
2.5
−25
dB
dB
dB
dBc
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dB
Degree
15
9
20
dB
dB
dB
20
30
40
mA
mA
mA
HMC8108
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Drain Bias Voltage
LNA_VD1
LNA_VD2
BUFF_VD
Gate Bias Voltage
LNA_VG1
LNA_VG2
MIX_VG
BUFF_VG
VCTRL
RF Input Power
LO Input Power
Maximum Peak Reflow Temperature (MSL3)1
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model (FICDM)
1
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
5.8 V
4.8 V
4.2 V
Table 3. Thermal Resistance
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
−2 V to + 0.15 V
20 dBm
24 dBm
260°C
165°C
−40°C to +85°C
−65°C to 150°C
Package Type
E-32-11
1
θJA
93
θJC
119.47
Unit
°C/W
See JEDEC standard JESD51-2 for additional information on optimizing the
thermal impedance (PCB with 3 × 3 vias).
ESD CAUTION
Class 0 (150 V)
Class C3 (250 V)
See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 4 of 18
Data Sheet
HMC8108
32
31
30
29
28
27
26
25
LNA_VD1
NIC
LNA_VD2
NIC
IF_Q
NIC
GND
NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC8108
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
NIC
BUFF_VD
NIC
NIC
LOIN
NIC
NIC
NIC
EPAD
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
15133-002
NIC
LNA_VG2
NIC
NIC
IF_I
NIC
MIX_VG
BUFF_VG
9
10
11
12
13
14
15
16
NIC
NIC
LNA_VG1
NIC
RFIN
NIC
VCTRL
NIC
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 2, 4, 6, 8, 9, 11, 12,
14, 17 to 19, 21, 22,
24, 25, 27, 29, 31
3
5
Mnemonic
NIC
Description
No Internal Connection. These pins are not connected internally.
LNA_VG1
RFIN
7
VCTRL
10
13, 28
15
16
20
23
26
30
32
LNA_VG2
IF_I, IF_Q
MIX_VG
BUFF_VG
LOIN
BUFF_VD
GND
LNA_VD2
LNA_VD1
EPAD
Gate Bias Voltage for the First Low Noise Amplifier. See Figure 3 for the interface schematic.
Radio Frequency Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
Voltage Control. Gate bias attenuation control for the low noise amplifier. See Figure 5 for the interface
schematic.
Gate Bias Voltage for the Second Low Noise Amplifier. See Figure 6 for the interface schematic.
In-Phase and Quadrature Intermediate Frequency Output Pins. See Figure 7 for the interface schematic.
Gate Bias Voltage for FET Mixer. See Figure 8 for the interface schematic.
Gate Bias Voltage for the Local Oscillator Buffer. See Figure 9 for the interface schematic.
Local Oscillator Input. This pin is ac-coupled and matched to 50 Ω. See Figure 10 for the interface schematic.
Drain Bias Voltage for the Local Oscillator Buffer. See Figure 11 for the interface schematic.
Ground Connect. This pin must be connected to RF/dc ground. See Figure 12 for the interface schematic.
Drain Bias Voltage for the Second Low Noise Amplifier. See Figure 13 for the interface schematic.
Drain Bias Voltage for the First Low Noise Amplifier. See Figure 14 for the interface schematic.
Exposed Pad. Connect the exposed pad to RF/dc ground. See Figure 12 for the interface schematic.
Rev. 0 | Page 5 of 18
HMC8108
Data Sheet
Figure 9. BUFF_VG Interface Schematic
15133-004
RFIN
15133-009
BUFF_VG
Figure 3. LNA_VG1 Interface Schematic
15133-010
LNA_VG1
15133-003
INTERFACE SCHEMATICS
LOIN
Figure 10. LOIN Interface Schematic
Figure 4. RFIN Interface Schematic
15133-005
Figure 5. VCTRL Interface Schematic
15133-006
LNA_VG2
Figure 11. BUFF_VD Interface Schematic
GND
Figure 6. LNA_VG2 Interface Schematic
15133-012
VCTRL
15133-011
BUFF_VD
Figure 12. GND and EPAD Interface Schematic
15133-007
15133-013
LNA_VD2
IF_I, IF_Q
Figure 7. IF_I and IF_Q Interface Schematic
Figure 13. LNA_VD2 Interface
15133-008
MIX_VG
15133-014
LNA_VD1
Figure 8. MIX_VG Interface Schematic
Figure 14. LNA_VD1 Interface Schematic
Rev. 0 | Page 6 of 18
Data Sheet
HMC8108
TYPICAL PERFORMANCE CHARACTERISTICS
20
16
16
CONVERSION GAIN (dB)
20
12
8
+85°C
+25°C
–40°C
9.4
9.6
9.8
10.0
0
–16
12
CONVERSION GAIN (dB)
16
12
8
9GHz
9.34GHz
9.375GHz
9.41GHz
10GHz
–9
–4
1
6
RF INPUT POWER (dBm)
4
16
CONVERSION GAIN (dB)
12
8
4
10GHz
9.41GHz
9GHz
0
–1.2V
–1V
–0.8V
–0.6V
–0.4V
–0.2V
0V
–0.6
–0.4
CONTROL VOLTAGE (V)
–0.2
0
9.2
9.4
9.6
9.8
10.0
12
8
4
0
9.0
15133-017
–0.8
–2
Figure 19. Conversion Gain vs. RF Frequency at Various Control Voltages
20
–1.0
–4
RF FREQUENCY (GHz)
16
–4
–1.2
–6
8
–4
9.0
Figure 16. Conversion Gain vs. RF Input Power at Various RF Frequencies
0
–8
0
15133-016
CONVERSION GAIN (dB)
16
–14
–10
Figure 18. Conversion Gain vs. LO Drive at Various RF Frequencies
20
–19
–12
LO DRIVE (dBm)
Figure 15. Conversion Gain vs. RF Frequency over Temperature
0
–24
–14
15133-018
9.2
4
10GHz
9.41GHz
9GHz
4
RF FREQUENCY (GHz)
CONVERSION GAIN (dB)
8
20MHz
60MHz
100MHz
9.2
500MHz
750MHz
1000MHz
9.4
9.6
RF FREQUENCY (GHz)
Figure 17. Conversion Gain vs. Control Voltage at Various RF Frequencies
15133-019
0
9.0
12
9.8
10.0
15133-020
4
15133-015
CONVERSION GAIN (dB)
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
Figure 20. Conversion Gain vs. RF Frequency at Various IF Frequencies
Rev. 0 | Page 7 of 18
HMC8108
Data Sheet
40
40
35
35
30
30
IMAGE REJECTION (dBc)
25
20
15
+85°C
+25°C
–40°C
10
9.6
9.8
10.0
15
10
0
–16
35
35
30
30
IMAGE REJECTION (dBc)
40
25
20
15
9GHz
9.34GHz
9.375GHz
9.41GHz
10GHz
–19
–14
–9
–4
1
6
–6
–4
–2
0
25
20
15
–1.2V
–1V
–0.8V
–0.6V
10
0
9.0
–0.4V
–0.2V
0V
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 22. Image Rejection vs. RF Input Power at Various RF Frequencies
Figure 25. Image Rejection vs. RF Frequency at Various Control Voltages
40
35
35
30
30
IMAGE REJECTION (dBc)
40
25
20
15
10GHz
9.41GHz
9GHz
5
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
25
20
15
10
5
–1.0
–0.8
–0.6
–0.4
CONTROL VOLTAGE (V)
–0.2
0
0
9.0
15133-023
0
–1.2
–8
5
RF INPUT POWER (dBm)
10
–10
15133-025
0
–24
15133-022
5
–12
Figure 24. Image Rejection vs. LO Drive at Various RF Frequencies
40
10
–14
LO DRIVE (dBm)
Figure 21. Image Rejection vs. RF Frequency over Temperature
IMAGE REJECTION (dBc)
20
15133-024
9.4
15133-021
9.2
RF FREQUENCY (GHz)
IMAGE REJECTION (dBc)
25
5
5
0
9.0
10GHz
9.41GHz
9GHz
9.2
9.4
9.6
RF FREQUENCY (GHz)
Figure 23. Image Rejection vs. Control Voltage at Various RF Frequencies
9.8
10.0
15133-026
IMAGE REJECTION (dBc)
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
Figure 26. Image Rejection vs. RF Frequency at Various IF Frequencies
Rev. 0 | Page 8 of 18
Data Sheet
HMC8108
12
10
10
8
8
INPUT IP3 (dBm)
12
6
4
+85°C
+25°C
–40°C
9.2
9.4
9.6
9.8
10.0
0
–16
–10
–8
–6
–4
–2
0
25
10
20
INPUT IP3 (dBm)
8
6
4
9GHz
9.34GHz
9.375GHz
9.41GHz
10GHz
–19
–14
–9
–4
1
–1.2V
–1V
–0.8V
–0.6V
15
–0.4V
–0.2V
0V
10
5
6
RF INPUT POWER (dBm)
0
9.0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 28. Input Third-Order Intercept (IP3) vs. RF Input Power at Various
RF Frequencies
15133-031
2
15133-028
INPUT IP3 (dBm)
–12
Figure 30. Input Third-Order Intercept (IP3) vs. LO Drive at Various
RF Frequencies
12
Figure 31. Input Third-Order Intercept (IP3) vs. RF Frequency at Various
Control Voltages
12
25
10
10GHz
9.41GHz
9GHz
INPUT IP3 (dBm)
20
INPUT IP3 (dBm)
–14
LO DRIVE (dBm)
Figure 27. Input Third-Order Intercept (IP3) vs. RF Frequency over
Temperature
15
10
5
20MHz
60MHz
100MHz
500MHz
750MHz
1000MHz
8
6
4
2
–1.0
–0.8
–0.6
–0.4
CONTROL VOLTAGE (V)
–0.2
0
0
9.0
15133-029
0
–1.2
4
2
RF FREQUENCY (GHz)
0
–24
6
9.2
9.4
9.6
RF FREQUENCY (GHz)
Figure 29. Input Third-Order Intercept (IP3) vs. Control Voltage at Various RF
Frequencies
9.8
10.0
15133-032
0
9.0
10GHz
9.41GHz
9GHz
15133-030
2
15133-027
INPUT IP3 (dBm)
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
Figure 32. Input Third-Order Intercept (IP3) vs. RF Frequency at Various IF
Frequencies
Rev. 0 | Page 9 of 18
HMC8108
Data Sheet
20
20
16
16
INPUT IP2 (dBm)
12
8
+85°C
+25°C
–40°C
0
9.0
9.2
9.4
9.8
9.6
10.0
RF FREQUENCY (GHz)
–12
–10
–8
–6
–4
–2
0
Figure 36. Input Second-Order Intercept (IP2) vs. LO Drive at Various
RF Frequencies
30
9GHz
9.34GHz
9.375GHz
9.41GHz
10GHz
25
INPUT IP2 (dBm)
INPUT IP2 (dBm)
–14
LO DRIVE (dBm)
35
25
8
0
–16
Figure 33. Input Second-Order Intercept (IP2) vs. RF Frequency over
Temperature
30
12
4
15133-033
4
10GHz
9.41GHz
9GHz
15133-036
INPUT IP2 (dBm)
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
20
15
20
15
10
10
–14
–9
–4
1
6
RF INPUT POWER (dBm)
0
9.0
Figure 34. Input Second-Order Intercept (IP2) vs. RF Input Power at Various
RF Frequencies
9.6
9.8
10.0
Figure 37. Input Second-Order Intercept (IP2) vs. RF Frequency at Various
Control Voltages
20
10GHz
9.41GHz
9GHz
16
INPUT IP2 (dBm)
20
15
10
12
8
20MHz
60MHz
100MHz
4
5
–0.8
–0.6
–0.4
CONTROL VOLTAGE (V)
–0.2
0
0
9.0
15133-035
–1.0
Figure 35. Input Second-Order Intercept (IP2) vs. Control Voltage at Various
RF Frequencies
9.2
9.4
9.6
RF FREQUENCY (GHz)
500MHz
750MHz
1000MHz
9.8
10.0
15133-038
25
INPUT IP2 (dBm)
9.4
RF FREQUENCY (GHz)
30
0
–1.2
9.2
–0.4V
–0.2V
0V
15133-037
–19
15133-034
0
–24
–1.2V
–1V
–0.8V
–0.6V
5
5
Figure 38. Input Second-Order Intercept (IP2) vs. RF Frequency at Various
IF Frequencies
Rev. 0 | Page 10 of 18
Data Sheet
HMC8108
0
0
–2
–2
–4
–6
+85°C
+25°C
–40°C
–10
9.0
9.2
10.0
9.8
9.6
9.4
RF FREQUENCY (GHz)
–10
9.0
20
9.4
9.6
10.0
9.8
5
160
150
5
140
0
130
–5
120
–10
110
–15
4
NOISE FIGURE (dB)
10
TOTAL DRAIN CURRENT (mA)
+85°C
+25°C
–40°C
3
2
1
+85°C
+25°C
–40°C
–20
–30
90
–26
–22
–18
–14
–6
–10
–2
2
10
6
0
9.0
RF INPUT POWER (dBm)
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 40. IF Output Power and Total Drain Current vs. RF Input Power over
Temperature
15133-043
100
15133-040
Figure 43. Noise Figure vs. RF Frequency over Temperature
16
10
10GHz
9.41GHz
9GHz
–0.5V
–1V
0V
12
NOISE FIGURE (dB)
8
6
4
8
4
2
–14
–12
–10
–8
–6
–4
–2
0
LO DRIVE (dBm)
Figure 41. Noise Figure vs. LO Drive at Various RF Frequencies
0
9.0
15133-041
0
–16
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 44. Noise Figure vs. RF Frequency at Various Control Voltages
Rev. 0 | Page 11 of 18
15133-044
IF OUTPUT POWER (dBm)
9.2
Figure 42. Input Power for 1 dB Compression (P1dB) vs. RF Frequency at
Various Control Voltages
170
15
–0.5V
–1V
0V
RF FREQUENCY (GHz)
Figure 39. Input Power for 1 dB Compression (P1dB) vs. RF Frequency over
Temperature
NOISE FIGURE (dB)
–6
–8
15133-039
–8
–4
15133-042
INPUT P1dB (dBm)
INPUT P1dB (dBm)
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
HMC8108
Data Sheet
Measurements performed as image reject mixer with lower sideband selected, external 90° hybrid at the IF ports, IF = 60 MHz,
LO drive = −5 dBm, and TA = −25°C, unless otherwise noted.
16
10GHz
9.41GHz
9GHz
10GHz
9.41GHz
9GHz
4
NOISE FIGURE (dB)
NOISE FIGURE (dB)
12
5
8
3
2
4
–0.8
–0.6
–0.4
–0.2
0
CONTROL VOLTAGE (V)
Figure 45. Noise Figure vs. Control Voltage at Various RF Frequencies
6
4
3
2
1
0
9.0
10MHz
20MHz
30MHz
40MHz
9.2
50MHz
60MHz
70MHz
80MHz
9.4
90MHz
100MHz
110MHz
120MHz
9.6
9.8
10.0
RF FREQUENCY (GHz)
15133-046
NOISE FIGURE (dB)
5
Figure 46. Noise Figure vs. RF Frequency at Various IF Frequencies
Rev. 0 | Page 12 of 18
0
10
20
30
40
50
60
70
80
90
100
110
120
IF FREQUENCY (MHz)
Figure 47. Noise Figure vs. IF Frequency at Various RF Frequencies
15133-047
0
–1.0
15133-045
1
Data Sheet
HMC8108
Measurements performed without external 90° hybrid at the IF ports and TA = −25°C, unless otherwise noted.
0
0
+85°C
+25°C
–40°C
–10
–15
–20
–15
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
–25
9.0
9.4
9.8
10.2
10.6
11.0
LO FREQUENCY (GHz)
Figure 48. RF Return Loss vs. RF Frequency over Temperature
15133-051
9.2
15133-048
–30
9.0
Figure 51. LO Return Loss vs. LO Frequency over Temperature
0
0
IF_I AT +85°C
IF_I AT +25°C
IF_I AT –40°C
IF_Q AT +85°C
IF_Q AT +25°C
IF_Q AT –40°C
–10
–10
LEAKAGE (dBm)
–5
–15
–20
LO TO RF
LO TO IF_I
LO TO IF_Q
RF TO IF_I
RF TO IF_Q
–20
–30
0
0.2
0.4
0.6
0.8
1.0
IF FREQUENCY (GHz)
–50
9.0
15133-049
–30
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 49. In-Phase and Quadrature IF Output Return Loss vs. IF Frequency
over Temperature
Figure 52. Leakage vs. RF Frequency
6
2
+85°C
+25°C
–40°C
0
PHASE BALANCE (Degrees)
4
2
0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
15133-050
–2
–4
9.0
9.2
15133-052
–40
–25
Figure 50. Amplitude Balance vs. RF Frequency over Temperature
–2
–4
+85°C
+25°C
–40°C
–6
–8
9.0
9.2
9.4
9.6
9.8
10.0
RF FREQUENCY (GHz)
Figure 53. Phase Balance vs. RF Frequency over Temperature
Rev. 0 | Page 13 of 18
15133-053
RETURN LOSS (dB)
–10
–20
–25
AMPLITUDE BALANCE (dB)
+85°C
+25°C
–40°C
–5
LO RETURN LOSS (dB)
RF RETURN LOSS (dB)
–5
HMC8108
Data Sheet
THEORY OF OPERATION
The RF input signal passes through two stages of low noise
amplification. The preamplified RF input signal then splits
through an internal hybrid to feed two singly balanced passive
mixers. A power divider followed by three LO buffer amplifiers
drives the two I and Q mixer cores to convert the amplified RF
input frequencies to a 60 MHz typical single-ended IF. A variable
attenuator allows gain control ranging from 10 dB to 30 dB.
The HMC8108 is a X-band, low noise converter with integrated
LO buffers that converts RF input signals ranging from 9 GHz
to 10 GHz down to a typical single-ended IF signal of 60 MHz
at its output. See Figure 54 for a functional block diagram of the
circuit architecture of the HMC8108.
IF_Q
VCTRL LNA_VD1 LNA_VD2
HYBRID
BUFF_VD
MIX
RFIN
ATTENUATOR
LNA1
LNA2
LOIN
MIX
BUFF3
BUFF2
BUFF1
DIV
LNA_VG1 LNA_VG2
MIX_VG IF_I
Figure 54. Functional Block Diagram of the Circuit Architecture
Rev. 0 | Page 14 of 18
BUFF_VG
15133-054
ESD
Data Sheet
HMC8108
APPLICATIONS INFORMATION
A typical lower sideband application circuit is shown in Figure 57.
The IF_Q output signal of the HMC8108 is connected to the
90° port of the hybrid coupler followed by a low-pass filter to
produce a lower sideband IF output signal. The LO input signal
passes through a voltage control oscillator (VCO) followed by
an optional buffer amplifier, a 2× frequency multiplier, and an
optional band-pass filter before entering the LO port of the
device. Band-pass filter and LO buffer are optional and depend
on the VCO specification and the LO input power requirement.
External capacitors of 0.6 pF, 1 nF, 10 nF, and 100 nF, and 5.6 nH
inductors are connected to the input voltage pin of the device.
The IF_I and IF_Q pins are dc-coupled and must not source or
sink more than 3 mA of current or device malfunction or possible
device failure may result. For applications not requiring
operation to dc, use an off chip dc blocking capacitor.
To turn off the HMC8108, take the following steps:
1.
2.
Turn off the LO and RF signal source.
Turn off the LNA_VD1, LNA_VD2, and BUFF_VD power
supplies.
Turn off the LNA_VG1, LNA_VG2, BUFF_VG, MIX_VG,
and VCTRL power supplies. Refer to Figure 55 for the
HMC8108 lab bench setup.
3.
RF INPUT
POWER
SUPPLY
POWER
SUPPLY
BIASING SEQUENCE
90°
The HMC8108 uses amplifier and LO buffer stages. These active
stages use depletion mode, pseudomorphic high electron
mobility transfer (pHEMT) transistors.
4.
5.
6.
7.
8.
LO INPUT
SPECTRUM
ANALYZER
Figure 55. HMC8108 Lab Bench Setup
RESULTS
Figure 56 shows the expected results when testing the HMC8108
with the following operating conditions:
RF = −15 dBm at 9.44 GHz
LO = −5 dBm at 9.5 GHz
The on board IF_Q port is connected to the 90° port of the
hybrid.
The lower sideband is selected.
Note that hybrid, cable, and board loss were not deembedded.
0
REF 0dBm
ATT 5dB
RWB 6.25kHz
VBW 20kHz
SWT 420ms
MARKER 1 [T1]
–4.31dBm
60.00MHz
1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 59.511MHz
1.63MHz/
Figure 56. Test Results at IF = 60 MHz
Rev. 0 | Page 15 of 18
SPAN 16.3MHz
15133-057
3.
Set the LNA_VG1, LNA_VG2, and BUFF_VG power
supplies to −2 V and the MIX_VG power supply to +1.4 V.
Do not turn on the power supplies.
Set the LNA_VD1, LNA_VD2, and BUFF_VD power
supplies to 3 V. Do not turn on the power supplies.
Set the VCTRL power supply to −1 V. Do not turn on the
power supply.
Turn on the power supplies in Step 1, Step 2, and Step 3 in
order.
Adjust the LNA_VG1, LNA_VG2, and BUFF_VG power
supplies between −2 V and 0 V to achieve an quiescent
current LNA_ID1, LNA_ID2, and BUFF_ID = 20 mA,
30 mA, and 40 mA, respectively.
Connect the signal generator to the RF and LO input.
Connect the 90° hybrid to the IF_I and IF_Q output. Note
that IF_Q is connected to the 90° port of the hybrid. Under
this condition, the lower sideband is selected.
Turn on the LO and RF input to see the output on the
spectrum analyzer.
(dBm)
2.
POWER
SUPPLY
15133-056
0°
To avoid transistor damage, follow these power-up bias
sequence steps:
1.
90° HYBRID FOR
I/Q IF OUTPUT
HMC8108
Data Sheet
15133-058
Figure 57. Typical Application Circuit
Rev. 0 | Page 16 of 18
Data Sheet
HMC8108
EVALUATION BOARD INFORMATION
15133-055
RF circuit design techniques were implemented for the evaluation
board PCB shown in Figure 58. Signal lines have 50 Ω impedance,
and the package ground leads and exposed pad are connected
directly to the ground plane. A sufficient number of via holes
connect the top and bottom ground planes. The full evaluation
circuit board shown in Figure 58 is available from Analog Devices,
Inc., upon request.
Figure 58. EV1HMC8108LC5 Evaluation PCB Top Layer
Table 5. Bill of Material for the EV1HMC8108LC5 Evaluation PCB
Reference Designator
600-01494-00-1
J1, J2
J3, J7
J4
J5, J6
C1
C2 to C12
C13 to C16, C18 to C21
C22 to C29
C30 to C32
L1 to L3
TP1 to TP3
U1
Quantity
1
2
2
1
2
1
11
8
8
3
3
3
1
Description
Evaluation board PCB; circuit board material: Rogers 4350 or Arlon 25FR
SMA connectors, SRI
SMA connectors, Johnson
Connector header, 2 mm ,12-position vertical, SMT
Terminal strips, single row, 3-pin, SMT
Ceramic capacitor, 0.5 pF, 50 V, C0G, 0402
Ceramic capacitors, 0.6 pF, ±0.1 pF, 50 V, C0G, 0402
Ceramic capacitors, 1 nF, 50 V, X7R, 0402
Ceramic capacitors, 10 nF, 50 V, 10%, X7R, 0402
Ceramic capacitors, 100 nF, 16 V, 10%, X7R, 0402
Inductors, 5.6 nH, 0402, ±5%, 760 mA
Test points, PC compact, SMT
Device under test (DUT), HMC8108LC5
Rev. 0 | Page 17 of 18
HMC8108
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.05
4.90 SQ
4.75
0.36
0.30
0.24
25
PIN 1
(0.32 × 0.32)
32
24
1
0.50
BSC
EXPOSED
PAD
3.50 SQ
17
8
16
9
BOTTOM VIEW
TOP VIEW
3.50 REF
4.10 BSC
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PKG-004843
SEATING
PLANE
03-02-2016-B
1.12 MAX
Figure 59. 32-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC8108LC5
Temperature
Range
−40°C to +85°C
Package Body
Material
Alumina Ceramic
Lead Finish
Gold over Nickel
MSL
Rating2
MSL3
Package Description
32-Terminal LCC
Package
Option
E-32-1
HMC8108LC5TR
−40°C to +85°C
Alumina Ceramic
Gold over Nickel
MSL3
32-Terminal LCC
E-32-1
HMC8108LC5TR-R5
−40°C to +85°C
Alumina Ceramic
Gold over Nickel
MSL3
32-Terminal LCC
E-32-1
EV1HMC8108LC5
−40°C to +85°C
Alumina Ceramic
1
2
3
Evaluation Board
The HMC8108LC5, the HMC8108LC5TR, and the HMC8108LC5TR-R5 are RoHS Compliant Parts.
See the Absolute Maximum Ratings section.
The HMC8108LC5, the HMC8108LC5TR, and the HMC8108LC5TR-R5 four-digit lot numbers are XXXX.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15133-0-2/17(0)
Rev. 0 | Page 18 of 18
Branding3
H8108
XXXX
H8108
XXXX
H8108
XXXX
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