10 W (40 dBm), 0.01 GHz to 2.8 GHz,
GaN Power Amplifier
HMC8500PM5E
Data Sheet
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
HMC8500PM5E
Extended battery operation for public mobile radios
Power amplifier stage for wireless infrastructures
Test and measurement equipment
Commercial and military radars
General-purpose transmitter amplification
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
APPLICATIONS
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
PACKAGE
BASE
16825-001
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
9
10
11
12
13
14
15
16
High small signal gain: 15.0 dB typical
POUT: 40 dBm typical at PIN = 30 dBm
High PAE: 55% typical at PIN = 30 dBm
Frequency range: 0.01 GHz to 2.8 GHz across all frequencies
VDD = 28 V at quiescent current of 100 mA
Internal prematching
Simple and compact external tuning for optimal
performance
5 mm × 5 mm, 32-lead LFCSP package
32
31
30
29
28
27
26
25
FEATURES
Figure 1.
GENERAL DESCRIPTION
The HMC8500PM5E is a gallium nitride (GaN), broadband
power amplifier delivering 10 W (40 dBm), typical, with up to
55% power added efficiency (PAE) across an instantaneous
bandwidth of 0.01 GHz to 2.8 GHz, at an input power of
30 dBm. The typical gain flatness is 3 dB at small signal levels.
The HMC8500PM5E is ideal for pulsed or continuous wave
(CW) applications, such as wireless infrastructure, radars,
public mobile radios, and general-purpose amplification.
Rev. A
The HMC8500PM5E amplifier is externally tuned using low
cost, surface-mount components and is available in a compact
LFCSP package.
Note that, throughout this data sheet, multifunction pins, such
as RFIN/VGG, are referred to either by the entire pin name or by
a single function of the pin, for example, RFIN, when only that
function is relevant.
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
HMC8500PM5E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
Functional Block Diagram .............................................................. 1
Interface Schematics .....................................................................6
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................7
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 14
Specifications..................................................................................... 3
Applications Information .............................................................. 15
Electrical Specifications ............................................................... 3
Evaluation Board ............................................................................ 16
Total Supply Current by VDD ....................................................... 4
Outline Dimensions ....................................................................... 17
Absolute Maximum Ratings ............................................................ 5
Ordering Guide .......................................................................... 17
Thermal Resistance ...................................................................... 5
REVISION HISTORY
9/2018—Rev. 0 to Rev. A
Changes to Storage Temperature Range Parameter, Table 4....... 5
7/2018—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
HMC8500PM5E
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, supply voltage (VDD) = 28 V, quiescent current (IDDQ) = 100 mA, and frequency range = 0.01 GHz to 1.3 GHz.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power
Power Added Efficiency
Symbol
Min
0.01
Typ
14.0
20.0
6
dB
dB
7
7
dB
dB
40
40
55
55
47
7
100
dBm
dBm
%
%
dBm
dB
mA
POUT
PAE
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
QUIESCENT CURRENT
OIP3
NF
IDDQ
SUPPLY VOLTAGE
VDD
24
28
Max
1.3
32
Unit
GHz
Test Conditions/Comments
Input power (PIN) = 28 dBm
PIN = 30 dBm
PIN = 28 dBm
PIN = 30 dBm
POUT per tone = 30 dBm
Adjust the gate bias control voltage (VGG) from −8 V
to 0 V to achieve IDDQ = 100 mA, VGG = −2.65 V typical
to achieve IDDQ = 100 mA
V
TA = 25°C, VDD = 28 V, IDDQ = 100 mA, and frequency range = 1.3 GHz to 2.8 GHz.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Small Signal Gain
Gain Flatness
RETURN LOSS
Input
Output
POWER
Output Power
Power Added Efficiency
Symbol
Min
1.3
Typ
12.0
15.0
3
dB
dB
9
9
dB
dB
39
40
40
47
47
4.5
100
dBm
dBm
%
%
dBm
dB
mA
POUT
PAE
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
QUIESCENT CURRENT
OIP3
NF
IDDQ
SUPPLY VOLTAGE
VDD
24
28
Max
2.8
32
Rev. A | Page 3 of 17
Unit
GHz
V
Test Conditions/Comments
PIN = 28 dBm
PIN = 30 dBm
PIN = 28 dBm
PIN = 30 dBm
POUT per tone = 30 dBm
Adjust the gate bias control voltage (VGG) from −8 V
to 0 V to achieve IDDQ = 100 mA, VGG = −2.65 V typical
to achieve IDDQ = 100 mA
HMC8500PM5E
Data Sheet
TOTAL SUPPLY CURRENT BY VDD
Table 3.
Parameter
QUIESCENT CURRENT
Symbol
IDDQ
Min
Typ
100
100
100
Max
Unit
mA
mA
mA
Test Conditions/Comments
Adjust the gate bias control voltage (VGG) between −8 V and 0 V to achieve
IDDQ = 100 mA typical
VDD = 24 V
VDD = 28 V
VDD = 32 V
Rev. A | Page 4 of 17
Data Sheet
HMC8500PM5E
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
1
Parameter
Supply Bias Voltage (VDD)
Gate Bias Voltage (VGG)
Radio Frequency (RF) Input Power (RFIN)
Maximum Voltage Standing Wave Ratio
(VSWR)2
Channel Temperature
Maximum Peak Reflow Temperature
(Moisture Sensitivity Level 3 (MSL3))3
Continuous Power Dissipation, PDISS (TA = 85°C,
Derate 147.0 mW/°C Above 85°C)
Storage Temperature Range
Operating Temperature Range
Electrostatic Discharge (ESD) Sensitivity
Human Body Model
Rating
35 V
−8 V to 0 V dc
33 dBm
6:1
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 5. Thermal Resistance
225°C
260°C
Package Type
CG-32-21
20.6 W
1
−65°C to +150°C
−40°C to +85°C
θJC
6.8
Unit
°C/W
Thermal resistance (θJC) determined by simulation under the following
conditions: the heat transfer is due solely to thermal conduction from the
channel, through the ground pad to the PCB. The ground pad is held
constant at the operating temperature of 85°C.
ESD CAUTION
Class 1B,
passed 500 V
1
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the absolute maximum
rating is listed. For full pin names of multifunction pins, refer to the Pin
Configuration and Function Descriptions section.
2
Restricted by maximum power dissipation.
3
See the Ordering Guide for additional information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 17
HMC8500PM5E
Data Sheet
32
31
30
29
28
27
26
25
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC8500PM5E
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
NIC
NIC
RFOUT/VDD
RFOUT/VDD
NIC
NIC
GND
PACKAGE
BASE
NOTES
1. NO INTERNAL CONNECTION. THESE PINS ARE NOT
CONNECTED INTERNALLY. HOWEVER, ALL DATA IS
MEASURED WITH THESE PINS CONNECTED TO RF
OR DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF OR DC GROUND.
16825-002
GND
NIC
NIC
NIC
NIC
NIC
NIC
GND
9
10
11
12
13
14
15
16
GND
NIC
NIC
RFIN/VGG
RFIN/VGG
NIC
NIC
GND
Figure 2. Pin Configuration
Table 6. Pad Function Descriptions
Pin No.
1, 8, 9, 16, 17, 24, 25, 32
Mnemonic
GND
2, 3, 6, 7, 10 to 15, 18,
19, 22, 23, 26 to 31
4, 5
NIC
20, 21
RFOUT/VDD
RFIN/VGG
EPAD
Description
Ground. These pins must be connected to RF or dc ground. See Figure 3 for the GND interface
schematic.
No Internal Connection. These pins are not connected internally. However, all data is measured with
these pins connected to RF or dc ground externally.
RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/VGG pin is dc-coupled
with internal prematching and requires external matching to 50 Ω, as shown in Figure 44. See
Figure 4 for the RFIN/VGG interface schematic.
RF Output/Drain Bias Voltage. This is a multifunction pin. The RFOUT/VDD pin is dc-coupled and requires
external matching to 50 Ω, as shown in Figure 44. See Figure 4 for the RFOUT/VDD interface schematic.
Exposed Pad. The exposed pad must be connected to RF or dc ground.
INTERFACE SCHEMATICS
RFIN/VGG
Figure 3. GND Interface Schematic
16825-004
GND
16825-003
RFOUT/VDD
Figure 4. RFIN/VGG and RFOUT/VDD Interface Schematic
Rev. A | Page 6 of 17
Data Sheet
HMC8500PM5E
TYPICAL PERFORMANCE CHARACTERISTICS
25
S11
S21
S22
21
10
19
GAIN (dB)
15
5
0
17
15
–5
13
–10
11
–15
9
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
7
0
1.0
1.5
2.0
2.5
3.0
Figure 8. Gain vs. Frequency at Various Temperatures
25
32V
28V
24V
23
21
19
19
GAIN (dB)
21
17
15
17
15
13
13
11
11
9
9
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
7
16825-006
7
0
50mA
100mA
150mA
200mA
250mA
23
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 6. Gain vs. Frequency at Various Supply Voltages
16825-009
25
Figure 9. Gain vs. Frequency at Various Quiescent Currents
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–2
OUTPUT RETURN LOSS (dB)
–2
–4
–6
–8
–10
–4
–6
–8
–10
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 7. Input Return Loss vs. Frequency at Various Temperatures
–12
16825-007
–12
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
16825-010
GAIN (dB)
0.5
FREQUENCY (GHz)
Figure 5. Gain and Return Loss vs. Frequency
INPUT RETURN LOSS (dB)
+85°C
+25°C
–40°C
23
16825-005
GAIN AND RETURN LOSS (dB)
20
16825-008
25
Figure 10. Output Return Loss vs. Frequency at Various Temperatures
Rev. A | Page 7 of 17
HMC8500PM5E
Data Sheet
44
44
+85°C
+25°C
–40°C
42
38
36
34
32
30
36
34
32
32V
28V
24V
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
28
0
42
42
40
40
OUTPUT POWER (dBm)
44
38
36
34
50mA
100mA
150mA
200mA
250mA
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
36
34
32
0
40
40
OUTPUT POWER (dBm)
42
36
34
32
1.0
1.5
2.0
32V
28V
24V
1.5
2.0
2.5
3.0
36
34
32
50mA
100mA
150mA
200mA
250mA
FREQUENCY (GHz)
Figure 13. Output Power vs. Frequency at Various Supply Voltages,
Input Power = 30 dBm
28
16825-013
1.0
3.0
38
30
28
2.5
Figure 15. Output Power vs. Frequency at Various Temperatures,
Input Power = 30 dBm
42
38
0.5
FREQUENCY (GHz)
44
0.5
+85°C
+25°C
–40°C
38
44
0
3.0
28
Figure 12. Output Power vs. Frequency at Various Quiescent Currents,
Input Power = 28 dBm
30
2.5
16825-015
1.0
16825-012
0.5
2.0
30
28
0
1.5
Figure 14. Output Power vs. Frequency at Various Supply Voltages,
Input Power = 28 dBm
44
30
1.0
FREQUENCY (GHz)
Figure 11. Output Power vs. Frequency at Various Temperatures,
Input Power = 28 dBm
32
0.5
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
16825-016
0.5
16825-011
0
OUTPUT POWER (dBm)
38
30
28
OUTPUT POWER (dBm)
40
16825-014
40
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
42
Figure 16. Output Power vs. Frequency at Various Quiescent Currents,
Input Power = 30 dBm
Rev. A | Page 8 of 17
Data Sheet
HMC8500PM5E
44
900
42
800
40
34
32
30
30dBm
28dBm
26dBm
24dBm
22dBm
20dBm
28
26
24
0.5
400
300
1.0
1.5
2.0
2.5
3.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 17. Output Power vs. Frequency at Various Input Powers
Figure 20. Supply Current vs. Frequency at Various Input Powers
80
+85°C
+25°C
–40°C
70
60
50
50
PAE (%)
60
40
40
30
30
20
20
10
10
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
0
16825-050
0
+85°C
+25°C
–40°C
70
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
16825-052
80
Figure 21. PAE vs. Frequency at Various Temperatures,
Input Power = 30 dBm
Figure 18. PAE vs. Frequency at Various Temperatures, Input Power = 28 dBm
55
80
30dBm
28dBm
26dBm
24dBm
22dBm
20dBm
70
+85°C
+25°C
–40°C
50
OUTPUT IP3 (dBm)
60
50
40
30
45
40
20
35
0
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
3.0
30
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 22. Output IP3 vs. Frequency at Various Temperatures,
POUT per Tone = 30 dBm
Figure 19. PAE vs. Frequency at Various Input Powers
Rev. A | Page 9 of 17
16825-018
10
16825-051
PAE (%)
30dBm
28dBm
26dBm
24dBm
22dBm
20dBm
100
FREQUENCY (GHz)
PAE (%)
500
200
22
0
600
16825-020
SUPPLY CURRENT (mA)
36
16825-017
OUTPUT POWER (dBm)
700
38
HMC8500PM5E
Data Sheet
55
55
32V
28V
24V
50
45
40
35
40
50mA
100mA
150mA
200mA
250mA
35
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
30
16825-021
30
0
2.0
2.5
3.0
0.4GHz
1.6GHz
2.2GHz
2.8GHz
1.2GHz
45
IMD3 (dBc)
40
35
40
35
30
18
20
22
24
26
28
30
32
POUT/TONE (dBm)
25
14
16825-022
16
18
16
20
22
24
26
28
30
32
POUT/TONE (dBm)
Figure 24. Output Third-Order Intermodulation (IMD3) vs. POUT per Tone,
VDD = 24 V
16825-023
30
Figure 27. IMD3 vs. POUT per Tone,
VDD = 28 V
50
0
+85°C
+25°C
–40°C
–10
REVERSE ISOLATION (dB)
45
40
35
0.4GHz
1.6GHz
2.2GHz
2.8GHz
1.2GHz
16
18
20
22
24
26
28
POUT/TONE (dBm)
30
–20
–30
–40
–50
32
–60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (GHz)
Figure 28. Reverse Isolation vs. Frequency at Various Temperatures
Figure 25. IMD3 vs. POUT per Tone,
VDD = 32 V
Rev. A | Page 10 of 17
16825-024
30
16825-026
IMD3 (dBc)
1.5
50
0.4GHz
1.6GHz
2.2GHz
2.8GHz
1.2GHz
45
25
14
1.0
Figure 26. Output IP3 vs. Frequency at Various Quiescent Currents,
POUT per Tone = 30 dBm
50
25
14
0.5
FREQUENCY (GHz)
Figure 23. Output IP3 vs. Frequency at Various Supply Voltages,
POUT per Tone = 30 dBm
IMD3 (dBc)
45
16825-019
OUTPUT IP3 (dBm)
OUTPUT IP3 (dBm)
50
Data Sheet
HMC8500PM5E
40
400
30
300
20
200
10
100
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
INPUT POWER (dBm)
50
550
40
450
30
350
20
250
10
150
50
0
0
POUT
GAIN
PAE
IDD
575
30
500
25
425
20
350
15
275
10
200
5
125
2
4
6
8
16825-028
0
10 12 14 16 18 20 22 24 26 28 30 32
INPUT POWER (dBm)
750
40
600
30
450
20
300
10
150
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
INPUT POWER (dBm)
Figure 30. POUT, Gain, PAE, and IDD vs. Input Power at 1.5 GHz
Figure 33. POUT, Gain, PAE, and IDD vs. Input Power at 2.8 GHz
40
35
+85°C
+25°C
–40°C
35
30
30
SECOND HARMONIC (dBc)
SECOND HARMONIC (dBc)
900
0
50
0
10 12 14 16 18 20 22 24 26 28 30 32
POUT
GAIN
PAE
IDD
50
POUT (dBm), GAIN (dB), PAE (%)
650
35
8
60
725
IDD (mA)
POUT (dBm), GAIN (dB), PAE (%)
40
6
Figure 32. POUT, Gain, PAE, and IDD vs. Input Power at 1 GHz
800
50
4
INPUT POWER (dBm)
Figure 29. POUT, Gain, PAE, and Total Supply Current (IDD) vs. Input Power at
0.1 GHz
45
2
25
20
15
10
25
20
15
10
32V
28V
24V
5
5
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
0
16825-032
0
Figure 31. Second Harmonic vs. Frequency at Various Temperatures,
Input Power = 15 dBm
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
2.5
3.0
16825-030
0
16825-027
0
0
650
IDD (mA)
500
60
POUT (dBm), GAIN (dB), PAE (%)
50
POUT
GAIN
PAE
IDD
16825-025
600
IDD (mA)
POUT (dBm), GAIN (dB), PAE (%)
60
750
70
16825-029
POUT
GAIN
PAE
IDD
IDD (mA)
700
70
Figure 34. Second Harmonic vs. Frequency at Various Supply Voltages,
Input Power = 15 dBm
Rev. A | Page 11 of 17
HMC8500PM5E
Data Sheet
40
50
50mA
100mA
150mA
200mA
250mA
SECOND HARMONIC (dBc)
40
20dBm
18dBm
16dBm
14dBm
12dBm
10dBm
35
SECOND HARMONIC (dBc)
45
35
30
25
20
15
30
25
20
15
10
10
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
0
16825-033
0
0
1.5
2.0
2.5
3.0
Figure 38. Second Harmonic vs. Frequency at Various Input Powers,
10 dBm to 20 dBm
50
10
30dBm
28dBm
26dBm
24dBm
22dBm
40
8
NOISE FIGURE (dB)
35
30
25
20
15
7
6
5
4
3
10
2
5
1
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
0
16825-053
0
0
+85°C
+25°C
–40°C
9
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
16825-055
45
Figure 39. Noise Figure vs. Frequency at Various Temperatures
Figure 36. Second Harmonic vs. Frequency at Various Input Powers,
22 dBm to 30 dBm
12
10
+85°C
+25°C
–40°C
32V
28V
24V
9
10
NOISE FIGURE (dB)
8
8
6
4
7
6
5
4
3
2
2
0
0
20
40
60
80
100
FREQUENCY (MHz)
16825-041
1
Figure 37. Noise Figure vs. Frequency at Various Temperatures,
Low Frequency
0
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
Figure 40. Noise Figure vs. Frequency at Various Supply Voltages
Rev. A | Page 12 of 17
16825-056
SECOND HARMONIC (dBc)
1.0
FREQUENCY (GHz)
Figure 35. Second Harmonic vs. Frequency at Various Quiescent Currents,
Input Power = 15 dBm
NOISE FIGURE (dB)
0.5
16825-054
5
5
Data Sheet
HMC8500PM5E
10
9
8
250
200
7
6
IDDQ (mA)
NOISE FIGURE (dB)
300
50mA
100mA
150mA
200mA
250mA
5
4
3
150
100
50
2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
–50
–3.2
16825-057
0
Figure 41. Noise Figure vs. Frequency at Various Quiescent Currents
0.01GHz
0.1GHz
0.6GHz
2GHz
2.8GHz
1GHz
2.5GHz
MAXIMUM PDISS AT 85°C
POWER DISSIPATION (W)
14
12
10
8
6
4
0
4
8
12
16
20
INPUT POWER (dBm)
24
28
32
16825-042
2
0
–2.9
–2.8
–2.7
–2.6
–2.5
–2.4
Figure 43. IDDQ vs. VGG at VDD = 28 V, Representative of a Typical Device
20
16
–3.0
VGG (V)
22
18
–3.1
16825-038
1
Figure 42. Power Dissipation vs. Input Power at Various Frequencies,
TA = 85°C
Rev. A | Page 13 of 17
HMC8500PM5E
Data Sheet
THEORY OF OPERATION
The HMC8500PM5E is a 10 W (40 dBm), gallium nitride (GaN),
power amplifier that consists of a single gain stage that operates like
a single field effect transistor (FET). The device is internally
prematched so that simple, external matching networks at the
RF input and RF output ports optimize the performance across
the entire operating frequency range. The recommended dc bias
conditions place the device in Class AB operation, resulting in
high output power (40 dBm typical at PIN = 30 dBm) at improved
levels of power efficiency (55% typical at PIN = 30 dBm).
Rev. A | Page 14 of 17
Data Sheet
HMC8500PM5E
APPLICATIONS INFORMATION
The recommended power-down bias sequence is as follows:
The drain bias voltage is applied through the RFOUT/VDD pin,
and the gate bias voltage is applied through the RFIN/VGG pin.
For operation of a single application circuit across the entire
frequency range, it is recommended to use the external matching
components specified in the typical application circuit (L1, C1,
C8, C11, and R2) shown in Figure 44. If operation is only
required across a narrower frequency range, performance
can be optimized additionally through the implementation
of alternate matching networks. Capacitive bypassing of VDD
and VGG is recommended.
1.
2.
3.
4.
All measurements for this device were taken using the typical
application circuit, configured as shown in the assembly diagram
(see Figure 44). The bias conditions shown in the electrical
specifications tables (see Table 1 and Table 2) are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the
HMC8500PM5E under other bias conditions may cause
performance that differs from that shown in the Typical
Performance Characteristics section.
The recommended power-up bias sequence is as follows:
The evaluation PCB provides the HMC8500PM5E in the typical
application circuit, allowing easy operation using standard dc
power supplies and 50 Ω RF test equipment.
VDD
VDD
VGG
8
GND
26
NIC
NIC
NIC
NIC
NIC
NIC
31
RFOUT/VDD
NIC
NIC
NIC
NIC
22
21
20
19
3
6
8
10
5
12
11
14
13
16
18
17
20
19
22
21
24
26
23
7
9
VGG
VGG
15
25
J1
L2
910nH
C3
2.2nF
L1
1.2nH
J3
RFOUT
C1
0.8pF
18
17
GND
GND
NOTES
1. CONNECT NIC PINS TO GND FOR BETTER THERMAL PERFORMANCE.
Figure 44. Typical Application Circuit
Rev. A | Page 15 of 17
16825-039
7
RFOUT/VDD
RFIN/VGG
23
VGG
1
4
GND
6
NIC
RFIN/VGG
NIC
C11
4.3pF
HMC8500PM5E
24
VGG
2
16
5
NIC
14 NIC
C8
2pF
NIC
15
4
GND
EPAD
NIC
12 NIC
13 NIC
3
GND
NIC
2
NIC
C2
2.2nF
R2
10Ω
GND
J2
RFIN
R1
25Ω
11
1
GND
L4
3.6nH
25
C5
2.2nF
27
C4
2.2nF
29
C10
10µF
28
C7
10µF
30
C9
10µF
32
C6
10µF
9
3.
Connect the power supply ground to circuit ground.
Set VGG to −8 V to pinch off the drain current. Set VDD to
28 V (drain current is pinched off). Adjust VGG between
−3 V and −2.5 V until a quiescent current of IDDQ =
100 mA is obtained.
Apply the RF signal.
10
1.
2.
Turn off the RF signal.
Set VGG to −8 V to pinch off the drain current.
Set VDD to 0 V.
Set VGG to 0 V.
HMC8500PM5E
Data Sheet
EVALUATION BOARD
The HMC8500PM5E evaluation board is a 2-layer board
fabricated with Rogers 4350 material and using layout
techniques recommended for high frequency RF designs.
The RF input and RF output traces have a 50 Ω characteristic
impedance. The board is attached to a heat sink using an
electrically and thermally conductive epoxy, providing a low
thermal and low dc resistance path. Components are mounted
using SN63 solder, allowing rework of the surface-mount
components without compromising the circuit board to heat
sink attachment.
The evaluation board and populated components are designed
to operate over the ambient temperature range of −40°C to +85°C.
During operation, attach the evaluation board to a temperature
controlled plate to control the temperature of the HMC8500PM5E
during operation. For the proper bias sequence, see the
Applications Information section.
16825-040
A fully populated and tested evaluation board, shown in Figure 45,
is available from Analog Devices, Inc., upon request.
Figure 45. Evaluation PCB
Table 7. Bill of Materials for Evaluation PCB EV1HMC8500PM5
Item
J2, J3
J1
C1
C2
C3, C4, C5
C6, C7, C9, C10
C8
C11
L1
L2
L4
R1
R2
Heat Sink
U1
PCB
Description
K connectors
Preform surface terminal strip
0.8 pF capacitor, 0402 package
2.2 nF capacitor, 0402 package
2.2 nF capacitors, 0603 package
10 μF capacitors, 1210-2 package
2 pF capacitor, 0402 package
4.3 pF capacitor, 0402 package
1.2 nH inductor, 0402 package
910 nH inductor, 1008CS package
3.6 nH inductor, 0603 package
25 Ω high precision resistor, 0603 package
10 Ω resistor, 0402 package
Used for thermal transfer from the HMC8500PM5E amplifier
HMC8500PM5E amplifier
EV1HMC8500PM5 circuit board material: Rogers 4350
Rev. A | Page 16 of 17
Manufacturer/Part Number
SRI/25-146-1000-92
SAMTEC/TSM-113-01-L-DV
Murata/GRM1555C1HR80BA01D
Samsung/CL05B222KB5NNNC
TDK/C1608C0G1H222J
TDK/C3225X7S1H106K250AB
AVX/04023U2R0BAT2A
Murata/GJM1552C1H4R3BB01C
TDK/MHQ1005P1N2CT000
Coilcraft/1008CS-911XGLB
Coilcraft/0603CS-3N6XGLU
Vishay/P0603E25R0BNT
Panasonic/ERJ-2RKF10R0X
Not applicable
Analog Devices/HMC8500PM5E
Analog Devices/EV1HMC8500PM5
Data Sheet
HMC8500PM5E
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
0.30
0.25
0.20
PIN 1
INDICATOR AREA OPTIONS
25
32
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
8
17
0.45
0.40
0.35
TOP VIEW
PKG-005068
1.35
1.25
1.15
0.60 REF SIDE VIEW
9
16
BOTTOM VIEW
0.40
0.050 MAX
0.035 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
(SEE DETAIL A)
1
24
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-15-2018-A
5.10
5.00 SQ
4.90
Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
HMC8500PM5E
HMC8500PM5ETR
EV1HMC8500PM5
Temperature Range
−40°C to +85°C
−40°C to +85°C
MSL Rating3
MSL3
MSL3
Package Description4
32-Lead Lead Frame Chip Scale Package [LFCSP_CAV]
32-Lead Lead Frame Chip Scale Package [LFCSP_CAV]
Evaluation Board
1
All models are RoHS compliant.
When ordering the evaluation board, use the reference model number, EV1HMC8500PM5.
See the Absolute Maximum Ratings section for additional information.
4
The lead finish of the HMC8500PM5E and the HMC8500PM5ETR is nickel palladium gold (NiPdAu).
2
3
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16825-0-9/18(A)
Rev. A | Page 17 of 17
Package Option
CG-32-2
CG-32-2
工商网监
湘ICP备2023018690号
