IA82510
Asynchronous Serial Controller
Data Sheet
February 25, 2011
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Asynchronous Serial Controller
Data Sheet
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Asynchronous Serial Controller
Data Sheet
February 25, 2011
Copyright 2008 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
Intel is a registered trademark of Intel Corporation
MILES™ is a trademark of Innovasic Semiconductor, Inc.
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Data Sheet
February 25, 2011
TABLE OF CONTENTS
List of Figures ..................................................................................................................................4
List of Tables ...................................................................................................................................5
1.
Features ...................................................................................................................................6
2.
Description ..............................................................................................................................8
3.
Functional Overview ............................................................................................................10
3.1 Transmitter ..................................................................................................................10
3.2 Receiver .......................................................................................................................10
3.3 Bus Interface ...............................................................................................................10
3.4 Register Description ....................................................................................................11
4.
Maximum Ratings and AC/DC Parameters ..........................................................................12
5.
Packaging Information..........................................................................................................15
5.1 PDIP Package ..............................................................................................................15
5.2 PLCC Package .............................................................................................................16
6.
Innovasic Part Number Cross-Reference..............................................................................17
7.
Errata.....................................................................................................................................18
7.1 Summary .....................................................................................................................18
7.2 Detail ...........................................................................................................................19
8.
Revision History ...................................................................................................................24
9.
For Additional Information...................................................................................................25
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Asynchronous Serial Controller
Data Sheet
February 25, 2011
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Package Pinout ................................................................................................................7
Functional Block Diagram ..............................................................................................9
PDIP Physical Package Dimensions .............................................................................15
PLCC Physical Package Dimensions ............................................................................16
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Data Sheet
February 25, 2011
LIST OF TABLES
Table 1.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Register Summary...........................................................................................................11
Absolute Maximum Ratings ...........................................................................................12
AC Parameters ................................................................................................................13
DC Parameters ................................................................................................................14
Innovasic Part Number Cross-Reference for the PDIP ..................................................17
Innovasic Part Number Cross-Reference for the PLCC .................................................17
Summary of Errata ..........................................................................................................18
Revision History .............................................................................................................24
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1.
Data Sheet
February 25, 2011
Features
Form, Fit, and Function Compatible with the Intel 82510
Packaging options available: 28-Pin Plastic (PDIP) or, 28-Lead Plastic Leaded Chip
Carrier (PLCC), Leaded or RoHS packages available (see Figure 1, Package Pinout)
Asynchronous Serial Channel Operation
Separate Transmit and Receive FIFOs with Programmable Threshold
Programmable Baud Rate Generators up to 288K Baud
Special Protocol Features
– Control Character Recognition
– Auto Echo and Loopback Modes
– 9-Bit Protocol Support
– 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces
replacement ICs using its MILES™, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while
ensuring they are compatible with the original IC. MILES™ captures the design of a clone so it
can be produced even as silicon technology advances. MILES™ also verifies the clone against
the original IC so that even the "undocumented features" are duplicated. This data sheet
documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
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Data Sheet
February 25, 2011
D7
D6
D5
D4
D3
D2
D1
(4)
(3)
(2)
(1)
(28)
(27)
(26)
D4
(1)
(28)
D3
D5
(2)
(27)
D2
D6
(3)
(26)
D1
D7
(4)
(25)
D0
INT
(5)
(24)
A2
INT
(5)
(25)
D0
(23)
A1
TXD
(6)
(24)
A2
(22)
A0
VSS
(7)
(23)
A1
(22)
A0
X1 or CLK
(9)
(20)
RDn
X1 or CLK
(9)
SCLK or RIn
VDD
(10)
(19)
WRn
DSRn or TA or OUT0n
(11)
(18)
CSn
DCDn or ICLK or OUT1n
(12)
(17)
RESET
RXD
(13)
(16)
RTSn
CTSn
(14)
(15)
DSRn or TA or OUT0n
IA82510
28-Pin PLCC
(21)
VDD
(10)
(20)
RDn
(11)
(19)
WRn
(12) (13) (14) (15) (16) (17) (18)
DTRn or TB
DCDn or ICLK or OUT1n
SCLK or RIn
(21)
(8)
CSn
(8)
X2 or OUT2n
RESET
X2 or OUT2n
28-Pin PDIP
RTSn
(7)
DTRn or TB
VSS
IA82510
RXD
(6)
CTSn
TXD
Figure 1. Package Pinout
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2.
Data Sheet
February 25, 2011
Description
The IA82510 is an asynchronous serial controller that provides a CPU interface to one transmit
and one receive channel. It is Form, Fit, and Function compatible with the Intel 82510.
Configuration registers are used to control the serial channel, interrupts, and modes of operation.
The CPU controls this device via address and data lines with read/write control. The CPU also
uses this interface to read and write data to receive and transmit data through the serial channel.
FIFOs and various serial modes can be used to help off-load the CPU from transmitting and
receiving data. An interrupt line provides an indication to the CPU that the device requires
servicing. The device can be configured for 8250A/16450 compatibility. See Figure 2,
Functional Block Diagram.
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Data Sheet
February 25, 2011
IA82510
A(2:0)
D(7:0)
RDn
WRn
CSn
TRANSMITTER
TXD
RECEIVER
RXD
BUS INTERFACE
(Reset Logic,
Registers,
Interrupt Generation,
INT
RESET
CTSn
RTSn
TIMING
(Baud Rate
Generators A & B,
Clocking
CONFIG., STATUS, RXDATA
TXDATA
PIN
CONFIGURATION
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
X1 or CLK
X2 or OUT2n
SCLK or RIn
Figure 2. Functional Block Diagram
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3.
Functional Overview
3.1
Transmitter
Data Sheet
February 25, 2011
The Transmit function consists of a 4 11 bit FIFO, and a Transmit Engine. The 4 11 FIFO is
configurable as any depth between one and four words inclusive. The transmit engine is
responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin.
The transmit engine is highly configurable to be compatible with numerous formats, including
16450 and 8250 modes of communication. Transmit Communication parameters that can be
programmed include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
RTS and CTS modes
For more details, see Section 3.4, Register Description.
3.2
Receiver
The Receiver function consists of a 4 11 configurable FIFO and a Receive Engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing
the data in the FIFO. The receive engine is highly configurable with parameters that include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
Address Matching Options
Control Character Detection
RTS and CTS modes
For more details, see Section 3.4, Register Description.
3.3
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82510 Registers. It consists of the following I/O lines:
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IA82510
Asynchronous Serial Controller
A0, A1, A2:
D0-D7:
RDn:
WRn:
CSn:
INT:
RESET:
3.4
Data Sheet
February 25, 2011
3 Bit Address
8 Bit Data
Active Low Read Enable
Active Low Write Enable
Active Low Chip Select
Interrupt Output
Chip Reset
Register Description
Table 1 presents the register summary.
Table 1. Register Summary
Register
ACR0
ACR1
BACF
BAH
BAL
BANK
BBCF
BBH
BBL
CLCF
FLR
FMD
GER
GIR_BANK
GSR
ICM
IMD
LCR
LSR
MCR
MIE
MSR
PMD
RCM
RIE
RMD
ADDR
111
101
001
001
000
010
011
001
000
000
100
001
001
010
111
111
100
011
101
100
100
101
110
110
100
101
110
111
Bank
00
10
11
00
00
X
11
11
11
11
01
10
00
X
01
01
10
00
00
00
01
11
00
01
11
01
10
10
®
DLAB
X
X
0
1
1
X
X
1
1
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Mode
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R
W
R/W
R/W
R/W
R/W
W
R/W
R/W
R
R/W
W
R/W
R/W
Default
00000000
00000000
00000100
00000000
00000010
00000000
10000100
00000000
00000101
00000000
00000000
00000000
00000000
00000001
00010010
N/A
00001100
00000000
01100000
00000000
00001111
00000000
11111100
N/A
00011110
00000000
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Data Sheet
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Table 2. Register Summary (Continued)
Register
RST
RXDATA
ADDR
101
000
RXF
TCM
TMCR
TMD
TMIE
TMST
TXDATA
001
110
011
011
110
011
000
TXF
001
4.
Bank
01
00
01
01
01
01
10
11
01
00
01
01
DLAB
X
0
X
X
X
X
X
X
X
0
X
X
Mode
R
R
Default
00000000
Unknown
R
W
W
R/W
R/W
R
W
Unknown
N/A
N/A
00000000
00000000
00110000
N/A
W
N/A
Maximum Ratings and AC/DC Parameters
Stresses beyond those listed in Table 2 may cause permanent damage to the device. Operating the
device beyond the conditions indicated in the “recommended operating conditions” section is not
recommended. Operation at the “absolute maximum ratings” may adversely affect device
reliability.
Table 3. Absolute Maximum Ratings
Parameter
Supply Voltage, VDD
Input Voltage, VIN
Input Pin Current, IIN
Operating Temperature Range
Ambient temperature under bias
Storage temperature
Lead Temperature
Power dissipation
Rating
-0.3V to +6.0V
-0.3V to VDD +0.3V
±10 mA, 25 C
-40 C to +85°C
-40°C to +85°C *
-55°C to +150°C
+300°C, 10 sec.
155 mW, 125°C, 25MHz, 15% Toggle
* The input and output parametric values are directly related to ambient temperature and DC supply
voltage. A temperature or supply voltage range other than those specified in the Operating Conditions
above will affect these values and part performance is not guaranteed by Innovasic.
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Data Sheet
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Table 4. AC Parameters
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
CLK Rise Time
Min
–
Max
250 ns
108 ns
–
–
10 ns
CLK Fall Time
–
10 ns
CLK Rise Time
CLK Fall Time
Crystal Frequency
Reset Width
RTS/DTR Low Setup to Reset
inactive
RTS/DTR Low Hold after
Reset inactive
RDn Active Width
–
–
15 ns
15 ns
20 Mhz
–
–
54 ns
54 ns
25 ns
25 ns
Address/CSn Setup Time to
RDn Active
Address/CSn Hold after RDn
Inactive
RDn or WRn Inactive to Active
Delay
Data Out Float Delay after
RDn Inactive
WRn Active Width
Address CSn Setup Time to
WRn Active
Address and CSn hold Time
after WRn
Data in Setup Time to WRn
Inactive
Data In Hold Time after WRn
Inactive
SCLK Period
SCLK Period
RXD Setup Time to SCLK High
RXD Hold Time after SCLK
High
TXD Valid after SCLK Low
TXD Delay after RXD
®
1 Mhz
8 * Clock Period
6 * Clock Period
–
Clock Period
–20 ns
–
2* clock period
+65 ns
7 ns
Notes
Divide by Two
No Divide by
–
–
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
No Divide by
No Divide by
–
–
–
–
–
–
–
0 ns
–
–
Clock Period
+15 ns
–
–
–
–
40 ns
2 * Clock Period
+15 ns
7 ns
–
–
–
–
0 ns
–
–
90 ns
–
–
12 ns
–
–
216 ns
3500 ns
250 ns
250 ns
–
–
–
–
–
–
170 ns
170 ns
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16x Clocking Mode
1x Clocking Mode
–
–
–
Remote Loopback
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Table 5. DC Parameters
Symbol
VIL
VIH1
VIH2
VOL
VOH
ILI
ILO
ICC
IPU
ISTBY
IOHR
IOLR
CIN
CIO
CXTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2),(8)
(3),(8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min
-0.5
2.1
2.1
Max
0.3
VDD+.3
VDD+.3
0.4
2.4
-28.3
1
10
1.12
-137
100
1.92
N/A
5
6
6
Unit
V
V
V
V
V
A
A
mA/MHz
A
A
mA
mA
pF
pF
pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA.
3. @IOH = 1.92 mA.
4. 0< VIN