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ETHERNET TRANSCEIVERS
• 1 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201B)
• 1.2 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201BI)
• Low Power Consumption 150 mV, LOS = 1, valid input signal
If magnitude of RXP–RXN < 150 mV and >50 mV, LOS is undefined
If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal
MODESEL
15
I
P/D(1)
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface.
When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected.
The default mode is the TBI.
LOOPEN
19
I
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
TCK
49
I
Test clock. IEEE1149.1 (JTAG)
JTDI
48
I
Test data input. IEEE1149.1 (JTAG)
JTDO
27
O
Test data output. IEEE1149.1 (JTAG)
JTRSTN
56
I
P/U(2)
Reset signal. IEEE1149.1 (JTAG)
JTMS
55
I
P/U(2)
Test mode select. IEEE1149.1 (JTAG)
ENABLE
28
I
P/U(2)
When this terminal is low, the device is disabled for Iddq testing. RD0 - RD9, RBCn, TXP, and
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
PRBSEN
16
I
P/D(1)
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
TEST
(1)
(2)
4
P/D = Internal pulldown
P/U = Internal pullup
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
TESTEN
I/O
NO.
DESCRIPTION
17
I
P/D(1)
Manufacturing test terminal
5, 10, 20, 23,
29, 37, 42,
50, 63
Supply
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
53, 57, 59,
60
Supply
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter.
18
Supply
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
POWER
VDD
VDDA
VDDPLL
GROUND
GNDA
GND
GNDPLL
51,58
1, 14, 21, 25,
33, 46
64
Ground Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.
Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Ground PLL ground. Provides a ground for the PLL circuitry.
DETAILED DESCRIPTION
DATA TRANSMISSION
These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR
clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is
selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0-TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode data is
aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent
to the serializer. The rising edge REFCLK clocks in bit 0-4, and the falling edge of REFCLK clocks in bits 5–9. (
Bit 0 is the first bit transmitted).
TRANSMISSION LATENCY
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The
minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.
10 Bit Code
TXP, TXN
b9
td(Tx latency)
10 Bit Code
TD(0−9)
REFCLK
Figure 1. Transmitter Latency Full Rate Mode
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DATA RECEPTION
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0, RBC1).
RECEIVER CLOCK SELECT MODE
There are two modes of operation for the parallel busses. 1) The 10-bit (TBI) mode and 2) 5-bit (DDR) mode.
When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal. 1)
Full-rate clock on RBC0 and 2) Half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate
clock is available on RBC0; refer to Table 1.
Table 1. Mode Selection
MODESEL
RBCMODE
MODE
FREQUENCY
(TLK2201B)
FREQUENCY
(TLK2201BI)
0
0
TBI half-rate
100–125 MHz
120–125 MHz
0
1
TBI full-rate
100–160 MHz
120–160 MHz
1
0
DDR
100–125 MHz
120–125 MHz
1
1
DDR
100–125 MHz
120–125 MHz
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at
one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is
output with respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel
bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data
valid on the rising edge of RBC1. Refer to the timing diagram shown in Figure 2.
td(S)
RBC0
td(S)
RBC1
td(H)
SYNC
td(H)
RD(0−9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (i.e., 1.25 Gbps data rate produces a
125 MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode.
Refer to the timing diagram shown in Figure 3.
RBC0
td(S)
td(H)
SYNC
RD(0−9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 3. Synchronous Timing Characteristics Waveforms (TBI full-rate mode)
6
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In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1
is low impedance. The data is clocked bit-0 first, and aligned to the rising edge of RBC0. Refer to the timing
diagram shown in Figure 4.
td(S)
RBC0
td(S)
td(H)
td(H)
SYNC
RD(0−4)
K28.5
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
K28.5
DXX.X
Bits 0−4 Bits 5−9
Figure 4. Synchronous Timing Characteristics Waveforms (DDR mode)
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The
received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02% (200
PPM) for proper operation.
RECEIVER WORD ALIGNMENT
These devices use the IEEE 802.3 Gigabit Ethernet defined 10-bit K28.5 character (comma character) word
alignment scheme. The following sections explain how this scheme works and how it realigns itself.
Comma Character on Expected Boundary
These devices provide 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial
input data to the seven bit synchronization pattern. The K28.5 character is defined by the 8-bit/10-bit coding
scheme as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs
(0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning
data words. As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is
properly aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1,
SYNC and RD0-RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1).
Comma Character Not on Expected Boundary
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the
misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 5. The
RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design
the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is
aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing characteristics of the
data realignment.
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31 Bit
Times
Max Receive
Path Latency
INPUT DATA
K28.5
DXX.X
30 Bit
Times (Max)
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
RBC0
RBC1
Worst Case
Misaligned K28.5
RD(0−9)
DXX.X
DXX.X
Misalignment Corrected
Corrupt Data
K28.5
DXX.X
DXX.X
K28.5
DXX.X
DXX.X
DXX.X
K28.5
SYNC
Figure 5. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the
SYNC pulse is present for the entire RBC0 period.
DATA RECEPTION LATENCY
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is 34
bit times.
10 Bit Code
RXP, RXN
td(Rx latency)
RD(0−9)
10 Bit Code
RBC0
Figure 6. Receiver Latency – TBI Normal Mode Shown
LOSS OF SIGNAL DETECTION
These devices have a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer
has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of
gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of
signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV.
The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
8
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TESTABILITY
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for a BIST( built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for
factory testing, and is not intended for the end-user.
LOOPBACK TESTING
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.
Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. (The external differential output is
held in a high-impedance state during the loopback testing.)
ENABLE FUNCTION
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an
ultralow-power idle state when the link is not active.
PRBS FUNCTION
These devices have a built-in 27-1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel
input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if
it were normal data and sent out to the transmitter. The output can be sent to a (BERT) bit error rate tester or to
the receiver of another TLK2201B or TLK2201BI. Since the PRBS is not really random and is really a
predetermined sequence of ones and zeros, the data can be captured and checked for errors by a BERT. These
devices also have a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a
PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. When
PRBS is enabled, RBCMODE is ignored. MODSEL must be low for the PRBS verifier to function correctly. The
device operates in TBI mode with a full-rate clock on RBC0. The PRBS testing supports two modes (normal and
latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate
test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS verification is latched
on the SYNC/PASS output (i.e., a single failure forces SYNC/PASS to remain low).
JTAG
The TLK2201B supports an IEEE1149.1 JTAG function while maintaining compatibility with the industry standard
64 pin QFP package footprint. In this way, the TLK1201B installed on a board layout that was designed for the
industry standard footprint such as for the TNETE2201B. (Provided the supply voltage can be programmed from
the older 3.3 V to 2.5 V.) The JTAG pins on the TLK2201B are chosen to either be on the ‘vender-unique’ pins of
the industry standard footprint, or are on pins that were previously power or ground. The TRSTN pin has been
placed on pin 56, which is a ground on the industry standard footprint. In this way, a TLK2201B installed onto the
older footprint has the JTAG tap controller held in reset, and thus disabled. If the JTAG function is desired, then
the 5 JTAG pins TRSTN, TMS, TCK, TDI, and TDO can be used in the usual manner for a JTAG function. If the
JTAG function is not desired, then connecting TRSTN to ground is recommended. TMS and TDI have internal
pullup resistors, and can thus be left unconnected if not used. TDO is an output and should be left unconnected
if JTAG is not used. TCK does not have an internal pullup, and can be tied to GND or PWR if not used, but with
TRSTN low, this input is not used, and thus can be left unconnected.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD
Supply voltage (2)
–0.3 to 3
V
VI
Input voltage range at TTL terminals
–0.5 to 4
V
Input voltage range at any other terminal
Tstg
Storage temperature
°C
1
kV
HDM
Characterized free-air operating temperature range
(2)
V
–65 to 150
CDM
Electrostatic discharge
(1)
–0.3 to VDD +0.3
2
kV
TLK2201B
0 to 70
°C
TLK2201BI
–40 to 85
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
DISSIPATION RATINGS (1)
(1)
(2)
(3)
(4)
(5)
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING
FACTOR (2)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
RCP64 (3)
5.25 W
46.58 mW/°C
2.89 W
RCP64 (4)
3.17 W
23.70 mW/°C
1.74 W
RCP64 (5)
2.01 W
13.19 mW/°C
1.11 W
For more information, refer to TI application note PowerPAD Thermally Enhanced Package
(SLMA002).
This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA).
2 oz. Trace and copper pad with solder.
2 oz. Trace and copper pad without solder.
Standard JEDEC high-K board
THERMAL CHARACTERISTICS
PARAMETER
RθJA
RθJC
Junction-to-free-air thermal resistance
Junction-to-case-thermal resistance
TEST CONDITIONS
MIN
Board-mounted, no air flow, high conductivity TI
recommended test board, chip soldered or greased
to thermal land
21.47
Board-mounted, no air flow, high conductivity TI
recommended test board with thermal land but no
solder or grease thermal connection to thermal land
42.20
Board-mounted, no air flow, JEDEC test board
75.83
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MAX
UNIT
°C/W
Board-mounted, no air flow, high conductivity TI
recommended test board, chip soldered or greased
to thermal land
0.38
Board-mounted, no air flow, high conductivity TI
recommended test board with thermal land but no
solder or grease thermal connection to thermal land
0.38
Board-mounted, no air flow, JEDEC test board
10
TYP
°C/W
7.8
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD, VDD(A)
Supply voltage
Frequency = 1.25 Gbps,
PRBS pattern
Frequency = 1.6 Gbps,
Worst case pattern (1)
Frequency = 1.25 Gbps,
PRBS pattern
Frequency = 1.6 Gbps,
Worst case pattern (1)
Vdda , Vdd = 2.7 V
IDD, IDD(A)
Total supply current
PD
Total power dissipation
IDD, IDD(A)
Total shutdown current
Enable = 0,
PLL
Startup lock time
VDD, VDD(A) = 2.5 V, EN↑ to PLL acquire
TA
(1)
Operating free-air temperature
MIN
NOM
MAX
2.3
2.5
2.7
80
111
200
310
UNIT
V
mA
mW
50
µA
500
µs
TLK2201B
0
70
TLK2201BI
–40
85
°C
Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.
TLK2201B REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
Frequency
PARAMETER
Minimum data rate
TEST CONDITIONS
TYP–0.01%
MIN
100 TYP–0.01%
MHz
Frequency
Maximum data rate
TYP–0.01%
160 TYP–0.01%
MHz
100
ppm
Accuracy
–100
Duty cycle
40%
Jitter
TYP
50%
60%
Random plus deterministic
40
ps
TLK2201BI REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
Frequency
PARAMETER
Minimum data rate
TEST CONDITIONS
TYP–0.01%
MIN
TYP
100 TYP–0.01%
MHz
Frequency
Maximum data rate
TYP–0.01%
160 TYP–0.01%
MHz
Accuracy
–100
100
ppm
Duty cycle
40%
Jitter
50%
60%
Random plus deterministic
40
ps
TTL ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –400 µA
VOL
Low-level output voltage
IOL = 1 mA
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
Input high current
VDD = 2.3 V,
VIN = 2.0 V
IIL
Input low current
VDD = 2.3 V,
VIN = 0.4 V
CIN
Input capacitance
MIN
TYP
VDD –0.2
2.3
GND
0.25
1.7
MAX
V
0.5
V
3.6
V
0.8
V
40
µA
µA
–40
4
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UNIT
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TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Vod = |TxD–TxN|
V(cm)
Transmit common mode voltage range
MIN
TYP
MAX
Rt = 50 Ω
600
850
1100
Rt = 75 Ω
800
1050
1200
Rt = 50 Ω
1000
1250
1400
Rt = 75 Ω
1000
1250
1400
Receiver Input voltage requirement,
Vid = |RxP - RxN|
200
UNIT
mV
mV
1600
mV
2250
mV
350
µA
2
pF
Receiver common mode voltage range,
(RxP + RxN)/2
1000
Ilkg(R)
Receiver input leakage current
–350
CI
Receiver input capacitance
t(TJ)
Serial data total jitter (peak-to-peak)
Differential output jitter, Random +
deterministic, PRBS pattern,
Rω = 125 MHz
0.24
UI
t(DJ)
Serial data deterministic jitter (peak-to-peak)
Differential output jitter, PRBS pattern,
Rω = 125 MHz
0.12
UI
tr, tf
Differential signal rise, fall time (20% to 80%)
RL = 50 Ω, CL = 5 pF,
See Figure 7 and Figure 8
100
250
ps
Serial data jitter tolerance minimum required
eye opening, (per IEEE-802.3 specification)
Differential input jitter, Random +
deterministic,
Rω = 125 MHz
0.25
Receiver data acquisition lock time from
powerup
Data relock time from loss of synchronization
td(Tx latency)
Tx latency
td(Rx
Rx latency
latency)
500
µs
1024
Bit
times
19
20
DDR
mode
29
30
TBI modes See Figure 6
21
31
DDR
mode
27
34
UI
UI
∼V
CL
5 pF
∼V
50 Ω
tf
tr
80%
50%
20%
TX−
tf
50 Ω
∼V
CL
5 pF
∼V
tr
∼ 1V
80%
0V
VOD
20%
∼ −1V
Figure 7. Differential and Common-Mode Output Voltage
Definitions
12
UI
TBI modes See Figure 1
80%
50%
20%
TX+
1250
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Figure 8. Transmitter Test Setup
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1.4 V
CLOCK
tf
tr
80%
50%
20%
DATA
2V
0.8 V
tf
tr
Figure 9. TTL Data I/O Valid Levels for AC Measurement
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
80% to 20% output voltage, C = 5 pF (see Figure 9)
TYP
MAX
UNIT
tr(RBC)
Clock rise time
0.3
1.5
tf(RBC)
Clock fall time
0.3
1.5
tr
Data rise timer
0.3
1.5
tf
Data fall time
0.3
1.5
tsu(D1)
Data setup time (RD0..RD9),
Data valid prior to RBC0 rising)
TBI normal mode (see Figure 3)
2.5
ns
th(D1)
Data hold time (RD0..RD9),
Data valid after RBC0 rising
TBI normal mode (see Figure 3)
2
ns
tsu(D2)
Data setup time (RD0..RD4)
DDR mode, Rω = 125 MHz (see Figure 4)
2
ns
th(D2)
Data hold time (RD0..RD4)
DDR mode, Rω = 125 MHz (see Figure 4)
0.8
ns
tsu(D3)
Data setup time (RD0..RD9)
TBI half-rate mode, Rω = 125 MHz (see Figure 2)
2.5
ns
th(D3)
Data hold time (RD0..RD9)
TBI half-rate mode, Rω = 125 MHz (see Figure 2)
1.5
ns
ns
ns
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tsu(D4)
Data setup time (TD0..TD9)
th(D4)
Data hold time (TD0..TD9)
tsu(D5)
Data setup time (TD0..TD9)
th(D5)
Data hold time (TD0..TD9)
tr, tf
TD[0,9] Data rise and fall time
(1)
TEST CONDITIONS
TBI modes
DDR modes
See Figure 9
MIN
TYP
MAX
1.6
UNIT
ns
0.59 (1)
0.7
ns
0.5
2
ns
Measured at 1.25V (midpoint of VIL and VIH) with input switching between 0V and VDD.
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Product Folder Link(s): TLK2201B TLK2201BI
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SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
APPLICATION INFORMATION
8B/10B TRANSMISSION CODE
The PCS maps GMII signals into ten-bit code groups and vice versa, using an 8b/10b block coding scheme. The
PCS uses the transmission code to improve the transmission characteristics of information to be transferred
across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in
the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the
likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of
information. The 8b/10b transmission code specified for use has a high transition density, is run length limited,
and is dc-balanced. The transition density of the 8b/10b symbols ranges from 3 to 8 transitions per symbol. The
definition of the 8b/10b transmission code is specified in IEEE 802.3 Gigabit Ethernet and ANSI X3.230-1994
(FC−PH), clause 11.
8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit
notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b
transmission code-groups, where A is the LSB. Each valid code group has been given a name using the
following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups,
where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K).
Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111
11110.
VDD
TXP
ZO
5 kΩ
RXP
7.5 kΩ
ZO
GND
+
_
VDD
ZO
5 kΩ
ZO
TXN
RXN
7.5 kΩ
GND
Transmitter
Media
Receiver
Figure 10. High-Speed I/O Directly-Coupled Mode
VDD
TXP
ZO
5 kΩ
RXP
7.5 kΩ
ZO
GND
+
_
VDD
ZO
5 kΩ
TXN
ZO
RXN
7.5 kΩ
GND
Transmitter
Media
Receiver
Figure 11. High-Speed I/O AC-Coupled Mode
14
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Product Folder Link(s): TLK2201B TLK2201BI
TLK2201B
TLK2201BI
www.ti.com
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
5 Ω at 100 MHz
2.5 V
2.5 V
18
VDD VDDA
GND
0.01 µF
VDDPLL
GNDPLL
64
GNDA
TLK2201B
TLK2201BI
17
TESTEN
10
TD0−TD9
22
16
TXP
62
Controlled Impedance
Transmission Line
61
Controlled Impedance
Transmission Line
54
Controlled Impedance
Transmission Line
REFCLK
PRBSEN
19
LOOPEN
24
Host
Protocol
Device
47
10
SYNCEN
TXN
SYNC/PASS
RD0−RD9
2
RBC0−RBC1
28
26
ENABLE
RXP
LOS
32
Rt
50 Ω
Rt
50 Ω
RBCMODE
15
MODESEL
49
55
48
JTAG
Controller
56
27
TCK
JTMS
RXN
52
Controlled Impedance
Transmission Line
JTDI
JTRSTN
JTDO
Figure 12. Typical Application Circuit (AC mode)
DESIGNING WITH PowerPAD
The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP (RCP64)
PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note
that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical
conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly
techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches
or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The
recommended convention, however, is to not run any etches or signal vias under the device, but to have only a
grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the
minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB
construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not
contain numerous thermal vias depending on PCB construction.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TLK2201B TLK2201BI
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SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD
Thermally Enhanced Package Application Report (SLMA002), available via the TI Web pages beginning at URL:
http://www.ti.com.
Figure 13. Example of a Thermal Land
For the TLK2201B, this thermal land must be grounded to the low-impedance ground plane of the device. This
improves not only thermal performance but also the electrical grounding of the device. It is also recommended
that the device ground pin landing pads be connected directly to the grounded thermal land. The land size must
be as large as possible without shorting device signal pins. The thermal land may be soldered to the exposed
PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low-impedance ground plane for the device. More
information may be obtained from the TI application note PHY Layout (SLLA020).
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLK2201BIRCP
ACTIVE
HVQFP
RCP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2201BI
TLK2201BIRCPR
ACTIVE
HVQFP
RCP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2201BI
TLK2201BIRCPRG4
ACTIVE
HVQFP
RCP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2201BI
TLK2201BRCP
ACTIVE
HVQFP
RCP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TLK2201B
TLK2201BRCPR
ACTIVE
HVQFP
RCP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TLK2201B
TLK2201BRCPRG4
ACTIVE
HVQFP
RCP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TLK2201B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of