LT1169
Dual Low Noise,
Picoampere Bias Current,
JFET Input Op Amp
U
DESCRIPTIO
FEATURES
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■
■
■
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■
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Input Bias Current, Warmed Up: 20pA Max
100% Tested Low Voltage Noise: 8nV/√Hz Max
S8 and N8 Package Standard Pinout
Very Low Input Capacitance: 1.5pF
Voltage Gain: 1.2 Million Min
Offset Voltage: 2mV Max
Input Resistance: 1013Ω
Gain-Bandwidth Product: 5.3MHz Typ
Guaranteed Specifications with ±5V Supplies
Guaranteed Matching Specifications
UO
APPLICATI
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■
S
Photocurrent Amplifiers
Hydrophone Amplifiers
High Sensitivity Piezoelectric Accelerometers
Low Voltage and Current Noise Instrumentation
Amplifier Front Ends
Two and Three Op Amp Instrumentation Amplifiers
Active Filters
The LT1169 achieves a new standard of excellence in noise
performance for a dual JFET op amp. For the first time low
voltage noise (6nV/√Hz) is simultaneously offered with
extremely low current noise (1fA/√Hz), providing the lowest total noise for high impedance transducer applications.
Unlike most JFET op amps, the very low input bias current
(5pA Typ) is maintained over the entire common mode
range which results in an extremely high input resistance
(1013Ω). When combined with a very low input capacitance (1.5pF) an extremely high input impedance results,
making the LT1169 the first choice for amplifying low level
signals from high impedance transducers. The low input
capacitance also assures high gain linearity when buffering
AC signals from high impedance transducers.
The LT1169 is unconditionally stable for gains of 1 or more,
even with 1000pF capacitive loads. Other key features are
0.6mV VOS and a voltage gain over 4 million. Each individual amplifier is 100% tested for voltage noise, slew rate
(4.2V/µs), and gain-bandwidth product (5.3MHz).
The LT1169 is offered in the S8 and N8 packages.
A full set of matching specifications are provided for
precision instrumentation amplifier front ends. Specifications at ±5V supply operation are also provided. For an
even lower voltage noise please see the LT1113 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UO
TYPICAL APPLICATI
Low Noise Light Sensor with DC Servo
1kHz Output Voltage Noise
Density vs Source Resistance
R1
1M
–
1/2 LT1169
3
1
CD
D1
1N914
HAMAMATSU
S1336-5BK
(908) 231-0960
R5
10k
V–
R4
1k
7
6
R2
100k
1/2 LT1169
+
2N3904
+V
8
R3
1k
VOUT
C2
0.022µF
+
D2
1N914
–
2
5
4
–V
R2C2 > C1R1
CD = PARASITIC PHOTODIODE CAPACITANCE
VOUT = 100mV/µWATT FOR 200nm WAVE LENGTH
330mV/µWATT FOR 633nm WAVE LENGTH
TOTAL 1kHz VOLTAGE NOISE DENSITY (nV/ √Hz)
C1
2pF
10k
–
1k
VN
+
RSOURCE
100
10
1
100
VN
SOURCE
RESISTANCE
ONLY
1k
TA = 25°C
VS = ±15V
10k 100k 1M 10M 100M 1G
SOURCE RESISTANCE (Ω)
VN = √(VOP AMP)2 + 4kTRS + 2qIBRS2
LT1169 • TA01
LT1169 • TA02
1
LT1169
U
U
RATI GS
W
W W
W
AXI U
U
ABSOLUTE
PACKAGE/ORDER I FOR ATIO
Supply Voltage
– 55°C to 105°C ............................................... ±20V
105°C to 125°C ............................................... ±16V
Differential Input Voltage ...................................... ±40V
Input Voltage (Equal to Supply Voltage) ............... ±20V
Output Short-Circuit Duration......................... Indefinite
Operating Temperature Range ............... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
ORDER PART
NUMBER
TOP VIEW
OUT A 1
–IN A 2
+IN A 3
V
–
8
7 OUT B
A
4
N8 PACKAGE
8-LEAD PDIP
V+
LT1169CN8
LT1169CS8
6 –IN B
B
5 +IN B
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
TJMAX = 150°C, θJA = 80°C/W (N8)
TJMAX = 160°C, θJA = 190°C/W (S8)
1169
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.
SYMBOL
PARAMETER
VOS
Input Offset Voltage
IOS
TYP
MAX
UNITS
VS = ±5V
0.60
0.65
2.0
2.2
mV
mV
Input Offset Current
Warmed Up (Note 2)
TJ = 25°C (Note 5)
2.5
0.7
15
4
pA
pA
IB
Input Bias Current
Warmed Up (Note 2)
TJ = 25°C (Note 5)
4.0
1.5
20
5
pA
pA
en
Input Noise Voltage
0.1Hz to 10Hz
2.4
µVP-P
Input Noise Voltage Density
fO = 10Hz
fO = 1000Hz
17
6
8
nV/√Hz
nV/√Hz
fO = 10Hz, fO = 1kHz (Note 3)
1
in
Input Noise Current Density
RIN
Input Resistance
Differential Mode
Common Mode
CONDITIONS (Note 1)
MIN
fA/√Hz
VCM = –10V to 13V
1014
1013
Ω
Ω
VS = ±5V
1.5
2.0
pF
pF
13.0
–10.5
13.5
–11.0
V
V
CIN
Input Capacitance
VCM
Input Voltage Range (Note 4)
CMRR
Common Mode Rejection Ratio
VCM = –10V to 13V
82
95
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ± 20V
83
98
dB
AVOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k
VO = ±10V, RL = 1k
1000
500
4500
3000
V/mV
V/mV
VOUT
Output Voltage Swing
RL = 10k
RL = 1k
±13.0
±12.0
±13.8
±13.0
V
V
SR
Slew Rate
RL ≥ 2k (Note 6)
2.4
4.2
V/µs
GBW
Gain-Bandwidth Product
fO = 100kHz
3.3
5.3
MHz
Channel Separation
fO = 10Hz, VO = ±10V, RL = 1k
126
dB
VS = ±5V
5.3
5.3
6.50
6.45
mA
mA
0.8
3.5
mV
3
20
IS
Supply Current per Amplifier
∆VOS
∆IB
Offset Voltage Match
+
Noninverting Bias Current Match
Warmed Up (Note 2)
∆CMRR
Common Mode Rejection Match
(Note 8)
78
94
dB
∆PSRR
Power Supply Rejection Match
(Note 8)
80
95
dB
2
pA
LT1169
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
VOS
Input Offset Voltage
∆VOS
∆Temp
Average Input Offset Voltage Drift
IOS
VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, (Note 9), unless otherwise noted.
TYP
MAX
UNITS
VS = ± 5V
●
●
0.7
0.8
3.2
3.4
mV
mV
(Note 5)
●
20
50
µV/°C
Input Offset Current
●
10
50
pA
IB
Input Bias Current
●
180
400
pA
VCM
Input Voltage Range
●
●
12.9
–10.0
13.4
–10.8
V
V
CMRR
Common Mode Rejection Ratio
VCM = –10V to 12.9V
●
79
94
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
●
81
97
A VOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k
VO = ±10V, RL = 1k
●
●
800
400
3400
2400
V/mV
V/mV
V OUT
Output Voltage Swing
R L = 10k
R L = 1k
●
●
±12.5
±11.5
±13.5
±12.7
V
V
SR
Slew Rate
R L ≥ 2k (Note 6)
●
1.9
4
V/µs
GBW
Gain-Bandwidth Product
f O = 100kHz
●
3
4.2
MHz
IS
Supply Current per Amplifier
VS = ±5V
●
●
5.3
5.3
6.55
6.50
mA
mA
●
1.5
5
mV
5.5
50
∆VOS
∆IB
CONDITIONS (Note 1)
Offset Voltage Match
MIN
dB
+
Noninverting Bias Current Match
∆CMRR
Common Mode Rejection Match
(Note 8)
●
74
93
dB
∆PSRR
Power Supply Rejection Match
(Note 8)
●
77
93
dB
MIN
TYP
MAX
UNITS
●
●
0.8
0.9
3.8
4.0
mV
mV
●
pA
VS = ±15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, (Note 7), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
VOS
Input Offset Voltage
∆VOS
∆Temp
Average Input Offset Voltage Drift
●
20
50
µV/°C
IOS
Input Offset Current
●
30
200
pA
IB
Input Bias Current
●
320
1200
pA
VCM
Input Voltage Range
●
●
12.6
–10.0
13.0
–10.5
V
V
CMRR
Common Mode Rejection Ratio
VCM = –10V to 12.6V
●
78
93
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
●
79
96
dB
A VOL
Large-Signal Voltage Gain
VO = ±12V, RL = 10k
VO = ±10V, RL = 1k
●
●
750
300
3000
2000
V/mV
V/mV
V OUT
Output Voltage Swing
RL = 10k
RL = 1k
●
●
±12.5
±11.3
±12.5
±12.0
V
V
VS = ±5V
SR
Slew Rate
RL ≥ 2k
●
1.8
3.8
V/µs
GBW
Gain-Bandwidth Product
fO = 100kHz
●
2.7
4
MHz
IS
Supply Current per Amplifier
VS = ±5V
●
●
5.30
5.25
6.55
6.50
mA
mA
3
LT1169
ELECTRICAL CHARACTERISTICS VS = ±15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, (Note 7), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
∆VOS
Offset Voltage Match
●
1.8
6
mV
∆IB+
Noninverting Bias Current Match
●
10
180
pA
∆CMRR
Common Mode Rejection Match
(Note 8)
●
73
93
dB
∆PSRR
Power Supply Rejection Match
(Note 8)
●
75
92
dB
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op
amps) typically 120 op amps will be better than the indicated specification.
Note 2: IB and IOS readings are extrapolated to a warmed-up temperature
from 25°C measurements and 45°C characterization data.
Note 3: Current noise is calculated from the formula:
in = (2qIB)1/2
where q = 1.6 × 10 –19 coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 4: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.8mV.
Note 5: This parameter is not 100% tested.
MIN
TYP
MAX
UNITS
Note 6: Slew rate is measured in AV = –1; input signal is ±7.5V, output
measured at ±2.5V.
Note 7: The LT1169 is designed, characterized and expected to meet these
extended temperature limits, but is not tested at – 40°C and 85°C.
Guaranteed I grade parts are available; consult factory.
Note 8: ∆CMRR and ∆PSRR are defined as follows:
(1) CMRR and PSRR are measured in µV/V on the individual
amplifiers.
(2) The difference is calculated between the matching sides in µV/V.
(3) The result is converted to dB.
Note 9: The LT1169 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed-up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
1kHz Input Noise Voltage
Distribution
0.1Hz to 10Hz Voltage Noise
Voltage Noise vs Frequency
100
50
30
20
10
0
2
4
6
TIME (SEC)
8
10
LT1169 • TPC01
4
RMS VOLTAGE NOISE (nV/√Hz)
PERCENT OF UNITS (%)
VOLTAGE NOISE (1µV/DIV)
40
TA = 25°C
VS = ±15V
TA = 25°C
VS = ±15V
510 OP AMPS TESTED
0
4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 7.4 7.8 8.2
INPUT VOLTAGE NOISE (nV/√Hz)
LT1169 • TPC02
10
TYPICAL
1/f CORNER
60Hz
1
1
10
100
1k
FREQUENCY (Hz)
10k
LT1169 • TPC03
LT1169
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias and Offset Currents
vs Chip Temperature
Voltage Noise vs Chip Temperature
30n
INPUT BIAS AND OFFSET CURRENTS (A)
9
8
7
6
5
4
3
2
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
10
VS = ±15V
VCM = –10 TO 13V
10n
3n
1n
BIAS
CURRENT
300p
100p
30p
OFFSET
CURRENT
10p
3p
1p
0.3p
100 125
25
0
75
100
50
TEMPERATURE (°C)
Common Mode Limit
vs Temperature
–2.0
3.0
2.5
V – = – 5V TO – 20V
V – +1.0
–60
–20
0
60
100
20
TEMPERATURE (°C)
OFFSET CURRENT
–2
–4
–6
–8
Power Supply Rejection Ratio
vs Frequency
120
TA = 25°C
VS = ±15V
100
80
60
40
20
0
140
1k
10k
100k
1M
FREQUENCY (Hz)
TA = 25°C
VS = ±15V
–PSRR
60
40
20
0
10
100
1k
10k 100k
FREQUENCY (Hz)
50
8
7
6
5
RL =10k
4
3
RL = 1k
2
10M
40
60
TA = 25°C
VS = ±15V
CL = 10pF
80
30
100
20
120
PHASE
10
140
GAIN
0
PHASE SHIFT (DEG)
VOLTAGE GAIN (V/µV)
140
1M
Gain and Phase Shift
vs Frequency
VS = ±15V
VO = ±10V, RL = 1k
VO = ±12V, RL = 10k
9
20
+PSRR
80
LT1169 • TPC09
10
180
60
100
10M
Voltage Gain vs Chip Temperature
100
TA = 25°C
LT1169 • TPC08
LT1169 • TPC07
Voltage Gain vs Frequency
15
10
–10
0
5
–5
COMMON MODE RANGE (V)
LT1169 • TPC06
POWER SUPPLY REJECTION RATIO (dB)
COMMON MODE REJECTION RATIO (dB)
COMMON MODE LIMIT (V)
REFERRED TO POWER SUPPLY
V + = 5V TO 20V
1.5
VOLTAGE GAIN (dB)
125
120
0
2.0
BIAS CURRENT
2
Common Mode Rejection Ratio
vs Frequency
–0.5
–1.5
6
4
LT1169 • TPC05*
LT1169 • TPC04
–1.0
TA = 25°C
VS = ±15V
8
–10
–15
VOLTAGE GAIN (dB)
VOLTAGE NOISE (AT 1kHz) (nV/√Hz)
VS = ±15V
INPUT BIAS AND OFFSET CURRENTS (pA)
10
V+
Input Bias and Offset Currents
Over the Common Mode Range
160
1
–20
0.01
1
10k
100
FREQUENCY (Hz)
1M
100M
LT1169 • TPC10
0
–75 –50 –25 0
25 50 75
CHIP TEMPERATURE (°C)
–10
100 125
LT1169 • TPC11
0.1
1
10
FREQUENCY (MHz)
180
100
LT1169 • TPC12
5
LT1169
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Small-Signal Transient Response
Large-Signal Transient Response
Supply Current vs Supply Voltage
SUPPLY CURRENT PER AMPLIFIER (mA)
5V/DIV
20mV/DIV
6
AV = 1
CL = 10pF
VS = ±15V, ±5V
2µs/DIV
AV = 1
CL = 10pF
VS = ±15V
LT1169 • TPC13
5µs/DIV
LT1169 • TPC14
25°C
–55°C
5
125°C
4
0
±10
±15
±5
SUPPLY VOLTAGE (V)
±20
LT1169 • TPC15
Output Voltage Swing
vs Load Current
50
–1.6
VS = ±5V TO ±20V
1.2
1.0
20
10
0
0.1
3
6
2
4
1
2
1
100
1000
10
CAPACITIVE LOAD (pF)
10000
0
25 50 75
–75 –50 –25 0
TEMPERATURE (°C)
Warm-Up Drift
Channel Separation vs Frequency
1000
40
30
20
10
0
–50 –40 –30 –20 –10 0
10 20 30
OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)
LT1169 • TPC19
140
TA = 25°C
VS = ±15V
N8 PACKAGE
800
120
CHANNEL SEPARATION (dB)
CHANGE IN OFFSET VOLTAGE (µV)
VS = ±15V
188 OP AMPS
600
400
200
LIMITED BY
THERMAL
INTERACTION
100
80
LIMITED BY
PIN-TO-PIN
CAPACITANCE
60
40
TA = 25°C
VS = ±15V
RL = 1k
VO = 10VP-P
20
0
0
0
100 125
LT1169 • TPC18
LT1169 • TPC17
Distribution of Offset Voltage Drift
with Temperature
PERCENT OF UNITS
8
GAIN-BANDWIDTH
AV = 10
25°C
LT1169 • TPC16
6
4
AV = 1
125°C
V – +0.4
–10 –8 –6 –4 –2 0 2 4 6 8 10
ISINK
ISOURCE
OUTPUT CURRENT (mA)
50
10
SLEW RATE
30
–55°C
0.6
12
5
SLEW RATE (V/µs)
– 1.4
0.8
VS = ±15V
TA = 25°C
RL ≥ 10k
VO = 100mVP-P
AV = +10, RF = 10k, CF = 20pF
40
–55°C
OVERSHOOT (%)
OUTPUT VOLTAGE SWING (V)
–1.2
6
125°C
25°C
–1.0
GAIN-BANDWIDTH PRODUCT (fO = 100kHz)(MHz)
V + – 0.8
1.4
Slew Rate and Gain-Bandwidth
Product vs Temperature
Capacitive Load Handling
5
2
3
4
1
TIME AFTER POWER ON (MIN)
6
LT1169 • TPC20
0
10
100
100k
10k
1k
FREQUENCY (Hz)
1M
10M
LT1169 • TPC21
LT1169
U W
TYPICAL PERFOR A CE CHARACTERISTICS
THD and Noise vs
Frequency for Inverting Gain
1
0.1
TOTAL HARMONIC DISTORTION + NOISE (%)
TOTAL HARMONIC DISTORTION + NOISE (%)
THD and Noise vs
Frequency for Noninverting Gain
ZL = 2k15pF
VO = 20VP-P
AV = 1, 10, 100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
AV = 100
0.01
AV = 10
AV = 1
0.001
NOISE FLOOR
0.0001
20
100
1k
FREQUENCY (Hz)
10k 20k
1
0.1
ZL = 2k15pF
VO = 20VP-P
AV = –1, –10, –100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
AV = –100
0.01
AV = –10
0.001
AV = –1
NOISE FLOOR
0.0001
20
100
1k
FREQUENCY (Hz)
10k 20k
LT1169 • TPC22
THD and Noise vs Output
Amplitude for Noninverting Gain
0.1
ZL = 2k15pF
fO = 1kHz
AV = –1, –10, –100
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
AV = –100
0.01
AV = –10
0.001
AV = –1
NOISE FLOOR
0.0001
0.3
1
10
OUTPUT SWING (VP-P)
30
CCIF IMD Test (Equal Amplitude
Tones at 13kHz, 14kHz)*
1
INTERMODULATION DISTORTION (AT 1kHz)(%)
1
TOTAL HARMONIC DISTORTION + NOISE (%)
TOTAL HARMONIC DISTORTION + NOISE (%)
THD and Noise vs Output
Amplitude for Inverting Gain
LT1169 • TPC23
ZL = 2k15pF
fO = 1kHz
AV = 1, 10, 100
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
0.1
AV = 100
0.01
AV = 10
AV = 1
0.001
NOISE FLOOR
0.0001
0.3
1
10
OUTPUT SWING (VP-P)
LT1169 • TPC24
30
LT1169 • TPC25
1
TA = 25°C
VS = ±15V
RL = 2k
0.1
AV = ±10
0.01
0.001
0.0001
0.02
0.1
1
OUTPUT SWING (VP-P)
10
30
LT1169 • TPC26
* SEE LT1115 DATA SHEET FOR DEFINITION OF
CCIF TESTING
U
W
U
UO
APPLICATI
S I FOR ATIO
LT1169 vs the Competition
With improved noise performance, the LT1169 dual in the
plastic DIP directly replaces such JFET op amps as the
OPA2111, OPA2604, OP215, and the AD822. The combination of low current and voltage noise of the LT1169
allows it to surpass most dual and single JFET op amps.
The LT1169 can replace many of the lowest noise bipolar
amps that are used in amplifying low level signals from
high impedance transducers. The best bipolar op amps
will eventually lose out to the LT1169 when transducer
impedance increases due to higher current noise.
The extremely high input impedance (1013Ω) assures that
the input bias current is almost constant over the entire
common mode range. Figure 1 shows how the LT1169
stands up to the competition. Unlike the competition, as the
input voltage is swept across the entire common mode
range the input bias current of the LT1169 hardly changes.
As a result the current noise does not degrade. This makes
the LT1169 the best choice in applications where an
amplifier has to buffer signals from a high impedance
transducer.
7
LT1169
UO
INPUT BIAS CURRENT (pA)
U
80
W
100
U
S I FOR ATIO
APPLICATI
CURRENT NOISE = √2qIB
60
40
OP215
20
LT1169
0
–20
AD822
–40
–60
–80
–100
–15
10
–10
0
5
–5
COMMON MODE RANGE (V)
15
LT1169 • F01
Figure 1. Comparison of LT1169, OP215, and AD822
Input Bias Current vs Common Mode Range
Amplifying Signals from High Impedance Transducers
The low voltage and current noise offered by the LT1169
makes it useful in a wide range of applications, especially
where high impedance, capacitive transducers are used
such as hydrophones, precision accelerometers, and
photodiodes. The total output noise in such a system is
the gain times the RMS sum of the op amp’s input referred
voltage noise, the thermal noise of the transducer, and the
op amp’s input bias current noise times the transducer
impedance. Figure 2 shows total input voltage noise
versus source resistance. In a low source resistance
(< 5k) application the op amp voltage noise will dominate
10k
LT1124*
INPUT NOISE VOLTAGE (nV/√
H
z)
CS
–
1k
LT1169*
RS
+
VO
RS
100
CS
LT1124†
LT1169
10
LT1169†
1
100
LT1124
RESISTOR NOISE ONLY
1k
10k 100k 1M 10M 100M
SOURCE RESISTANCE (Ω)
1G
LT1169 • F02
SOURCE RESISTANCE = 2RS = R
* PLUS RESISTOR
† PLUS RESISTOR 1000pF CAPACITOR
Vn = AV √Vn2(OP AMP) + 4kTR + 2qIBR2
Figure 2. Comparison of LT1169 and LT1124 Total Output
1kHz Voltage Noise vs Source Resistance
8
the total noise. This means the LT1169 is superior to most
dual JFET op amps. Only the lowest noise bipolar op amps
have the advantage at low source resistances. As the
source resistance increases from 5k to 50k, the LT1169
will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR)
begins to dominate the total noise. A further increase in
source resistance, above 50k, is where the op amp’s
current noise component (2qIBR2) will eventually dominate the total noise. At these high source resistances, the
LT1169 will out perform the lowest noise bipolar op amps
due to the inherently low current noise of FET input op
amps. Clearly, the LT1169 will extend the range of high
impedance transducers that can be used for high signalto-noise ratios. This makes the LT1169 the best choice for
high impedance, capacitive transducers.
Optimization Techniques for Charge Amplifiers
The high input impedance JFET front end makes the
LT1169 suitable in applications where very high charge
sensitivity is required. Figure 3 illustrates the LT1169 in its
inverting and noninverting modes of operation. A charge
amplifier is shown in the inverting mode example; the gain
depends on the principal of charge conservation at the
input of the LT1169. The charge across the transducer
capacitance CS is transferred to the feedback capacitor CF
resulting in a change in voltage dV, which is equal to dQ/CF.
The gain therefore is 1 + CF/CS. For unity-gain, the CF
should equal the transducer capacitance plus the input
capacitance of the LT1169 and RF should equal RS.
In the noninverting mode example, the transducer current
is converted to a change in voltage by the transducer
capacitance, CS. This voltage is then buffered by the
LT1169 with a gain of 1 + R1/R2. A DC path is provided by
RS, which is either the transducer impedance or an
external resistor. Since RS is usually several orders of
magnitude greater than the parallel combination of R1
and R2, RB is added to balance the DC offset caused by the
noninverting input bias current and RS. The input bias
currents, although small at room temperature, can create
significant errors over increasing temperature, especially
with transducer resistances of up to 1000MΩ or more.
The optimum value for RB is determined by equating the
thermal noise (4kTRS) to the current noise (2qIB) times
RS2. Solving for RS results in RB = RS = 2VT/IB. A parallel
LT1169
W
U
U
UO
APPLICATI
S I FOR ATIO
RF
R2
CB
CF
RB
–
CS
RS
+
OUTPUT
R1
CB = CF CS
RB = RF RS
TRANSDUCER
CB
RB
–
CS
dQ
dV
Q = CV;
=I=C
dt
dt
OUTPUT
+
RS
CB ≅ C S
RB = RS
RS > R1 OR R2
TRANSDUCER
LT1169 • F03
Figure 3. Inverting and Noninverting Gain Configurations
Input: ±5.2 Sine Wave
LT1169 Output
LT1169 • F04a
OPA2111 Output
LT1169 • F04b
LT1169 • F04c
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range (VS = ±5V)
capacitor CB, is used to cancel the phase shift caused by
the op amp input capacitance and RB.
Reduced Power Supply Operation
To take full advantage of a wide input common-mode
range, the LT1169 was designed to eliminate phase reversal. Referring to the photographs in Figure 4, the LT1169
is shown operating in the follower mode (AV = 1) at ±5V
supplies with the input swinging ±5.2V. The output of the
LT1169 clips cleanly and recovers with no phase reversal,
unlike the competition as shown by the last photograph.
This has the benefit of preventing lockup in servo systems
and minimizing distortion components. The effect of input
and output overdrive on one amplifier has no effect on the
other, as each amplifier is biased independently.
amps. Two or three op amp instrumentation amplifiers,
tracking voltage references and low drift active filters
are some of the circuits requiring matching between two
op amps.
Advantages of Matched Dual Op Amps
The well-known triple op amp configuration in Figure 5
illustrates these concepts. Output offset is a function of the
difference between the two halves of the LT1169. This error
cancellation principle holds for a considerable
number of input referred parameters in addition to
offset voltage and bias current. Input bias current will
be the average of the two noninverting input currents (IB+).
The difference between these two currents (∆I B+)
is the offset current of the instrumentation amplifier. Common-mode and power supply rejections will be
dependent only on the match between the two amplifiers
(assuming perfect resistor matching).
In many applications the performance of a system
depends on the matching between two operational amplifiers rather than the individual characteristics of the two op
The concepts of common mode and power supply
rejection ratio match (∆CMRR and ∆PSRR) are best demonstrated with a numerical example:
9
LT1169
W
U
U
UO
S I FOR ATIO
APPLICATI
Input offset current = 3pA
Input resistance = 1013Ω
Input noise = 3.4µVP-P
15V
IN–
3
+
8
1/2
LT1169
IC1
2
–
4
R6
10k
R4
1k
1
C1
30pF
R1
1k
High Speed Operation
–15V
R2
200Ω
6
IN+
–
1/2
LT1169
5 + IC1
7
R3
1k
R5
1k
2
–
1/2
LT1169
3 + IC2
1
OUTPUT
CL
R7
10k
GAIN = 100
BANDWIDTH = 330kHz
INPUT REFERRED NOISE = 8.7nV/√
Hz AT 1kHz
WIDEBAND NOISE DC TO 330kHz = 5.3µVRMS
CL ≤ 0.01µF
LT1169 • F05
Figure 5. Three Op Amp Instrumentation Amplifier
Assume CMRRA = 50µV/V or 86dB,
and CMRRB = 39µV/V or 88dB,
then ∆CMRR = 11µV/V or 99dB;
if CMRRB = – 39µV/V which is still 88dB,
then ∆CMRR = 89µV/V or 81dB
The low noise performance of the LT1169 was achieved by
enlarging the input JFET differential pair to maximize the
first stage gain. Enlarging the JFET geometry also increases
the parasitic gate capacitance, which if left unchecked, can
result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be
created with RF, the source resistance and capacitance
(RS,CS), and the amplifier input capacitance (CIN = 1.5pF).
In closed-loop gain configurations with RS and RF in the
MΩ range (Figure 6), this pole can create excess phase shift
and even oscillation. A small capacitor (CF) in parallel with
RF eliminates this problem. With RS(CS + CIN) = RFCF, the
effect of the feedback pole is completely removed.
CF
RF
–
By specifying and guaranteeing all of these matching
parameters, the LT1169 can significantly improve the
performance of matching-dependent circuits.
RS
CS
+
CIN
OUTPUT
Typical performance of the instrumentation amplifier:
LT1169 • F06
Figure 6
Input offset voltage = 0.8mV
Input bias current = 4pA
U
TYPICAL APPLICATIONS N
Unity-Gain Buffer with Extended Load Capacitance
Drive Capability
Light Balance Detection Circuit
R2
1k
R1
1M
C1
–
I1
PD1
R1
33Ω
VOUT
1/2 LT1169
VIN
+
C1
3pF TO 5pF
CL
–
I2
1/2 LT1169
PD2
+
VOUT
LT1169 • TA03
C1 = CL ≤ 0.1µF
OUTPUT SHORT CIRCUIT CURRENT (∼ 30mA) WILL LIMIT THE RATE
AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS
dV
(I = C dt )
10
LT1169 • TA04
VOUT = 1M × (I1 – I2)
PD1,PD2 = HAMAMATSU S1336-5BK
WHEN EQUAL LIGHT ENTERS PHOTODIODES, VOUT < 3mV.
LT1169
U
TYPICAL APPLICATIONS N
Low Noise Hydrophone Amplifier with DC Servo
Accelerometer Amplifier with DC Servo
C1
1250pF
R1*
100M
R3
3.9k
5V TO 15V
2
–
3
+LT1169
1
1/2
R2 C1*
200Ω
R1
100M
8
C2
2µF
R3
2k
OUTPUT
C2
0.47µF
4
R2
18k
–5V TO –15V
–
R6
100k
7
1/2
LT1169
+
R7
1M
6
5
R4
1M
7
R5
1M
5V TO 15V
ACCELEROMETER
B & K MODEL 4381
OR EQUIVALENT
(800) 442-1030
2
LT1169 • TA05
5
R5
20M
C3
2µF
8
1
1/2 LT1169
3
DC OUTPUT ≤ 2.5mV FOR TA < 70°C
OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20)
C1 ≈ CT ≈ 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL
–
R4
20M
1/2 LT1169
+
HYDROPHONE
R8
100M
–
CT
6
OUTPUT
+
R4C2 = R5C3 > R1 (1 + R2/R3) C1
OUTPUT = 0.8mV/pC* = 8.0mV/g**
4
DC OUTPUT ≤ 1.9mV
–5V TO –15V OUTPUT NOISE = 8nV/√
Hz AT 1kHz
*PICOCOULOMBS
**g = EARTH’S GRAVITATIONAL CONSTANT
LT1169 • TA07
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.189 – 0.197*
(4.801 – 5.004)
0.004 – 0.010
(0.101 – 0.254)
8
7
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 0996
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2
3
4
11
LT1169
U
TYPICAL APPLICATIONS N
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)
R2
237k
R1
237k
15V
R3
249k
2
VIN
–
8
C1
33nF
1/2 LT1169
C2
100nF
3
1
R5
154k
R4
154k
+
R6
249k
6
C4
330nF
4
–
C3
10nF
1/2 LT1169
5
+
7
VOUT
–15V
LT1169 • TA08
TYPICAL OFFSET ≈ 0.8mV
1% TOLERANCES
FOR VIN = 10VP-P, VOUT = –121dB AT f > 330Hz
= – 6dB AT f = 16.3Hz
LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
Paralleling Amplifiers to Reduce Voltage Noise
3
2
+
A1
1/2 LT1169
1
1.6k
–
91Ω
3k
10k
3
2
15V
+
A2
1/2 LT1169
1
1.6k
6
–
–
8
1/2 LT1169
91Ω
5
3k
+
7
OUTPUT
4
15V
–15V
5
6
+
8
An
1/2 LT1169
–
4
–15V
91Ω
3k
7
1.6k
1. ASSUME VOLTAGE NOISE OF LT1169 AND 51 Ω SOURCE RESISTOR = 6.1nV/√
H
z
2. GAIN WITH n LT1169s IN PARALLEL = n × 200
3. OUTPUT NOISE = √
n × 200 × 6.1nV/√
H z
OUTPUT NOISE 6.1
4. INPUT REFERRED NOISE =
=
nV/√
Hz
n × 200
√
n
5. NOISE CURRENT AT INPUT INCREASES √
n
TIMES
2.1µV
6. IF n = 5, GAIN = 1000, BANDWIDTH = 110kHz, RMS NOISE, DC TO 1MHz =
= 1.0µV
√5
LT1169 • TA06
RELATED PARTS
PART NUMBER
LT1113
LT1462
LT1464
12
DESCRIPTION
Lowest Noise Dual JFET Op Amp
Micro Power Dual JFET Op Amp
Low Power Dual JFET Op Amp
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417● (408) 432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
COMMENTS
4.5nV/√Hz Voltage Noise
3.0pA IB, 45µA ISUPPLY
3.0pA (Max) Input Bias Current
1169fa LT/TP 0198 REV A 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1994
工商网监
湘ICP备2023018690号
