LT1575/LT1577
Ultrafast Transient Response,
Low Dropout Regulators
Adjustable and Fixed
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DESCRIPTION
FEATURES
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UltraFastTM Transient Response Eliminates
Tantalum and Electrolytic Output Capacitors
FET RDS(ON) Defines Dropout Voltage
1% Reference/Output Voltage Tolerance Over
Temperature
Typical Load Regulation: 1mV
High Side Sense Current Limit
Multifunction Shutdown Pin with Latchoff
The LT®1575/LT1577 are single/dual controller ICs that
drive low cost external N-channel MOSFETs as source
followers to produce ultrafast transient response, low
dropout voltage regulators.
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APPLICATIONS
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Pentium® Processor Supplies
PowerPCTM Supplies
5V to 3.XXV or 3.3V to 2.XXV Microprocessor Supplies
GTL Termination
Low Voltage Logic Supplies
LT1575CN8/LT1575CS8
LT1575CN8-1.5/LT1575CS8-1.5
LT1575CN8-2.8/LT1575CS8-2.8
LT1575CN8-3.3/LT1575CS8-3.3
LT1575CN8-3.5/LT1575CS8-3.5
LT1575CN8-5/LT1575CS8-5
LT1577CS-ADJ/ADJ
LT1577CS-3.3/ADJ
LT1577CS-3.3/2.8
Adjustable
1.5V Fixed
2.8V Fixed
3.3V Fixed
3.5V Fixed
5V Fixed
Adjustable, Adjustable
3.3V Fixed, Adjustable
3.3V Fixed, 2.8V Fixed
The LT1575/LT1577 achieve unprecedented transientload performance by eliminating expensive tantalum or
bulk electrolytic output capacitors in the most demanding
modern microprocessor applications. Precision-trimmed
adjustable and fixed output voltage versions accommodate any required microprocessor power supply voltage.
Selection of the N-channel MOSFET RDS(ON) allows very
low dropout voltages to be achieved.
Unique protection features include a high side current
limit amplifier that activates a fault protection timer
circuit. A multifunction Shutdown pin provides either
current limit time-out with latchoff, overvoltage protection, thermal shutdown or a combination of these functions. The LT1575 is available in 8-pin SO or PDIP and the
LT1577 is available in 16-pin narrow body SO.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Consult factory for additional output voltage combinations available
in the LT1577.
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TYPICAL APPLICATION
Transient Response for
0.2A to 5A Output Load Step
Ultrafast Transient Response 5V to 3.3V Low Dropout Regulator
(For Schematic Including Current Limit, See Typical Applications)
LT1575-3.3
12V
1
* FOR T < 45°C:
C6 = 24 × 1µF Y5V
CERAMIC SURFACE
MOUNT CAPACITORS.
FOR T > 45°C:
C6 = 24 × 1µF X7R
CERAMIC SURFACE
MOUNT CAPACITORS.
PLACE C6 IN THE
MICROPROCESSOR
SOCKET CAVITY
2
SHDN
C2
VIN
1µF 3
GND
4
OUT
IPOS
INEG
GATE
COMP
C3
10pF
8
+
7
6
5
R2
5Ω
R1
7.5k
C4
1000pF
Q1
IRFZ24
5V
50mV/DIV
C5
220µF
VOUT
3.3V
5A
2A/DIV
C6*
24µF
GND
1575/77 TA01
100µs/DIV
1575/77 TA02
1
LT1575/LT1577
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AXI U
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ABSOLUTE
RATI GS
(Note 1)
VIN, IPOS, INEG ...................................................... 22V
SHDN ....................................................................... VIN
Operating Ambient Temperature Range ..... 0°C to 70°C
Junction Temperature (Note 2) ................ 0°C to 100°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
SHDN 1
8
IPOS
SHDN 1
8
IPOS
VIN 2
7
INEG
VIN 2
7
INEG
GND 3
6
GATE
GND 3
6
GATE
5
COMP
OUT 4
5
COMP
FB 4
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
TJMAX = 100°C, θJA = 100°C/ W (N8)
TJMAX = 100°C, θJA = 130°C/ W (S8)
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
ORDER PART NUMBER
LT1575CN8
LT1575CS8
LT1575CN8-1.5
LT1575CS8-1.5
LT1575CN8-2.8
LT1575CS8-2.8
LT1575CN8-3.3
S8 PART MARKING
157515
157528
157533
LT1575CS8-3.3
LT1575CN8-3.5
LT1575CS8-3.5
LT1575CN8-5
LT1575CS8-5
15 INEG1
14 GATE1
13 COMP1
SHDN2 5
12 IPOS2
VIN2 6
11 INEG2
GND2 7
10 GATE2
9
TJMAX = 100°C, θJA = 100°C/ W
ORDER PART NUMBER
157535
15755
LT1577CS-ADJ/ADJ
TOP VIEW
SHDN1 1
16 IPOS1
SHDN1 1
16 IPOS1
VIN1 2
15 INEG1
VIN1 2
15 INEG1
GND1 3
14 GATE1
GND1 3
14 GATE1
OUT-3.3 4
13 COMP1
OUT-3.3 4
13 COMP1
SHDN2 5
12 IPOS2
SHDN2 5
12 IPOS2
VIN2 6
11 INEG2
VIN2 6
11 INEG2
GND2 7
10 GATE2
GND2 7
10 GATE2
FB 8
9
COMP2
OUT-2.8 8
9
COMP2
S PACKAGE
16-LEAD PLASTIC NARROW SO
S PACKAGE
16-LEAD PLASTIC NARROW SO
TJMAX = 100°C, θJA = 100°C/ W
TJMAX = 100°C, θJA = 100°C/ W
ORDER PART NUMBER
ORDER PART NUMBER
LT1577CS-3.3/ADJ
LT1577CS-3.3/2.8
Consult factory for Industrial and Military grade parts.
COMP2
S PACKAGE
16-LEAD PLASTIC NARROW SO
TOP VIEW
2
VIN1 2
GND1 3
FB2 8
S8 PART MARKING
1575
16 IPOS1
FB1 4
TJMAX = 100°C, θJA = 100°C/ W (N8)
TJMAX = 100°C, θJA = 130°C/ W (S8)
ORDER PART NUMBER
SHDN1 1
LT1575/LT1577
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 12V, GATE = 6V, IPOS = INEG = 5V, SHDN = 0.75V unless otherwise noted.
SYMBOL
PARAMETER
IQ
Supply Current
VFB
LT1575 Reference Voltage
VOUT
CONDITIONS
MIN
TYP
MAX
●
5
12
19
mA
●
– 0.6
– 1.0
1.210
1.210
0.6
1.0
%
%
●
– 0.6
– 1.0
1.500
1.500
0.6
1.0
%
%
●
– 0.6
– 1.0
2.800
2.800
0.6
1.0
%
%
●
– 0.6
– 1.0
3.300
3.300
0.6
1.0
%
%
●
– 0.6
– 1.0
3.500
3.500
0.6
1.0
%
%
●
– 0.6
– 1.0
5.000
5.000
0.6
1.0
%
%
LT1575-1.5 Output Voltage
LT1575-2.8 Output Voltage
LT1575-3.3 Output Voltage
LT1575-3.5 Output Voltage
LT1575-5 Output Voltage
UNITS
Line Regulation
10V ≤ VIN ≤ 20V
●
0.01
0.03
%/V
IFB
FB Input Bias Current
FB = VFB
●
– 0.6
– 4.0
µA
IOUT
OUT Divider Current
OUT = VOUT
●
0.5
1.0
1.5
mA
AVOL
LT1575 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
69
84
dB
LT1575-1.5 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
67
82
dB
LT1575-2.8 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
60
76
dB
LT1575-3.3 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
60
75
dB
LT1575-3.5 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
60
74
dB
56
LT1575-5 Large-Signal Voltage Gain
VGATE = 3V to 10V
●
VOL
GATE Output Swing Low (Note 3)
IGATE = 0mA
●
VOH
GATE Output Swing High
IGATE = 0mA
●
VIN – 1.6
VIN – 1
IPOS + INEG Supply Current
3V ≤ IPOS ≤ 20V
●
0.3
0.625
1.0
mA
●
42
37
50
50
58
63
mV
mV
– 0.20
– 0.50
%/V
Current Limit Threshold Voltage
71
2.5
dB
3.0
V
V
Current Limit Threshold Voltage
Line Regulation
3V ≤ IPOS ≤ 20V
●
SHDN Sink Current
Current Flows Into Pin
●
2.5
5.0
8.0
µA
SHDN Source Current
Current Flows Out of Pin
●
–8
– 15
– 23
µA
SHDN Low Clamp Voltage
●
0.1
0.25
V
SHDN High Clamp Voltage
●
1.50
1.85
2.20
V
SHDN Threshold Voltage
●
1.18
1.21
1.240
V
SHDN Threshold Hysteresis
●
50
100
150
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LT1575CN8: TJ = TA + (PD • 100°CW)
LT1575CS8: TJ = TA + (PD • 130°CW)
LT1577CS: TJ = TA + (PD • 100°CW)
mV
Because the LT1577 consists of two regulators in the package, the total
LT1577 power dissipation must be used for its junction temperature
calculation. The total LT1577 PD = PD (Regulator 1) + PD (Regulator 2).
Note 3: The VGS(th) of the external MOSFET must be greater than
3V – VOUT.
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LT1575/LT1577
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TYPICAL PERFORMANCE CHARACTERISTICS
Adjustable LT1575 VREF
vs Temperature
1.210
1.208
1.206
1.204
1.485
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
2.828
2.824
2.800
2.816
2.812
2.808
2.804
2.800
2.796
2.792
2.788
2.784
2.780
2.776
2.772
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G04
VIN = 20V
VIN = 12V
VIN = 8V
1575/77 G03
LT1575-3.3 VOUT vs Temperature
3.333
3.327
3.321
3.315
3.309
3.303
3.297
3.291
3.285
3.279
3.273
3.267
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G06
OUT Divider Current
vs Temperature
LT1575-5 VOUT vs Temperature
5.050
1.5
5.040
1.4
5.030
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.0
1575/77 G05
LT1575-3.5 VOUT vs Temperature
4
1.5
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
REFERENCE VOLTAGE (V)
1.488
1575/77 G07
2.0
LT1575-2.8 VOUT vs Temperature
1.491
3.535
3.530
3.525
3.520
3.515
3.510
3.505
3.500
3.495
3.490
3.485
3.480
3.475
3.470
3.465
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
2.5
1575/77 G02
1.509
1.494
3.0
0.5
1.198
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.512
1.497
FB INPUT BIAS CURRENT (µA)
1.214
1.212
LT1575-1.5 VOUT vs Temperature
1.500
3.5
1.218
1.216
1.202
1.200
1.515
1.503
4.0
1.222
1.220
1575/77 G01
1.506
FB Input Bias Current
vs Temperature
OUT DIVIDER CURRENT (mA)
19
18
17
16
15
VIN = 12V
14
VIN = 20V
13
12
VIN = 8V
11
10
9
8
7
6
5
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
QUIESCENT CURRENT (mA)
Quiescent Current vs Temperature
5.020
5.010
5.000
4.990
4.980
4.970
1.3
1.2
1.1
1.0
0.9
0.8
0.7
4.960
0.6
4.950
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G08
1575/77 G09
LT1575/LT1577
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TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Large-Signal
Voltage Gain vs Temperature
VREF/VOUT Line Regulation
vs Temperature
0.030
0.020
0.015
0.010
0.005
115
ERROR AMPLIFIER GAIN AND PHASE
LARGE-SIGNAL VOLTAGE GAIN (dB)
LINE REGULATION (%/V)
0.025
110
105
100
95
90
85
80
75
1575/77 G10
GAIN
50
0
1k
NO LOAD
2.25
2.00
1.75
1.50
100k
1M
FREQUENCY (Hz)
10M
3.0
1000
2.5
900
1.25
1.00
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
2.0
1.5
100M
1575/77 G12
IPOS + INEG SUPPLY CURRENT (µA)
GATE OUTPUT SWING HIGH (V)
2.50
10k
IPOS + INEG Supply Current
vs Temperature
ILOAD = 50mA
ILOAD = 50mA
1.0
NO LOAD
0.5
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
800
700
IPOS = INEG = 5V
IPOS = INEG = 12V
IPOS = INEG = 20V
600
IPOS = INEG = 3V
500
400
300
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G14
1575/77 G13
1575/77 G15
Current Limit Threshold Voltage
Line Regulation vs Temperature
Current Limit Threshold Voltage
vs Temperature
0
65
CURRENT LIMIT THRESHOLD
VOLTAGE LINE REGULATION (%/V)
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
100
Gate Output Swing High
vs Temperature
3.00
60
55
PHASE
1575/77 G11
Gate Output Swing Low
vs Temperature
2.75
150
70
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
GATE OUTPUT SWING LOW (V)
Gain and Phase vs Frequency
200
120
IPOS = 5V
IPOS = 3V
50
IPOS = 20V
45
40
35
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G16
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G17
5
LT1575/LT1577
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TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Low Clamp Voltage
vs Temperature
SHDN Source Current
vs Temperature
–10
7.0
– 11
6.5
6.0
5.5
5.0
4.5
4.0
3.5
0.25
SHDN LOW CLAMP VOLTAGE (V)
7.5
SHDN SOURCE CURRENT (µA)
SHDN SINK CURRENT (µA)
SHDN Sink Current
vs Temperature
– 12
– 13
– 14
– 15
– 16
– 17
– 18
3.0
– 19
2.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
– 20
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G18
0.20
0.15
0.10
0.05
0
– 75 – 50 – 25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G19
SHDN High Clamp Voltage
vs Temperature
1575/77 G20
SHDN Hysteresis vs Temperature
2.1
150
SHDN HYSTERESIS (mV)
SHDN HIGH CLAMP VOLTAGE (V)
140
2.0
1.9
1.8
1.7
130
120
110
100
90
80
70
1.6
60
1.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G21
6
50
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G22
LT1575/LT1577
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PIN FUNCTIONS
SHDN (Pin 1): This is a multifunction shutdown pin that
provides GATE drive latchoff capability. A 15µA current
source, that turns on when current limit is activated,
charges a capacitor placed in series with SHDN to GND
and performs a current limit time-out function. The pin is
also the input to a comparator referenced to VREF (1.21V).
When the pin pulls above VREF, the comparator latches the
gate drive to the external MOSFET off. The comparator
typically has 100mV of hysteresis and the Shutdown pin
can be pulled low to reset the latchoff function. This pin
provides overvoltage protection or thermal shutdown
protection when driven from various resistor divider
schemes.
VIN (Pin 2): This is the input supply for the IC that powers
the majority of internal circuitry and provides sufficient
gate drive compliance for the external N-channel MOSFET.
The typical supply voltage is 12V with 12.5mA of quiescent
current. The maximum operating VIN is 20V and the
minimum operating VIN is set by VOUT + VGS of the
MOSFET at max. IOUT + 1.6V (worst-case VIN to GATE
output swing).
GND (Pin 3): Analog Ground. This pin is also the negative
sense terminal for the internal 1.21V reference. Connect
external feedback divider networks that terminate to GND
and frequency compensation components that terminate
to GND directly to this pin for best regulation and performance.
FB (Pin 4): This is the inverting input of the error amplifier
for the adjustable voltage LT1575. The noninverting input
is tied to the internal 1.21V reference. Input bias current
for this pin is typically 0.6µA flowing out of the pin. This pin
is normally tied to a resistor divider network to set output
voltage. Tie the top of the external resistor divider directly
to the output voltage for best regulation performance.
OUT (Pin 4): This is the inverting input of the error
amplifier for the fixed voltage LT1575. The fixed voltage
parts contain a precision resistor divider network to set
output voltage. The typical resistor divider current is 1mA
into the pin. Tie this pin directly to the output voltage for
best regulation performance.
sation. The transconductance of the error amplifier is 15
millimhos and open-loop voltage gain is typically 84dB.
Frequency compensation is generally performed with a
series RC network to ground.
GATE (Pin 6): This is the output of the error amplifier that
drives N-channel MOSFETs with up to 5000pF of “effective” gate capacitance. The typical open-loop output
impedance is 2Ω. When using low input capacitance
MOSFETs (< 1500pF), a small gate resistor of 2Ω to 10Ω
dampens high frequency ringing created by an LC resonance that is created by the MOSFET gate’s lead inductance and input capacitance. The GATE pin delivers up to
50mA for a few hundred nanoseconds when slewing the
gate of the N-channel MOSFET in response to output load
current transients.
INEG (Pin 7): This is the negative sense terminal of the
current limit amplifier. A small sense resistor is connected
in series with the drain of the external MOSFET and is
connected between the IPOS and INEG pins. A 50mV
threshold voltage in conjunction with the sense resistor
value sets the current limit level. The current sense resistor can be a low value shunt or can be made from a piece
of PC board trace. If the current limit amplifier is not used,
tie the INEG pin to IPOS to defeat current limit. An
alternative is to ground the INEG pin. This action disables
the current limit amplifier and additional internal circuitry
activates the timer circuit on the SHDN pin if the GATE pin
swings to the VIN rail. This option provides the user with
a “sense-less” current limit function.
IPOS (Pin 8): This is the positive sense terminal of the
current limit amplifier. Tie this pin directly to the main
input voltage from which the output voltage is regulated.
The typical input voltage is a 5V logic supply. This pin is
also the input to a comparator on the fixed voltage versions that monitors the input/output differential voltage of
the external MOSFET. If this differential voltage is less than
0.5V, then the SHDN timer is not allowed to start even if the
GATE is at the VIN rail. This allows the regulator to start up
normally as the input voltage is ramping up, even with very
slow ramp rates.
COMP (Pin 5): This is the high impedance gain node of the
error amplifier and is used for external frequency compen-
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LT1575/LT1577
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BLOCK DIAGRAM
LT1575 Adjustable Voltage
VTH1
50mV
+
ILIM AMP
OR1
SW1
NORMALLY
OPEN
SHDN
IPOS
+
–
I1
15µA
INEG
–
D1
+
COMP1
I2
5µA
R2
5k
Q6
–
D2
–
COMP2
100mV
HYSTERESIS
+
OR2
SW2
NORMALLY
CLOSED
+
START-UP
VREF
1.21V
COMP3
VTH2
1V
+
–
–
VIN
GND
+
GATE
ERROR AMP
FB
–
COMP
I3
100µA
Q4
Q1
R1
50k
8
Q2
Q5
Q3
1575/77 BD1
LT1575/LT1577
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BLOCK DIAGRAM
LT1575 Fixed Voltage
IPOS
+
ILIM AMP
OR1
SW1
NORMALLY
OPEN
–
D1
+
–
I1
15µA
VTH1
50mV
INEG
SHDN
–
COMP4
COMP1
R2
5k
Q6
+
–
+
–
D2
+
VTH3
500mV
100mV
HYSTERESIS
I2
5µA
–
COMP2
OR2
SW2
NORMALLY
CLOSED
+
+
START-UP
VREF
1.21V
COMP3
Q7
GND
VTH2
1V
+
–
–
VIN
+
OUT
GATE
ERROR AMP
–
R3*
COMP
I3
100µA
R4*
*VOUT = (1 + R3/R4)VREF
Q4
Q1
R1
50k
Q2
Q5
Q3
1575/77 BD2
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LT1575/LT1577
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APPLICATIONS INFORMATION
Introduction
The current generation of microprocessors place stringent demands on the power supply that powers the
processor core. These microprocessors cycle load current from near zero to amps in tens of nanoseconds.
Output voltage tolerances as low as ±100mV include
transient response as part of the specification. Some
microprocessors require only a single output voltage from
which the core and I/O circuitry operate. Other higher
performance processors require a separate power supply
voltage for the processor core and the I/O circuitry. These
requirements mandate the need for very accurate, very
high speed regulator circuits.
Previously employed solutions included monolithic
3-terminal linear regulators, PNP transistors driven by low
cost control circuits and simple buck converter switching
regulators. The 3-terminal regulator achieves a high level
of integration, the PNP driven regulator achieves very low
dropout performance and the switching regulator achieves
high electrical efficiency.
However, the common trait manifested by these solutions
is that transient response is measured in many microseconds. This fact translates to a regulator output decoupling
capacitor scheme that requires several hundred microfarads of very low ESR bulk capacitance using multiple
capacitors surrounding the CPU. This required bulk capacitance is in addition to the ceramic decoupling capacitor network that handles the transient load response
during the first few hundred nanoseconds as well as
providing microprocessor clock frequency noise immunity. The combined cost of all capacitors is a significant
percentage of the total power supply cost.
The LT1575/LT1577 family of single/dual controller ICs
are unique, easy to use devices that drive external
N-channel MOSFETs as source followers and permit a user
to realize an extremely low dropout, ultrafast transient
response regulator. These circuits achieve superior regulator bandwidth and transient load performance by completely eliminating expensive tantalum or bulk electrolytic
capacitors in the most modern and demanding microprocessor applications. For example, a 200MHz Pentium
processor can operate with only the recommended 24 1µF
ceramic capacitors. Users benefit directly by saving sig-
10
nificant cost as all additional bulk capacitance is removed.
The additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent.
Precision-trimmed adjustable and fixed output voltage
versions accommodate any required microprocessor
power supply voltage. Proper selection of the N-channel
MOSFET RDS(ON) allows user-settable dropout voltage
performance. The only output capacitors required are the
high frequency ceramic decoupling capacitors. This regulator design provides ample bandwidth and responds to
transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
The ceramic capacitor network generally consists of 10 to
24 1uF capacitors for individual microprocessor requirements. The LT1575/LT1577 family also incorporates current limiting for no additional system cost, provides on/off
control and overvoltage protection or thermal shutdown
with simple external components.
Therefore, the unique design of these new ICs combines
the benefits of low dropout voltage, high functional integration, precision performance and ultrafast transient
response, as well as providing significant cost savings on
the output capacitance needed in fast load transient applications. As lower input/output differential voltage applications become increasingly prevalent, an LT1575-based
solution achieves comparable efficiency performance with
a switching regulator at an appreciable cost savings.
The new LT1575/LT1577 family of low dropout regulator
controller ICs step to the next level of performance required by system designers for the latest generation
motherboards and microprocessors. The simple versatility and benefits derived from these circuits allow the
power supply needs of today’s high performance microprocessors to be met with ease.
Block Diagram Operation
The primary block diagram elements consist of a simple
feedback control loop and the secondary block diagram
elements consist of multiple protection functions. Examining the block diagram for the LT1575, a start-up circuit
provides controlled start-up for the IC, including the
precision-trimmed bandgap reference, and establishes all
internal current and voltage biasing.
LT1575/LT1577
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APPLICATIONS INFORMATION
Reference voltage accuracy for the adjustable version and
output voltage accuracy for the fixed voltage versions are
specified as ±0.6% at room temperature and as ±1% over
the full operating temperature range. This places the
LT1575/LT1577 family among a select group of regulators
with a very tightly specified output voltage tolerance. The
accurate 1.21V reference is tied to the noninverting input
of the main error amplifier in the feedback control loop.
The error amplifier consists of a single high gain gm stage
with a transconductance equal to 15 millimhos. The
inverting terminal is brought out as the FB pin in the
adjustable voltage version and as the OUT pin in fixed
voltage versions. The gm stage provides differential-tosingle ended conversion at the COMP pin. The output
impedance of the gm stage is about 1MΩ and thus, 84dB
of typical DC error amplifier open-loop gain is realized
along with a typical 75MHz uncompensated unity-gain
crossover frequency. Note that the overall feedback
loop’s DC gain decreases from the gain provided by the
error amplifier by the attenuation factor in the resistor
divider network which sets the DC output voltage. These
attenuation factors are already built into the Open-Loop
Voltage Gain specifications for the LT1575 fixed voltage
versions in the Electrical Characteristics table to simplify
user calculations. External access to the high impedance
gain node of the error amplifier permits typical loop
compensation to be accomplished with a series RC
network to ground.
A high speed, high current output stage buffers the COMP
node and drives up to 5000pF of “effective” MOSFET gate
capacitance with almost no change in load transient performance. The output stage delivers up to 50mA peak
when slewing the MOSFET gate in response to load
current transients. The typical output impedance of the
GATE pin is typically 2Ω. This pushes the pole due to the
error amplifier output impedance and the MOSFET input
capacitance well beyond the loop crossover frequency. If
the capacitance of the MOSFET used is less than 1500pF,
it may be necessary to add a small value series gate
resistor of 2Ω to 10Ω. This gate resistor helps damp the
LC resonance created by the MOSFET gate’s lead inductance and input capacitance. In addition, the pole formed
by this resistance and the MOSFET input capacitance can
be fine tuned.
Because the MOSFET pass transistor is connected as a
source follower, the power path gain is much more predictable than designs that employ a discrete PNP transistor as the pass device. This is due to the significant
production variations encountered with PNP Beta.
MOSFETs are also very high speed devices which enhance
the ability to produce a stable wide bandwidth control
loop. An additional advantage of the follower topology is
inherently good line rejection. Input supply disturbances
do not propagate through to the output. The feedback loop
for a regulator circuit is completed by providing an error
signal to the FB pin in the adjustable voltage version and
the OUT pin in the fixed voltage version. In both cases, a
resistor divider network senses the output voltage and
sets the regulated DC bias point. In general, the LT1575
regulator feedback loop permits a loop crossover frequency on the order of 1MHz while maintaining good
phase and gain margins. This unity-gain frequency is a
factor of 20 to 30 times the bandwidth of currently
implemented regulator solutions for microprocessor power
supplies. This significant performance benefit is what
permits the elimination of all bulk output capacitance.
Several other unique features are included in the design
that increase its functionality and robustness. These functions comprise the remainder of the block diagram.
A high side sense, current limit amplifier provides active
current limiting for the regulator. The current limit amplifier uses an external low value shunt resistor connected in
series with the external MOSFET’s drain. This resistor can
be a discrete shunt resistor or can be manufactured from
a Kelvin-sensed section of “free” PC board trace. All load
current flows through the MOSFET drain and thus, through
the sense resistor. The advantage of using high side
current sensing in this topology is that the MOSFET’s gain
and the main feedback loop’s gain remain unaffected. The
sense resistor develops a voltage equal to IOUT(RSENSE).
The current limit amplifier’s 50mV threshold voltage is a
good compromise between power dissipation in the sense
resistor, dropout voltage impact and noise immunity.
Current limit activates when the sense resistor voltage
equals the 50mV threshold.
Two events occur when current limit activates: the first is
that the current limit amplifier drives Q2 in the block
11
LT1575/LT1577
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APPLICATIONS INFORMATION
diagram and clamps the positive swing of the COMP node
in the main error amplifier to a voltage that provides an
output load current of 50mV/RSENSE. This action continues as long as the output current overload persists. The
second event is that a timer circuit activates at the SHDN
pin. This pin is normally held low by a 5µA active pull-down
that limits to ≈ 100mV above ground. When current limit
activates, the 5µA pull-down turns off and a 15µA pull-up
current source turns on. Placing a capacitor in series with
the SHDN pin to ground generates a programmable time
ramp voltage.
provide thermal shutdown with the use of a thermistor in
the divider network. Diode-ORing these functions together is simple to accomplish and provides multiple
functionality for one pin.
The SHDN pin is also the positive input of COMP1. The
negative input is tied to the internal 1.21V reference. When
the SHDN pin ramps above VREF, the comparator drives
Q4 and Q5. This action pulls the COMP and GATE pins low
and latches the external MOSFET drive off. This condition
reduces the MOSFET power dissipation to zero. The time
period until the latched-off condition occurs is typically
equal to CSHUT(1.11V)/15µA. For example, a 1µF capacitor
on the SHDN pin yields a 74ms ramp time. In short, this
unique circuit block performs a current limit time-out
function that latches off the regulator drive after a predefined time period. The time-out period selected is a
function of system requirements including start-up and
safe operating area. The SHDN pin is internally clamped to
typically 1.85V by Q6 and R2. The comparator tied to the
SHDN pin has 100mV of typical hysteresis to provide
noise immunity. The hysteresis is especially useful when
using the SHDN pin for thermal shutdown.
However, a second available choice permits a user to
provide short-circuit protection with no external sensing.
This technique is activated by grounding the INEG pin.
This action disables the current limit amplifier because
Schottky diode D1 clamps the amplifier’s output and
prevents Q2 from pulling down the COMP node. In addition, Schottky diode D2 turns off pull-down transistor Q1.
Q1 is normally on and holds internal comparator COMP3’s
output low. This comparator circuit, now enabled, monitors the GATE pin and detects saturation at the positive rail.
When a saturated condition is detected, COMP3 activates
the shutdown timer. Once the time-out period occurs, the
output is shut down and latched off. The operation of
resetting the latch remains the same. Note that this technique does not limit the FET current during the time-out
period. The output current is only limited by the input
power supply and the input/output impedance. Setting the
timer to a short period in this mode of operation keeps the
external MOSFET within its SOA (safe operating area)
boundary and keeps the MOSFET’s temperature rise under
control.
Restoring normal operation after the load current fault is
cleared is accomplished in two ways. One option is to
recycle the nominal 12V LT1575 supply voltage as long as
an external bleed path for the Shutdown pin capacitor is
provided. The second option is to provide an active reset
circuit that pulls the SHDN pin below VREF. Pulling the
SHDN pin below VREF turns off the 15µA pull-up current
source and reactivates the 5µA pull-down. If the SHDN pin
is held below VREF during a fault condition, the regulator
continues to operate in current limit into a short. This
action requires being able to sink 15µA from the SHDN pin
at less than 1V. The 5µA pull-down current source and the
15µA pull-up current source are designed low enough in
value so that an external resistor divider network can drive
the SHDN pin to provide overvoltage protection or to
12
If the current limit amplifier is not used, two choices
present themselves. The simplest choice is to tie the INEG
pin directly to the IPOS pin. This action defeats current
limit and provides the simplest, no frills circuit. An application in which the current limit amplifier is not used is
where an extremely low dropout voltage must be achieved
and the 50mV threshold voltage cannot be tolerated.
Unique circuit design incorporated into the LT1575 alleviates all concerns about power supply sequencing. The
issue of power supply sequencing is an important topic as
the typical LT1575 application has inputs from two separate power supply voltages. If the typical 12V VIN supply
voltage is slow in ramping up, insufficient MOSFET gate
drive is present and therefore, the output voltage does
not come up. If the VIN supply voltage is present, but the
typical 5V supply voltage tied to the IPOS pin has not
started yet, then the feedback loop wants to drive the
GATE pin to the positive VIN rail. This would result in a
LT1575/LT1577
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APPLICATIONS INFORMATION
very large current spike as soon as the 5V supply started
to ramp up. However, undervoltage lockout circuit COMP2,
which monitors the IPOS supply voltage, holds Q3 on and
pulls the COMP pin low until the IPOS voltage increases
to greater than the internal 1.21 reference voltage. The
undervoltage lockout circuit then smoothly releases the
COMP pin and allows the output voltage to come up in
dropout from the input supply voltage. An additional
benefit derived from the speed of the LT1575 feedback
loop is that turn-on overshoot is virtually nonexistent in
a properly compensated system.
cessors dictate that precision resistors must be used with
currently available adjustable voltage regulators to meet
the initial set point tolerance. The LT1575 fixed voltage
versions incorporate the precision resistor divider into the
IC and still maintain a 1% output voltage tolerance over
temperature. Thus, the LT1575 fixed voltage versions
completely eliminate the requirement for precision resistors and this results in additional system cost savings.
Applications Support
Linear Technology invests an enormous amount of time,
resources and technical expertise in understanding, designing and evaluating microprocessor power supply solutions for system designers. As processor speeds and
power increase, the power supply challenges presented to
the motherboard designer increase as well. Application
Note 69, “Using the LT1575 Linear Regulator Controller,”
has been written and serves as an extremely useful guide
for this new family of ICs. This Application Note covers
topics including PC board layout for the LT1575/LT1577
family, MOSFET selection criteria, external component
selection (capacitors) and loop compensation. Linear
Technology welcomes the opportunity to discuss, design,
evaluate and optimize a microprocessor power supply
solution with a customer. For additional information,
consult the factory.
An additional circuit feature is built-in to the LT1575 fixed
voltage versions. When the regulator circuit starts up, it
must charge up the output capacitors. The output voltage
typically tracks the input voltage supply as it ramps up with
the difference in input/output voltage defined by the dropout voltage. Until the feedback loop comes into regulation,
the circuit operation results in the GATE pin being at the
positive VIN rail, which starts the timer at the SHDN pin if
the current limit amplifier is disabled. However, internal
comparator COMP4 monitors the input/output voltage
differential. This comparator does not permit the shutdown timer to start until the differential voltage is greater
than 500mV. This permits normal start-up to occur.
One final benefit is derived in using an LT1575 fixed
voltage version. Today’s highest performance micropro-
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TYPICAL APPLICATIONS N
UltraFast Transient Response 5V to 3.5V Low Dropout Regulator
with Current Limit and Timer Latchoff
LT1575-3.5
12V
1
RESET
Q2
VN2222L
*R3 IS MADE FROM
“FREE” PC BOARD
TRACE
**C6 = 24 × 1µF X7R
CERAMIC SURFACE
MOUNT CAPACITORS.
PLACE C6 IN THE
MICROPROCESSOR
SOCKET CAVITY
C1
1µF
2
SHDN
C2
VIN
1µF 3
GND
4
OUT
IPOS
INEG
GATE
COMP
C3
10pF
8
5V
R3*
0.007Ω
7
6
5
+
R2
5Ω
R1
7.5k
C4
1000pF
Q1
IRFZ24
C5
220µF
VOUT
3.5V
5A
C6**
24µF
GND
1575/77 TA11
13
LT1575/LT1577
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TYPICAL APPLICATIONS N
Setting Output Voltage with the Adjustable LT1575
Using “Sense-Less” Current Limit
VOUT
R3
10Ω
SHDN
R2
IPOS
VCC
C1
10µF
CT
FB
INEG
R1
Q1
GATE
VOUT = 1.21V(1 + R2/R1)
VOUT
1575 TA03
Setting Current Limit
IPOS
Setting Current Limit with Foldback Limiting
IPOS
VCC
VCC
R5
10Ω
RSENSE*
R4
INEG
INEG
D1
1N4148
D2
1N4148
Q2
GATE
GATE
VOUT
1575 TA06
Shutdown Time-Out with Reset
Q1
VN2222L
R1
100k
5V
RT1
10k
NTC
C1*
SHDN
*C1 = 15µA(t)/1.11V
t = SHUTDOWN LATCHOFF TIME
1575 TA07
Shutdown Time-Out with Reset
R2
100k
R4
549Ω
RT1 = DALE NTHS-1206N02
THERMALLY MOUNT RT1
IN CLOSE PROXIMITY
TO THE EXTERNAL
N-CHANNEL MOSFET 1575 TA08
Overvoltage Protection
SHDN
Q2
2N3904
R3
100k
VOUT
Basic Thermal Shutdown
SHDN
RESET
0V TO 5V
Q3
R6
1.2k
*ILIM = 50mV/RSENSE
RSENSE = DISCRETE SHUNT RESISTOR OR
RSENSE = KELVIN-SENSED PC BOARD TRACE
ACTIVATING CURRENT LIMIT ALSO ACTIVATES
THE SHDN PIN TIMER
1575 TA05
RESET
0V TO 5V
1575 TA04
VOUT
R6
C2*
SHDN
R5
*C2 = 15µA(t)/1.11V
t = SHUTDOWN LATCH-OFF TIME
1575 TA09
1575 TA10
VOUT(uth) = 1.21(R6/R5) + 5µA(R6)
VOUT(lth) = 1.11(R6/R5) – 15µA(R6)
14
LT1575/LT1577
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TYPICAL APPLICATIONS N
Pentium ® II Processor GTL+ Power Supply
VTT
1.5V
VIN
3.3V
12V
+
C1
220µF
6.3V
R4
75Ω
VREF
LT1575-1.5
1
RESET
2
C2
0.22µF
C3
1µF
3
4
SHDN
IPOS
VIN
INEG
GND
GATE
OUT
COMP
8
7
6
R2
3.9Ω
5
R1
0.005Ω
R5
150Ω
Q1
IRFZ24
RX
R8
100Ω
R3
4.99k
C5
1000pF
C4
10pF
NOTE: LTC RECOMMENDS CENTRALLY
LOCATING THE LT1575-1.5 OUTPUT
TO MINIMIZE VTT DISTRIBUTION
DROPS AND USING SEPARATE VREF
GENERATORS AT EACH BUS END
R6
75Ω
R9
100Ω
VREF
C6
0.1µF
C7
0.1µF
R7
150Ω
RX
TX
C8 TO C23
1µF
CERAMIC
0805
CASE
R10
R11
100Ω 100Ω
Q3
Q2
TX
RX
RX
TX
•
•
•
142 TOTAL SIGNAL LINES
Q4
TX
Q5
1575/77 TA12
Generating 12V Gate Drive from a 5V Power Supply
LT1262
SHDN
2
C1+
GND
3
C2–
VOUT
4
C2+
VCC
8
7
6
5
+
C2
0.22µF
C1–
+
C1
0.22µF
1
VCC
4.75V TO 5.5V
C4
4.7µF
C3
4.7µF
D1
1N5818
L1
33µH
12V
25mA
2
12V
25mA
SW
C5
100µF
10V
VCC
4.75V TO 5.5V
+
LT1109CZ-12
VOUT
GND
1
3
+
C6
10µF
25V
D2
BAT85
VCC
4.75V TO 5.5V
C9
0.22µF
74HC14
C7
100µF
10V
+
R1
2k
C8
390pF
D3
BAT85
D4
BAT85
D5
BAT85
12V
25mA
×5
D6
BAT85
C10
0.22µF
C11
0.22µF
C12
0.22µF
1575/77 TA13
Pentium is a registered trademark of Intel Corporation.
15
LT1575/LT1577
U
TYPICAL APPLICATIONS N
12V to 3.3V/9A (14A Peak) Hybrid Regulator
LT1575
1
2
12V
3
4
C6
0.1µF
SHDN
IPOS
VIN
INEG
GND
GATE
OUT
COMP
8
7
Q1
IRLZ44
6
5
C21, 10pF
12V
+
C11
150µF
16V
+
C12
150µF
16V
+
C13
150µF
16V
+
9
1
C8, 68pF
2
C7, 0.1µF
C10, 1000pF
C9
1500pF
R5
16.5k
C14
150µF
16V
C17
1µF
13
VIN
EXTVCC
TG
COSC
SW
RUN/SS
BOOST
LTC1435
12
ITH
INTVCC
4
11
6
BG
SGND
S+
VOS
S
PGND
10
R1
2.1k, 1%
C16
1µF
R2
1.21k
1%
L1
4µH
C3, 0.1µF
D1, CMDSH-3
Q3
R3
100
R4
100
+
C18
C20
1000µF 1000µF
10V
10V
+
C2, 1000pF
+
C4, 4.7µF
1µF
X7R
CERAMIC
0805 CASE
× 40
R6
0.0075Ω
8
– 7
C5
0.1µF
VCORE
3.3V
C1, 470pF
Q2
14
15
SFB
C15
1µF
16
3
5
R9
2k
C22, 1000pF
D2
MBRS330T3
+
C23
1µF
C19
1000µF
10V
R7
35.7k
1575/77 TA16
R8
15K
L1 =COILTRONICS CTX02-13199
Q2, Q3 =SILICONIX SUD50N03-10
50mV/DIV
Transient Response to a 10A Load Step
200µs/DIV
16
1575/77 TA17
LT1575/LT1577
U
TYPICAL APPLICATIONS N
3.3V to 2.8V ±100mV at 5.7A with Sense-Less Current Limit and Timer Latchoff
INPUT
3.3V
+
+
C1
330µF
6.3V
C2
330µF
6.3V 12V
R2
10Ω
FAULT RESET
LT1575-2.8
1
RTN
2
3
4
C3
680pF
SHDN
IPOS
VIN
INEG
GND
GATE
OUT
COMP
C6
0.1µF
C7
10µF
8
7
6
Q1
IRL3303
5
VCORE
2.8V
R1
4.7k
C5
22pF
+
C4
1000pF
C8 TO C31*
1µF
1575/77 TA14
*X7R CERAMIC 0805 CASE
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
17
LT1575/LT1577
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
18
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
SO8 0996
LT1575/LT1577
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0.014 – 0.019
(0.355 – 0.483)
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
7
0.050
(1.270)
TYP
S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1575/LT1577
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TYPICAL APPLICATION
LT1577 Split Plane System
FAULT RESET
INPUT
5V
C1
330µF
6.3V
+
+
1/2 LT1577
1/2 LT1577
1
2
12V
3
C3
0.33µF
4
SHDN1
IPOS1
VIN1
INEG1
GND1
GATE1
OUT-3.3 COMP1
16
5
15
6
14
13
C5
10pF
C4
1µF
C2
330µF
6.3V
R1
3.9Ω
7
Q1
IRFZ24
R2
3.9k
C6
1500pF
8
SHDN2
IPOS2
VIN2
INEG2
GND2
GATE2
OUT-2.8 COMP2
VI/O
3.3V
12
11
10
R5
3.9Ω
9
VCORE
2.8V
R6
7.5k
C7
10pF
C9 TO
C20*
1µF
Q2
IRFZ24
C21 TO
C44*
1µF
C8
1000pF
*X7R CERAMIC 0805 CASE
1575/77 TA15
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1266
Current Mode, Step-Up/Down Switching Regulator Controller
Synchronous N- or P-Channel FETs, Comparator/Low
Battery Detector
LTC1392
Micropower Temperature, Power Supply and Differential
Voltage Monitor
Temperature to Bits Control
LTC1430
High Power Step-Down Switching Regulator Controller
Voltage Mode, 5V to 3.xxV at >10A
LTC1435
High Efficiency, Low Noise Synchronous Step-Down
Switching Regulator
Current Mode with Wide Input Voltage Range
LTC1553
Digitally Controlled Synchronous Switching Regulator Controller
Controller for Pentium II Processor, Buck Conversion
from 5V or 12V Main Power
LTC1553L
Digitally Controlled Synchronous Switching Regulator Controller
Controller for Pentium II Processor, Buck Conversion
from 5V Main Power
LT1573
Low Dropout Regulator Driver
Drives Low Cost PNP Transistor for High Power,
Low Dropout Applications
LT1580
7A, Very Low Dropout Linear Regulator
0.54V Dropout at 7A, Fixed 2.5VOUT and Adjustable
LT1585-1.5
Fixed 1.5V, 5A Low Dropout Fast Response Regulator
GTL+ Regulator
20
Linear Technology Corporation
15757f LT/TP 0598 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1996
工商网监
湘ICP备2023018690号
