LT1640AHIS8#TRPBF

LT1640AL/LT1640AH Negative Voltage Hot Swap Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®1640AL/LT1640AH are 8-pin, negative voltage Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable electronic circuit breaker protects the system against shorts. The PWRGD (LT1640AL) or PWRGD (LT1640AH) signal can be used to directly enable a power module. The LT1640AL is designed for modules with a low enable input and the LT1640AH for modules with a high enable input. Allows Safe Board Insertion and Removal from a Live – 48V Backplane Operates from –10V to – 80V Programmable Inrush Current Allows 50mA of Reverse Drain Pin Current Programmable Electronic Circuit Breaker Programmable Overvoltage Protection Programmable Undervoltage Lockout Power Good Control Output U APPLICATIO S ■ ■ ■ Central Office Switching – 48V Distributed Power Systems Negative Power Supply Control The LT1640AL/LT1640AH are available in 8-pin PDIP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO GND Input Inrush Current (SHORT PIN) GND R4† 562k 1% UV = 37V OV = 71V R5† 9.09k 1% R6† 10k 1% 8 VDD 3 2 VEE SENSE 4 PWRGD GATE DRAIN 5 1 6 C1† 150nF 25V R1† 0.02Ω 5% 3 1 7 R2 10Ω 5% 4 2 * DIODES INC. SMAT70A THESE COMPONENTS ARE APPLICATION SPECIFIC AND MUST BE SELECTED BASED UPON OPERATING CONDITIONS AND DESIRED PERFORMANCE. SEE APPLICATIONS INFORMATION. † LT1640AL OV * – 48V CONTACT BOUNCE UV † R3 † 18k C2 5% 3.3nF 100V 2 Q1 IRF530 C3 0.1µF 100V + C4 100µF 100V ON/OFF 1 9 VOUT+ VIN+ 8 SENSE + 7 TRIM – 6 SENSE 4 5 VOUT– VIN– LUCENT JW050A1-E 5V + C5 100µF 16V 1640A TA01 1640A F07b 1 LT1640AL/LT1640AH U W W W ABSOLUTE MAXIMUM RATINGS (Note 1), All Voltages Referred to VEE Supply Voltage (VDD – VEE) .................... – 0.3V to 100V PWRGD, PWRGD Pins ........................... – 0.3V to 100V DRAIN Pin ................................................. – 2V to 100V SENSE, GATE Pins .................................... – 0.3V to 20V UV, OV Pins .............................................. – 0.3V to 60V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LT1640ALC/LT1640AHC ........................ 0°C to 70°C LT1640ALI/LT1640AHI ...................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW PWRGD 1 8 VDD OV 2 7 DRAIN UV 3 6 GATE VEE 4 5 SENSE N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) LT1640ALCN8 LT1640ALCS8 LT1640ALIN8 LT1640ALIS8 S8 PART MARKING ORDER PART NUMBER TOP VIEW PWRGD 1 8 VDD OV 2 7 DRAIN UV 3 6 GATE VEE 4 5 SENSE N8 PACKAGE 8-LEAD PDIP 1640AL 640ALI S8 PACKAGE 8-LEAD PLASTIC SO LT1640AHCN8 LT1640AHCS8 LT1640AHIN8 LT1640AHIS8 S8 PART MARKING TJMAX = 125°C, θJA = 120°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) 1640AH 640AHI Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC VDD Supply Operating Range IDD Supply Current VCB IPU ● 10 V 5 mA UV = 3V, OV = VEE, SENSE = VEE ● Circuit Breaker Trip Voltage VCB = (VSENSE – VEE) ● 40 50 60 mV GATE Pin Pull-Up Current Gate Drive On, VGATE = VEE ● – 30 – 45 – 60 µA IPD GATE Pin Pull-Down Current Any Fault Condition 24 50 70 mA ISENSE SENSE Pin Current VSENSE = 50mV ∆VGATE External Gate Drive (VGATE – VEE), 15V ≤ VDD ≤ 80V (VGATE – VEE), 10V ≤ VDD < 15V ● ● 10 6 13.5 8 18 15 V V VUVH UV Pin High Threshold Voltage UV Low to High Transition ● 1.213 1.243 1.272 V VUVL UV Pin Low Threshold Voltage UV High to Low Transition ● 1.198 1.223 1.247 V VUVHY UV Pin Hysteresis IINUV UV Pin Input Current VUV = VEE ● – 0.02 – 0.5 µA VOVH OV Pin High Threshold Voltage OV Low to High Transition ● 1.198 1.223 1.247 V VOVL OV Pin Low Threshold Voltage OV High to Low Transition ● 1.165 1.203 1.232 V VOVHY OV Pin Hysteresis IINOV OV Pin Input Current VOV = VEE ● 2 1.3 80 µA – 20 20 mV 20 – 0 .03 mV – 0.5 µA LT1640AL/LT1640AH ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPG Power Good Threshold VDRAIN – VEE, High to Low Transition 1.1 1.4 2.0 V VPGHY Power Good Threshold Hysteresis IDRAIN Drain Input Bias Current VDRAIN = 48V ● 50 500 µA VOL PWRGD Output Low Voltage PWRGD (LT1640AL), (VDRAIN – VEE) < VPG IOUT = 1mA IOUT = 5mA ● 0.48 1.50 0.8 3.0 V V ● 0.75 1.0 V 0.05 10 µA 0.4 10 V PWRGD Output Low Voltage (PWRGD – DRAIN) PWRGD (LT1640AH), VDRAIN = 5V IOUT = 1mA IOH Output Leakage PWRGD (LT1640AL), VDRAIN =48V, VPWRGD = 80V ● ROUT Power Good Output Impedance (PWRGD to DRAIN) PWRGD (LT1640AH), (VDRAIN – VEE) < VPG ● tPHLOV OV High to GATE Low tPHLUV UV Low to GATE Low tPLHOV OV Low to GATE High tPLHUV UV High to GATE High tPHLSENSE SENSE High to Gate Low Figures 1, 4 tPHLPG DRAIN Low to PWRGD Low DRAIN Low to (PWRGD – DRAIN) High (LT1640AL) Figures 1, 5 (LT1640AH) Figures 1, 5 0.5 0.5 µs µs tPLHPG DRAIN High to PWRGD High DRAIN High to (PWRGD – DRAIN) Low (LT1640AL) Figures 1, 5 (LT1640AH) Figures 1, 5 0.5 0.5 µs µs 2 6.5 kΩ Figures 1, 2 1.7 µs Figures 1, 3 1.5 µs Figures 1, 2 5.5 µs Figures 1, 3 6.5 µs AC 2 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 3 µs 4 Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Temperature 1.6 1.8 TA = 25°C 15 VDD = 48V 1.5 1.4 1.3 1.2 13 GATE VOLTAGE (V) 1.6 TA = 25°C 14 1.5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.7 Gate Voltage vs Supply Voltage 1.4 1.3 1.2 12 11 10 9 8 1.1 1.1 0 7 0 20 40 80 60 SUPPLY VOLTAGE (V) 100 1640A G01 1.0 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640A G02 6 0 20 80 60 40 SUPPLY VOLTAGE (V) 100 1640A G03 3 LT1640AL/LT1640AH U W TYPICAL PERFOR A CE CHARACTERISTICS VDD = 48V TRIP VOLTAGE (mV) GATE VOLTAGE (V) 14.5 14.0 13.5 13.0 12.5 55 48 54 47 VGATE = 0V GATE PULL-UP CURRENT (µA) 15.0 53 52 51 50 49 12.0 – 50 – 25 25 50 0 TEMPERATURE (°C) 75 48 – 50 100 0.5 – 25 50 0 25 TEMPERATURE (°C) 75 49 46 43 0 50 25 TEMPERATURE (°C) 43 42 40 – 50 100 75 100 – 25 0 25 50 TEMPERATURE (°C) 75 PWRGD Output Impedance vs Temperature (LT1640AH) 8 IOUT = 1mA VDRAIN – VEE > 2.4V 7 0.4 0.3 0.2 0.1 0 – 50 100 1640A G06 OUTPUT IMPEDANCE (kΩ) PWRGD OUTPUT LOW VOLTAGE (V) 52 – 25 44 PWRGD Output Low Voltage vs Temperature (LT1640AL) VGATE = 2V 40 – 50 45 1640A G05 Gate Pull-Down Current vs Temperature 55 46 41 1640A G04 GATE PULL-DOWN CURRENT (mA) Gate Pull-Up Current vs Temperature Circuit Breaker Trip Voltage vs Temperature Gate Voltage vs Temperature 6 5 4 3 – 25 25 50 0 TEMPERATURE (°C) 1640A G07 75 100 1640A G08 2 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 1640A G09 U U U PI FU CTIO S PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will toggle when VDRAIN is within VPG of VEE. This pin can be connected directly to the enable pin of a power module. When the DRAIN pin of the LT1640AL is above VEE by more than VPG, the PWRGD pin will be high impedance, allowing the pull-up current of the module’s enable pin to pull the pin high and turn the module off. When VDRAIN drops below VPG, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module. 4 When the DRAIN pin of the LT1640AH is above VEE by more than VPG, the PWRGD pin will sink current to the DRAIN pin which pulls the module’s enable pin low, forcing it off. When VDRAIN drops below VPG, the PWRGD sink current is turned off and a 6.5k resistor is connected between PWRGD and DRAIN, allowing the module’s pullup current to pull the enable pin high and turn on the module. LT1640AL/LT1640AH U U U PIN FUNCTIONS OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.223V low-to-high threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.203V high-to-low threshold. UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.223V high to low threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.243 low-to-high threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds 50mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low and (VSENSE – VEE) < 50mV. The GATE pin is pulled high by a 45µA current source and pulled low with a 50mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel and the V – pin of the power module. When the DRAIN pin is below VPG, the PWRGD or PWRGD pin will toggle. In some conditions, the DRAIN pin is pulled below VEE. The part is not damaged if the reverse DRAIN pin current is limited to 50mA. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. The input supply voltage ranges from 10V to 80V. W BLOCK DIAGRA VDD – UV VCC AND REFERENCE GENERATOR + VCC REF OUTPUT DRIVE PWRGD/PWRGD REF – OV + 50mV –+ LOGIC AND GATE DRIVE – + + + – – VPG VEE 1640A BD VEE SENSE GATE DRAIN 5 LT1640AL/LT1640AH TEST CIRCUIT V+ 5V R 5k PWRGD/PWRGD VDD OV VOV + – DRAIN 48V VDRAIN LT1640AL/LT1640AH UV GATE VEE SENSE VUV VSENSE 1640A F01 Figure 1. Test Circuit W UW TIMING DIAGRAMS 2V OV 1.223V 2V 1.203V 1.223V UV 0V 1.243V 0V tPHLOV GATE 1V tPLHOV 1V tPHLUV GATE tPLHUV 1V 1640A F02 Figure 2. OV to GATE Timing 1V Figure 3. UV to GATE Timing 1.8V SENSE 1640A F03 50mV 1.4V DRAIN VEE GATE tPHLPG tPLHPG tPHLSENSE PWRGD 1V VEE 1V 1V 1640A F04 Figure 4. SENSE to GATE Timing 1.8V 1.4V DRAIN 0V PWRGD VPWRGD – VDRAIN = 0V tPLHPG tPHLPG 1V 1V Figure 5. DRAIN to PWRGD/PWRGD Timing 6 1640A F05 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion Power Supply Ramping When circuit boards are inserted into a live – 48V backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board’s components and cause glitches on the system power supply. The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a, all waveforms are with respect to the VEE pin of the LT1640A). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. By ramping the gate of Q1 up at a slow rate, the surge current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection. The LT1640A is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The inrush current can be calculated with the following equation: IINRUSH = (45µA • CL)/C2 where CL is the total load capacitance equal to C3 + C4 + module input capacitance. GND (SHORT PIN) GND R4 562k 1% UV = 37V OV = 71V R5 9.09k 1% VICOR VI-J3D-CY 8 C3 0.1µF 100V VDD 3 2 R6 10k 1% UV VEE SENSE 4 GATE DRAIN 5 6 C1 150nF 25V R1 0.02Ω 5% 3 * DIODES INC. SMAT70A PWRGD C4 100µF 100V 1 VIN+ VOUT+ 4 5V + GATE IN OV * – 48V LT1640AH + VIN– C5 100µF 16V VOUT– 7 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V 1640A F06a 1 2 Q1 IRF530 Figure 6a. Inrush Control Circuitry 7 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to VEE • C2/CGS(Q1) before the LT1640A could power up and actively pull the gate low. By placing capacitor C1 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3, the problem is solved. The value of C1 should be:  VINMAX − VTH    • (C 2 + C GD )   VTH R3’s value is not critical and is given by (VINMAX + ∆VGATE)/ 5mA. The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT1640A senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected. Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the DRAIN voltage has finished ramping, the GATE pin then ramps to its final value. where VTH is the MOSFET’s minimum gate threshold and VINMAX is the maximum operating input voltage. CONTACT BOUNCE 1640A F07b Figure 6b. Inrush Control Waveforms 8 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO Electronic Circuit Breaker The LT1640A features an electronic circuit breaker function that protects against short circuits or excessive supply currents. By placing a sense resistor between the VEE and SENSE pin, the circuit breaker will be tripped whenever the voltage across the sense resistor is greater than 50mV for more than 3µs as shown in Figure 7. on R7. This voltage will be counted into the circuit breaker trip voltage just as the voltage across the sense resistor. A small resistor is recommended for R7. A 100Ω for R7 will cause a 2mV error. The following equation can be used to estimate the delay time at the SENSE pin:  V( t) – V( tO ) t = –R • C • In  1 –  Vi – V( tO )   Note that the circuit breaker threshold should be set sufficiently high to account for the sum of the load current and the inrush current. If the load current can be controlled by the PWRGD/PWRGD pin (as in Figure 6a), the threshold can be set lower, since it will never need to accommodate inrush current and load current simultaneously. Where V(t) is the circuit breaker trip voltage, typically 50mV. V(tO) is the voltage drop across the sense resistor before the short or overcurrent condition occurs. Vi is the voltage across the sense resistor when the short current or overcurrent is applied on it. When the circuit breaker trips, the GATE pin is immediately pulled to VEE and the external N-channel turns off. The GATE pin will remain low until the circuit breaker is reset by pulling UV low, then high or cycling power to the part. Example: A system has a 1A current load and a 0.02Ω sense resistor is used. An extended delay circuit needs to be designed for a 50µs delay time after the load jumps to 5A. In this case: If more than 3µs deglitching time is needed to reject current noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 8. R7 and C3 act as a lowpass filter that will slow down the SENSE pin voltage from rising too fast. Since the SENSE pin will source current, typically 20µA, there will be a voltage drop V(t) = 50mV V(tO) = 20mV Vi = 5A • 0.02Ω = 100mV If we choose R = 100Ω, we will get C = 1µF. GND (SHORT PIN) GND 8 R4 562k 1% UV = 37V OV = 71V R5 9.09k 1% VDD 3 UV LT1640AL 2 PWRGD + OV R6 10k 1% SENSE VEE 4 5 GATE DRAIN 6 * R7 1 * DIODES INC. SMAT70A C1 150nF 25V R1 0.02Ω 5% 3 – 48V Figure 7. Short-Circuit Protection Waveforms CL 100µF 100V 7 C3 1640A F07 1 4 2 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V Q1 IRF530 1640A F08 Figure 8. Extending the Short-Circuit Protection Delay 9 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO Under some conditions, a short circuit at the output can cause the input supply to dip below the UV threshold, resetting the circuit breaker immediately. Transistors Q2 and Q3 along with R7, R8, C4 and D1 form a programmable one-shot circuit. Before a short occurs, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge C4 and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. As soon as C4 is fully charged, R8 turns off Q2, UV goes high and the GATE starts to ramp up. Q3 turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating. The LT1640A then cycles on and off repeatedly until the short is removed. This can be minimized by adding a deglitching delay to the UV pin with a capacitor from UV to VEE. This capacitor forms an RC time constant with the resistors at UV, allowing the input supply to recover before the UV pin resets the circuit breaker. A circuit that automatically resets the circuit breaker after a current fault is shown in Figure 9. GND (SHORT PIN) GND R7 1M 5% 2 C4 1µF 100V * Q2 2N2222 D1 1N4148 – 48V * DIODES INC. SMAT70A R4 562k 1% R5 9.09k 1% R6 10k 1% 3 8 VDD 3 2 UV PWRGD GATE DRAIN OV VEE SENSE 5 4 Q3 ZVN3310 R8 510k 5% LT1640AL C1 150nF 25V R1 0.02Ω 5% 3 1 6 4 2 + C3 100µF 100V 7 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V Q1 IRF530 1640A F09b Figure 9. Automatic Restart After Current Fault 10 1 1640A F09a LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO Undervoltage and Overvoltage Detection Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10k, the undervoltage threshold is set to 37V and the overvoltage threshold is set to 71V. The resistor divider will also amplify the 20mV hysteresis at the UV pin and OV pin to 0.6V and 1.2V at the input, respectively. The UV (Pin 3) and OV (Pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power supply input. The UV and OV pins are internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. More hysteresis can be added to the UV threshold by connecting resistor R3 between the UV pin and the GATE pin as shown in Figure 10b. The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in (SHORT PIN) GND GND 8 VUV = 1.223 ( ( R4 + R5+ R6 R5 + R6 R4 + R5+ R6 VOV = 1.223 R6 ) ) R4 VDD 3 UV LT1640AL LT1640AH R5 2 OV VEE R6 4 – 48V 1640A F10a Figure 10a. Undervoltage and Overvoltage Sensing GND (SHORT PIN) GND 8 R4 506k 1% UV = 37.6V UV = 43V OV = 71V VDD 2 R1 562k 1% R5 8.87k 1% R2 16.9k 1% OV LT1640AL /LT1640AH 3 R3 1.62M 1% UV VEE 4 * * DIODES INC. SMAT70A 5 1 6 C1 150nF 25V R1 0.02Ω 5% 3 – 48V GATE SENSE R6 10Ω 5% 4 2 Q1 1640A F10b IRF530 Figure 10b. Programmable Hysteresis for Undervoltage Detection 11 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO The new threshold voltage when the input moves from low to high is:  R4 + R5  VOV = VOVH    R5   R2 • R3 + R1 • R3 + R1 • R2  VUV,LH = VUVH   R2 • R3   With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the overvoltage threshold will be 71V. where VUVH is typically 1.243V. PWRGD/PWRGD Output The new threshold voltage when the input moves from high to low is: The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT1640AL has a PWRGD output for modules with an active low enable input, and the LT1640AH has a PWRGD output for modules with an active high enable input.  R2 • R3 + R1 • R3 + R1 • R2   R1 VUV,HL = VUVL   –  VGATE •  R2 • R3 R3     where VUVL is typically 1.223V. When the DRAIN voltage of the LT1640AH is high with respect to VEE (Figure 11), the internal transistor Q3 is turned off and R7 and Q2 clamp the PWRGD pin one diode drop (≈ 0.7V) above the DRAIN pin. Transistor Q2 sinks the module’s pull-up current and the module turns off. The new hysteresis value will be:  R2 • R3 + R1 • R3 + R1 • R2   R1 VHYS = VUVHY   +  VGATE •  R2 • R3 R3     With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE = 13.5V and VUVHY = 20mV, the undervoltage threshold will be 43V (from low to high) and 37.6V (from high to low). The hysteresis is 5.4V. A separate resistor divider should be used to set the overvoltage threshold given by: GND When the DRAIN voltage drops below VPG, Q3 will turn on, shorting the bottom of R7 to DRAIN and turning Q2 off. The pull-up current in the module then flows through R7, pulling the PWRGD pin high and enabling the module. ACTIVE HIGH ENABLE MODULE (SHORT PIN) VIN+ GND 8 LT1640AH R4 3 UV PWRGD 1 R7 6.5k + + – R5 2 VDD + ON/OFF C3 Q2 Q3 VPG – OV VEE VIN– DRAIN 7 R6 SENSE VEE 4 GATE 5 6 * C1 3 – 48V R2 R3 C2 4 R1 1640A F11 1 2 Q1 * DIODES INC. SMAT70A Figure 11. Active High Enable Module 12 VOUT+ VOUT– LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO When the DRAIN voltage of the LT1640AL is high with respect to VEE, the internal pull-down transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure␣ 12). The PWRGD pin will be pulled high by the module’s internal pull-up current source, turning the module off. When the DRAIN voltage drops below VPG, Q2 will turn on and the PWRGD pin will pull low, enabling the module. than 6V. The gate voltage will be no greater than 18V for supply voltages up to 80V. Drain Pin Protection A unique feature of the LT1640A is the ruggedness of the DRAIN pin. The DRAIN is designed to withstand negative voltages (with respect to VEE) without requiring an external diode. A short circuit on the – 48V backplane pulls up the VEE pin, but due to the storage capacitor C3 (Figure␣ 12), the DRAIN pin is held more negative than the VEE pin. The body diode of Q1, plus the I • R drop across R1 (if R1 is small), holds the DRAIN pin to less than 1.5V below VEE. A 1.5V reverse voltage gives rise to a 50mA reverse drain current, which is within the design capability of the LT1640A. A design with R1 larger than 0.1Ω may require a resistor in series with the DRAIN pin to not exceed the 50mA drain current maximum. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good as shown in Figure 13. Gate Pin Voltage Regulation When the supply voltage to the chip is more than 15.5V, the GATE pin voltage is regulated at 13.5V above VEE. If the supply voltage is less than 15.5V, the GATE voltage will be about 2V below the supply voltage. At the minimum 10V supply voltage, the gate voltage is guaranteed to be greater GND ACTIVE LOW ENABLE MODULE (SHORT PIN) VIN+ GND 8 3 R5 VDD LT1640AL R4 2 PWRGD + UV + – VPG 1 + Q2 ON/OFF C3 VEE – OV VOUT+ DRAIN VIN– 7 VOUT– R6 SENSE VEE 4 GATE 5 6 * C1 3 – 48V R2 R3 C2 4 R1 1640A F12 1 2 Q1 * DIODES INC. SMAT70A Figure 12. Active Low Enable Module 13 LT1640AL/LT1640AH U W U U APPLICATIO S I FOR ATIO GND (SHORT PIN) GND R4 562k 1% R5 9.09k 1% R7 51k 5% 8 PWRGD + VDD 3 2 UV LT1640AL PWRGD GATE DRAIN 4N25 1 C3 100µF 100V OV R6 10k 1% VEE SENSE 4 5 R1 0.02Ω 5% 3 1 * DIODES INC. SMAT70A 4 2 7 R2 R3 10Ω 18k C2 5% 5% 3.3nF 100V C1 150nF 25V * – 48V 6 Q1 IRF530 1640A F13 Figure 13. Using PWRGD to Drive an Optoisolator U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 14 0.130 ± 0.005 (3.302 ± 0.127) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 LT1640AL/LT1640AH U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 1298 15 LT1640AL/LT1640AH U TYPICAL APPLICATION Using an EMI Filter Module using the Lucent FLTR100V10 filter module is shown in Figure 14. When using a filter, an optoisolator is required to prevent common mode transients from destroying the PWRGD and ON/OFF pins. Many applications place an EMI filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. A typical application R7 51k 5% GND (SHORT PIN) 4N25 GND R4 562k 1% R5 9.09k 1% 8 1 1 DRAIN UV 7 LT1640AL 2 R6 10k 1% OV GATE 6 VIN+ C2 3.3nF 100V R3 18k 5% SENSE VEE 5 4 R1 0.02Ω 5% * 3 – 48V VIN+ VOUT+ PWRGD VDD 3 LUCENT JW050A1-E 1 R2 10Ω 5% C1 150nF 25V C3 0.1µF 100V LUCENT FLTR100V10 VIN– 2 VOUT+ C4 0.1µF 100V + C5 100µF 100V C6 0.1µF 100V VOUT– CASE SENSE ON/OFF + TRIM 9 5V 8 7 + 6 4 SENSE – VOUT– VIN– C7 100µF 16V 5 CASE 3 1640A F14 4 2 Q1 IRF530 * DIODES INC. SMAT70A Figure 14. Typical Application Using a Filter Module RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC®1421 Dual Channel, Hot Swap Controller Operates from 3V to 12V LTC1422 Hot Swap Controller in SO-8 System Reset Output with Programmable Delay, 3V to 12V LT1641 Positive 48V Hot Swap Controller in SO-8 Foldback Analog Current Limit LTC1642 Fault Protected Hot Swap Controller Operates Up to 16.5V, Protected to 33V LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, – 12V Supplies for PCI Bus LTC1645 Dual Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing TM LTC1646 CompactPCI Hot Swap Controller 3.3V, 5V Supplies, 1V Precharge, Local PCI Reset Logic LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group 16 Linear Technology Corporation 1640alahf LT/TP 0501 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 2001