LT1719
4.5ns Single/Dual Supply
3V/5V Comparator with
Rail-to-Rail Output
DESCRIPTION
FEATURES
n
n
n
n
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UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive
Low Power: 4.2mA at 3V
Separate Input and Output Power Supplies
(SO-8 Only)
Output Optimized for 3V and 5V Supplies
TTL/CMOS Compatible Rail-to-Rail Output
Low Power Shutdown Mode: 0.1μA
Low Profile (1mm) SOT-23 (ThinSOT™) Package
APPLICATIONS
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High Speed Differential Line Receiver
Crystal Oscillator Circuits
Level Translators
Threshold Detectors/Discriminators
Zero-Crossing Detectors
High Speed Sampling Circuits
Delay Lines
The LT ®1719 is an UltraFast™ comparator optimized for low
voltage operation. The input voltage range extends from
100mV below VEE to 1.2V below VCC. Internal hysteresis
makes the LT1719 easy to use even with slow moving input
signals. The rail-to-rail outputs directly interface to TTL
and CMOS. Alternatively the symmetric output drive can be
harnessed for analog applications or for easy translation to
other single supply logic levels. A shutdown control allows
for reduced power consumption and extended battery life
in portable applications.
The LT1719 is available in the SO-8 and 6-lead SOT-23
package. The SO-8 package has separate supplies which
allow flexible operation, accomodating separate analog
input ranges and output logic levels.
For a dual/quad comparator with similar performance, see
the LT1720/LT1721.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
2.7V to 6V Crystal Oscillator with TTL/CMOS Output
Propagation Delay vs Overdrive
2.7V TO 6V
8
1MHz TO 10MHz
CRYSTAL (AT-CUT)
2k
7
220Ω
RISING EDGE
(tPDLH)
620Ω
+
GROUND
CASE
C1
LT1719
OUTPUT
–
5
4
FALLING EDGE
(tPDHL)
3
2
2k
1719 TA01
0.1μF
DELAY (ns)
6
25°C
VSTEP = 100mV
V+ = 5V
CLOAD = 10pF
1.8k
1
0
0
10
20
30
OVERDRIVE (mV)
40
50
1719 TA02
1719fa
1
LT1719
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage
+ VS to GND (LT1719S8) ........................................ 7V
VCC to VEE (LT1719S8) ........................................ 12V
+VS to VEE (LT1719S8) ....................................... 12V
VEE to GND (LT1719S8) ....................... –12V to 0.3V
V+ to V– (LT1719S6) ...............................................7V
Input Current (+IN, –IN or SHDN) ...................... ±10mA
Output Current (Continuous) ........................... ± 20mA
Operating Temperature Range
C-Grade .................................................. 0°C to 70°C
I-Grade ............................................... –40°C to 85°C
Junction Temperature ......................................... 150°C
Storage Temperature Range.................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
PIN CONFIGURATION
TOP VIEW
VCC 1
+IN 2
+
–IN 3
–
VEE 4
8
+VS
7
OUT
6
5
TOP VIEW
–IN 1
SHDN
V– 2
GND
+IN 3
6 SHDN
5 OUT
4 V+
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 110°C/W
TJMAX = 150°C, θJA = 230°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1719CS8#PBF
LT1719CS8#TRPBF
1719
8-Lead Plastic SO
0°C to 70°C
LT1719IS8#PBF
LT1719IS8#TRPBF
1719I
8-Lead Plastic SO
–40°C to 85°C
LT1719CS6#PBF
LT1719CS6#TRPBF
LTHW
6-Lead Plastic TSOT-23
0°C to 70°C
LT1719IS6#PBF
LT1719IS6#TRPBF
LTJF
6-Lead Plastic TSOT-23
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1719fa
2
LT1719
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the
LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
VCC – VEE Input Supply Voltage
+ VS
Output Supply Voltage
MIN
MAX
UNITS
(LT1719S8 Only)
l
2.7
10.5
V
(LT1719S8 Only)
l
2.7
6
V
(LT1719CS6 Only)
l
2.7
6
V
(LT1719S8)
(LT1719S6)
l
l
VEE – 0.1
V– – 0.1
VCC – 1.2
V + – 1.2
V
V
l
l
–1.5
–5.5
5.5
1.5
mV
mV
0.4
2.5
3.5
mV
mV
3.5
7
mV
V+ – V –
Supply Voltage
VCMR
Input Voltage Range
(Note 2)
VTRIP+
VTRIP–
Input Trip Points
(Note 3)
VOS
Input Offset Voltage
(Note 3)
VHYST
Input Hysteresis Voltage
(Note 3)
ΔVOS/ΔT
Input Offset Voltage Drift
l
l
l
IB
Input Bias Current
l
IOS
Input Offset Current
l
CMRR
Common Mode Rejection Ratio
(Note 4)
(Note 5)
(LT1719S8)
(LT1719S6)
PSRR
Power Supply Rejection Ratio
(Note 6)
(Note 7)
(LT1719S8)
(LT1719S6)
AV
Voltage Gain
(Note 8)
VOH
Output High Voltage
ISOURCE = 4mA, VIN = VTRIP+ + 10mV
VOL
Output Low Voltage
ISINK = 10mA, VIN = VTRIP– – 10mV
l
tPD20
Propagation Delay
VOVERDRIVE = 20mV (Note 9) VEE = 0V(LT1719S8)
V – = 0V(LT1719S6)
l
VOVERDRIVE = 20mV, VEE = –5V
TYP
l
l
2.0
10
–6
μV/°C
–2.5
0
μA
0.2
0.6
μA
55
55
70
65
dB
dB
65
65
80
80
dB
dB
∞
(LT1719S8)
(LT1719S6)
l
l
+VS – 0.4
V+ – 0.4
4.5
(LT1719S8 Only)
tPD5
Propagation Delay
VOVERDRIVE = 5mV (Notes 9, 10) VEE = 0V(LT1719S8)
V – = 0V(LT1719S6)
tSKEW
Propagation Delay Skew
tr
tf
V
V
0.4
V
6.5
8.0
ns
ns
4.2
ns
7
10
13
ns
ns
(Note 11)
0.5
1.5
ns
Output Rise Time
10% to 90%
2.5
ns
Output Fall Time
90% to 10%
2.2
ns
15
11
psRMS
psRMS
l
tPD+
tPD–
tJITTER
Output Timing Jitter
VIN = 1.2VP-P (6dBm), ZIN = 50Ω
f = 20MHz
fMAX
Maximum Toggle Frequency
VOVERDRIVE = 50mV, +VS or V+ = 3V
VOVERDRIVE = 50mV, +VS or V+ = 5V
tOFF
Turn-Off Delay
Time to ZOUT ≥10kΩ
75
ns
tON
Wake-Up Delay
Time to VOH or VOL, ILOAD = 1mA
350
ns
ICC
Positive Input Stage Supply Current
+ VS = VCC = 5V, VEE = –5V
IEE
Negative Input Stage Supply Current
(LT1719S8 Only) + VS = VCC = 3V, VEE = 0V
+ VS = VCC = 5V, VEE = –5V
(LT1719S8 Only) + VS = VCC = 3V, VEE = 0V
70
62.5
l
l
MHz
MHz
1
2.2
mA
0.9
1.8
mA
l
–4.8
–2.6
mA
l
–3.8
–2.2
mA
1719fa
3
LT1719
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the
LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise specified.
SYMBOL PARAMETER
IS
CONDITIONS
Positive Output Stage Supply Current
MIN
+ VS = VCC = 5V, VEE = –5V
Supply Current
ISHDN5
(LT1719S6)
Shutdown Pin Current
8
mA
6
mA
4.6
9
mA
V+ = 3V
l
4.2
7
mA
+VS
or V+ = 5V
l
–300
–110
–30
μA
+VS
or V+ = 3V
l
–200
–80
–20
μA
30
50
–30
0.2
7
–0.2
μA
μA
μA
l
7
80
μA
l
l
l
0.1
0.1
0.1
20
20
μA
μA
μA
0.2
40
μA
Disabled Supply Currents (LT1719S8) + VS = 6V, VCC = 5V, VEE = –5V
(LT1719S8) VSHDN = +VS – 0.5V
(LT1719S8)
V+ = 6V, V
I+
(LT1719S6)
ICCSO
ISSO
IEEO
(LT1719S8) + VS = 6V, VCC = 5V, VEE = –5V
(LT1719S8) Shutdown Pin Open
(LT1719S8)
(LT1719S6)
4.2
3.3
ICCS
ISS
IEES
O
l
l
Shutdown Pin Current
I+
UNITS
l
ISHDN3
S
MAX
V+ = 5V
(LT1719S8 Only) VS = VCC = 3V, VEE = 0V
I+
TYP
SHDN = +VS – 0.5V
V+ = 6V, Shutdown Pin Open
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.
Note 3: The LT1719 comparator includes internal hysteresis. The trip
points are the input voltage needed to change the output state in each
direction. The offset voltage is defined as the average of VTRIP+ and VTRIP–,
while the hysteresis voltage is the difference of these two.
Note 4: The LT1719S8 common mode rejection ratio is measured with
VCC = 5V, VEE = – 5V and is defined as the change in offset voltage measured
from VCM = –5.1V to VCM = 3.8V, divided by 8.9V.
Note 5: The LT1719S6 common mode rejection ratio is measured with
V+ = 5V and is defined as the change in offset voltage measured from
VCM = –0.1V to VCM = 3.8V, divided by 3.9V.
Note 6: The LT1719S8 power supply rejection ratio is measured with
VCM = 1V and is defined as the worst of: the change in offset voltage from
l
l
l
l
–20
VEE = – 5.5V to VEE = 0V divided by 5.5V, or the change in offset voltage
from VCC = +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V) divided by 3.3V.
Note 7: The LT1719S6 power supply rejection ratio is measured with
VCM = 1V and is defined as the change in offset voltage measured from
V+ = 2.7V to V+ = 6V, divided by 3.3V.
Note 8: Because of internal hysteresis, there is no small-signal region in
which to measure gain. Proper operation of internal circuity is ensured by
measuring VOH and VOL with only 10mV of overdrive.
Note 9: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to VTRIP±.
Note 10: t PD cannot be measured in automatic handling equipment with
low values of overdrive. The LT1719 is 100% tested with a 100mV step
and 20mV overdrive. Correlation tests have shown that tPD limits can be
guaranteed with this test, if additional DC tests are performed to guarantee
that all internal bias conditions are correct.
Note 11: Propagation Delay Skew is defined as:
tSKEW = |tPDLH – tPDHL|
1719fa
4
LT1719
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset and Trip Voltages
vs Supply Voltage
Input Offset and Trip Voltages
vs Temperature
4.2
3
2
1
VOS
0
–1
VTRIP–
25°C
VCM = 1V
VEE OR V– = GND
–2
–3
2.5
VTRIP
2
+
COMMON MODE INPUT VOLTAGE (V)
VTRIP+
VOS AND TRIP POINT VOLTAGE (mV)
1
VOS
0
–1
–2
VTRIP–
+
+VS = VCC or V = 5V
VCM = 1V
VEE OR V– = GND
–3
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
5.5 6.0
3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE, VCC = +VS OR V+ (V)
Input Current
vs Differential Input Voltage
VCC = +VS OR V+ = 5V
8 VEE = GND
0
6
SUPPLY CURRENT (mA)
INPUT BIAS (μA)
–2
–3
–4
–5
2
ICC (LT1719S8)
0
–2
IEE (LT1719S8)
5
–25
0
25
50
75
8.0
7.5
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
RISING EDGE
(tPDLH)
FALLING EDGE
(tPDHL)
3
2
1
0
10
20
40
30
OUTPUT LOAD CAPACITANCE (pF)
50
1719 G07
50
25
75
0
TEMPERATURE (°C)
100
tPDLH
VCM = 1V
VSTEP = 100mV
7.0
100
I+ (LT1719S6)
TA = 25°C
VEE = GND
IS (LT1719S8)
3
2
ICC (LT1719S8)
1
0
–1
–2
IEE (LT1719S8)
–3
125
0
1
3
4
5
6
2
SUPPLY VOLTAGE, VCC = +VS OR V+ (V)
6.0
5.5
1719 G06
5V
OVERDRIVE = 5mV
OVERDRIVE = 20mV
3V
4.5
5V
4.0
–50 –25
5.5
CLOAD = 10pF
VEE OR V– = GND
+VS = VCC = V+
5.0
0
50
75
25
TEMPERATURE (°C)
7
Propagation Delay
vs Supply Voltage
3V
6.5
125
4
Propagation Delay
vs Temperature
4
0
VEE = –5V (LT1719S8)
1339 G05
Propagation Delay
vs Load Capacitance
5
–5.2
TEMPERATURE (°C)
1719 G04
6
–5.0
5
+IS (LT1719S8)
4
–6
–50
–7
–5 –4 –3 –2 –1 0 1 2 3 4
DIFFERENTIAL INPUT VOLTAGE (V)
V– = GND (LT1719S6)
6
I+ (LT1719S6)
–4
–6
7
–0.2
Quiescent Supply Current
vs Supply Voltage
SUPPLY CURRENTS (mA)
1
8
0
1719 G03
10
25°C
25°C
VSTEP = 100mV
OVERDRIVE = 20mV
+VS = VCC OR V+ = 5V
VEE OR V– = 0V
3.8
Quiescent Supply Current
vs Temperature
2
9
4.0
1719 G02
1719 G01
–1
+VS = VCC OR V+ = 5V
–5.4
–50 –25
PROPAGATION DELAY (ns)
VOS AND TRIP POINT VOLTAGE (mV)
3
Input Common Mode Limits
vs Temperature
100
125
1719 G08
5.0
tTPLH
tTPHL
25°C
VSTEP = 100mV
OVERDRIVE = 20mV
CLOAD = 10pF
VEE/V–= GND
4.5
tTPLH
4.0
tTPHL
VEE = –5V
(VCC, +VS = 5.5VMAX)
(LT1719S8 ONLY)
3.5
2.5
5.5 6.0
3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE, +VS = VCC OR V+ (V)
1719 G09
1719fa
5
LT1719
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
Output High Voltage
vs Load Current
OUTPUT VOLTAGE RELATIVE TO +VS (V)
+VS OR V+ = 5V
VIN = –10mV
OUTPUT VOLTAGE (V)
125°C
0.4
125°C
VCC = 2.7V
25°C
0.3
–55°C
0.2
0.1
4
12
16
8
OUTPUT SINK CURRENT (mA)
–55°C
25°C
–0.4
–0.6
–0.8
20
4
12
16
8
OUTPUT SOURCE CURRENT (mA)
5
CLOAD = 10pF
4
NO LOAD
20
0
10
20
30
40
FREQUENCY (MHz)
1719 G11
1719 G12
Shutdown Currents
vs Shutdown Voltage
5
IS
SUPPLY I+
CURRENT (mA)
3
SUPPLY
CURRENTS (mA)
CLOAD = 20pF
6
2
0
4
LT1719S8
2
1
ICC
–100
VS –4
4
LT1719S6
3
2
1
TA = 25°C
VEE = GND
+VS = VCC = 5V
SHDN PIN
CURRENT (μA)
SHDN PIN
CURRENT (μA)
7
3
Shutdown Currents
vs Shutdown Voltage
–50
25°C
+VS = 5V
8
25°C
VCC = 2.7V
1719 G10
0
9
+VS OR V+= 5V
VIN = 10mV
125°C
–0.2
–1.0
0
Supply Current vs Frequency
0.0
+VS SUPPLY CURRENT (mA)
Output Low Voltage
vs Load Current
VS –2
VS –1
VS –3
SHDN PIN VOLTAGE (V)
VS
0
–50
TA = 25°C
V+ = 5V
–100
V+ –4
1719 G13a
V+ –2
V+ –1
V+ –3
SHDN PIN VOLTAGE (V)
V+
1719 G13b
Shutdown Currents
vs Temperature
Wake-Up Delay
vs Temperature
700
SHUTDOWN = +VS – 0.5V
+IS
SHUTDOWN
PIN
CURRENT
1
+IS
0.1
600
WAKE-UP DELAY (ns)
SHUTDOWN CURRENTS (μA)
10
500
400
300
SHUTDOWN PIN OPEN
200
VCC = +VS = 5V
VEE = –5V
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1719 G14
100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1719 G15
1719fa
6
LT1719
PIN FUNCTIONS
LT1719S8
LT1719S6
VCC (Pin 1): Positive Supply Voltage for Input Stage.
–IN (Pin 1): Inverting Input of Comparator.
+ IN (Pin 2): Noninverting Input of Comparator.
V – (Pin 2): Negative Supply, Usually Grounded.
–IN (Pin 3): Inverting Input of Comparator.
+ IN (Pin3): Noninverting Input of Comparator.
VEE (Pin 4): Negative Supply Voltage for Input Stage and
Chip Substrate.
V+ (Pin 4): Positive Supply Voltage.
GND (Pin 5): Ground.
SHDN (Pin 6): Shutdown. Pull to ground to enable
comparator.
SHDN (Pin 6): Shutdown. Pull to ground to enable
comparator.
OUT (Pin 5): Output of Comparator.
OUT (Pin 7): Output of Comparator.
+VS (Pin 8): Positive Supply Voltage for Output Stage.
1719fa
7
LT1719
TEST CIRCUITS
Response Time Test Circuit
+Vs – VCM
(V+ – VCM)
0V
VCC – VCM
–100mV
1
25Ω
25Ω
0.1μF
PULSE
IN
0V
2
50k
3
130Ω
V1*
2N3866
0.01μF
8
+
DUT
LT1719S8
–
5
4
50Ω
7
10 × SCOPE PROBE
(CIN ≈ 10pF)
6(6)
0.01μF
VEE – VCM
1N5711
–3V
50Ω
–VCM
750Ω
400Ω
*V1 = –1000 • (OVERDRIVE + VTRIP+)
NOTE: RISING EDGE TEST SHOWN.
FOR FALLING EDGE, REVERSE LT1719 INPUTS
–5V
1719 TC02
±VTRIP Test Circuit
LTC203
BANDWIDTH-LIMITED TRIANGLE WAVE
~ 1kHz, VCM ±7.5V
VCC
14
15
2
1000 × VTRIP+
50k
1μF
10nF
+
50Ω
3
0.1μF
50Ω
DUT
LT1719
–
16
1
9
8
10k
1/2 LT1112
200k
–
1000 × VHYST
+
VCM
11
10
6
7
1000 × VOS
10k
LTC203
3
1/2 LT1638
+
100k
15
+
1μF
10nF
1
16
8
9
2.4k
–
100k
14
1000 × VTRIP–
100k
–
100k
2
1/2 LT1638
1/2 LT1112
–
0.15μF
6
NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.
200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS
WHEN DUT IS NOT POWERED
7
11
+
10
1719 TC01
1719fa
8
LT1719
APPLICATIONS INFORMATION
Power Supply Configurations (SO-8 Package)
The LT1719S8 has separate supply pins for the input and
output stages that allow flexible operation, accommodating
separate voltage ranges for the analog input and the output
logic. Of course, a single 3V/5V supply may be used by
tying + VS and VCC together as well as GND and VEE.
The minimum voltage requirement can be simply stated
as both the output and the input stages need at least 2.7V
and the VEE pin must be equal to or less than ground.
The following rules must be adhered to in any
configuration:
2.7V ≤ (VCC – VEE) ≤ 10.5V
2.7V ≤ (+ VS – GND) ≤ 6V
(+VS – VEE) ≤ 10.5V
VEE ≤ Ground
Although the ground pin need not be tied to system ground,
most applications will use it that way. Figure 1 shows three
common configurations. The final one is uncommon, but
it will work and may be useful as a level translator; the
input stage is run from – 5.2V and ground while the output
stage is run from 3V and ground. In this case the common mode input voltage range does not include ground,
so it may be helpful to tie VCC to 3V anyway. Conversely,
VCC may also be tied below ground, as long as the above
rules are not violated.
Input Voltage Considerations
The LT1719 is specified for a common mode range of
–100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
range is 100mV below VEE /V – to 1.2V below VCC /V+. The
criterion for this common mode limit is that the output still
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other
input signal can go outside the common mode limits, up
to the absolute maximum limits, and the output will retain
the correct polarity.
2.7V TO 6V
5V
VCC
+
VCC
+VS
LT1719S8
3V
+VS
LT1719S8
GND
–
+
GND
–
VEE
VEE
–5V
Single Supply
±5VIN, 3VOUT
10V
VCC
+
+VS
LT1719S8
+
3V
+VS
LT1719S8
GND
–
VCC
5V
VEE
GND
–
VEE
–5.2V
10VIN, 5VOUT
1719 F01
Front End Entirely Negative
Figure 1. Variety of SO-8 Power Supply Configurations
When either input signal falls below the negative common mode limit, the internal PN diode formed with the
substrate can turn on, resulting in significant current
flow through the die. An external Schottky clamp diode
between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate
diode from turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least – 400mV common mode.
However, the offset and hysteresis in this mode will increase
dramatically, to as much as 15mV each. The input bias
currents will also increase.
When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state can take as long as 1μs.
1719fa
9
LT1719
APPLICATIONS INFORMATION
The propagation delay does not increase significantly when
driven with large differential voltages, but with low levels
of overdrive, an apparent increase may be seen with large
source resistances due to an RC delay caused by the 2pF
typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection circuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.
The LT1719 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1719 outputs, a 4mV step can
be created at a 100Ω input source with only 0.02pF of
output to input coupling. The LT1719’s pinout has been
arranged to minimize problems by placing the sensitive
inputs away from the outputs, shielded by the power rails.
The input and output traces of the circuit board should
also be separated, and the requisite level of isolation is
readily achieved if a topside ground plane runs between
the output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.
Figure 2 shows a typical topside layout of the LT1719S8
on such a multilayer board. Shown is the topside metal
etch including traces, pin escape vias, and the land pads
for an SO-8 LT1719 and its adjacent X7R 10nF bypass
capacitors in the 1206 case. The same principles should
be used with the SOT 23-6.
1719 F02
Input Bias Current
Input bias current is measured with both inputs held at
1V. As with any PNP differential input stage, the LT1719
bias current flows out of the device. It will go to zero
on the higher of the two inputs and double on the lower
of the two inputs. With more than two diode drops of
differential input voltage, the LT1719’s input protection
circuitry activates, and current out of the lower input will
increase an additional 30% and there will be a small bias
current into the higher of the two input pins, of 4μA or
less. See the Typical Performance curve Input Current vs
Differential Input Voltage.
High Speed Design Considerations
Application of high speed comparators is often plagued by
oscillations. The LT1719 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
The ground trace from Pin 5 runs under the device up
to the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1719
and the bypass capacitors, which minimizes interference
from high frequency energy running around the ground
plane or power distribution traces.
The supply bypass should include an adjacent
10nF ceramic capacitor and a 2.2μF tantalum capacitor
no farther than 5cm away; use more capacitance on + VS
if driving more than 4mA loads. To prevent oscillations,
it is helpful to balance the impedance at the inverting and
noninverting inputs; source impedances should be kept
low, preferably 1kΩ or less.
1719fa
10
LT1719
APPLICATIONS INFORMATION
Shutdown Control
The LT1719 features a shutdown control pin for reduced
quiescent current when the comparator is not needed.
During shutdown, the inputs and the outputs become high
impedances. The LT1719 is enabled when the shutdown
input is pulled low with a threshold roughly two diode drops
below + VS or V+. Therefore, if driven by a standard TTL
gate, a pull-up resistor should be used. Because shutdown
is active high, this resistor adds little power drain during
shutdown. A logic high disables the comparator. The
LT1719S8 logic interface is based on the output power
rails, +VS and GND.
For applications that do not use the shutdown feature,
it may be helpful to tie the shutdown control to ground
through a 100Ω resistor rather than directly. This allows
the SHDN pin to be pulled high during debug or in-circuit
test (bed of nails) so that the output node can be wiggled
without damaging the low impedance output driver of
the LT1719.
Power Supply Sequencing
The LT1719S8 is designed to tolerate any power supply
sequencing at system turn-on and power down. In any
of the previously shown power supply configurations, the
various supplies can activate in any order without excessive current drain by the LT1719.
As always, the Absolute Maximum Ratings must not be
exceeded, either on the power supply terminals or the input
terminals. Power supply sequencing problems can occur
when input signals are powered from supplies that are
independent of the LT1719’s supplies. For the comparator inputs, the signals should be powered from the same
VCC and VEE supplies as the LT1719. For the shutdown
input, the signal should be powered from the same +VS
as the LT1719.
Hysteresis
The LT1719 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.
The input-output transfer characteristic is illustrated in
Figure 3 showing the definitions of VOS and VHYST based
upon the two measurable trip points. The hysteresis band
makes the LT1719 well behaved, even with slowly moving
inputs.
VOUT
The outputs of the LT1719 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1719 can drive DC
terminations of 200Ω or more, but lower characteristic
impedance traces can be used with series termination or
AC termination topologies.
VOH
The shutdown state is not guaranteed to be useful as a
multiplexer. Digital signals can have extremely fast edge
rates that may be enough to momentarily activate the
LT1719 output stage via internal capacitive coupling. No
damage to the LT1719 will result, but this could prove
deleterious to the intended recipient of the signal.
The LT1719 includes a FET pull-up on the shutdown control
pin (see the Simplified Schematic) as well as other internal structures to make the shutdown state current drain
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