LT3027EDD#PBF

LT3027 Dual 100mA, Low Dropout, Low Noise, Micropower Regulator with Independent Inputs U FEATURES DESCRIPTIO ■ The LT ®3027 is a dual, micropower, low noise, low dropout regulator with independent inputs. With an external 0.01µF bypass capacitor, output noise is a low 20µVRMS over a 10Hz to 100kHz bandwidth. Designed for use in battery-powered systems, the low 25µA quiescent current per channel makes it an ideal choice. In shutdown, quiescent current drops to less than 0.1µA. Shutdown control is independent for each channel, allowing for flexibility in power management. The device is capable of operating over an input voltage from 1.8V to 20V, and can supply 100mA of output current from each channel with a dropout voltage of 300mV. Quiescent current is well controlled in dropout. The LT3027 regulator is stable with output capacitors as low as 1µF. Small ceramic capacitors can be used without the series resistance required by other regulators. Internal protection circuitry includes reverse battery protection, current limiting and thermal limiting protection. The device is available as an adjustable device with a 1.22V reference voltage. The LT3027 regulator is available in the thermally enhanced 10-lead MSOP and low profile (0.75mm) 3mm × 3mm DFN packages. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low Noise: 20µVRMS (10Hz to 100kHz) Low Quiescent Current: 25µA/Channel Independent Inputs Wide Input Voltage Range: 1.8V to 20V Output Current: 100mA/Channel Very Low Shutdown Current: 3300pF 1.5 1.0 0.5 X5R 0 –20 –40 Y5V –60 –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF –100 –50 –25 0 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (µF) 50 25 75 0 TEMPERATURE (°C) 100 125 3027 F04 3027 F02 Figure 2. Stability Figure 4. Ceramic Capacitor Temperature Characteristics 3027fa 10 LT3027 U W U U APPLICATIO S I FOR ATIO Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 5’s trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. COUT = 10µF CBYP = 0.01µF ILOAD = 100mA For continuous normal conditions, the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. Table 1. MSE Package, 10-Lead MSOP COPPER AREA TOPSIDE* BACKSIDE VOUT 500µV/DIV 3027 F05 Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125°C). The power dissipated by the device will be made up of two components (for each channel): THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 40°C/W 2 2500mm 2 2 45°C/W 2500mm 2 2 50°C/W 2500mm 2 2 62°C/W 1000mm 100ms/DIV BOARD AREA 225mm 2 100mm 2 2500mm 2500mm 2500mm *Device is mounted on topside. Table 2. DD Package, 10-Lead DFN COPPER AREA TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 40°C/W 2 2500mm 2 2 45°C/W 2500mm 2 2 2500mm 50°C/W 2500mm2 62°C/W 1000mm 225mm 2 100mm2 2500mm2 2500mm 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN – VOUT), and *Device is mounted on topside. 2. GND pin current multiplied by the input voltage: (IGND)(VIN). The thermal resistance juncton-to-case (θJC), measured at the Exposed Pad on the back of the die is 10°C/W for the 10-lead MS package and 3°C for the 10-lead DFN package. The ground pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the sum of the two components listed above. Power dissipation from both channels must be considered during thermal analysis. The LT3027 regulator has internal thermal limiting designed to protect the device during overload conditions. Calculating Junction Temperature Example: Given an output voltage on the first channel of 3.3V, an output voltage of 2.5V on the second channel, an input voltage range of 4V to 6V, output current ranges of 0mA to 100mA for the first channel and 0mA to 50mA for the second channel, with a maximum ambient temperature of 50°C, what will the maximum junction temperature be? 3027fa 11 LT3027 U W U U APPLICATIONS INFORMATION The power dissipated by each channel of the device will be equal to: IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX)) where (for the first channel): IOUT(MAX) = 100mA VIN(MAX) = 6V IGND at (IOUT = 100mA, VIN = 6V) = 2mA so: P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W and (for the second channel): IOUT(MAX) = 50mA VIN(MAX) = 6V IGND at (IOUT = 50mA, VIN = 6V) = 1mA so: P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W The thermal resistance will be in the range of 40°C/W to 60°C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: (0.28W + 018W)(60°C/W) = 27.8°C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50°C + 27.8°C = 77.8°C Protection Features The LT3027 regulator incorporates several protection features which makes it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C. The input of the device will withstand reverse voltages of 20V. Current flow into the device will be limited to less than 1mA (typically less than 100µA) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The output of the LT3027 can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20V. The output will act like an open circuit; no current will flow out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN pins will turn off the device and stop the output from sourcing the short-circuit current. The ADJ pins can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. In situations where the ADJ pins are connected to a resistor divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 7V. The 13V difference between output and ADJ pin divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 2.6k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. When the IN pins of the LT3027 are forced below the corresponding OUT pins or the OUT pins are pulled above the IN pins, input current will typically drop to less than 2µA. This can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN pins will have no effect on the reverse output current when the output is pulled above the input. 3027fa 12 LT3027 U TYPICAL APPLICATIO S Noise Bypassing Slows Startup, Allows Outputs to Track VSHDN1/SHDN2 1V/DIV VIN1 3.7V TO 20V VOUT1 1V/DIV VOUT2 1V/DIV 10µF 0.01µF BYP1 VIN2 2.9V TO 20V 3.3V AT 100mA OUT1 IN1 1µF 422k 249k IN2 LT3027 Startup Time 1µF 10µF 0.01µF 261k BYP2 SHDN2 GND ADJ2 STARTUP TIME (ms) SHDN1 100 2.5V AT 100mA OUT2 OFF ON 3027 TA02b 2ms/DIV ADJ1 249k 3027 TA02a 10 1 0.1 100 10 1000 10000 CBYP (pF) 3027 TA02c Power Supply Controller Provides Coincident Tracking Q1 VIN 3.3V 1µF 3.3V 10nF 154k VOL GATE RAMP ON 255k IN1 FB1 100k IN2 BYP1 ADJ1 LTC2923 243k RAMPBUF 255k STATUS SDO 2.5V OUT1 10µF LT3027 SHDN1 BYP2 SHDN2 OUT2 TRACK1 121k 115k TRACK2 GND FB2 1.8V ADJ2 GND 93.1k 243k 115k 10µF 3027 TA04 3027fa 13 LT3027 U PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.38 ± 0.10 10 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD10) DFN 1005 5 0.25 ± 0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1 0.75 ±0.05 0.00 – 0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3027fa 14 LT3027 U PACKAGE DESCRIPTIO MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1663) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 ± 0.102 (.110 ± .004) 5.23 (.206) MIN 0.889 ± 0.127 (.035 ± .005) 1 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136) 10 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0.254 (.010) DETAIL “A” 0° – 6° TYP 1 2 3 4 5 GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MSE) 1005 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3027fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT3027 U TYPICAL APPLICATIO S Startup Sequencing VIN1 3.7V TO 20V 1µF 10µF 0.01µF BYP1 VIN2 2.9V TO 20V 3.3V AT 100mA OUT1 IN1 422k 35.7k 249k 28k Turn-On Waveforms Turn-Off Waveforms ADJ1 IN2 LT3027 1µF 2.5V AT 100mA OUT2 OFF ON 10µF 0.01µF SHDN1 BYP2 SHDN2 GND 261k VSHDN1 1V/DIV VSHDN1 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV ADJ2 0.47µF 249k 2ms/DIV 3027 TA03b 2ms/DIV 3027 TA03c 3027 TA03a RELATED PARTS PART NUMBER LT1761 DESCRIPTION 100mA, Low Noise Micropower, LDO LT1762 150mA, Low Noise Micropower, LDO LT1763 500mA, Low Noise Micropower, LDO LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO LTC1844 150mA, Very Low Drop-Out LDO LT1962 300mA, Low Noise Micropower, LDO LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO LT1964 200mA, Low Noise Micropower, Negative LDO LT3020 100mA, VLDO in MSOP LT3023 Dual 100mA, Low Noise Micropower, LDO LT3024 Dual 100mA/500mA, Low Noise Micropower, LDO LT3028 Dual 100mA/500mA, Low Noise Micropower, LDO with Independent Inputs COMMENTS Low Noise < 20µVRMS, Stable with 1µF Ceramic Capacitors, VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.3V, IQ = 20µA, ISD =