LT3040
20V, 200mA, Ultralow Noise, Ultrahigh PSRR
Precision DAC/Reference Buffer
FEATURES
DESCRIPTION
Ultralow Wideband Noise: 1.2µVRMS (10Hz to
100kHz)
nn Ultralow 1/f Noise: 0.6µV
P-P (0.1Hz to 10Hz)
nn Ultralow Spot Noise: 4nV/√Hz at 1kHz and Above
nn Ultrahigh PSRR: 73dB at 1MHz
nn Ultralow Input Offset: 125µV
nn Output Source Current: 200mA
nn Wide Input Voltage Range: 1.8V to 20V
nn Rail to Rail Output Voltage Range: 0V to 15V
nn Single Capacitor Improves Noise and PSRR
nn Fast Start-Up for V Pin
IN
nn FAULT Flag
nn High Bandwidth: 1MHz
nn Low Dropout Voltage: 350mV
nn Programmable Current Limit
nn Precision Enable/UVLO
nn Parallelable for Lower Noise and Higher Current
nn Internal Current Limit with Foldback
nn Minimum Output Capacitor: 4.7µF Ceramic
nn Reverse Supply and Reverse Current Protection
nn Thermal Limit with Hysteresis
nn 10-Lead 3mm × 3mm DFN and 12-Lead MSOP
The LT®3040 is a high performance, robust Voltage Output
Reference/DAC buffer that employs a unique architecture
that seeks to maintain the precision and accuracy of the
Reference or DAC while sourcing up to 200mA. It features ADI’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive, high accuracy systems.
Designed as an advanced voltage buffer for Voltage Output
References/DACs, the LT3040 features extremely low 1/f
noise, very low wideband noise, excellent PSRR over a
wide frequency range and low dropout performance – a
typical 350mV dropout at 200mA of source current.
nn
Operating quiescent current is nominally 2.5mA and drops
to 12V. Some level of
output current is provided at all V+ – VOUT differential voltages. Consult the
Typical Performance Characteristics graph for current limit vs V+ – VOUT.
Note 13: For an output voltage less then 1V, the LT3040 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-VFB differential is guaranteed by design.
Note 15: The bias current cancellation circuit used to cancel any IR drop
across external resistors does not operate for VIN pin voltages below
100mV due to circuit limitations. As a result, the bias current increases
exponentially below this voltage. See Typical Performance Characteristics
Note 16: The Offset Voltage specification does not include the effects of
line and load regulation.
Note 17: Deviations in output voltage from the reference setpoint are
cumulative; errors in output regulation due to offset, line and load
regulation add up.
Note 18: Hysteresis in the offset voltage is created by package stress
that differs depending on whether the IC was previously at a higher
or lower temperature. Offset voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis measures the maximum output change for
the averages of three hot or cold temperature cycles. For instruments
that are stored at well controlled temperatures (within 20 to 30 degrees
of operational temperature), it’s usually not a dominant error source.
Typical hysteresis is the worst-case of 25°C to cold to 25°C to hot to 25°C,
preconditioned by one thermal cycle.
Note 19: To achieve rail-to-rail output operation, LT3040 uses either a PNP
or a NPN input differential pair. There is a transition from the PNP to NPN
differential pair at around the 0.9V with a typical hysteresis of about 35mV.
See Applications Section for more information.
Note 20: Long-term stability typically has a logarithmic characteristic.
Changes after 1000 hours tend to be much smaller than before that time.
Total drift in the second thousand hours is normally less than one-third
that of the first thousand hours with a continuing trend toward reduced
drift with time. Long-term stability is also affected by differential stresses
between the IC and the board material created during board assembly.
Note 21: Dropout voltage measurements are done by forcing a voltage at
the VIN pin.
Rev. 0
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5
LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage
750
Input Offset Voltage
750
100
V+ = 2V
VIN = 1.25V
625 ILOAD = 1mA
N = 4448
500
375
250
125
V+ = 2V
ILOAD = 1mA
80
60
40
500
VOS (µV)
NUMBER OF UNITS
V+ = 2V
VIN = 0.3V
625 ILOAD = 1mA
N = 4448
NUMBER OF UNITS
TJ = 25°C, unless otherwise noted.
375
250
20
0
–20
–40
–60
125
VIN 0.3V
VIN 1.25V
–80
0
–120 –90 –60 –30 0
30 60
DISTRIBUTION (µV)
90
0
–120 –90 –60 –30 0
30 60
DISTRIBUTION (µV)
120
90
3040 G01
750
500
20
0
–20
–40
–60
–80
–20
–10
0
10
IVIN (nA)
20
0
–30
30
V+ = 20V
80
ILOAD = 1mA
60
–20
–10
3040 G04
Input Bias Current
100
0
10
IVIN (nA)
20
–100
–50
30
TJ = 125°C
TJ = 25°C
TJ = –40°C
+
60
80
60
20
20
20
PNP TO NPN DIFF
PAIR TRANSITION
–60
VOS (µV)
40
–40
0
–20
IOS CANCELLATION STOPS
WORKING BELOW 0.1V
–80
0
3040 G07
–100
–60
PNP TO NPN DIFF
PAIR TRANSITION
–80
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VIN (V)
0
0
2
4
6
8
10
VIN (V)
–80
12
14
16
3040 G08
PNP TO NPN DIFF
PAIR TRANSITION
–20
–40
–40
–60
125
Input Offset Voltage
40
–20
100
100
40
0
0
25
50
75
TEMPERATURE (°C)
3040 G06
TJ = 125°C
TJ = 25°C
TJ = –40°C
V = 20V
ILOAD = 1mA
80
–25
3040 G05
Input Bias Current
100
IVIN (nA)
IVIN (nA)
VIN = 0.3V
VIN = 1.25V
40
1000
250
0
–30
–100
125
60
250
125
V+ = 2V
ILOAD = 1mA
80
IVIN (nA)
NUMBER OF UNITS
NUMBER OF UNITS
375
100
Input Bias Current
100
V+ = 2V
VIN = 1.25V
1250 ILOAD = 1mA
N = 4448
875 VIN = 0.3V
ILOAD = 1mA
750 N = 4448
500
0
25
50
75
TEMPERATURE (°C)
3040 G03
Input Bias Current
1500
V+ = 2V
625
–25
3040 G02
Input Bias Current
1000
–100
–50
120
V+ = 20V
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 1mA
–100
0.0
0.2
TJ = 125°C
TJ = 25°C
TJ = –40°C
0.4
0.6
VIN (V)
0.8
1
3040 G09
Rev. 0
6
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LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Line Regulation
0
80
–1.0
–2.0
60
–2.0
–4.0
40
–3.0
20
–4.0
0
PNP TO NPN DIFF
PAIR TRANSITION
–60
–80
–100
0
2
4
–7.0
–8.0
TJ = 125°C
TJ = 25°C
TJ = –40°C
6
8
10
VIN (V)
–6.0
12
14
–10.0
16
VIN = 0.3V
VIN = 1.25V
175.0
4
250.0
75.0
50.0
25.0
0
–25.0
100
V+ = 2V
80
60
175.0
40
150.0
20
125.0
100.0
50.0
–60
VIN = 0.3V
VIN = 1.25V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
400
IVIN (nA)
250
200
150
100
–40
0
–80
–50
–100
–100
20 40 60 80 100 120 140 160 180 200
ILOAD (mA)
3040 G16
2
4
6
8
10 12 14 16 18 20
V+ (V)
3040 G15
120
110
100
90
80
70
60
50
50
–60
0
Power Supply Ripple Rejection
TJ = 125°C
TJ = 25°C
TJ = –40°C
300
0
–80
–100
VIN = 2.5V
ILOAD = 1mA
450
350
–20
VIN = 0.3V
VIN = 1.25V
–40
Input Bias Current
40
125
0
75.0
500
60
100
–20
3040 G14
VIN = 0.3V
VIN = 1.25V
ILOAD = 1mA
80
3040 G13
0
0
25
50
75
TEMPERATURE (°C)
Input Bias Current
100
ILOAD = 1mA TO 200mA
0
–50
300
20
–25
VIN = 0.3V
VIN = 1.25V
3040 G12
200.0
Input Bias Current
100
V+ = 2V to 20V
ILOAD = 1mA
–20.0
–50
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
25.0
10
ILOAD (mA)
–16.0
V+ = 2V
225.0
VOS LOAD REGULATION (µV)
100.0
1
–14.0
Load Regulation
125.0
VOS (µV)
2
–12.0
3040 G11
V+ = 2V
150.0
–50.0
0
–10.0
–18.0
ILOAD = 1mA
3040 G10
Load Regulation
200.0
VIN = 0.3V
VIN = 1.25V
–9.0
–8.0
IVIN (nA)
V+ = 20V
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 1mA
–5.0
–6.0
PSRR (dB)
–20
VOS LINE REGULATION (µV)
0
–40
IVIN (nA)
Line Regulation
100
VOS (µV)
VOS (µV)
Input Offset Voltage
TJ = 25°C, unless otherwise noted.
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V+ TO VIN DIFFERENTIAL (V)
3040 G17
V+ = 5V
40 V = 3.3V
IN
CIN = 4.7µF
30 COUT = 4.7µF
ILOAD = 200mA
CIN = 0.47µF
20
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
3040 G18
Rev. 0
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7
LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Ripple Rejection
TJ = 25°C, unless otherwise noted.
Power Supply Ripple Rejection
110
110
100
100
100
90
90
90
80
80
80
70
60
PSRR (dB)
110
PSRR (dB)
120
PSRR (dB)
120
70
60
50
90
140
FAST START THRESHOLD (mV)
80
70
PSRR (dB)
VIN = 3.3V
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
f = 100kHz
f = 500kHz
f = 1MHz
f = 2MHz
20
10
0
0
1
2
3
4
SUPPLY-TO-OUTPUT DIFFERENTIAL (V)
V+ = 20V
100
80
60
PNP TO NPN DIFFERENTIAL
PAIR TRANSITION
40
0
5
0
2
4
6
14
40
TURN OFF
0
25
50
75
TEMPERATURE (°C)
60
40
100
125
3040 G25
–25
0
25
50
75
TEMPERATURE (°C)
3040 G23
100
125
3040 G24
Fast Start Current Limit
20
18
V+ = 2V
VFS = VIN + 0.2V
VIN = 0.3V
VIN = 1.25V
16
14
12
10
8
6
14
12
10
8
6
4
4
2
2
0
TURN OFF
0
–50
16
VIN PIN CURRENT (mA)
60
–25
12
16
80
0
–50
8
10
VIN (V)
V+ = 20V
VFS = VIN + 0.2V
18
TURN ON
20
80
Fast Start Current Limit
100
TURN ON
100
20
20
V+ = 2V
VIN = 1.25V
CIN = 2.2µF
V+ = 2V
VIN = 0.3V
CIN = 2.2µF
120
20
VIN PIN CURRENT (mA)
120
140
120
Fast Start Threshold Voltage
140
Fast Start Threshold Voltage
160
TURN ON
TURN OFF
CIN = 2.2µF
3040 G22
160
3040 G21
Fast Start Threshold Voltage
160
30
V+ = V IN + 2V
40 C = 4.7µF
IN
VIN = 3.3V
30 COUT = 4.7µF
ILOAD = 200mA
VIN = 0.3V
20
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
FAST START THRESHOLD (mV)
Power Supply Rejection Ratio
40
50
3040 G20
100
50
60
V+ = 5V
ILOAD = 1mA
40 V = 3.3V
ILOAD = 50mA
IN
ILOAD = 100mA
30 CIN = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
20
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
3040 G19
60
70
50
V+ = 5V
40 V = 3.3V
IN
COUT = 4.7µF
30 CIN = 4.7µF
ILOAD = 200mA
COUT = 22µF
20
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
FAST START THRESHOLD (mV)
Power Supply Ripple Rejection
120
0
2
4
6
8
10
VIN (V)
12
14
16
3040 G26
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3040 G27
Rev. 0
8
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LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Time with and without
Fast Start Enabled
TJ = 25°C, unless otherwise noted.
Noise Spectral Density
Noise Spectral Density
100
100
0.25V/DIV
VOUT WITH FAST
START DISABLED
VOUT WITH FAST
START ENABLED
V+ = 2V
RIN = 1kΩ
CIN = 2.2µF
ILOAD = 1mA
10
1
V+ = 5V
VIN = 3.3V
COUT = 4.7µF
ILOAD = 200mA
3040 G28
2ms/DIV
OUTPUT NOISE (nV/√Hz)
OUTPUT NOISE (nV/√Hz)
REFERENCE VOLTAGE
POWERED UP
0.1
10
100
10
1
CIN = 470nF
CIN = 4.7µF
CIN = 22µF
1k
10k 100k
FREQUENCY (Hz)
1M
0.1
10M
V+ = 5V
VIN = 3.3V
CIN = 4.7µF
ILOAD = 200mA
10
100
COUT = 4.7µF
COUT = 22µF
1k
10k 100k
FREQUENCY (Hz)
1M
3040 G29
Noise Spectral Density
Noise Spectral Density
1
V+ = 5V
VIN = 3.3V
CIN = 4.7µF
COUT = 4.7µF
100
1k
10k 100k
FREQUENCY (Hz)
1M
10
1
0.1
10M
V+ = V IN + 2V
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
10
100
1k
10k 100k
FREQUENCY (Hz)
VIN = 3.3V
VIN = 0.3V
1M
3040 G31
1k
OUTPUT NOISE (V/√Hz)
OUTPUT NOISE (nV/√Hz)
10
0.1
10M
100
V+ = 5V
VIN = 3.3V
CIN = 4.7µF
COUT = 4.7µF
1
FREQUENCY (Hz)
10
1
FREQUENCY (Hz)
Integrated RMS Output Noise
(10Hz to 100kHz)
2.0
VIN = 0.3V
VIN = 3.3V
1.8
100
V+ = V IN + 2V
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
10
0.1
10
3040 G33
Noise Spectral Density
ILOAD = 1mA
ILOAD = 20mA
10
0.1
V+ = 5V
VIN = 3.3V
COUT = 4.7µF
ILOAD = 200mA
3040 G32
Noise Spectral Density
1k
CIN = 4.7µF
CIN = 22µF
100
RMS OUTPUT NOISE (µVRMS)
10
Noise Spectral Density
1k
OUTPUT NOISE (nV/√Hz)
ILOAD = 1mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 200mA
10
0.1
3040 G30
100
OUTPUT NOISE (nV/√Hz)
OUTPUT NOISE (nV/√Hz)
100
10M
1
FREQUENCY (Hz)
3040 G34
1.6
1.4
1.2
1.0
0.8
0.6
V+ = 4.5V BATTERY
VIN = 3.3V
CIN = 4.7µF
COUT = 4.7µF
0.4
0.2
10
3040 G35
0
0
20 40 60 80 100 120 140 160 180 200
LOAD CURRENT (mA)
3040 G36
Rev. 0
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9
LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
Quiescent Current in Shutdown
4.0
4.0
1.8
3.5
3.5
1.6
1.4
1.2
1.0
0.8
V+ = V
0.4
CIN = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
0.2
0
OUT + 2V
0
1.5
3
3.0
2.5
2.0
1.5
V+ = 2V
1.0
VEN/UV = V+
VIN = 1.25V
ILOAD = 10µA
0.5
0
–50
4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)
–25
0
25
50
75
TEMPERATURE (°C)
100
3040 G37
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
VEN/UV
VIN = 1.25V
ILOAD = 10µA
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
2.5
2.0
1.5
1.0
0
TJ = 125°C
TJ = 25°C
TJ = –40°C
0
2
4
V+ = 20V
VEN/UV = V+
ILOAD = 10µA
6
8
10 12
OUTPUT VOLTAGE (V)
14
ILOAD = 200mA
ILOAD = 150mA
100
50
0
–50
–25
300
250
200
150
100
0
25
50
75
TEMPERATURE (°C)
100
125
TJ = 125°C
TJ = 25°C
TJ = –40°C
50
0
16
0
20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA)
3040 G42
GND Pin Current
10
9
VIN = 3.3V
8
6
5
4
3
2
0
25
50 75 100 125 150 175 200
OUTPUT CURRENT (mA)
3040 G43
3040 G44
ILOAD = 150mA
6
ILOAD = 100mA
5
4
ILOAD = 1mA
3
1
0
ILOAD = 200mA
7
2
1
ILOAD = 1mA
VIN = VOUT(NOMINAL) = 2.5V
RIN = 5kΩ
350
GND PIN CURRENT (mA)
150
GND PIN CURRENT (mA)
DROPOUT VOLTAGE (mV)
200
125
400
V+ = 4.3V
7
400
100
3040 G39
GND Pin Current
ILOAD = 100mA
0
25
50
75
TEMPERATURE (°C)
3040 G41
VIN = VOUT(NOMINAL) = 2.5V
RIN = 5kΩ
250
–25
Typical Dropout Voltage
3.0
8
300
V+ = 2V
0
–50
125
450
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
350
V+ = 20V
1.0
3.5
Dropout Voltage
450
1.5
500
3040 G40
500
2.0
4.0
0.5
0
2.5
Quiescent Current
= V+
3.5
3.0
3040 G38
Quiescent Current
4.0
VEN/UV = 0V
0.5
DROPOUT VOLTAGE (mV)
0.6
QUIESCENT CURRENT (µA)
2.0
QUIESCENT CURRENT (mA)
RMS OUTPUT NOISE (µVRMS)
Integrated RMS Output Noise
(10Hz to 100kHz)
TJ = 25°C, unless otherwise noted.
V+ = 5V
VIN = VOUT(NOMINAL) = 3.3V
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3040 G45
Rev. 0
10
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LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current
VIN = VOUT(NOMINAL) = 3.3V
RLOAD = 16.5Ω
7
6
RLOAD = 66Ω
5
RLOAD = 33Ω
4
3
2
RLOAD = 3.3kΩ
0
3.3
4.3
5.3 6.3 7.3 8.3
SUPPLY VOLTAGE (V)
9.3
1.28
FALLING UVLO
1.50
1.25
1.00
0.75
0.50
0
–50
10.3
–25
0
25
50
75
TEMPERATURE (°C)
100
3040 G46
EN/UV Pin Hysteresis
150
125
0
25
50
75
TEMPERATURE (°C)
100
3.50
3.00
2.50
2.00
1.50
1.00
0
125
TJ = 125°C
TJ = 25°C
TJ = –40°C
0
2
4
EN/UV PIN CURRENT (mA)
EN/UV PIN CURRENT (µA)
–30
–40
–50
–60
–70
–90
TJ = 125°C
TJ = 25°C
TJ = –40°C
–100
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)
V+ = 2V
7
6
5
4
V+ = 20V
3
2
1
0
6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)
0
2
4
6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)
3040 G51
Supply Pin Current
0.3
–20
–80
8
3040 G50
V+ = 2V
V+ = 2V
125
9
4.00
Reverse Enable Pin Current
–10
100
Enable Pin Current
3040 G49
0
0
25
50
75
TEMPERATURE (°C)
10
0.50
–25
–25
3040 G48
EN/UV PIN CURRENT (µA)
EN/UV PIN CURRENT (µA)
EN/UV PIN HYSTERESIS (mV)
V+ = 2V
100
–50
1.18
–50
125
V+ = 20V
4.50
225
V+ = 10V
V+ = 10V
1.22
Enable Pin Current
5.00
200
V+ = 2V
1.24
3040 G47
250
175
1.26
1.20
0.25
RLOAD = 330Ω
1
RISING UVLO
1.75
TURN-ON THRESHOLD (V)
GND PIN CURRENT (mA)
8
EN/UV Turn-On Threshold
1.30
Internal Current Limit
500
TJ = 125°C
TJ = 25°C
TJ = –40°C
450
VOUT = 0V
RILIM = 0Ω
400
OUTPUT CURRENT (mA)
9
Minimum Supply Voltage
2.00
SUPPLY ULVO THRESHOLD (V)
10
TJ = 25°C, unless otherwise noted.
0.2
0.1
350
V+ = 7.5V
300
V+ = 2.5V
250
200
150
100
50
0
0
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)
3040 G52
0
3040 G53
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3040 G54
Rev. 0
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11
LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
Internal Current Limit
300
250
200
150
START OF FOLDBACK
350
300
250
200
150
100
100
50
50
–25
450
400
350
0
–50
VOUT = 0V
RILIM = 0Ω
450
0
25
50
75
TEMPERATURE (°C)
100
0
125
2
4
50
V+ = 2.5V
40
30
140
120
250
200
100
125
0
10
OUTPUT SINK CURRENT (mA)
IFAULT (nA)
0
–50
20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA)
10
5
125
3040 G61
0
25
50
75
TEMPERATURE (°C)
9
8
7
6
5
4
3
2
0
TJ = 125°C
TJ = 25°C
TJ = –40°C
0
2
4
6
100
125
Output Overshoot Recovery
Current Sink
10
1
100
–25
3040 G60
V+ = 5V
VIN = 3.3V
9
15
0
25
50
75
TEMPERATURE (°C)
20
Output Overshoot Recovery
Current Sink
VFAULT = 2V
VFAULT = 20V
–25
40
V+ = 2.5V
V+ = 5V
V+ = 10V
3040 G59
FAULT Pin Leakage Current
0
–50
80
60
3040 G58
20
100
150
0
125
180
300
50
100
FAULT Output Low Voltage
160
100
0
25
50
75
TEMPERATURE (°C)
0
25
50
75
TEMPERATURE (°C)
200
350
10
–25
–25
3040 G57
400
20
0
–50
0
–50
VFAULT (mV)
OUTPUT CURRENT (µA)
OUTPUT CURRENT (mA)
80
V+ = 7.5V
V+ = 2.5V
150
50
VILIM = 0V
VIN = 1.25V
450
70
V+ = 7.5V
200
ILIM Pin Current
500
VOUT = 0V
RILIM = 2.49kΩ
60
250
3040 G56
Programmable Current Limit
90
300
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
3040 G55
100
350
100
TJ = 125°C
TJ = 25°C
TJ = –40°C
0
VOUT = 0V
RILIM = 625Ω
400
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
400
V+ = 20V
VOUT = 0V
RILIM = 0Ω
Programmable Current Limit
500
8
10 12 14 16 18 20
VOUT – VIN (mV)
3040 G62
OUTPUT SINK CURRENT (mA)
450
Internal Current Limit
500
OUTPUT CURRENT (mA)
500
TJ = 25°C, unless otherwise noted.
8
V+ = 5V
VIN = 3.3V
VOUT – VIN = 7.5mV
7
6
5
4
3
2
1
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3040 G63
Rev. 0
12
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LT3040
TYPICAL PERFORMANCE CHARACTERISTICS
10.0
VOUT Forced Above VOUT(NOMINAL)
V+ = 5V
VIN = 3.3V
RIN = 5kΩ
9.0
8.0
TJ = 25°C, unless otherwise noted.
Load Transient Response
200mA/DIV
Line Transient Response
LOAD STEP
500mV/DIV
SUPPLY VOLTAGE
CURRENT (mA)
7.0
6.0
5.0
10mV/DIV OUTPUT VOLTAGE
INPUT CURRENT
4.0
OUTPUT VOLTAGE
3.0
OUTPUT CURRENT
2.0
20µs/DIV
V+ = 5V
VIN = 3.3V
COUT = 4.7µF
CIN = 0.47µF
LOAD STEP = 10mA TO 200mA
1.0
0
1mV/DIV
4
5
6
7 8 9 10 11 12 13 14 15
OUTPUT VOLTAGE (V)
3040 G64
Line Transient Response
3040 G65
V+ = 4V to 4.5V
3040 G66
4µs/DIV
VIN = 3.3V
COUT = 4.7µF
CIN = 0.47µF
ILOAD = 200mA
tRISE = tFALL = 100ns
Output Noise: 0.1Hz to 10kHz
Output Noise: 10Hz to 100kHz
500mV/DIV
SUPPLY VOLTAGE
0.2µV/DIV
5µV/DIV
1mV/DIV
OUTPUT VOLTAGE
V+ = 4V to 4.5V
VIN = 3.3V
COUT = 4.7µF
CIN = 0.47µF
ILOAD = 200mA
tRISE = tFALL = 1µs
4µs/DIV
3040 G67
V+ = 4V
1s/DIV
VIN = 2.5V (LTC6655 SUPPLYING VIN)
COUT = 4.7µF
CIN = 4.7µF
RIN = 5kΩ
ILOAD = 200mA
3040 G68
V+ = 5V
3040 G69
1ms/DIV
VIN = 3.3V (LT3042 SUPPLYING VIN)
COUT = 4.7µF
CIN = 4.7µF
RIN = 5kΩ
ILOAD = 200mA
Rev. 0
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13
LT3040
PIN FUNCTIONS
(DFN/MSOP)
V+ (Pins 1, 2/Pins 1, 2, 3): Supply. These pins supply
power to the buffer. The LT3040 requires a bypass capacitor at the V+ pin. In general, a battery’s output impedance rises with frequency, so include a bypass capacitor
in battery-powered applications. While a 4.7µF supply
bypass capacitor generally suffices, applications with
large load transients may require higher supply capacitance to prevent supply droop. The LT3040 withstands
reverse voltages on V+ with respect to GND, VFB and OUT.
In the case of a reversed supply, which occurs if a battery
is plugged-in backwards, the LT3040 acts as if a diode is
in series with its input. Hence, no reverse current flows
into the LT3040 and no negative voltage appears at the
load. The device protects itself and the load.
EN/UV (Pin 3/Pin 4): Enable/UVLO. Pulling the LT3040’s
EN/UV pin low places the part in shutdown. Quiescent
current in shutdown drops to less than 1µA and the output
voltage turns off. Alternatively, the EN/UV pin can set a V+
supply under-voltage lockout (UVLO) threshold using a
resistor divider between V+, EN/UV and GND. The LT3040
typically turns on if the EN/UV voltage exceeds 1.24V on
its rising edge, with a 170mV hysteresis on its falling
edge. The EN/UV pin can be driven above the supply voltage and maintain proper functionality. If unused, tie EN/
UV to V+. Do not float the EN/UV pin.
FAULT (Pin 4/Pin 5): Fault Flag. FAULT is an open drain pin
that indicates an OUT pin fault. FAULT pulls low if the fast
start circuitry is active (See FS pin description for more
details). FAULT pin also pulls low if the output is not in
regulation due to current limit, thermal shutdown, the part
in dropout and UVLO. If this functionality is not used, float
the FAULT pin. A parasitic substrate diode exists between
the FAULT pin and GND pin of the LT3040; do not drive
FAULT more than 0.3V below GND. FAULT functionality
is valid only when the part is powered on and enabled.
ILIM (Pin 5/Pin 6): Current Limit Programming.
Connecting a resistor between ILIM and GND programs
the current limit. For best accuracy, Kelvin connect this
resistor directly to the LT3040’s GND pin. The programming scale factor is nominally 125mA • kΩ. The ILIM pin
sources current proportional (1:400) to output current;
therefore, it also serves as a current monitoring pin with
a 0V to 300mV range. If the programmable current limit
functionality is not needed, tie ILIM to GND. A parasitic
substrate diode exists between ILIM and GND pins of the
LT3040; do not drive ILIM more than 0.3V below GND
during normal operation or during a fault condition.
FS (Pin 6/Pin 7): Fast Start. Connecting this pin across
an input low pass filter resistor (see Typical Application)
fast starts the LT3040. Fast Start Circuitry is typically triggered active if VFS – VIN ≥ 100mV and stays active until
VFS – VIN ≤ 7mV. If the fast start circuit is active, it typically sources 10mA of current into the VIN pin (See Fast
Start under Applications Information section). If fast start
functionality is not needed, connect this pin to VIN.
VIN (Pin 7/Pin 8): Input. This pin is the noninverting input
of the error amplifier and the regulation set-point for the
LT3040. The LT3040’s output voltage is determined by
VIN. Output voltage range is from 0V to 15V. Adding a
capacitor from VIN to GND improves noise, PSRR and
transient response at the expense of increased start- up
time. A parasitic substrate diode exists between VIN and
GND pins of the LT3040; do not drive VIN more than
0.3V below GND during normal operation or during a
fault condition. VIN is internally clamped to VFB by a 1.5V
clamp. Refer to the Power Supply Sequencing section in
Applications Information for additional details.
GND (Pin 8, Exposed Pad Pin 11/Pin 9, Exposed Pin
Pad 13): Ground. The exposed backside is an electrical
connection to GND. To ensure proper electrical and thermal performance, solder the exposed backside to the PCB
ground and tie it directly to the GND pin.
VFB (Pin 9/Pin 10): Output Feedback. This pin is the inverting input to the error amplifier. This pin should always be
tied to OUT pin in unity gain feedback. For optimal transient performance and load regulation, Kelvin connect
VFB directly to the output capacitor and the load. Also, tie
the GND connections of the output capacitor and the VIN
pin capacitor directly together. Moreover, place the supply
and output capacitors (and their GND connections) very
close together. A parasitic substrate diode exists between
VFB and GND pins of the LT3040; do not drive VFB more
than 0.3V below GND during normal operation or during
a fault condition.
Rev. 0
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LT3040
PIN FUNCTIONS
(DFN/MSOP)
OUT (Pin 10/Pins 11, 12): Output. This pin supplies
power to the load. For stability, use a minimum 4.7µF
output capacitor with an ESR below 50mΩ and an ESL
below 2nH. Large load transients require larger output
capacitance to limit peak voltage transients. Refer to the
Applications Information section for more information
on output capacitance. A parasitic substrate diode exists
between OUT and GND pins of the LT3040; do not drive
OUT more than 0.3V below GND during normal operation
or during a fault condition.
BLOCK DIAGRAM
V+
CV+
3
V+
1, 2
EN/UV
ENABLE
COMPARATOR
+
–
BIAS
–
+
QFS
+
–
+
–
INPUT
UVLO
FAST START
COMPARATOR
INTERNAL
CURRENT LIMIT
V+ UVLO
CURRENT LIMIT
THERMAL SHDN
DROPOUT
VIN-TO-VFB
PROTECTION
CLAMP
FAULT
LOGIC
GND
8
VIN
6
FS
7
VIN
PROGRAMMABLE
CURRENT LIMIT
9
VFB
10
VOUT
RLOAD
COUT
–
+
FAST
START
DISABLE
LOGIC
OUT
1.5V
+
–
FAULT
QPWR
OUTPUT OVERSHOOT
RECOVERY
1.24V
THERMAL
SHDN
4
QP
QC
DRIVER
–
+
+
–
270Ω
+
–
300mV
+
–
300mV
5
ILIM
RILIM
RIN
CIN
3040 BD
Rev. 0
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15
LT3040
APPLICATIONS INFORMATION
The LT3040 is easy to use and incorporates all of the protection features expected in a high-performance voltage
buffer. Included are short-circuit protection, safe operating area protection, reverse supply voltage protection,
reverse current protection and thermal shutdown with
hysteresis.
100
80
60
40
20
VOS (µV)
The LT3040 is a high performance low dropout voltage
buffer featuring ADI’s ultralow noise (4nV/√Hz at 10kHz)
and ultrahigh PSRR (73dB at 1MHz) architecture for powering noise sensitive applications. Designed as a highperformance rail-to-rail voltage buffer, the LT3040 can be
easily paralleled to further reduce noise, increase output
current and spread heat on the PCB. The device additionally features programmable current limit, fast start-up
capability and fault indicator flag.
0
–20
–40
–60
VIN RISING
VIN FALLING
–80
–100
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0
VIN (V)
3040 F01
Figure 1. PNP to NPN Diff Pair Transition
100
90
Output Voltage
TJ = 25°C
ILOAD=1mA
The LT3040’s rail-to-rail error amplifier allows for a wide
output voltage range from 0V to V+ minus dropout—up
to 15V. A PNP-based input pair is active for 0V to ~0.9V
output and an NPN-based input pair is active for output
voltages greater than ~0.9V, with an abrupt transition
between the two input pairs at ~0.9V output with approximately 35mV of hysteresis. The NPN-based input pair is
designed to offer the best overall performance. Refer to
the Electrical Characteristics table for details on offset
voltage, VIN offset pin current, output noise and PSRR
variation with the error amp input pair.
The PNP and the NPN input pairs are trimmed separately
for offset voltage. As a result, the PNP and the NPN offsets
could end up significantly different from each other within
the offset limits specified in the EC table. The offset voltage behavior in the transition region for a typical part is
as shown in Figure 1. The range of variation in the offset
voltage is shown in Figure 2.
The LT3040 always operates in unity gain configuration.
This allows the LT3040 to have loop gain, frequency
response and bandwidth independent of the output voltage. As a result, noise, PSRR and transient performance
do not change with output voltage. Moreover, since none
NUMBER OF UNITS
80
70
60
50
40
30
20
10
0
–150
–100 –50
0
50
100
150
VOS[VIN = 0.95V]–VOS[VIN = 0.85V] (µV)
3040 F02
Figure 2. PNP to NPN VOS Distribution
of the error amp gain is needed to amplify the VIN pin
voltage to a higher output voltage, output load regulation
is more tightly specified in the hundreds of microvolts
range and not as a fixed percentage of the output voltage.
If an application uses the LT3040 with a filter resistor from
FS to VIN or a current limit resistor into VIN, any leakage
paths to or from the VIN pin create errors in the output
voltage. If necessary, use high quality insulation (e.g.,
Teflon, Kel-F); moreover, cleaning of all insulating surfaces
to remove fluxes and other residues may be required.
High humidity environments may require a surface coating at the VIN pin to provide a moisture barrier.
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LT3040
APPLICATIONS INFORMATION
Minimize board leakage by encircling the VIN pin with a
guard ring operated at a potential close to itself—ideally
tied to the OUT pin. Guarding both sides of the circuit
board is recommended. Bulk leakage reduction depends
on the guard ring width. Leakages of 100nA into or out
of the VIN pin creates a 100µV error (with a 1kΩ resistor
connecting to VIN) in the reference voltage. Leakages of
this magnitude, coupled with other sources of leakage,
can cause significant errors in the output voltage, especially over wide operating temperature range. Figure 3
illustrates a typical guard ring layout technique.
1
10
2
9
3
11
7
5
6
CV+
RFAULT
FAULT
VIN
EN/UV
V+
LT3040
FS
RIN
CIN
VIN
+
–
QPWR
OUT
QDRV
VOUT
VFB
RLOAD
GND ILIM
RILIM
COUT
3040 TA04
OUT
Figure 4. CIN and COUT Connections for Stability
8
4
V+
VIN
3040 F03
Figure 3. DD Package Guard Ring Layout
Since the VIN pin is a high impedance node, unwanted
signals may couple into the VIN pin and cause erratic
behavior. This is most noticeable when operating with
a minimum output capacitor at heavy load currents.
Bypassing the VIN pin with a small capacitance to ground
if allowed by the application resolves this issue—10nF is
normally sufficient.
Output Sensing
The LT3040’s VFB pin provides a Kelvin sense connection
to the output.
Additionally, as shown in Figure 4, it is very important for
stability to tie the VFB pin directly to the output capacitor
(COUT) and the GND side of the VIN pin capacitor (CIN)
directly to the GND side of COUT as well as keeping the
GND sides of supply capacitor (CV+) and COUT close
together. Refer to the PCB Layout Considerations section
for an example layout that meets these requirements.
The LT3040 requires an output capacitor for stability.
Given its high bandwidth (about 1MHz), ADI recommends
low ESR and ESL ceramic capacitors. A minimum 4.7µF
output capacitor with an ESR below 50mΩ and an ESL
below 2nH is required for stability. To minimize effects
of board inductances on the LT3040’s dynamic performance, Kelvin connect the VFB pin directly to the output
capacitor as well as Kelvin connect the GND side of the VIN
pin capacitor (CIN) directly to the GND side of the output
capacitor. Also, tie the supply capacitor’s GND connection as close as possible to the output capacitor’s GND
connection.
Given the high PSRR and low noise performance attained
using a single 4.7µF ceramic output capacitor, larger values of output capacitor only marginally improves the
performance because the regulator bandwidth decreases
with increasing output capacitance — hence, there is little
to be gained by using larger than the minimum 4.7µF output capacitor. Nonetheless, larger values of output capacitance do decrease peak output deviations during a load
transient. Note that bypass capacitors used to decouple
individual components powered by the LT3040 increase
the effective output capacitance.
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17
LT3040
APPLICATIONS INFORMATION
Give extra consideration to the type of ceramic capacitors used. They are manufactured with variety of dielectrics, each with different behavior across temperature and
applied voltage. The most common dielectrics used are
specified with EIS temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitance in the small packages, but they tend to have stronger voltage and temperature coefficients as shown in Figure 5 and Figure 6. When
used with a 5V regulator, a 16V 10µF Y5V capacitor can
exhibit an effective value as low as 1µF to 2µF for the DC
bias voltage applied over the operating temperature range.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
–20
20
–40
0
–60
Y5V
–80
–100
0
2
4
16
14
6
12
8 10
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
CHANGE IN VALUE (%)
0
X5R and X7R dielectrics result in more stable characteristics and are thus more suitable for LT3040. The X7R
dielectric has better stability across temperature, while
X5R is less expensive and is available in higher values.
Nonetheless, care must still be exercised when using
X5R and X7R capacitors. The X5R and X7R codes only
specify operating temperature range and the maximum
capacitance change over temperature. While capacitance
change due to DC bias for X5R and X7R is better than
Y5V and Z5U dielectrics, it can still be significant enough
to drop capacitance below sufficient levels. As shown
in Figure 7, capacitor DC bias characteristics tend to
improve as component case size increases, but verification of expected capacitance at the operating voltage is
highly recommended.
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
CHANGE IN VALUE (%)
–40
–60
–100
MURATA: X7R, 25V,4.7µF CERAMIC
1
5
10
15
DC BIAS (V)
20
25
3040 F07
40
Figure 7. Capacitor Voltage Coefficient for Different Case Sizes
X5R
0
–20
–40
Y5V
–60
–80
–100
–50
–20
–80
3040 F05
Figure 5. Ceramic Capacitor DC Bias Characteristics
1210, 2.2mm THICK
1206, 1.8mm THICK
0805, 1.4mm THICK
–25
0
25
75
50
TEMPERATURE (°C)
100
125
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress
upon it, similar to how a piezoelectric microphone works.
For a ceramic capacitor, this stress can be induced by
mechanical vibrations within the system or due to
thermal transients.
3040 F06
Figure 6. Ceramic Capacitor Temperature Characteristics
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18
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LT3040
APPLICATIONS INFORMATION
One measure of stability is the closed loop response of
the buffer. Figure 8 shows the closed loop response for
LT3040 with a 4.7µF output capacitor.
CLOSED LOOP GAIN (dB)
10
ILOAD = 200mA
ILOAD = 1mA
0
–10
–20 V+ = 2V
VIN = 1.25V
CIN = 10nF
COUT = 4.7µF
–30
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
3040 F08
Figure 8. LT3040 Closed Loop Response
Stability and Supply Capacitance
The LT3040 is stable with a minimum 4.7µF V+ pin capacitor. ADI recommends using low ESR ceramic capacitors.
In cases where long wires connect the power supply to
the LT3040’s supply and ground terminals, the use of low
value supply capacitors combined with a large load current can result in instability. The resonant LC tank circuit
formed by the wire inductance and the supply capacitor is
the cause and not because of LT3040’s instability.
The self-inductance, or isolated inductance, of a wire
is directly proportional to its length. The wire diameter,
however, has less influence on its self-inductance. For
example, the self-inductance of a 2-AWG isolated wire
with a diameter of 0.26” is about half the inductance
of a 30-AWG wire with a diameter of 0.01”. One foot of
30-AWG wire has 465nH of self-inductance.
Several methods exist to reduce a wire’s self-inductance.
One method divides the current flowing towards the
LT3040 between two parallel conductors. In this case,
placing the wires further apart reduces the inductance;
up to a 50% reduction when placed only a few inches
apart. Splitting the wires connect two equal inductors in
parallel. However, when placed in close proximity to each
other, their mutual inductance adds to the overall selfinductance of the wires — therefore a 50% reduction is
not possible in such cases. The second and more effective technique to reduce the overall inductance is to place
the forward and return current conductors (the supply
and ground wires) in close proximity. Two 30-AWG wires
separated by 0.02” reduce the overall inductance to about
one-fifth of a single wire.
If a battery mounted in close proximity powers the
LT3040, a 4.7µF supply capacitor suffices for stability.
However, if a distantly located supply powers the LT3040,
use a larger value input capacitor. Use a rough guideline
of 1µF (in addition to the 4.7µF minimum) per 8” of wire
length. The minimum supply capacitance needed to stabilize the application also varies with the output capacitance
as well as the load current. Placing additional capacitance
on the LT3040’s output helps. However, this requires significantly more capacitance compared to additional supply
bypassing. Series resistance between the power supply
and the LT3040 V+ input also helps stabilize the application; as little as 0.1Ω to 0.5Ω suffices. This impedance
dampens the LC tank circuit at the expense of dropout
voltage. A better alternative is to use a higher ESR tantalum or electrolytic capacitor at the LT3040 supply in
parallel with a 4.7µF ceramic capacitor.
Output Noise
The LT3040 offers many advantages with respect to noise
performance. Traditional buffers or linear regulators have
several sources of noise. The most critical noise sources
for a traditional regulator are its voltage reference, error
amplifier, noise from the resistor divider network used for
setting output voltage and the noise gain created by this
resistor divider. Many low noise regulators pin out their
voltage reference to allow for noise reduction by bypassing the reference voltage.
Unlike most linear regulators, the LT3040 does not use
an internal voltage reference. The external voltage source
(Voltage Reference/Voltage Output DAC) will dominate
the output voltage noise. The resultant voltage noise
equals the external reference noise which in turn is RMS
summed with the error amplifier’s noise. The typical noise
contribution from LT3040’s error amplifier is 4nV/√Hz.
In order to achieve this noise specification, the external
voltage source can use a filter resistor connected between
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19
LT3040
APPLICATIONS INFORMATION
the LT3040’s FS and VIN pins. The low pass filter (LPF)
created by this bypass resistor along with the VIN pin
capacitor bypasses the noise contribution from the voltage source. To ensure fast start-up of LT3040 with this
LPF in place, the LT3040’s fast start-up circuit charges
the VIN pin capacitor with a 10mA (typical) current source.
One problem that conventional linear regulators face is
that the resistor divider setting the output voltage gains up
the reference noise. In contrast, the LT3040’s unity-gain
follower architecture presents no gain from the VIN pin to
the output. Therefore, if a capacitor bypasses the voltage
source noise, then the output noise is independent of the
programmed output voltage. The resultant output noise
is then set just by the error amplifier’s noise — typically
4nV/√Hz from 10kHz to 1MHz and 1.2µVRMS in a 10Hz
to 100kHz bandwidth using a 4.7µF VIN pin capacitor.
Paralleling multiple LT3040s further reduces noise by
√N, for N parallel regulators.
Refer to the Typical Performance Characteristics section
for noise spectral density and RMS integrated noise over
various load currents and VIN pin capacitances.
VIN Pin (BYPASS) Capacitance: Noise, PSRR,
Transient Response and Soft-Start
In addition to reducing output noise, using a VIN pin
bypass capacitor also improves PSRR and transient performance. Note that any bypass capacitor leakage may
deteriorate the LT3040’s DC regulation. Capacitor leakage
of 100nA results in a 100µV DC error for a 1k impedance at the VIN pin. The use of a good quality low leakage
ceramic capacitor is recommended.
Using a VIN bypass capacitor may soft-start the output
and limit inrush current. If fast start functionality is not
used and a filter resistor (RIN) is used (refer to Figure 9)
then the RC time constant, formed by the VIN pin resistor
and capacitor, controls the soft start time. Ramp up rate
from 0% to 90% of nominal VOUT is:
tss = 2.3 • RIN • CIN
If the fast start functionality is used (see next section)
then the soft-start time is dependent on the amount of the
capacitor used and the voltage input at the FS pin. In this
case the ramp up rate to within 10mV of nominal VOUT is:
tss(FS) = CIN • VFS/10mA
V+
CV+
VIN
RFAULT
EN/UV
FAULT
RIN
V+
LT3040
FS
VIN
CIN
+
–
QPWR
OUT
QDRV
VFB
VOUT
RLOAD
GND ILIM
RILIM
COUT
3040 TA09
Figure 9. Low Pass Filter with Fast-Startup Disabled
Fast Start
For ultralow noise applications that require low 1/f noise,
a VIN filter with a very low frequency pole may be necessary. This significantly increases the start-up time in
accordance with the RC time constant of the VIN filter.
The LT3040 incorporates fast start-up circuitry that
sources the VIN pin with a typical current of 10mA during
start-up to rapidly charge the filter capacitor, decreasing
start-up time.
The 10mA current source turns on if the FS to VIN differential is greater than 100mV and remains engaged if the
FS pin is greater than the VIN pin by 7mV. This current
decreases to 0mA as VIN pin charges to the FS pin voltage. If the regulator is in current limit, dropout, thermal
shutdown or if supply voltage is below minimum V+, the
fast start function is disabled.
While using the fast start functionality, if the VIN slew
rate approaches the FS slew rate during startup, the VIN
pin voltage may catch up to the FS pin while FS is rising. This will shut off the fast start current until FS rises
~100mV above VIN. This is intended operation. This turn
on and turn off will cause stair stepping at the VIN pin
Rev. 0
20
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LT3040
APPLICATIONS INFORMATION
voltage. Increasing the VIN cap value will smooth the VIN
pin start‑up.
If fast start-up capability is not used, tie FS to VIN.
V+
CV+
RFAULT
FAULT
VIN
EN/UV
V+
LT3040
Power Supply Sequencing
FS
RIN
CIN
VIN
When using a minimum output capacitor without any
external current limit, use at least 2.2µF capacitor at the
VIN pin if using the fast start circuitry. This capacitor limits
the slew rate on the VIN pin while also ensuring that the
VIN pin doesn’t overshoot during fast start up. For applications with lower current limit or higher output capacitance, a larger VIN capacitor is required.
+
–
QPWR
OUT
QDRV
VFB
VOUT
RLOAD
GND ILIM
RILIM
COUT
3040 TA10
Figure 10. Low Pass Filter with Fast-Startup Enabled
VIN Slew Rate
The LT3040’s error amplifier is bandwidth limited. If the
VIN pin slews too fast in the positive direction, the error
amplifier reacts and enters current limit. If the VIN pin
voltage stops slewing, the LT3040’s bandwidth limitation
causes the output to overshoot significantly before settling into regulation. In order to avoid undesirable overshoots at the output, ADI recommends limiting the VIN
pin slew rate to less than or equal to 1V/µs.
A similar behavior is expected for negative slew rates on
the VIN pin where the output undershoots significantly. If
VIN slews fast in the negative direction, the error amplifier shuts off and the output discharge is a function of
the LT3040’s load current. Thus, larger undershoots are
expected at heavier load conditions.
To limit slew rates when using the fast start functionality of the LT3040, the minimum CIN requirement is
governed by:
100mA • COUT/ILIM ≤ CIN
where ILIM is the output current limit. The internal current
limit for LT3040 is around 280mA (180mA in foldback).
The LT3040 is able to withstand voltages as high as the
Absolute Maximum rating on the FS and VIN pins even
when the part is turned off. However, for optimum application performance and to protect the peripheral circuitry
used with the LT3040, ADI recommends that the LT3040
is powered up (or enabled) before or in sync with the voltage application at VIN. During turn-off, ADI recommends
powering down VIN before or in sync with the LT3040.
The LT3040’s VIN pin is internally clamped to the VFB pin
(typical clamp voltage of 1.5V), if VIN is powered while
the LT3040 is shutdown, there is a possibility that the
Absolute Maximum rating for the voltage differential from
VIN to VFB or the current rating (max 20mA) on the VIN
and VFB pins or both may be exceeded; damaging the part.
In applications where the VIN supply is not current limited
to less than or equal to 20mA, connect a protection resistor from the Voltage Source (Voltage Reference/Voltage
Output DAC) to the FS/VIN pin. Use a minimum resistor
of 50Ω/V to limit the current below the Abs Max Rating
of 20mA for the VIN to VFB clamp. For example, if connecting a 5V reference use at least a 250Ω (5V • 50Ω/V)
resistor. If the VIN pin is powered high while LT3040 is in
shutdown, the DC current flowing through the internal VIN
to VFB clamp may pull output above ground.
Filtering High Frequency Spikes
For applications where the LT3040 is used to post-regulate a switching converter, its high PSRR effectively suppresses any “noise” present at the switcher’s switching
frequency — typically 100kHz to 4MHz. However, the very
high frequency (100s of MHz) “spikes” — beyond the
LT3040’s bandwidth — associated with the switcher’s
power switch transition times will almost directly pass
Rev. 0
For more information www.analog.com
21
LT3040
APPLICATIONS INFORMATION
through the LT3040. While the output capacitor is partly
intended to absorb these spikes, its ESL will limit its ability
at these frequencies. A ferrite bead or even the inductance
associated with a short (e.g. 0.5˝) PCB trace between the
switcher’s output and the LT3040’s input can serve as an
LC-filter to suppress these very high frequency spikes.
Output Overshoot Recovery
Enable/UVLO
As illustrated in the Block Diagram, the LT3040 incorporates an overshoot recovery circuitry that turns on a
current sink to discharge the output capacitor in the event
VFB is higher than VIN. This current is typically about 4mA.
No load recovery is disabled for supply voltages less than
2.5V or output voltages less than 1.5V.
During a load step from full load to no load (or light
load), the output voltage overshoots before the regulator
responds to turn the power transistor OFF. Given that there
is no load (or very light load) present at the output, it takes
a long time to discharge the output capacitor.
The EN/UV pin is used to put the buffer into a micro-power
shutdown state. The LT3040 has an accurate 1.24V turnon threshold on the EN/UV pin with 170mV of hysteresis.
This threshold can be used in conjunction with a resistor
divider from the V+ supply to define an accurate undervoltage lockout (UVLO) threshold for the buffer. The EN/
UV pin current (IEN) at the threshold from the Electrical
Characteristics table needs to be considered when calculating the resistor divider network:
If VFB is externally held above VIN, the current sink turns
ON in an attempt to restore VFB to its programmed voltage. The current sink remains ON until the external circuitry releases VFB.
V+(UVLO) = 1.24V • (1+(REN2/REN1)) + IEN • REN2
Output Source and Sink
The EN/UV pin current (IEN) can be ignored if REN1 is less
than 75kΩ. If unused, tie EN/UV pin to V+.
Externally Programmable Current Limit
The ILIM pin’s current limit threshold is 300mV.
Connecting a resistor from ILIM to GND sets the maximum current flowing out of the ILIM pin, which in turn
programs the LT3040’s current limit. The programming
scale factor is 125mA • kΩ. For example, a 1kΩ resistor
programs the current limit to 125mA and a 2kΩ resistor
programs the current limit to 62.5mA. For good accuracy,
Kelvin connect this resistor to the LT3040’s GND pin.
In cases where V+-to-OUT differential is greater than 12V,
the LT3040’s foldback circuitry decreases the internal current limit. As a result, internal current limit may over-ride
the externally programmed current limit level to keep the
LT3040 within its safe-operating-area (SOA). See the
Internal Current Limit vs Supply-to-Output Differential
graph in the Typical Performance Characteristics section.
As shown in the Block Diagram, the ILIM pin sources
current proportional (1:400) to output current; therefore,
it also serves as a current monitoring pin with a 0V to
300mV range. If external current limit or current monitoring is not used, tie ILIM to GND.
The LT3040 is capable of sourcing 200mA of current.
However, the LT3040 does not support a current sink
capability. Although the output overshoot recovery circuit can typically sink 4mA of current, this capability is
triggered only for AC loop perturbations. For a DC current
sink capability tie a resistor from OUT to GND.
Direct Paralleling for Higher Current
Higher output current is obtained by paralleling multiple
LT3040s. Tie all VIN pins together and all V+ pins together.
Connect the OUT pins together using small pieces of PCB
trace (used as a ballast resistor) to equalize currents in
the LT3040s. PCB trace resistance in mΩ/inch is shown
in Table 1.
Table 1. PC Board Trace Resistance
WEIGHT (oz)
10mil WIDTH
20mil WIDTH
1
54.3
27.1
2
27.1
13.6
Trace resistance is measured in mΩ/in
Rev. 0
22
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LT3040
APPLICATIONS INFORMATION
PCB Layout Considerations
V+
CV+
EN/UV
V+
Given the LT3040’s high bandwidth and ultrahigh PSRR,
careful PCB layout must be employed to achieve full
device performance. Figure 12 shows an example layout
that delivers full performance of the regulator. Refer to the
LT3040’s DC2783A demo board manual for further details.
LT3040
FAULT
FS
VIN
QPWR
+
–
OUT
QDRV
VFB
50mΩ
GND ILIM
COUT
RILIM
VOUT
IOUT(MAX) = 400mA
EN/UV
V+
LT3040
FAULT
VIN
FS
RIN
VIN
+
–
QPWR
50mΩ
OUT
QDRV
VFB
GND ILIM
CIN
COUT
RILIM
3040 TA11
Figure 11. Parallel Devices
3040 F12
The small worst-case offset of 0.3mV for each paralleled LT3040 minimizes the required ballast resistor
value. Figure 11 illustrates that two LT3040s, each using
a 50mΩ PCB trace ballast resistor, provide better than
20% accurate output current sharing at full load. The two
50mΩ external resistors only add 10mV of output regulation drop with a 400mA maximum current. With a 3.3V
output, this only adds 0.3% to the regulation accuracy.
As has been discussed previously, tie the VFB pin directly
to the output capacitor.
More than two LT3040s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3040s is also useful for distributing heat on the
PCB. For applications with high supply-to-output voltage
differential, an input series resistor or resistor in parallel
with the LT3040 can also be used to spread heat.
Figure 12. Example DFN Layout
Thermal Considerations
The LT3040 has internal power and thermal limiting circuits that protect the device under overload conditions.
The thermal shutdown temperature is nominally 162°C
with about 8°C of hysteresis. For continuous normal
load conditions, do not exceed the maximum junction
temperature, (125°C for E-, I-grades). It is important to
consider all sources of thermal resistance from junction to
ambient. This includes junction-to-case, case-to-heat sink
interface, heat sink resistance or circuit board-to-ambient
as the application dictates. Additionally, consider all heat
sources in close proximity to the LT3040.
The undersides of the DFN and MSOP packages have
exposed metal from the lead frame to the die attachment.
Both packages allow heat to directly transfer from the die
Rev. 0
For more information www.analog.com
23
LT3040
APPLICATIONS INFORMATION
junction to the PCB metal to limit maximum operating
junction temperature.The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PCB and
its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by the regulator.
Table 2 and Table 3 list thermal resistance as a function of
copper area on a fixed board size. All measurements were
taken in still air on a 4 layer FR-4 board with 1oz solid
internal planes and 2oz top/bottom planes with a total
board thickness of 1.6mm. The four layers were electrically isolated with no thermal vias present. PCB layers,
copper weight, board layout and thermal vias affect the
resultant thermal resistance. For more information on thermal resistance and high thermal conductivity test boards,
refer to JEDEC standard JESD51, notably JESD51-7 and
JESD51-12. Achieving low thermal resistance necessitates attention to detail and careful PCB layout.
Table 2. Measured Thermal Resistance for DFN Package
COPPER AREA
TOP SIDE*
BOTTOM SIDE
BOARD AREA
THERMAL
RESISTANCE
2500mm2
2500mm2
2500mm2
34°C/W
1000mm2
2500mm2
2500mm2
34°C/W
225mm2
2500mm2
2500mm2
35°C/W
100mm2
2500mm2
2500mm2
36°C/W
*Device is mounted on top side
Table 3. Measured Thermal Resistance for MSOP Package
COPPER AREA
TOP SIDE*
BOTTOM SIDE
BOARD AREA
THERMAL
RESISTANCE
2500mm2
2500mm2
2500mm2
33°C/W
1000mm2
2500mm2
2500mm2
33°C/W
225mm2
2500mm2
2500mm2
34°C/W
100mm2
2500mm2
2500mm2
35°C/W
*Device is mounted on top side
Calculating Junction Temperature
Example: Given an output voltage of 2.5V and supply voltage of 5V ± 5%, output current range from 1mA to 200mA
and a maximum ambient temperature of 85°C, what is the
maximum junction temperature?
The LT3040’s power dissipation is:
IOUT(MAX) • (V+(MAX) – VOUT) + IGND • V+(MAX)
where:
IOUT(MAX) = 200mA V+(MAX) = 5.25V
IGND (at IOUT = 200mA and V+ = 5.25V) = 7.2mA
thus:
PDISS = 0.2A • (5.25V–2.5V) + 7.2mA • 5.25V = 0.59W
Using a DFN package, the thermal resistance is in the
range of 34°C/W to 36°C/W depending on the copper
area. Therefore, the junction temperature rise above ambient approximately equals:
0.59W • 35°C/W = 20.7°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction temperature rise above ambient:
TJMAX = 85°C + 20.7°C = 105.7°C
Overload Recovery
Like many IC power regulators, the LT3040 incorporates
safe-operating-area (SOA) protection. The SOA protection
activates at supply-to-output differential voltages greater
than 12V. The SOA protection decreases the current limit
as the supply-to-output differential increases and keeps
the power transistor inside a safe operating region for all
values of supply-to-output voltages up to the LT3040’s
absolute maximum ratings. The LT3040 provides some
level of output current for all values of supply-to-output
differentials. Refer to the Current Limit curves in the
Typical Performance Characteristics section. When power
is first applied and supply voltage rises, the output follows
the supply and keeps the supply-to-output differential low
to allow the regulator to supply large output current and
start-up into high current loads.
Rev. 0
24
For more information www.analog.com
LT3040
APPLICATIONS INFORMATION
The LT3040 incorporates several protection features for
battery-powered applications. Precision current limit and
thermal overload protection protect the LT3040 against
overload and fault conditions at the device’s output. For
normal operation, do not allow the junction temperature
to exceed 125°C (E-, I-grade).
To protect the LT3040’s low noise error amplifier, the
VIN-to-VFB protection clamp limits the maximum voltage
between VIN and VFB to ±1.5V with a maximum DC current
of 20mA through the clamp. So, for applications where VIN
is actively driven by a voltage source, the voltage source
must be current limited to 20mA or less. Moreover, to limit
the transient current flowing through these clamps during
a transient fault condition, limit the maximum value of the
VIN pin capacitor (CIN) to 22µF.
The LT3040 also incorporates reverse supply protection
whereby the V+ pin withstands reverse voltages of up to
–20V without causing any supply current flow and without
developing negative voltages at the OUT pin. The regulator
protects both itself and the load against batteries that are
plugged-in backwards.
In circuits where a backup battery is required, several different output to supply conditions can occur. The output
voltage may be held up while the supply is either pulled
to GND, pulled to some intermediate voltage, or left opencircuit. In all of these cases, the reverse current protection
circuitry prevents current flow from output to the supply.
Long Term Drift
Long term drift is a settling of the offset voltage while the
part is powered up. The offset slowly drifts at levels of µV.
The first 1000 hours of being powered up sees the most
shift. By the end of 3000 hours, most parts have settled
and will not shift appreciably. The plot in Figure 13 is
representative of the LT3040 long term drift.
20
16
12
LONG-TERM DRIFT (µV)
Protection Features
Nonetheless, due to the VFB-to-VIN clamp, unless the
VIN pin is floating, current can flow to GND through the
bypass resistor as well as up to 15mA to GND through
the output overshoot recovery circuitry. This current flow
through the output overshoot recovery circuitry can be
significantly reduced by placing a Schottky diode between
VFB and VIN pins, with its anode at the VFB pin.
8
4
0
–4
–8
–12
DFN PACKAGE
VIN = 1.25V
–16
–20
0
500 1000 1500 2000 2500 3000 3500 4000
TIME (Hrs)
3040 F13a
20
16
12
LONG-TERM DRIFT (µV)
Due to current limit foldback, however, at high supply voltages a problem can occur if the output voltage is low and
the load current is high. Such situations occur after the
removal of a short-circuit or if the EN/UV pin is pulled high
after the supply voltage has already turned ON. The load
line in such cases intersects the output current profile at
two points. The regulator now has two stable operating
points. With this double intersection, the power supply
may need to be cycled down to zero and brought back up
again to make the output recover. Other linear regulators
with foldback current limit protection (such as the LT1965
and LT1963A, etc.) also exhibit this phenomenon, so it is
not unique to the LT3040.
8
4
0
–4
–8
–12
MSE PACKAGE
VIN = 1.25V
–16
–20
0
500 1000 1500 2000 2500 3000 3500 4000
TIME (Hrs)
3040 F13b
Figure 13. LT3040 Long Term Drift
Rev. 0
For more information www.analog.com
25
LT3040
APPLICATIONS INFORMATION
IR Reflow Shift
Thermal Hysteresis
As with many precision devices, the LT3040 will experience an offset voltage shift when soldered to a PCB. This
shift is caused by uneven contraction and expansion of
the plastic mold compound against the die and the copper
pad underneath the die. Critical devices in the circuit will
experience a change of physical force or pressure, which
in turn changes its electrical characteristics, resulting in
subtle changes in circuit behavior. Lead free solder reflow
profiles reach over 250°C, which is considerably higher
than lead based solder. A typical lead-free IR reflow profile
is shown in Figure 14. The experimental results simulating this shift are shown in Figure 15. In this experiment,
LT3040 is run through IR reflow oven once.
Thermal hysteresis is caused by the same effect as IR
reflow shift. However, in the case of thermal hysteresis,
the temperature is cycled between its specified operating
extremes to simulate how the part will behave as it experiences extreme temperature excursions and then returns
to room temperature. For example, the LT3040 rated for
–40°C to 125°C was repeatedly cycled between 125°C and
–40°C. Figure 16 illustrates the thermal hysteresis of the
LT3040, where each time the part’s temperature passed
through 25°C after cold and hot excursions, the offset
voltage was recorded.
380s
TL = 217°C
TS(MAX) = 200°C
TS = 190°C
225
TEMPERATURE (°C)
TP = 260°C
150
RAMP
DOWN
tP
30s
T = 150°C
NUMBER OF UNITS
300
50
tL
130s
RAMP TO
150°C
75
40s
15
3040 F16a
0
2
6
4
MINUTES
8
10
50
3040 F14
DFN PACKAGE
MSE PACKAGE
V+ = 2V
VIN = 1.25V
12
NUMBER OF UNITS
HALF CYCLE
FULL CYCLE
0
–20 –16 –12 –8 –4 0 4 8 12 16 20
OFFSET VOLTAGE HYSTERESIS (µV)
10
NUMBER OF UNITS
14
20
5
Figure 14. IR Reflow Profile
16
25
10
120s
0
DFN PACKAGE
45 V+ = 5V
VIN = 1.25V
40
26 UNITS × 3 CYCLES
35 HALF CYCLE = 26°C, 125°C, 26°C
FULL CYCLE = 26°C, 125°C, 26°C,
30 –40°C, 26°C
MSE PACKAGE
45 V+ = 5V
VIN = 1.25V
40
26 UNITS × 3 CYCLES
35 HALF CYCLE = 26°C, 125°C, 26°C
FULL CYCLE = 26°C, 125°C, 26°C,
30 –40°C, 26°C
25
20
HALF CYCLE
FULL CYCLE
15
10
8
5
6
0
–20 –16 –12 –8 –4 0 4 8 12 16 20
OFFSET VOLTAGE HYSTERESIS (µV)
4
2
3040 F16b
0
–20 –10 0 10 20 30 40 50 60 70 80
VOS SHIFT DUE TO IR REFLOW (µV)
Figure 16. Input Offset Thermal Hysteresis
3040 F15
Figure 15. ∆VOS due to IR Reflow
Rev. 0
26
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LT3040
TYPICAL APPLICATIONS
200mA 3.3V Precision Reference
V+
5V ±5%
CIN
4.7µF
RFAULT
200k
LTC6655-3.3
IN
OUT_F
SHDN OUT_S
CREF
2.2µF
GND
FAULT EN/UV
LT3040
V+
FS
RIN
5k
VIN
QPWR
+
–
OUT
QDRV
VOUT = 3.3V
IOUT(MAX) = 200mA
VFB
GND ILIM
CIN
2.2µF
COUT
4.7µF
RILIM
499Ω
3040 TA02
200mA 0V to 2.5V Precision DAC
V+
5V ±5%
CIN
4.7µF
RFAULT
200k
VDD
2.5V
VIN
REF LTC2641 V(OUT)
FAULT EN/UV
V+
LT3040
FS
VIN
GND
+
–
QPWR
OUT
QDRV
VOUT = 0V TO 2.5V
IOUT(MAX) = 200mA
VFB
GND ILIM
CIN
10nF
COUT
4.7µF
RILIM
499Ω
3040 TA03
200mA 3.3V Precision Reference*
V+
5V ±5%
CV+
4.7µF
RFAULT
200k
LT6654-3.3
VIN
VOUT
GND
CREF
2.2µF
RIN
5k
FAULT EN/UV
V+
LT3040
FS
VIN
+
–
CIN
2.2µF
*CHEAPER SOLUTION COMPARED TO LTC6655-3.3
AT THE COST OF POOR PERFORMANCE
QPWR
OUT
QDRV
VOUT = 3.3V
IOUT(MAX) = 200mA
VFB
GND ILIM
COUT
4.7µF
RILIM
499Ω
3040 TA05
Rev. 0
For more information www.analog.com
27
LT3040
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ±0.10
10
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
5
0.75 ±0.05
0.00 – 0.05
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
Rev. 0
28
For more information www.analog.com
LT3040
PACKAGE DESCRIPTION
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
6
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
12
0.65
0.42 ±0.038
(.0256)
(.0165 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
1 2 3 4 5 6
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0213 REV G
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
29
LT3040
TYPICAL APPLICATION
V+
5V ±5%
CV+
4.7µF
RFAULT
200k
ADR4533
VIN
VOUT
GND
CREF
2.2µF
RIN
5k
CIN
2.2µF
FAULT EN/UV
V+
LT3040
FS
VIN
QPWR
+
–
OUT
QDRV
VOUT = 3.3V
IOUT(MAX) = 200mA
VFB
GND ILIM
COUT
4.7µF
RILIM
499Ω
3040 TA04
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3050
100mA LDO with Diagnostics and
Precision Current Limit
340mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V, 3mm × 2mm DFN and
MSOP Packages
LT3060
100mA Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V, 2mm × 2mm DFN and
ThinSOT Packages
LT3082
200mA, Parallelable, Low Noise LDO
Outputs May Be Paralleled for Higher Output Current or Heat Spreading, Wide Input Voltage
Range: 1.2V to 40V, Low Value Input/Output Capacitors Required: 2.2µF, Single Resistor Sets
Output Voltage, 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages
LT3085
500mA, Parallelable, Low Noise, Low
Dropout Linear Regulator
275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V to
35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op Amp
Required), Stable with Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages
LT3042
200mA, Ultralow Noise and Ultrahigh
PSRR LDO
0.8μVRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V, 350mV Dropout Voltage,
Programmable Current Limit and Power Good, 3mm × 3mm DFN and MSOP Packages
LT6658
36V, Dual Output (150mA/50mA) Low 0.05% Max, 10ppm/°C Max Drift, 1.5ppmP-P Noise (0.1Hz to 10Hz), 1.2V/1.8V/2.5V/3.3V/5V
Versions, MSOP-16E Package
Noise Buffered Voltage Reference
LTC6655
Precision Low Noise Reference
2ppm/°C Max, 650nVP-P Noise (0.1Hz to 10Hz) 100% Tested at 25°C, –40°C and 125°C
LTC2641
Single 16-/14-/12-Bit VOUT DACs with
±1LSB INL, DNL
±1LSB (Max) INL, DNL, 3mm x 3mm DFN and MSOP Packages, 120µA Supply Current,
SPI Interface
Rev. 0
30
11/19
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For more information www.analog.com
ANALOG DEVICES, INC. 2019
