LT3042
20V, 200mA, Ultralow Noise,
Ultrahigh PSRR RF Linear Regulator
FEATURES
DESCRIPTION
Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
nn Ultralow Spot Noise: 2nV/√Hz at 10kHz
nn Ultrahigh PSRR: 79dB at 1MHz
nn Output Current: 200mA
nn Wide Input Voltage Range: 1.8V to 20V
nn Single Capacitor Improves Noise and PSRR
nn 100µA SET Pin Current: ±1% Initial Accuracy
nn Single Resistor Programs Output Voltage
nn High Bandwidth: 1MHz
nn Programmable Current Limit
nn Low Dropout Voltage: 350mV
nn Output Voltage Range: 0V to 15V
nn Programmable Power Good
nn Fast Start-Up Capability
nn Precision Enable/UVLO
nn Parallelable for Lower Noise and Higher Current
nn Internal Current Limit with Foldback
nn Minimum Output Capacitor: 4.7µF Ceramic
nn Reverse Battery and Reverse Current Protection
nn 10-Lead MSOP and 3mm × 3mm DFN Packages
The LT®3042 is a high performance low dropout linear
regulator featuring LTC’s ultralow noise and ultrahigh PSRR
architecture for powering noise sensitive RF applications.
Designed as a precision current reference followed by a
high performance voltage buffer, the LT3042 can be easily
paralleled to further reduce noise, increase output current
and spread heat on the PCB.
nn
The device supplies 200mA at a typical 350mV dropout
voltage. Operating quiescent current is nominally 2mA
and drops to 12V. Some level of
output current is provided at all VIN – VOUT differential voltages. Consult
the Typical Performance Characteristics graph for current limit vs VIN –
VOUT.
Note 13: For output voltages less than 1V, the LT3042 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 15: The PSRR at 120Hz is guaranteed by design, characterization,
and correlation with statistical process controls.
TYPICAL PERFORMANCE CHARACTERISTICS
SET Pin Current
Offset Voltage (VOUT – VSET)
SET Pin Current
101.0
VIN = 2V
100.8 IL = 1mA
VOUT = 1.3V
100.6
2.0
VIN = 2V
1.5 IL = 1mA
VOUT = 1.3V
OFFSET VOLTAGE (mV)
N = 4354
100.4
100.2
100.0
99.8
99.6
99.4
1.0
0.5
0
–0.5
–1.0
–1.5
99.2
98
0 25 50 75 100 125 150
TEMPERATURE (°C)
99
101
100
ISET DISTRIBUTION (µA)
3042 G01
Offset Voltage
3042 G02
IL = 1mA
VOUT = 1.3V
100.8
100.6
150°C
125°C
25°C
–55°C
100.4
100.2
100.0
99.8
99.6
99.4
2
3042 G04
99.0
2.0
Offset Voltage (VOUT – VSET)
IL = 1mA
VOUT = 1.3V
1.5
1.0
150°C
125°C
25°C
–55°C
0.5
0
–0.5
–1.0
–1.5
99.2
–1
1
0
VOS DISTRIBUTION (mV)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G03
SET Pin Current
101.0
N = 4354
–2
–2.0
–75 –50 –25
102
OFFSET VOLTAGE (mV)
99.0
–75 –50 –25
SET PIN CURRENT (µA)
SET PIN CURRENT (µA)
TJ = 25°C, unless otherwise noted.
0
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
3042 G05
–2.0
0
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
3042 G06
3042fb
For more information www.linear.com/LT3042
5
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
100.4
100.2
100.0
99.8
99.6
99.4
1.0
0.5
0
–0.5
–1.0
20
14
0.08
6
1.5
3
4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)
Quiescent Current in Shutdown
20
VIN = 2V
VEN/UV = VIN
2.5 IL = 10µA
RSET = 13kΩ
QUIESCENT CURRENT (µA)
1.5
1.0
0.5
Quiescent Current
2.5
VEN/UV = 0V
18
2.0
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G09
16
14
12
VIN = 20V
10
8
VIN = 2V
6
4
QUIESCENT CURRENT (mA)
Quiescent Current
0.04
0.02
3042 G08
3.0
0.06
ISET
4
0
–75 –50 –25
0
0.12
0.10
2
4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)
0.14
8
–2.0
3
0.16
10
99.0
1.5
0.18
VOS
12
99.2
0
0.20
VIN = 2.5V
18 ∆IL = 1mA TO 200mA
VOUT = 1.3V
16
–1.5
3042 G07
QUIESCENT CURRENT (mA)
Load Regulation
150°C
125°C
25°C
–55°C
IL = 1mA
VIN = 20V
1.5
OFFSET VOLTAGE (mV)
SET PIN CURRENT (µA)
100.6
Offset Voltage (VOUT – VSET)
VOS LOAD REGULATION (mV)
150°C
125°C
25°C
–55°C
IL = 1mA
VIN = 20V
100.8
2.0
ISET LOAD REGULATION (nA)
SET Pin Current
101.0
TJ = 25°C, unless otherwise noted.
IL = 10µA
RSET = 33.2kΩ
2.0
1.5
1.0
0.5
2
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G10
DROPOUT VOLTAGE (mV)
QUIESCENT CURRENT (mA)
2.0
1.5
1.0
150°C
125°C
25°C
–55°C
0.5
0
0
2
4
8
6
10 12
OUTPUT VOLTAGE (V)
16
3042 G13
6
450
400
350
300
250
200
150
150°C
125°C
25°C
–55°C
100
50
14
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
Dropout Voltage
500
RSET = 33.2kΩ
450
2.5
2
3042 G12
Typical Dropout Voltage
500
VIN = 20V
VEN/UV = VIN
IL = 10µA
3.0
0
3042 G11
Quiescent Current
3.5
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
DROPOUT VOLTAGE (mV)
0
–75 –50 –25
0
0
25
RSET = 33.2kΩ
400
350
300
250
200
IL = 200mA
IL = 150mA
IL = 100mA
IL = 1mA
150
100
50
50 75 100 125 150 175 200
OUTPUT CURRENT (mA)
3042 G14
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G15
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current
GND Pin Current
8
VIN = 5V
RSET = 33.2kΩ
9
6
IL = 150mA
5
4
IL = 100mA
3
2
GND PIN CURRENT (mA)
IL = 1mA
7
6
5
4
3
2
0
50 75 100 125 150 175 200
OUTPUT CURRENT (mA)
Minimum Input Voltage
RSET = 33.2kΩ
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
10
9
3042 G18
EN/UV Turn-On Threshold
EN/UV Pin Hysteresis
1.32
250
1.30
225
1.50
TURN-ON THRESHOLD (V)
FALLING UVLO
1.25
1.00
0.75
0.50
EN/UV PIN HYSTERESIS (mV)
RISING UVLO
1.75
INPUT UVLO THRESHOLD (V)
RL = 3.3kΩ
3042 G17
2.00
1.28
1.26
VIN = 2V
1.24
VIN = 10V
1.22
1.20
0.25
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1.18
–75 –50 –25
3.5
3.0
2.5
2.0
1.5
150°C
125°C
25°C
–55°C
1.0
0.5
0
2
4
6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)
3042 G22
EN/UV PIN CURRENT (µA)
4.0
VIN = 2V
150
125
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G21
Enable Pin Current
VIN = 20V
4.5
VIN = 10V
175
3042 G20
Enable Pin Input Current
5.0
200
100
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G19
0
RL = 330Ω
2
0
25
RL = 66Ω
3
0
–75 –50 –25
0
RL = 33Ω
4
1
3042 G16
EN/UV PIN CURRENT (µA)
5
1
0 25 50 75 100 125 150
TEMPERATURE (°C)
RL = 16.5Ω
6
1
Negative Enable Pin Current
10
0
9
–10
VIN = 2V
8
7
6
5
VIN = 20V
4
3
2
0
2
4
6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)
3042 G23
VIN = 2V
–20
–30
–40
–50
–60
–70
–80
–90
1
0
EN/UV PIN CURRENT (µA)
GND PIN CURRENT (mA)
IL = 200mA
7
VIN = 4.3V
RSET = 33.2kΩ
7
8
GND Pin Current
8
GND PIN CURRENT (mA)
10
TJ = 25°C, unless otherwise noted.
150°C
125°C
25°C
–55°C
–100
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)
0
3042 G24
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For more information www.linear.com/LT3042
7
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
Input Pin Current
Internal Current Limit
150°C
125°C
25°C
–55°C
450
Internal Current Limit
300
RILIM = 0Ω
VOUT = 0V
250
400
0.2
0.1
350
CURRENT LIMIT (mA)
VIN = 2V
500
CURRENT LIMIT (mA)
INPUT CURRENT (mA)
0.3
TJ = 25°C, unless otherwise noted.
VIN = 7.5V
300
250
VIN = 2.5V
200
150
VIN = 20V
RILIM = 0Ω
VOUT = 0V
200
150
100
100
50
50
0
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)
0
–75 –50 –25
0
3042 G25
350
350
300
250
200
150
150°C
125°C
25°C
–55°C
100
50
0
0
RILIM = 625Ω
VOUT = 0V
90
250
VIN = 7.5V
200
VIN = 2.5V
150
100
250
200
150
VIN = 2.5V
VIN = 5V
VIN = 10V
50
0
0
20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA)
3042 G31
8
30
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G30
PGFB Hysteresis
8
VIN = 2V
306
304
302
300
298
296
294
6
5
4
3
2
1
292
290
–75 –50 –25
VIN = 2V
7
PGFB HYSTERESIS (mV)
ILIM PIN CURRENT (µA)
300
PGFB RISING THRESHOLD (mV)
308
350
VIN = 2.5V
40
PGFB Rising Threshold
310
400
VIN = 7.5V
50
3042 G29
VILIM = 0V
RSET = 33.2kΩ
100
60
10
0
–75 –50 –25
ILIM Pin Current
450
70
20
50
2 4 6 8 10 12 14 16 18 20
INPUT-TO-OUTPUT DIFFERENTIAL (V)
RILIM = 2.49kΩ
VOUT = 0V
80
300
3042 G28
500
Programmable Current Limit
100
CURRENT LIMIT (mA)
START OF FOLDBACK
CURRENT LIMIT (mA)
CURRENT LIMIT (mA)
400
3042 G27
Programmable Current Limit
400
RILIM = 0Ω
450
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G26
Internal Current Limit
500
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G32
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G33
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
PG Output Low Voltage
30
60
25
20
ISET (mA)
70
50
40
15
30
10
20
5
10
10
VPGFB = 290mV
VSET = 1.3V
OUTPUT SINK CURRENT (mA)
2.0
1.5
1.0
0.5
2
8
4
2
VOUT Forced Above VOUT(NOMINAL)
0
5
PSRR (dB)
CURRENT (mA)
8
6
OUTPUT CURRENT
0
4
5
6
7 8 9 10 11 12 13 14 15
OUTPUT VOLTAGE (V)
3042 G40
3
2
0
–75 –50 –25
20
3042 G39
Power Supply Ripple Rejection
120
110
90
CSET = 0.47µF
80
70
60
20
100
1k
10k 100k
FREQUENCY (Hz)
70
60
40
30
1M
10M
3042 G41
COUT = 22µF
80
50
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
IL = 200mA
10
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G38
100
30
INPUT CURRENT
4
90
40
2
5
100
50
4
10
15
VOUT – VSET (mV)
CSET = 4.7µF
110
10
VIN = 5V
RSET = 33.2kΩ
VOUT – VSET > 5mV
6
Power Supply Ripple Rejection
120
VIN = 5V
RSET = 33.2kΩ
12
7
1
3042 G37
14
155°C
130°C
25°C
–55°C
6
0
4 6 8 10 12 14 16 18 20
VIN-TO-VSET DIFFERENTIAL (V)
VIN = 5V
RSET = 33.2kΩ
Output Overshoot Recovery
Current Sink
PSRR (dB)
ISET (mA)
2.5
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G36
Output Overshoot Recovery
Current Sink
3.5
0
0
–75 –50 –25
3042 G35
ISET During Start-Up with Fast
Start-Up Enabled
0
1.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
3042 G34
3.0
1.5
0.5
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
VIN = 2.5V
VPGFB = 290mV
VSET = 1.3V
2.0
80
35
0
–75 –50 –25
2.5
VPG = 2V
VPGFB = 310mV
90
IPG (nA)
VPG (mV)
100
VIN = 2V
VPGFB = 290mV
IPG = 100µA
40
ISET During Start-Up with Fast
Start-Up Enabled
PG Pin Leakage Current
OUTPUT SINK CURRENT (mA)
50
45
TJ = 25°C, unless otherwise noted.
20
COUT = 4.7µF
VIN = 5V
RSET = 33.2kΩ
CSET = 0.47µF
IL = 200mA
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
3042 G42
3042fb
For more information www.linear.com/LT3042
9
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Ripple Rejection
as a Function of Error Amplifier
Input Pair
100
110
110
90
100
100
80
90
90
70
80
80
60
70
60
30
20
10
100
70
60
50
IL = 200mA
IL = 100mA
IL = 50mA
IL = 1mA
10k 100k
1k
FREQUENCY (Hz)
1M
VIN = VOUT + 2V
IL = 200mA
COUT = 4.7µF
CSET = 0.47µF
40
30
20
10M
10
100
10k 100k
1k
FREQUENCY (Hz)
9
1.2
1.0
0.8
0.6
0.4
0
7
6
5
4
3
2
0.1
1
10
SET PIN CAPACITANCE (µF)
3042 G46
0.1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
3042 G49
10
0
100
0
1.5
3
4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)
3042 G48
Noise Spectral Density
COUT = 4.7µF
COUT = 22µF
10
1
0.1
VIN = 5V
RSET = 33.2kΩ
CSET = 4.7µF
IL = 200mA
10
100
1k
10k 100k
FREQUENCY (Hz)
100
OUTPUT NOISE (nV/√Hz)
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
IL = 200mA
100
OUTPUT NOISE (nV/√Hz)
10
VIN = VOUT + 2V
CSET = 4.7µF
COUT = 4.7µF
ILOAD = 200mA
1.8
Noise Spectral Density
CSET = 0.047µF
CSET = 0.47µF
CSET = 1µF
CSET = 4.7µF
CSET = 22µF
100
1
2.0
3042 G47
Noise Spectral Density
5
0.2
0
0.01
20 40 60 80 100 120 140 160 180 200
LOAD CURRENT (mA)
1000
1
2
3
4
INPUT-TO-OUTPUT DIFFERENTIAL (V)
3042 G45
1
0.2
0
0
Integrated RMS Output Noise
(10Hz to 100kHz)
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
IL = 200mA
8
RMS OUTPUT NOISE (µVRMS)
1.4
0
Integrated RMS Output Noise
(10Hz to 100kHz)
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 4.7µF
1.6
10
10M
1M
100kHz
500kHz
1MHz
2MHz
20
VOUT ≥ 1.3V
0.6V < VOUT < 1.3V
VOUT ≤ 0.6V
3042 G44
Integrated RMS Output Noise
(10Hz to 100kHz)
1.8
40
30
3042 G43
2.0
IL = 200mA
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 0.47µF
50
RMS OUTPUT NOISE (µVRMS)
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 0.47µF
40
PSRR (dB)
120
50
RMS OUTPUT NOISE (µVRMS)
Power Supply Ripple Rejection
120
PSRR (dB)
PSRR (dB)
Power Supply Ripple Rejection
OUTPUT NOISE (nV/√Hz)
TJ = 25°C, unless otherwise noted.
1M
10M
3042 G50
IL = 200mA
IL = 100mA
IL = 50mA
IL = 1mA
10
1
0.1
VIN = 5V
RSET = 33.2kΩ
CSET = 4.7µF
COUT = 4.7µF
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
3042 G51
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL PERFORMANCE CHARACTERISTICS
Noise Spectral Density as
a Function of Error Amplifier
Input Pair
OUTPUT NOISE (nV/√Hz)
1000
Output Noise: 10Hz to 100kHz
Load Transient Response
VOUT ≥ 1.3V
0.6V < VOUT < 1.3V
VOUT ≤ 0.6V
100
200mA/DIV
5µV/DIV
10mV/DIV
10
1
0.1
TJ = 25°C, unless otherwise noted.
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 4.7µF
IL = 200mA
VIN = VOUT + 2V
IL = 200mA
COUT = 4.7µF
CSET = 4.7µF
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
3042 G53
1ms/DIV
LOAD STEP
OUTPUT VOLTAGE
3042 G54
20µs/DIV
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 0.47µF
LOAD STEP = 10mA TO 200mA
10M
3042 G52
Start-Up Time with and
without Fast Start-Up Circuitry for
Large CSET
Line Transient Response
Input Supply Ramp-Up and
Ramp-Down
500mV/DIV
500mV/DIV
1mV/DIV
OUTPUT WITH
FAST START-UP
(SET AT 95%)
INPUT VOLTAGE
OUTPUT VOLTAGE
5µs/DIV
VIN = 4V TO 4.5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 0.47µF
IL = 200mA
OUTPUT WITHOUT
FAST START-UP
3042 G55
PULSE EN/UV
100ms/DIV
2V/DIV
INPUT VOLTAGE
2V/DIV
OUTPUT VOLTAGE
3042 G56
VIN = 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 4.7µF
RL = 16.5Ω
50ms/DIV
3042 G57
VIN = 0V TO 5V
RSET = 33.2kΩ
COUT = 4.7µF
CSET = 0.47µF
RL = 16.5Ω
3042fb
For more information www.linear.com/LT3042
11
LT3042
PIN FUNCTIONS
IN (Pins 1, 2): Input. These pins supply power to the
regulator. The LT3042 requires a bypass capacitor at the
IN pin. In general, a battery’s output impedance rises with
frequency, so include a bypass capacitor in battery-powered
applications. While a 4.7µF input bypass capacitor generally suffices, applications with large load transients may
require higher input capacitance to prevent input supply
droop. Consult the Applications Information section on the
proper use of an input capacitor and its effect on circuit
performance, in particular PSRR. The LT3042 withstands
reverse voltages on IN with respect to GND, OUTS and OUT.
In the case of a reversed input, which occurs if a battery
is plugged-in backwards, the LT3042 acts as if a diode is
in series with its input. Hence, no reverse current flows
into the LT3042 and no negative voltage appears at the
load. The device protects itself and the load.
EN/UV (Pin 3): Enable/UVLO. Pulling the LT3042’s EN/UV
pin low places the part in shutdown. Quiescent current in
shutdown drops to less than 1µA and the output voltage
turns off. Alternatively, the EN/UV pin can set an input
supply undervoltage lockout (UVLO) threshold using a
resistor divider between IN, EN/UV and GND. The LT3042
typically turns on when the EN/UV voltage exceeds 1.24V
on its rising edge, with a 170mV hysteresis on its falling
edge. The EN/UV pin can be driven above the input voltage
and maintain proper functionality. If unused, tie EN/UV to
IN. Do not float the EN/UV pin.
PG (Pin 4): Power Good. PG is an open-collector flag that
indicates output voltage regulation. PG pulls low if PGFB
is below 300mV. If the power good functionality is not
needed, float the PG pin. A parasitic substrate diode exists
between PG and GND pins of the LT3042; do not drive
PG more than 0.3V below GND during normal operation
or during a fault condition.
ILIM (Pin 5): Current Limit Programming Pin. Connecting
a resistor between ILIM and GND programs the current
limit. For best accuracy, Kelvin connect this resistor directly
to the LT3042’s GND pin. The programming scale factor
is nominally 125mA•kΩ. The ILIM pin sources current
proportional (1:400) to output current; therefore, it also
12
serves as a current monitoring pin with a 0V to 300mV
range. If the programmable current limit functionality is
not needed, tie ILIM to GND. A parasitic substrate diode
exists between ILIM and GND pins of the LT3042; do not
drive ILIM more than 0.3V below GND during normal
operation or during a fault condition.
PGFB (Pin 6): Power Good Feedback. The PG pin pulls
high if PGFB increases beyond 300mV on its rising edge,
with 7mV hysteresis on its falling edge. Connecting an
external resistor divider between OUT, PGFB and GND
sets the programmable power good threshold with the
following transfer function: 0.3V • (1 + RPG2 /RPG1). As
discussed in the Applications Information section, PGFB
also activates the fast start-up circuitry. Tie PGFB to IN
if power good and fast start-up functionalities are not
needed, and if reverse input protection is additionally
required, tie the anode of a 1N4148 diode to IN and its
cathode to PGFB. See the Typical Applications section for
details. A parasitic substrate diode exists between PGFB
and GND pins of the LT3042; do not drive PGFB more
than 0.3V below GND during normal operation or during
a fault condition.
SET (Pin 7): SET. This pin is the inverting input of the error
amplifier and the regulation set-point for the LT3042. SET
sources a precision 100µA current that flows through an
external resistor connected between SET and GND. The
LT3042’s output voltage is determined by VSET = ISET • RSET.
Output voltage range is from zero to 15V. Adding a capacitor from SET to GND improves noise, PSRR and transient
response at the expense of increased start-up time. For
optimum load regulation, Kelvin connect the ground side
of the SET pin resistor directly to the load. A parasitic
substrate diode exists between SET and GND pins of the
LT3042; do not drive SET more than 0.3V below GND
during normal operation or during a fault condition.
GND (Pin 8, Exposed Pad Pin 11): Ground. The exposed
backside is an electrical connection to GND. To ensure
proper electrical and thermal performance, solder the
exposed backside to the PCB ground and tie it directly to
the GND pin.
3042fb
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LT3042
PIN FUNCTIONS
OUTS (Pin 9): Output Sense. This pin is the noninverting input to the error amplifier. For optimal transient
performance and load regulation, Kelvin connect OUTS
directly to the output capacitor and the load. Also, tie the
GND connections of the output capacitor and the SET
pin capacitor directly together. Moreover, place the input
and output capacitors (and their GND connections) very
close together. A parasitic substrate diode exists between
OUTS and GND pins of the LT3042; do not drive OUTS
more than 0.3V below GND during normal operation or
during a fault condition.
OUT (Pin 10): Output. This pin supplies power to the load.
For stability, use a minimum 4.7µF output capacitor with
an ESR below 50mΩ and an ESL below 2nH. Large load
transients require larger output capacitance to limit peak
voltage transients. Refer to the Applications Information
section for more information on output capacitance. A
parasitic substrate diode exists between OUT and GND pins
of the LT3042; do not drive OUT more than 0.3V below
GND during normal operation or during a fault condition.
BLOCK DIAGRAM
VIN
3
EN/UV
CIN
IN
1, 2
CURRENT
REFERENCE
2mA
100µA
–
+
ENABLE
COMPARATOR
+
–
+
–
BIAS
INPUT
UVLO
V
+
–
300mV
–
OUT
COUT
RPG2
4
PG
RPG
GND
8
–
300mV
+
V
PGFB
270Ω
+
PROGRAMMABLE
CURRENT LIMIT
SET-TO-OUTS
PROTECTION
CLAMP
6
VOUT
INTERNAL CURRENT
LIMIT
V
INPUT UVLO
CURRENT LIMIT
THERMAL SHDN
DROPOUT
FAST START-UP
DISABLE LOGIC
10
RL
1.5V
–
+
–
+
–
+
THERMAL
SHDN
FAST START-UP
PROGRAMMABLE
POWER GOOD
V
QPWR
OUTPUT OVERSHOOT
RECOVERY
1.24V
+
QP
QC
DRIVER
–
+
V
ERROR
AMPLIFIER
7
SET
RSET
9
OUTS
CSET
–
300mV
5
ILIM
RILIM
RPG1
3042 BD
3042fb
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13
LT3042
APPLICATIONS INFORMATION
The LT3042 is a high performance low dropout linear
regulator featuring LTC’s ultralow noise (2nV/√Hz at
10kHz) and ultrahigh PSRR (79dB at 1MHz) architecture
for powering noise sensitive applications. Designed as a
precision current source followed by a high performance
rail-to-rail voltage buffer, the LT3042 can be easily paralleled to further reduce noise, increase output current and
spread heat on the PCB. The device additionally features
programmable current limit, fast start-up capability and
programmable power good.
The LT3042 is easy to use and incorporates all of the
protection features expected in high performance regulators. Included are short-circuit protection, safe operating
area protection, reverse battery protection, reverse current
protection, and thermal shutdown with hysteresis.
Output Voltage
The LT3042 incorporates a precision 100µA current source
flowing out of the SET pin, which also ties to the error
amplifier’s inverting input. Figure 1 illustrates that connecting a resistor from SET to ground generates a reference
voltage for the error amplifier. This reference voltage is
simply the product of the SET pin current and the SET
pin resistor. The error amplifier’s unity-gain configuration
produces a low impedance version of this voltage on its
noninverting input, i.e. the OUTS pin, which is externally
tied to the OUT pin.
The LT3042’s rail-to-rail error amplifier and current reference allows for a wide output voltage range from 0V (using a 0Ω resistor) to VIN minus dropout — up to 15V. A
PNP-based input pair is active for 0V to 0.6V output and an
VIN
5V ±5%
LT3042
IN
100µA
4.7µF
–
+
EN/UV
OUT
PGFB
VOUT, 3.3V
IOUT(MAX), 200mA
OUTS
SET
GND ILIM
4.7µF
PG
3042 F01
0.47µF
33.2k
Figure 1. Basic Adjustable Regulator
14
NPN-based input pair is active for output voltages greater
than 1.3V, with a smooth transition between the two input
pairs from 0.6V to 1.3V output. While the NPN-based input
pair is designed to offer the best overall performance, refer
to the Electrical Characteristics Table for details on offset
voltage, SET pin current, output noise and PSRR variation
with the error amp input pair. Table 1 lists many common
output voltages and their corresponding 1% RSET resistors.
Table 1. 1% Resistor for Common Output Voltages
VOUT (V)
RSET (kΩ)
2.5
24.9
3.3
33.2
5
49.9
12
121
15
150
The benefit of using a current reference compared with
a voltage reference as used in conventional regulators is
that the regulator always operates in unity gain configuration, independent of the programmed output voltage. This
allows the LT3042 to have loop gain, frequency response
and bandwidth independent of the output voltage. As a
result, noise, PSRR and transient performance do not
change with output voltage. Moreover, since none of the
error amp gain is needed to amplify the SET pin voltage
to a higher output voltage, output load regulation is more
tightly specified in the hundreds of microvolts range and
not as a fixed percentage of the output voltage.
Since the zero TC current source is highly accurate, the
SET pin resistor can become the limiting factor in achieving high accuracy. Hence, it should be a precision resistor.
Additionally, any leakage paths to or from the SET pin
create errors in the output voltage. If necessary, use high
quality insulation (e.g., Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and other
residues may be required. High humidity environments
may require a surface coating at the SET pin to provide
a moisture barrier.
Minimize board leakage by encircling the SET pin with a
guard ring operated at a potential close to itself — ideally
tied to the OUT pin. Guarding both sides of the circuit
board is recommended. Bulk leakage reduction depends
on the guard ring width. Leakages of 100nA into or out of
3042fb
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LT3042
APPLICATIONS INFORMATION
the SET pin creates a 0.1% error in the reference voltage.
Leakages of this magnitude, coupled with other sources
of leakage, can cause significant errors in the output voltage, especially over wide operating temperature range.
Figure 2illustrates a typical guard ring layout technique.
VIN
IN
LT3042
100µA
CIN
EN/UV
PGFB
1
10
2
9
3
11
PG
OUT
7
5
6
VOUT
IOUT(MAX): 200mA
OUTS
SET
8
4
OUT
DEMO BOARD
PCB LAYOUT
ILLUSTRATES
4-TERMINAL
CONNECTION
TO COUT
GND
COUT
ILIM
SET
RSET
3042 F02
CSET
Figure 2. Guard Ring Layout
3042 F03
Since the SET pin is a high impedance node, unwanted
signals may couple into the SET pin and cause erratic
behavior. This is most noticeable when operating with a
minimum output capacitor at heavy load currents. Bypassing the SET pin with a small capacitance to ground
resolves this issue — 10nF is sufficient.
For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven
by an external voltage source capable of sinking 100µA.
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage due
to the reference current and SET pin resistor tolerances.
Output Sensing and Stability
The LT3042’s OUTS pin provides a Kelvin sense connection
to the output. The SET pin resistor’s GND side provides a
Kelvin sense connection to the load’s GND side.
Additionally, for ultrahigh PSRR, the LT3042 bandwidth
is made quite high (~1MHz), making it close to a typical
4.7µF (1206 case size) ceramic output capacitor’s selfresonance frequency (~2.3MHz). Therefore, it is very
important to avoid adding extra impedance (ESR and
ESL) outside the feedback loop. To that end, as shown
in Figure 3, minimize the effects of PCB trace and solder
inductance by tying the OUTS pin directly to COUT and the
GND side of CSET directly to the GND side of COUT, as
well as keep the GND sides of CIN and COUT reasonably
close. Refer to the LT3042 demo board manual for more
information on the recommended layout that meets these
Figure 3. COUT and CSET Connections for Stability
requirements. While the LT3042 is robust enough not
to oscillate if the recommended layout is not followed,
depending on the actual layout, phase/gain margin, noise
and PSRR performance may degrade.
Stability and Output Capacitance
The LT3042 requires an output capacitor for stability.
Given its high bandwidth, LTC recommends low ESR and
ESL ceramic capacitors. A minimum 4.7µF output capacitor with an ESR below 50mΩ and an ESL below 2nH is
required for stability.
Given the high PSRR and low noise performance attained
using a single 4.7µF ceramic output capacitor, larger values
of output capacitor only marginally improves the performance because the regulator bandwidth decreases with
increasing output capacitance — hence, there is little to
be gained by using larger than the minimum 4.7µF output
capacitor. Nonetheless, larger values of output capacitance
do decrease peak output deviations during a load transient.
Note that bypass capacitors used to decouple individual
components powered by the LT3042 increase the effective
output capacitance.
Give extra consideration to the type of ceramic capacitors
used. They are manufactured with a variety of dielectrics,
each with different behavior across temperature and applied
voltage. The most common dielectrics used are specified
with EIA temperature characteristic codes of Z5U, Y5V,
3042fb
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15
LT3042
APPLICATIONS INFORMATION
X5R
–20
–40
–60
Y5V
–80
–100
0
2
4
16
14
6
12
8 10
DC BIAS VOLTAGE (V)
3042 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
X5R
0
–20
–40
Y5V
–60
–80
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress upon
it, similar to how a piezoelectric microphone works. For a
ceramic capacitor, this stress can be induced by mechanical
vibrations within the system or due to thermal transients.
LT3042 applications in high vibration environments have
three distinct piezoelectric noise generators: ceramic
output, input, and SET pin capacitors. However, due to
LT3042’s very low output impedance over a wide frequency range, negligible output noise is generated using
a ceramic output capacitor. Similarly, due to LT3042’s
ultrahigh PSRR, negligible output noise is generated
using a ceramic input capacitor. Nonetheless, given the
high SET pin impedance, any piezoelectric response
from a ceramic SET pin capacitor generates significant
output noise – peak-to-peak excursions of hundreds of
µVs. However, due to the SET pin capacitor’s high ESR
–100
–50
–25
0
25
75
50
TEMPERATURE (°C)
100
125
3042 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
20
1210, 2.2mm THICK
1206, 1.8mm THICK
0805, 1.4mm THICK
0
CHANGE IN VALUE (%)
High Vibration Environments
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
CHANGE IN VALUE (%)
X5R and X7R dielectrics result in more stable characteristics and are thus more suitable for LT3042. The X7R
dielectric has better stability across temperature, while
the X5R is less expensive and is available in higher values.
Nonetheless, care must still be exercised when using
X5R and X7R capacitors. The X5R and X7R codes only
specify operating temperature range and the maximum
capacitance change over temperature. While capacitance
change due to DC bias for X5R and X7R is better than
Y5V and Z5U dielectrics, it can still be significant enough
to drop capacitance below sufficient levels. As shown in
Figure 6, capacitor DC bias characteristics tend to improve
as component case size increases, but verification of
expected capacitance at the operating voltage is highly
recommended.
20
CHANGE IN VALUE (%)
X5R and X7R. The Z5U and Y5V dielectrics are good for
providing high capacitance in the small packages, but they
tend to have stronger voltage and temperature coefficients
as shown in Figure 4 and Figure 5. When used with a 5V
regulator, a 16V 10µF Y5V capacitor can exhibit an effective
value as low as 1µF to 2µF for the DC bias voltage applied
over the operating temperature range.
–20
–40
–60
–80
–100
MURATA: X7R, 25V,4.7µF CERAMIC
1
5
10
15
DC BIAS (V)
20
25
3042 F06
Figure 6. Capacitor Voltage Coefficient for Different Case Sizes
3042fb
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LT3042
APPLICATIONS INFORMATION
and ESL tolerance, any non-piezoelectrically responsive
(tantalum, electrolytic, or film) capacitor can be used at
the SET pin – although electrolytic capacitors tend to have
high 1/f noise. In any case, use of surface mount capacitor
is highly recommended.
Stability and Input Capacitance
The LT3042 is stable with a minimum 4.7µF IN pin capacitor.
LTC recommends using low ESR ceramic capacitors. In
cases where long wires connect the power supply to the
LT3042’s input and ground terminals, the use of low value
input capacitors combined with a large load current can
result in instability. The resonant LC tank circuit formed by
the wire inductance and the input capacitor is the cause
and not because of LT3042’s instability.
The self-inductance, or isolated inductance, of a wire
is directly proportional to its length. The wire diameter,
however, has less influence on its self-inductance. For
example, the self-inductance of a 2-AWG isolated wire
with a diameter of 0.26" is about half the inductance of a
30-AWG wire with a diameter of 0.01". One foot of 30-AWG
wire has 465nH of self-inductance.
Several methods exist to reduce a wire’s self-inductance.
One method divides the current flowing towards the LT3042
between two parallel conductors. In this case, placing the
wires further apart reduces the inductance; up to a 50%
reduction when placed only a few inches apart. Splitting
the wires connect two equal inductors in parallel. However,
when placed in close proximity to each other, their mutual inductance adds to the overall self inductance of the
wires — therefore a 50% reduction is not possible in such
cases. The second and more effective technique to reduce
the overall inductance is to place the forward and return
current conductors (the input and ground wires) in close
proximity. Two 30-AWG wires separated by 0.02" reduce
the overall inductance to about one-fifth of a single wire.
If a battery mounted in close proximity powers the LT3042,
a 4.7µF input capacitor suffices for stability. However, if a
distantly located supply powers the LT3042, use a larger
value input capacitor. Use a rough guideline of 1µF (in
addition to the 4.7µF minimum) per 8" of wire length.
The minimum input capacitance needed to stabilize the
application also varies with the output capacitance as well
as the load current. Placing additional capacitance on the
LT3042’s output helps. However, this requires significantly
more capacitance compared to additional input bypassing.
Series resistance between the supply and the LT3042 input
also helps stabilize the application; as little as 0.1Ω to 0.5Ω
suffices. This impedance dampens the LC tank circuit at
the expense of dropout voltage. A better alternative is to
use a higher ESR tantalum or electrolytic capacitor at the
LT3042 input in parallel with a 4.7µF ceramic capacitor.
PSRR and Input Capacitance
For applications utilizing the LT3042 for post-regulating
switching converters, placing a capacitor directly at
the LT3042 input results in ac current (at the switching
frequency) to flow near the LT3042. This relatively high
frequency switching current generates a magnetic field
that couples to the LT3042 output, thereby degrading its
effective PSRR. While highly dependent on the PCB, the
switching pre-regulator, the input capacitance, amongst
other factors, the PSRR degradation can be easily over
30dB at 1MHz. This degradation is present even if the
LT3042 is de-soldered from the board, because it effectively degrades the PSRR of the PC board itself. While
negligible for conventional low PSRR LDOs, LT3042’s
ultrahigh PSRR requires careful attention to higher order
parasitics in order to extract the full performance offered
by the regulator.
To mitigate the flow of high-frequency switching current
near the LT3042, the LT3042 input capacitor can be entirely
removed—as long as the switching converter’s output
capacitor is located more than an inch away from the
LT3042. Magnetic coupling rapidly decreases with increasing distance. Nonetheless, if the switching pre-regulator
is placed too far away (conservatively more than a couple
inches) from the LT3042, with no input capacitor present,
as with any regulator, the LT3042 input will oscillate at the
parasitic LC resonance frequency. Besides, it is generally a
very common (and a preferred) practice to bypass regulator input with some capacitance. So this option is fairly
limited in its scope and not the most palatable solution.
3042fb
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17
LT3042
APPLICATIONS INFORMATION
To that end, LTC recommends using the LT3042 demo
board (DC2246B) layout for achieving the best possible
PSRR performance. The LT3042 demo board layout
utilizes magnetic field cancellation techniques to prevent
PSRR degradation caused by this high-frequency current
flow—while utilizing the input capacitor.
Filtering High Frequency Spikes
For applications where the LT3042 is used to post-regulate
a switching converter, its high PSRR effectively suppresses any “noise” present at the switcher’s switching
frequency — typically 100kHz to 4MHz. However, the very
high frequency (100s of MHz) “spikes” — beyond the
LT3042’s bandwidth — associated with the switcher’s
power switch transition times will almost directly pass
through the LT3042. While the output capacitor is partly
intended to absorb these spikes, its ESL will limit its ability
at these frequencies. A ferrite bead or even the inductance
associated with a short (e.g. 0.5”) PCB trace between the
switcher’s output and the LT3042’s input can serve as an
LC-filter to suppress these very high frequency spikes.
Output Noise
The LT3042 offers many advantages with respect to noise
performance. Traditional linear regulators have several
sources of noise. The most critical noise sources for a
traditional regulator are its voltage reference, error amplifier,
noise from the resistor divider network used for setting
output voltage and the noise gain created by this resistor
divider. Many low noise regulators pin out their voltage
reference to allow for noise reduction by bypassing the
reference voltage.
Unlike most linear regulators, the LT3042 does not use a
voltage reference; instead, it uses a 100µA current reference. The current reference operates with typical noise
current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz
bandwidth). The resultant voltage noise equals the current
noise multiplied by the resistor value, which in turn is RMS
summed with the error amplifier’s noise and the resistor’s
own noise of √4kTR — whereby k = Boltzmann’s constant
1.38 • 10–23J/K and T is the absolute temperature.
One problem that conventional linear regulators face is
that the resistor divider setting the output voltage gains up
18
the reference noise. In contrast, the LT3042’s unity-gain
follower architecture presents no gain from the SET pin
to the output. Therefore, if a capacitor bypasses the SET
pin resistor, then the output noise is independent of the
programmed output voltage. The resultant output noise
is then set just by the error amplifier’s noise — typically
2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz to
100kHz bandwidth using a 4.7µF SET pin capacitor. Paralleling multiple LT3042s further reduces noise by √N, for
N parallel regulators.
Refer to the Typical Performance Characteristics section
for noise spectral density and RMS integrated noise over
various load currents and SET pin capacitances.
Set Pin (Bypass) Capacitance: Noise, PSRR, Transient
Response and Soft-Start
In addition to reducing output noise, using a SET pin bypass
capacitor also improves PSRR and transient performance.
Note that any bypass capacitor leakage deteriorates the
LT3042’s DC regulation. Capacitor leakage of even 100nA
is a 0.1% DC error. Therefore, LTC recommends the use
of a good quality low leakage ceramic capacitor.
Using a SET pin bypass capacitor also soft-starts the output
and limits inrush current. The RC time constant, formed
by the SET pin resistor and capacitor, controls soft-start
time. Ramp-up rate from 0 to 90% of nominal VOUT is:
tSS ≈ 2.3 • RSET • CSET (fast start-up disabled)
Fast Start-Up
For ultralow noise applications that require low 1/f noise
(i.e. at frequencies below 100Hz), a larger value SET pin
capacitor is required, up to 22µF. While normally this would
significantly increase the regulator’s start-up time, the
LT3042 incorporates fast start-up circuitry that increases
the SET pin current to about 2mA during start-up.
As shown in the Block Diagram, the 2mA current source
remains engaged while PGFB is below 300mV, unless the
regulator is in current limit, dropout, thermal shutdown
or input voltage is below minimum VIN.
If fast start-up capability is not used, tie PGFB to IN or to
OUT for output voltages above 300mV. Note that doing
so also disables power good functionality.
3042fb
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LT3042
APPLICATIONS INFORMATION
ENABLE/UVLO
The EN/UV pin is used to put the regulator into a micropower shutdown state. The LT3042 has an accurate
1.24V turn-on threshold on the EN/UV pin with 170mV
of hysteresis. This threshold can be used in conjunction
with a resistor divider from the input supply to define an
accurate undervoltage lockout (UVLO) threshold for the
regulator. The EN/UV pin current (IEN) at the threshold from
the Electrical Characteristics table needs to be considered
when calculating the resistor divider network:
⎞
⎛ R
VIN(UVLO) = 1.24V • ⎜ 1+ EN2 ⎟ +IEN • R EN2
⎝ R EN1 ⎠
The EN/UV pin current (IEN) can be ignored if REN1 is less
than 100k. If unused, tie EN/UV pin to IN.
Programmable Power Good
As illustrated in the Block Diagram, power good threshold is user programmable using the ratio of two external
resistors, RPG2 and RPG1:
⎞
⎛ R
VOUT(PG _ THRESHOLD) = 0.3V • ⎜ 1+ PG2 ⎟ +IPGFB • R PG2
⎝ R PG1 ⎠
If the PGFB pin increases above 300mV, the open-collector
PG pin de-asserts and becomes high impedance. The
power good comparator has 7mV hysteresis and 5µs of
deglitching. The PGFB pin current (IPGFB) from the Electrical
Characteristics table must be considered when determining
the resistor divider network. The PGFB pin current (IPGFB)
can be ignored if RPG1 is less than 30k. If power good
functionality is not used, float the PG pin. Please note that
programmable power good and fast start-up capabilities
are disabled for output voltages below 300mV or when
the device is in shutdown.
Externally Programmable Current Limit
The ILIM pin’s current limit threshold is 300mV. Connecting
a resistor from ILIM to GND sets the maximum current
flowing out of the ILIM pin, which in turn programs the
LT3042’s current limit. With a 125mA • kΩ programming
scale factor, the current limit can be calculated as follows:
For example, a 1kΩ resistor programs the current limit to
125mA and a 2kΩ resistor programs the current limit to
62.5mA. For good accuracy, Kelvin connect this resistor
to the LT3042’s GND pin.
In cases where IN-to-OUT differential is greater than 12V,
the LT3042’s foldback circuitry decreases the internal
current limit. As a result, internal current limit may override the externally programmed current limit level to keep
the LT3042 within its safe-operating-area (SOA). See the
Internal Current Limit vs Input-to-Output Differential graph
in the Typical Performance Characteristics section.
As shown in the Block Diagram, the ILIM pin sources current
proportional (1:400) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
range. If external current limit or current monitoring is
not used, tie ILIM to GND.
Output Overshoot Recovery
During a load step from full load to no load (or light
load), the output voltage overshoots before the regulator
responds to turn the power transistor OFF. Given that there
is no load (or very light load) present at the output, it takes
a long time to discharge the output capacitor.
As illustrated in the Block Diagram, the LT3042 incorporates
an overshoot recovery circuitry that turns on a current
sink to discharge the output capacitor in the event OUTS
is higher than SET. This current is typically about 4mA.
No load recovery is disabled for input voltages less than
2.5V or output voltages less than 1.5V.
If OUTS is externally held above SET, the current sink
turns ON in an attempt to restore OUTS to its programmed
voltage. The current sink remains ON until the external
circuitry releases OUTS.
Direct Paralleling for Higher Current
Higher output current is obtained by paralleling multiple
LT3042s. Tie all SET pins together and all IN pins together.
Connect the OUT pins together using small pieces of PCB
trace (used as a ballast resistor) to equalize currents in
the LT3042s. PCB trace resistance in milliohms/inch is
shown in Table 2.
Current Limit = 125mA • kΩ / RILIM
3042fb
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19
LT3042
APPLICATIONS INFORMATION
PCB Layout Considerations
Table 2. PC Board Trace Resistance
WEIGHT (oz)
10mil WIDTH
20mil WIDTH
1
54.3
27.1
2
27.1
13.6
Trace resistance is measured in mΩ/in.
The small worst-case offset of 2mV for each paralleled
LT3042 minimizes the required ballast resistor value.
Figure 7 illustrates that two LT3042s, each using a 50mΩ
PCB trace ballast resistor, provide better than 20% accurate output current sharing at full load. The two 50mΩ
external resistors only add 10mV of output regulation drop
with a 400mA maximum current. With a 3.3V output, this
only adds 0.3% to the regulation accuracy. As has been
discussed previously, tie the OUTS pin directly to the
output capacitor.
Given the LT3042’s high bandwidth and ultrahigh PSRR,
careful PCB layout must be employed to achieve full
device performance. Figure 8 shows an example layout
that delivers full performance of the regulator. Refer to the
LT3042’s DC2246B demo board manual for further details.
More than two LT3042s can also be paralleled for even
higher output current and lower output noise. Paralleling
multiple LT3042s is also useful for distributing heat on the
PCB. For applications with high input-to-output voltage
differential, an input series resistor or resistor in parallel
with the LT3042 can also be used to spread heat.
VIN
5V ±5%
LT3042
IN
100µA
10µF
–
+
EN/UV
OUT
PGFB
3042 F08
50mΩ
OUTS
SET
GND ILIM
PG
VOUT
3.3V
IOUT(MAX)
400mA
LT3042
IN
Figure 8. Example DFN Layout
4.7µF
100µA
–
+
EN/UV
OUT
PGFB
50mΩ
OUTS
SET
GND ILIM
PG
4.7µF
3042 F07
16.5k
0.47µF
Figure 7. Parallel Devices
20
3042fb
For more information www.linear.com/LT3042
LT3042
APPLICATIONS INFORMATION
Thermal Considerations
Table 3. Measured Thermal Resistance for DFN Package
The LT3042 has internal power and thermal limiting circuits
that protect the device under overload conditions. The
thermal shutdown temperature is nominally 162°C with
about 8°C of hysteresis. For continuous normal load conditions, do not exceed the maximum junction temperature,
(125°C for E-, I-grades and 150°C for H-, MP-grades). It
is important to consider all sources of thermal resistance
from junction to ambient. This includes junction-to-case,
case-to-heat sink interface, heat sink resistance or circuit
board-to-ambient as the application dictates. Additionally,
consider all heat sources in close proximity to the LT3042.
The undersides of the DFN and MSOP packages have
exposed metal from the lead frame to the die attachment.
Both packages allow heat to directly transfer from the die
junction to the PCB metal to limit maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PCB and its
copper traces. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by
the regulator.
Tables 3 and 4 list thermal resistance as a function of copper
area on a fixed board size. All measurements were taken
in still air on a 4 layer FR-4 board with 1oz solid internal
planes and 2oz top/bottom planes with a total board thickness of 1.6mm. The four layers were electrically isolated
with no thermal vias present. PCB layers, copper weight,
board layout and thermal vias affect the resultant thermal
resistance. For more information on thermal resistance
and high thermal conductivity test boards, refer to JEDEC
standard JESD51, notably JESD51-7 and JESD51-12.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout.
COPPER AREA
TOP SIDE*
BOTTOM SIDE
BOARD AREA
THERMAL
RESISTANCE
2500mm2
2500mm2
2500mm2
34°C/W
1000mm2
2500mm2
2500mm2
34°C/W
225mm2
2500mm2
2500mm2
35°C/W
100mm2
2500mm2
2500mm2
36°C/W
*Device is mounted on topside
Table 4. Measured Thermal Resistance for MSOP Package
COPPER AREA
TOP SIDE*
BOTTOM SIDE
BOARD AREA
THERMAL
RESISTANCE
2500mm2
2500mm2
2500mm2
33°C/W
1000mm2
2500mm2
2500mm2
33°C/W
225mm2
2500mm2
2500mm2
34°C/W
100mm2
2500mm2
2500mm2
35°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 2.5V and input voltage
of 5V ± 5%, output current range from 1mA to 200mA,
and a maximum ambient temperature of 85°C, what is the
maximum junction temperature?
The LT3042’s power dissipation is:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = 200mA
VIN(MAX) = 5.25V
IGND (at IOUT = 200mA and VIN = 5.25V) = 7.2mA
thus:
PDISS = 0.2A • (5.25V – 2.5V) + 7.2mA • 5.25V = 0.59W
Using a DFN package, the thermal resistance is in the
range of 34°C/W to 36°C/W depending on the copper area.
Therefore, the junction temperature rise above ambient
approximately equals:
0.59W • 35°C/W = 20.7°C
3042fb
For more information www.linear.com/LT3042
21
LT3042
APPLICATIONS INFORMATION
The maximum junction temperature equals the maximum ambient temperature plus the maximum junction
temperature rise above ambient:
TJMAX = 85°C + 20.7°C = 105.7°C
Overload Recovery
Like many IC power regulators, the LT3042 incorporates
safe-operating-area (SOA) protection. The SOA protection
activates at input-to-output differential voltages greater
than 12V. The SOA protection decreases the current limit
as the input-to-output differential increases and keeps
the power transistor inside a safe operating region for
all values of input-to-output voltages up to the LT3042’s
absolute maximum ratings. The LT3042 provides some
level of output current for all values of input-to-output differentials. Refer to the Current Limit curves in the Typical
Performance Characteristics section. When power is first
applied and input voltage rises, the output follows the input
and keeps the input-to-output differential low to allow the
regulator to supply large output current and start-up into
high current loads.
Due to current limit foldback, however, at high input voltages a problem can occur if the output voltage is low and
the load current is high. Such situations occur after the
removal of a short-circuit or if the EN/UV pin is pulled high
after the input voltage has already turned ON. The load line
in such cases intersects the output current profile at two
points. The regulator now has two stable operating points.
With this double intersection, the input power supply may
need to be cycled down to zero and brought back up again
to make the output recover. Other linear regulators with
foldback current limit protection (such as the LT1965 and
LT1963A, etc.) also exhibit this phenomenon, so it is not
unique to the LT3042.
22
Protection Features
The LT3042 incorporates several protection features for
battery-powered applications. Precision current limit and
thermal overload protection protect the LT3042 against
overload and fault conditions at the device’s output. For
normal operation, do not allow the junction temperature
to exceed 125°C (E-, I-grade) or 150°C (H-, MP-grade).
To protect the LT3042’s low noise error amplifier, the SETto-OUTS protection clamp limits the maximum voltage
between SET and OUTS with a maximum DC current of
20mA through the clamp. So for applications where SET
is actively driven by a voltage source, the voltage source
must be current limited to 20mA or less. Moreover, to limit
the transient current flowing through these clamps during
a transient fault condition, limit the maximum value of the
SET pin capacitor (CSET) to 22µF.
The LT3042 also incorporates reverse input protection
whereby the IN pin withstands reverse voltages of up to
–20V without causing any input current flow and without
developing negative voltages at the OUT pin. The regulator
protects both itself and the load against batteries that are
plugged-in backwards.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
GND, pulled to some intermediate voltage, or left opencircuit. In all of these cases, the reverse current protection
circuitry prevents current flow from output to the input.
Nonetheless, due to the OUTS-to-SET clamp, unless the
SET pin is floating, current can flow to GND through the
SET pin resistor as well as up to 15mA to GND through
the output overshoot recovery circuitry. This current flow
through the output overshoot recovery circuitry can be
significantly reduced by placing a Schottky diode between
OUTS and SET pins, with its anode at the OUTS pin.
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL APPLICATIONS
12VIN to 3.3VOUT with 0.8µVRMS Integrated Noise
VIN
12V ±5%
LT3042
IN
4.7µF
100µA
EN/UV
200k
–
+
VOUT
3.3V
IOUT(MAX)
100mA
OUT
PG
OUTS
SET
ILIM
GND
PGFB
4.7µF
453k
1k
33.2k
4.7µF
49.9k
3042 TA02
PGFB Disabled without Reverse Input Protection
LT3042
IN
VIN
4.7µF
PGFB Disabled with Reverse Input Protection
4.7µF
100µA
–
+
EN/UV
–
+
1N4148
OUT
PG
0.47µF
100µA
EN/UV
PGFB
OUT
VOUT
PGFB
OUTS
SET
LT3042
IN
VIN
GND
ILIM
PG
4.7µF
RSET
0.47µF
VOUT
OUTS
SET
GND
ILIM
4.7µF
RSET
3042 TA03
3042 TA04
Low Noise CC/CV Lab Power Supply
LT3042
IN
VIN
4.7µF
VOUT(MAX) = 100μA • RSET
100µA
–
+
EN/UV
IOUT(MAX) =
PGFB
OUT
PG
VOUT
OUTS
SET
0.47µF
125mA • kΩ
RIOUT
RSET
GND
ILIM
4.7µF
RIOUT
3042 TA05
3042fb
For more information www.linear.com/LT3042
23
LT3042
TYPICAL APPLICATIONS
Programming Undervoltage Lockout
VIN
4V Turn-ON
3.4V Turn-OFF
4.7µF
⎛
110k ⎞⎟
VIN(UVLO) = 1.24V • ⎜⎜ 1+
⎟
⎝ 49.9k ⎠
LT3042
IN
100µA
PGFB
REN2
110k
PG
–
+
VOUT
3.3V
IOUT(MAX)
200mA
OUT
EN/UV
REN1
49.9k
OUTS
SET
4.7µF
GND ILIM
3042 TA06
0.47µF
33.2k
Ratiometric Tracking
LT3042
IN
100µA
–
+
EN/UV
PGFB
IN
VIN
5.5V TO 20V
EN/UV
0.1µF
PGFB
OUT
PG
OUTS
SET
0.1µF
24
GND
ILIM
4.7µF
VOUT
5V
OUTS
SET
100µA
4.7µF
OUT
PG
LT3042
16.9k
GND
4.7µF
ILIM
3042 TA07
VOUT
3.3V
MIN LOAD 200µA
33.2k
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL APPLICATIONS
Ultralow 1/f Noise Reference Buffer
VIN
6V ±5%
LT3042
IN
100µA
4.7µF
–
+
EN/UV
PGFB
1,2
PG
6,7
LTC6655-5
OUTS
SET
3,4,5
VOUT = 5V
IOUT(MAX)
200mA
OUT
GND
4.7µF
ILIM
1k
3042 TA08
10µF
49.9k
4.7µF
Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop
LT3042
IN
22µF
LT3042
100µA
EN/UV
VOUT = 3.3V
IOUT(MAX) = 400mA
PGFB
OUT
PG
OUTS
SET
IN
100µA
–
+
GND
ILIM
+
–
VIN
5V ±5%
OUT
50mΩ
50mΩ
4.7µF
4.7µF
RILIM
549Ω
EN/UV
PGFB
PG
OUTS
ILIM
GND
SET
549Ω
3042 TA09
1µF
16.5k
N = NUMBER OF DEVICES IN PARALLEL
RCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR
RILIM = CURRENT LIMIT PROGRAMMING RESISTOR
RBALLAST = BALLAST RESISTOR
ILIM = OUTPUT CURRENT LIMIT
RCDC
10Ω
RILIM = 125mA • kΩ/ILIM – RCDC • N
= 549Ω (FOR 200mA ILIM PER REGULATOR)
RCDC = RBALLAST • 400/N
= 10Ω
3042fb
For more information www.linear.com/LT3042
25
LT3042
TYPICAL APPLICATIONS
Paralleling Multiple LT3042s for Higher Output Current
LT3042
IN
VIN
5V ±5%
4.7µF
LT3042
100µA
IN
100µA
EN/UV
PNP
Q1
PNP
Q2
OUT
OUT
200k
PG
50mΩ
OUTS
SET ILIM
GND
PGFB
50mΩ
4.7µF
+
–
–
+
EN/UV
PGFB
PG
OUTS
ILIM
4.7µF
GND
SET
453k
49.9k
VOUT = 3.3V
IOUT(MAX) = 800mA
DROPOUT = 350mV
0.8µVRMS
4
= 0.4µVRMS
OUTPUT NOISE =
LT3042
IN
LT3042
100µA
100µA
PNP
Q4
PGFB
PNP
Q3
OUT
PG
OUT
OUTS
SET
GND
ILIM
4.7µF
50mΩ
50mΩ
4.7µF
4.7µF
+
–
–
+
EN/UV
IN
EN/UV
PGFB
PG
OUTS
ILIM
GND
SET
8.25k
3042 TA10
26
3042fb
For more information www.linear.com/LT3042
LT3042
TYPICAL APPLICATIONS
Ultralow Noise Higher Current Regulator with External PNP
VIN
5.5V ±5%
22µF
47µF
0.2Ω
10Ω
D45VH10G
150k
PGFB
LT3042
100µA
EN/UV
49.9k
IN
–
+
VOUT
3.3V
IOUT(MAX)
1.5A
10µF
OUT
PG
OUTS
SET
4.7µF
GND
ILIM
750Ω
33.2k
3042 TA11
Ultralow Noise Higher Current Regulator with External NPN
VIN
5V ±5%
47µF
LT3042
IN
100µA
–
+
EN/UV
4.7µF
OUT
PG
D44VH10
10µF
10k
OUTS
SET
4.7µF
20k
GND ILIM PGFB
750Ω
249k
VOUT
2V
10µF IOUT(MAX)
1A
49.9k
3042 TA12
3042fb
For more information www.linear.com/LT3042
27
LT3042
TYPICAL APPLICATIONS
Low Noise Wheatstone Bridge Power Supply
LT1763 NOISE: 20µVRMS (10Hz TO 100kHz)
LT3042 NOISE: 0.8µVRMS (10Hz TO 100kHz)
LT3042
IN
VIN
5V ±5%
4.7µF
100µA
EN/UV
200k
–
+
OUT
PG
RESISTOR
TOLERANCE
BRIDGE PSRR
NOISE AT VBRIDGE
USING LT1763
NOISE AT VBRIDGE
USING LT3042
PERFECT
MATCHING
INFINITE
–
–
1%
40dB
200nVRMS
8nVRMS
5%
26dB
1000nVRMS
42.5nVRMS
VOUT: 3.3V AND IOUT(MAX): 200mA
R1
OUTS
SET
GND ILIM PGFB
4.7µF
453k
+
R2
4.7µF
33.2k
R3
VBRIDGE
–
R4
49.9k
3042 TA13
28
3042fb
For more information www.linear.com/LT3042
LT3042
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3042#packaging for the most recent package drawings.
DD Package
Package
10-Lead Plastic DFNDD
(3mm
× 3mm)
10-Lead
Plastic
DFN (3mm
(Reference LTC DWG # 05-08-1699
Rev C)× 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ±0.10
10
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
5
0.75 ±0.05
0.00 – 0.05
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3042fb
For more information www.linear.com/LT3042
29
LT3042
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3042#packaging for the most recent package drawings.
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
MSE Package
(Reference LTC DWG # 05-08-1664 Rev I)
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88 ±0.102
(.074 ±.004)
5.10
(.201)
MIN
1
0.889 ±0.127
(.035 ±.005)
1.68 ±0.102
(.066 ±.004)
0.05 REF
10
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
10 9 8 7 6
DETAIL “A”
0° – 6° TYP
1 2 3 4 5
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
30
0.497 ±0.076
(.0196 ±.003)
REF
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0.254
(.010)
0.29
REF
1.68
(.066)
3.20 – 3.45
(.126 – .136)
0.50
0.305 ± 0.038
(.0197)
(.0120 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
1.88
(.074)
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE) 0213 REV I
3042fb
For more information www.linear.com/LT3042
LT3042
REVISION HISTORY
REV
DATE
DESCRIPTION
A
6/15
Updated text in the second paragraph
1
Updated Line Reg ∆VOS, Change in VOS, Output Noise Spectral Density specs
3
Updated text to clarify fast start-up test condition
4
Updated text to clarify Notes 5, 6, and 7
4
Updated text to clarify Note 10
5
Updated Graph 10 and Graph 12
6
Updated conditions on Graph 18 and Graph 24
7
Updated conditions on Graph 28
8
Updated title of Graph 40
Updated Output Voltage section
B
11/17
PAGE NUMBER
9
14, 15
Updated Fast Start-up section
18
Modified Direct Paralleling for Higher Current section
19
Updated Typical Application circuit TA02
22
Added Equation text to the Typical Application circuit TA03
22
Updated Typical Application circuit TA06 and TA13
24
Updated text in the Typical Application circuit TA14 and TA07
25
Updated text in the Typical Application circuit TA08
26
Modified Typical Application schematic.
1
Removed Ripple Rejection minimum spec in the Electrical Characteristics table.
3
Modified Start-Up Time conditions in the Electrical Characteristics table.
4
Revised Graph 37.
9
Changed scale on Graph 55.
11
Revised PGFB pin description in the Pin Functions section.
12
Modified Figure 3, and ‘Output Sensing and Stability’ and ‘Stability and Output Capacitance’ sections.
15
Added High Vibration Environments section.
16
Added PSRR + Input Capacitance section.
17
Revised Externally Programmable Current Limit section.
19
Revised Figure 8.
20
Modified Protection Features section.
22
3042fb
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license
granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
For ismore
information
www.linear.com/LT3042
31
LT3042
TYPICAL APPLICATION
Parallel Devices
LT3042
IN
VIN
5V ±5%
100µA
10µF
–
+
EN/UV
OUT
PGFB
50mΩ
OUTS
SET
ILIM
GND
PG
4.7µF
VOUT
3.3V
IOUT(MAX)
400mA
LT3042
IN
100µA
–
+
EN/UV
OUT
PGFB
50mΩ
OUTS
SET
GND
ILIM
PG
4.7µF
3042 TA14
16.5k
0.47µF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN = 1.8V to 20V,
SO-8 Package
LT3050
100mA LDO with Diagnostics and Precision Current Limit
340mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V,
3mm × 2mm DFN and MSOP Packages
LT3060
100mA Low Noise LDO with Soft-Start
300mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V,
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LT3080
1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator
300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS,
VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with
1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required),
Stable with Ceramic Capacitors; TO-220, DD-Pak, SOT-223, MSOP
and 3mm × 3mm DFN-8 Packages; LT3080-1 Version Has Integrated
Internal Ballast Resistor
LT3082
200mA, Parallelable, Low Noise LDO
Outputs May Be Paralleled for Higher Output Current or Heat Spreading,
Wide Input Voltage Range: 1.2V to 40V, Low Value Input/Output
Capacitors Required: 2.2µF, Single Resistor Sets Output Voltage,
8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN
Packages
LT3085
500mA, Parallelable, Low Noise, Low Dropout Linear
Regulator
275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V
to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor
VOUT Set, Directly Parallelable (No Op Amp Required), Stable with
Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages
32
3042fb
LT 1117 REV B • PRINTED IN USA
For more information www.linear.com/LT3042
www.linear.com/LT3042
ANALOG DEVICES, INC. 2017
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