LT3045EDD#PBF

LT3045 20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator FEATURES DESCRIPTION Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz) nn Ultralow Spot Noise: 2nV/√Hz at 10kHz nn Ultrahigh PSRR: 76dB at 1MHz nn Output Current: 500mA nn Wide Input Voltage Range: 1.8V to 20V nn Single Capacitor Improves Noise and PSRR nn 100µA SET Pin Current: ±1% Initial Accuracy nn Single Resistor Programs Output Voltage nn High Bandwidth: 1MHz nn Programmable Current Limit nn Low Dropout Voltage: 260mV nn Output Voltage Range: 0V to 15V nn Programmable Power Good nn Fast Start-Up Capability nn Precision Enable/UVLO nn Parallelable for Lower Noise and Higher Current nn Internal Current Limit with Foldback nn Minimum Output Capacitor: 10µF Ceramic nn Reverse-Battery and Reverse-Current Protection nn 12-Lead MSOP and 10-Lead 3mm × 3mm DFN Packages The LT®3045 is a high performance low dropout linear regulator featuring LTC’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive applications. Designed as a precision current reference followed by a high performance voltage buffer, the LT3045 can be easily paralleled to further reduce noise, increase output current and spread heat on the PCB. nn APPLICATIONS RF Power Supplies: PLLs, VCOs, Mixers, LNAs, PAs Very Low Noise Instrumentation nn High Speed/High Precision Data Converters nn Medical Applications: Imaging, Diagnostics nn Precision Power Supplies nn Post-Regulator for Switching Supplies nn nn The device supplies 500mA at a typical 260mV dropout voltage. Operating quiescent current is nominally 2.2mA and drops to 12V. If operating at maximum output current, limit the input voltage range. If operating at the maximum input voltage, limit the output current range. Note 4: OUTS ties directly to OUT. Note 5: Dropout voltage is the minimum input-to-output differential voltage needed to maintain regulation at a specified output current. The dropout voltage is measured when output is 1% out of regulation. This definition results in a higher dropout voltage compared to hard dropout — which is measured when VIN = VOUT(NOMINAL). For lower output voltages, below 1.5V, dropout voltage is limited by the minimum input voltage specification. For DFN package: Linear Technology is unable to %/W guarantee maximum dropout voltage specifications at high currents due to production test limitations with Kelvin-sensing the package pins. Please consult the Typical Performance Characteristics for curves of dropout voltage as a function of output load current and temperature measured in a typical application circuit. Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. Therefore, the device is tested while operating in dropout. This is the worst-case GND pin current. GND pin current decreases at higher input voltages. Note that GND pin current does not include SET pin or ILIM pin current but Quiescent current does include them. Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series resistors. For less than 5ms transients, this clamp circuitry can carry more than the rated current. Refer to Applications Information for more information. Note 8: Adding a capacitor across the SET pin resistor decreases output voltage noise. Adding this capacitor bypasses the SET pin resistor’s thermal noise as well as the reference current’s noise. The output noise then equals the error amplifier noise. Use of a SET pin bypass capacitor also increases start-up time. Rev. B 4 For more information www.analog.com LT3045 ELECTRICAL CHARACTERISTICS Note 9: The LT3045 is tested and specified under pulsed load conditions such that TJ ≈ TA. The LT3045E is 100% tested at 25°C and performance is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization, and correlation with statistical process controls. The LT3045I is guaranteed over the full –40°C to 125°C operating temperature range. LT3045H is 100% tested at the 150°C operating junction temperature. LT3045MP is 100% tested and guaranteed over the full −55°C to 150°C operating temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 10: Parasitic diodes exist internally between the ILIM, PG, PGFB, SET, OUTS, and OUT pins and the GND pin. Do not drive these pins more than 0.3V below the GND pin during a fault condition. These pins must remain at a voltage more positive than GND during normal operation. Note 11: The current limit programming scale factor is specified while the internal backup current limit is not active. Note that the internal current limit has foldback protection for VIN – VOUT differentials greater than 12V. Note 12: The internal back-up current limit circuitry incorporates foldback protection that decreases current limit for VIN – VOUT > 12V. Some level of output current is provided at all VIN – VOUT differential voltages. Consult the Typical Performance Characteristics graph for current limit vs VIN – VOUT. Note 13: For output voltages less than 1V, the LT3045 requires a 10µA minimum load current for stability. Note 14: Maximum OUT-to-OUTS differential is guaranteed by design. Note 15: MP-Grade is only offered in the DFN package. TYPICAL PERFORMANCE CHARACTERISTICS SET Pin Current 101.0 2.0 N = 3250 Offset Voltage (VOUT – VSET) VIN = 2V IL = 1mA VOUT = 1.3V 1.5 OFFSET VOLTAGE (mV) 100.6 100.4 100.2 100.0 99.8 99.6 99.4 1.0 0.5 0 –0.5 –1.0 –1.5 99.2 98 0 25 50 75 100 125 150 TEMPERATURE (°C) 99 100 101 ISET DISTRIBUTION (µA) 3045 G01 Offset Voltage 3045 G02 SET Pin Current IL = 1mA 100.8 V OUT = 1.3V 2.0 100.6 100.4 150°C 125°C 25°C –55°C 100.2 100.0 99.8 99.6 99.4 2 3045 G04 99.0 Offset Voltage (VOUT – VSET) IL = 1mA VOUT = 1.3V 1.5 1.0 150°C 125°C 25°C –55°C 0.5 0 –0.5 –1.0 –1.5 99.2 –1 0 1 VOS DISTRIBUTION (mV) 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G03 101.0 N = 3250 –2 –2.0 –75 –50 –25 102 OFFSET VOLTAGE (mV) 99.0 –75 –50 –25 SET PIN CURRENT (µA) SET PIN CURRENT (µA) SET Pin Current VIN = 2V IL = 1mA VOUT = 1.3V 100.8 TJ = 25°C, unless otherwise noted. 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) 3045 G05 –2.0 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) 3045 G06 Rev. B For more information www.analog.com 5 LT3045 TYPICAL PERFORMANCE CHARACTERISTICS SET Pin Current 101.0 2.0 100.2 100.0 99.8 99.6 99.4 1.5 0.5 0 –0.5 99.0 –2.0 3 4.5 6 7.5 9 10.5 12 13.5 15 OUTPUT VOLTAGE (V) 0 1.5 8 2.0 1.5 1.0 0.08 0.06 0.04 ISET 0.02 3 4.5 6 7.5 9 10.5 12 13.5 15 OUTPUT VOLTAGE (V) 0 –75 –50 –25 Quiescent Current 3.0 VEN/UV = VIN IL = 10µA RSET = 33.2k 2.5 40 35 30 VIN = 20V 25 20 VIN = 2V 15 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G09 VEN/UV = 0V 45 2.5 0.10 VOS Quiescent Current 50 VIN = 2V VEN/UV = VIN 3.5 IL = 10µA RSET = 13k 3.0 QUIESCENT CURRENT (µA) 10 2.0 1.5 1.0 0.5 5 0 –75 –50 –25 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Quiescent Current DROPOUT VOLTAGE (mV) 2.5 2.0 1.5 1.0 150°C 125°C 25°C –55°C 0.5 0 2 4 6 8 10 12 OUTPUT VOLTAGE (V) 16 3045 G13 450 400 350 300 250 200 150 150°C 125°C 25°C –55°C 100 50 14 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) Dropout Voltage 500 RSET = 33.2k 450 3.0 2 3045 G12 Typical Dropout Voltage 500 VIN = 20V VEN/UV = VIN IL = 10µA 3.5 0 3045 G11 3045 G10 4.0 0 0 25 50 75 100 125 150 TEMPERATURE (°C) DROPOUT VOLTAGE (mV) QUIESCENT CURRENT (mA) 10 3045 G08 0.5 QUIESCENT CURRENT (mA) 0.12 2 Quiescent Current 0 0.14 12 4 3045 G07 4.0 0.16 14 QUIESCENT CURRENT (mA) 1.5 0.18 6 –1.0 99.2 0.20 V = 2.5V 18 ∆IIN= 1mA to 500mA L 16 VOUT = 1.3V 150°C 125°C 25°C –55°C 1.0 –1.5 0 IL = 1mA VIN = 20V Load Regulation 20 ∆ISET (nA) 100.4 Offset Voltage (VOUT – VSET) ∆ VOS (mV) SET PIN CURRENT (µA) 100.6 150°C 125°C 25°C –55°C OFFSET VOLTAGE (mV) IL = 1mA VIN = 20V 100.8 TJ = 25°C, unless otherwise noted. 0 0 RSET = 33.2k 400 IL = 400mA 350 300 IL = 500mA 250 200 IL = 1mA 150 100 50 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3045 G14 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G15 Rev. B 6 For more information www.analog.com LT3045 TYPICAL PERFORMANCE CHARACTERISTICS GND Pin Current 22 VIN = 5V RSET = 33.2k 18 18 GND PIN CURRENT (mA) IL = 500mA 12 10 IL = 300mA 8 6 IL = 100mA 4 2 0 –75 –50 –25 16 14 12 10 8 6 150°C 125°C 25°C –55°C 4 2 IL = 1mA 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 1.30 1.00 0.75 0.50 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.26 1.24 VIN = 2V 1.22 VIN = 10V 1.5 150°C 125°C 25°C –55°C 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 ENABLE PIN VOLTAGE (V) EN/UV PIN CURRENT (µA) EN/UV PIN CURRENT (µA) 4.5 2.0 3 4 5 6 7 INPUT VOLTAGE (V) 8 10 VIN = 10V 140 125 110 VIN = 2V 95 80 50 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G21 Negative Enable Pin Current 0 –10 VIN = 2V 8 7 6 5 VIN = 20V 4 3 2 1 0 9 155 3045 G20 9 2.5 2 65 1.18 –75 –50 –25 VIN = 20V 3.0 1 170 EN/UV Pin Current 3.5 0 185 10 4.0 RL = 330Ω RL = 3.3kΩ EN/UV Pin Hysteresis 1.28 EN/UV Pin Current 5.0 RL = 33Ω 4 200 3045 G19 5.5 6 3045 G18 1.20 RISING UVLO FALLING UVLO RL = 11Ω 8 0 EN/UV PIN HYSTERESIS (mV) 1.75 0 –75 –50 –25 10 EN/UV Turn-On Threshold 1.32 TURN-ON THRESHOLD (V) INPUT UVLO THRESHOLD (V) Minimum Input Voltage 1.25 RL = 6.6Ω 12 3045 G17 2.00 0.25 14 2 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3045 G16 1.50 RSET = 33.2k 16 EN/UV PIN CURRENT (µA) GND PIN CURRENT (mA) 14 VIN = 4.3V RSET = 33.2k 20 16 GND Pin Current 18 GND PIN CURRENT (mA) GND Pin Current 20 TJ = 25°C, unless otherwise noted. –20 –30 –40 –50 –60 –70 –80 –90 0 2 4 6 8 10 12 14 16 18 20 ENABLE PIN VOLTAGE (V) 3045 G23 3045 G22 VIN = 2V 150°C 125°C 25°C –55°C –100 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 ENABLE PIN VOLTAGE (V) 0 3045 G24 Rev. B For more information www.analog.com 7 LT3045 TYPICAL PERFORMANCE CHARACTERISTICS Input Pin Current Internal Current Limit 0.3 1000 150°C 125°C 25°C –55°C 900 Internal Current Limit 600 RILIM = 0Ω VOUT = 0V 500 0.2 0.1 CURRENT LIMIT (mA) 800 CURRENT LIMIT (mA) INPUT CURRENT (µA) VIN = 2V TJ = 25°C, unless otherwise noted. 700 600 500 400 300 200 100 0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 ENABLE PIN VOLTAGE (V) 3045 G25 Internal Current Limit CURRENT LIMIT (mA) CURRENT LIMIT (mA) 800 700 600 500 400 150°C 125°C 25°C –55°C 100 0 RILIM = 300Ω VOUT = 0V 500 400 300 2 4 6 8 10 12 14 16 18 20 INPUT-TO-OUTPUT DIFFERENTIAL (V) 100 308 500 400 300 2.5VIN 5VIN 10VIN 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) VIN = 12V 60 20 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G30 PGFB Hysteresis 8 VIN = 2V 7 306 PGFB HYSTERESIS (mV) 600 VIN = 2.5V 80 PGFB Rising Threshold PGFB RISING THRESHOLD (mV) ILIM PIN CURRENT (uA) 120 3045 G29 VILIM = 0V 900 RSET = 13k 0 140 310 700 RILIM = 1.5k VOUT = 0V 40 VIN = 2.5V VIN = 12V 0 –75 –50 –25 ILIM Pin Current 100 160 600 100 1000 200 180 700 3045 G28 0 Programmable Current Limit 200 200 800 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G27 CURRENT LIMIT (mA) 900 800 0 0 –75 –50 –25 Programmable Current Limit RILIM = 0Ω 200 200 0 25 50 75 100 125 150 TEMPERATURE (°C) 1000 300 300 3045 G26 1000 900 400 100 VIN = 2.5V VIN = 12V 0 –75 –50 –25 0 VIN = 20V RILIM = 0Ω VOUT = 0V 304 302 300 298 296 294 6 5 4 3 2 1 292 290 –75 –50 –25 VIN = 2V 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G32 3045 G31 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G33 Rev. B 8 For more information www.analog.com LT3045 TYPICAL PERFORMANCE CHARACTERISTICS PG Output Low Voltage ISET During Start-Up with Fast Start-Up Enabled PG Pin Leakage Current 100 50 VIN = 2V VPGFB = 290mV IPG = 100µA 80 70 30 60 IPG (nA) 35 25 20 40 30 10 20 5 10 0.5 3045 G35 ISET During Start-Up with Fast Start-Up Enabled 12 VPGFB = 290mV VSET = 1.3V OUTPUT SINK CURRENT (mA) ISET (mA) 2.5 2.0 1.5 1.0 0.5 0 2 10 6 4 2 VOUT Forced Above VOUT(NOMINAL) 0 5 4 100 5 6 7 8 9 10 11 12 13 14 15 OUTPUT VOLTAGE (V) 3045 G40 2 Power Supply Ripple Rejection 110 80 80 70 60 100 70 60 50 VIN = 5V RSET = 30.1k COUT = 10µF IL = 500mA 10 COUT = 10µF COUT = 22µF 100 90 20 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G39 90 40 4 3 3045 G38 CSET = 4.7µF CSET = 0.47µF 110 30 0 4 120 50 2 5 Power Supply Ripple Rejection IIN when VEN = 0V IOUT when VEN = 0V IIN when VEN = VIN IOUT when VEN = VIN VIN = 5V RSET = 33.2k VOUT – VSET > 5mV 0 –75 –50 –25 20 120 PSRR (dB) CURRENT (mA) 6 10 15 VOUT – VSET (mV) PSRR (dB) VIN = 5V RSET = 33.2k 6 1 3045 G37 8 150°C 125°C 25°C –55°C 8 0 4 6 8 10 12 14 16 18 20 VIN-TO-VSET DIFFERENTIAL (V) Output Overshoot Recovery Current Sink 7 VIN = 5V RSET = 33.2k 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G36 Output Overshoot Recovery Current Sink 3.5 0 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3045 G34 3.0 1.5 1.0 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) VIN = 2.5V VPGFB = 290mV VSET = 1.3V 2.0 50 15 0 –75 –50 –25 2.5 ISET (mA) 40 3.0 VPG = 2V VPGFB = 310mV 90 OUTPUT SINK CURRENT (mA) 45 VPG (mV) TJ = 25°C, unless otherwise noted. VIN = 5V RSET = 30.1k 30 CSET = 0.47µF IL = 500mA 20 10 100 1k 10k 100k FREQUENCY (Hz) 40 1k 10k 100k FREQUENCY (Hz) 1M 10M 3045 G41 1M 10M 3045 G42 Rev. B For more information www.analog.com 9 LT3045 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Ripple Rejection as a Function of Error Amplifier Input Pair Power Supply Ripple Rejection 140 120 120 100 90 80 10 100 70 60 VIN = 5V RSET = 30.1k COUT = 10µF CSET = 0.47µF 1k 10k 100k FREQUENCY (Hz) 1M 20 10M 40 10 100 10 1k 10k 100k FREQUENCY (Hz) 1M 0 10M 0.8 0.6 0.4 7 6 5 4 3 2 1 0.2 0.1 1 10 SET PIN CAPACITANCE (µF) 3045 G46 1.4 1.2 1.0 0.8 0.6 0.4 0 100 Noise Spectral Density 1M 10M 3045 G49 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 OUTPUT VOLTAGE (V) 3045 G48 Noise Spectral Density OUTPUT NOISE (nV/√Hz) 10 0 3045 G47 1000 1 V = 5V IN RSET = 33.2k COUT = 10µF ILOAD = 500mA 0.1 10 100 1k 10k 100k FREQUENCY (Hz) 1.6 0.2 0 0.01 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA) VIN = VOUT + 2V COUT = 10µF CSET = 4.7µF ILOAD = 500mA 1.8 RMS OUTPUT NOISE (µVRMS) RMS OUTPUT NOISE (µVRMS) 1.0 Noise Spectral Density 1000 1000 100 100 10 5 2.0 VIN = 5V COUT = 10µF RSET = 33.2k ILOAD = 500mA 8 1.2 100 1 2 3 4 INPUT–TO–OUTPUT DIFFERENTIAL (V) Integrated RMS Output Noise (10Hz to 100kHz) 9 VIN = 5V RSET = 33.2k 1.6 COUT = 10µF CSET = 4.7µF 1.4 CSET = 0.047µF CSET = 0.47µF CSET = 1µF CSET = 4.7µF CSET = 22µF 0 3045 G45 Integrated RMS Output Noise (10Hz to 100kHz) 1.8 0 IL = 500mA RSET = 30.1k COUT = 10µF CSET = 0.47µF 100kHz 500kHz 1MHz 2MHz 20 3045 G44 2.0 RMS OUTPUT NOISE (µVRMS) 50 VOUT ≥ 1.3V 0.6V < VOUT < 1.3V VOUT ≤ 0.6V 30 Integrated RMS Output Noise (10Hz to 100kHz) OUTPUT NOISE (nV/√Hz) 60 30 40 3045 G43 0 70 COUT = 10µF 1 V = 5V IN RSET = 33.2k COUT = 22µF CSET = 4.7µF ILOAD = 500mA 0.1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 3045 G50 OUTPUT NOISE (nV/√Hz) 20 80 50 IL = 500mA IL = 300mA IL = 100mA IL = 50mA IL = 1mA 40 80 90 PSRR (dB) PSRR (dB) PSRR (dB) 100 Power Supply Ripple Rejection 100 VIN = VOUT + 2V IL = 500mA COUT = 10µF CSET = 0.47µF 110 60 TJ = 25°C, unless otherwise noted. IL = 500mA IL = 300mA IL = 100mA IL = 10mA IL = 1mA 10 1 V = 5V IN RSET = 33.2k CSET = 4.7µF COUT = 10µF 0.1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3045 G51 Rev. B 10 For more information www.analog.com LT3045 TYPICAL PERFORMANCE CHARACTERISTICS Noise Spectral Density as a Function of Error Amplifier Input Pair TJ = 25°C, unless otherwise noted. Output Noise: 10Hz to 100kHz Load Transient Response OUTPUT NOISE (nV/√Hz) 1000 VOUT ≥ 1.3V 0.6V < VOUT < 1.3V VOUT ≤ 0.6V 100 OUTPUT CURRENT 500mA/DIV 5µV/DIV VIN = 5V RSET = 33.2k COUT = 10µF CSET = 4.7µF IL = 500mA 10 1 V =V IN OUT + 2V IL = 500mA COUT = 10µF CSET = 4.7µF 0.1 10 100 1k 10k 100k FREQUENCY (Hz) OUTPUT VOLTAGE 20mV/DIV 3042 G53 1ms/DIV 1M 20µs/DIV VIN = 5V RSET = 33.2k COUT = 10µF CSET = 0.47µF LOAD STEP = 10mA TO 500mA 10M 3045 G52 Start-Up Time with and without Fast Start-Up Circuitry for Large CSET Line Transient Response 3042 G54 Input Supply Ramp-Up and Ramp-Down 500mV/DIV INPUT VOLTAGE OUTPUT WITH FAST START–UP (SET AT 90%) INPUT VOLTAGE 500mV/DIV 2V/DIV OUTPUT VOLTAGE 1mV/DIV OUTPUT WITHOUT FAST START–UP 5µs/DIV VIN = 4.5V TO 5V RSET = 33.2k COUT = 10µF CSET = 0.47µF IL = 500mA 3042 G55 VIN = 5V RSET = 33.2k COUT = 10µF CSET = 4.7µF RL = 6.6Ω 100ms/DIV PULSE EN/UV 2V/DIV OUTPUT VOLTAGE 3042 G56 50ms/DIV 3042 G57 VIN = 0V TO 5V VEN/UV = VIN RSET = 33.2k COUT = 10µF CSET = 0.47µF RL = 6.6Ω Rev. B For more information www.analog.com 11 LT3045 PIN FUNCTIONS (DFN/MSOP) IN (Pins 1, 2/Pins 1, 2, 3): Input. These pins supply power to the regulator. The LT3045 requires a bypass capacitor at the IN pin. In general, a battery’s output impedance rises with frequency, so include a bypass capacitor in battery-powered applications. While a 4.7µF input bypass capacitor generally suffices, applications with large load transients may require higher input capacitance to prevent input supply droop. Consult the Applications Information section on the proper use of an input capacitor and its effect on circuit performance, in particular PSRR. The LT3045 withstands reverse voltages on IN with respect to GND, OUTS and OUT. In the case of a reversed input, which occurs if a battery is plugged-in backwards, the LT3045 acts as if a diode is in series with its input. Hence, no reverse current flows into the LT3045 and no negative voltage appears at the load. The device protects itself and the load. EN/UV (Pin 3/Pin 4): Enable/UVLO. Pulling the LT3045’s EN/UV pin low places the part in shutdown. Quiescent current in shutdown drops to less than 1µA and the output voltage turns off. Alternatively, the EN/UV pin can set an input supply undervoltage lockout (UVLO) threshold using a resistor divider between IN, EN/UV and GND. The LT3045 typically turns on when the EN/UV voltage exceeds 1.24V on its rising edge, with a 130mV hysteresis on its falling edge. The EN/UV pin can be driven above the input voltage and maintain proper functionality. If unused, tie EN/UV to IN. Do not float the EN/UV pin. PG (Pin 4/Pin 5): Power Good. PG is an open-collector flag that indicates output voltage regulation. PG pulls low if PGFB is below 300mV. If the power good functionality is not needed, float the PG pin. A parasitic substrate diode exists between PG and GND pins of the LT3045; do not drive PG more than 0.3V below GND during normal operation or during a fault condition. ILIM (Pin 5/Pin 6): Current Limit Programming Pin. Connecting a resistor between ILIM and GND programs the current limit. For best accuracy, Kelvin connect this resistor directly to the LT3045’s GND pin. The programming scale factor is nominally 150mA•kΩ. The ILIM pin sources current proportional (1:500) to output current; therefore, it also serves as a current monitoring pin with a 0V to 300mV range. If the programmable current limit functionality is not needed, tie ILIM to GND. A parasitic substrate diode exists between ILIM and GND pins of the LT3045; do not drive ILIM more than 0.3V below GND during normal operation or during a fault condition. PGFB (Pin 6/Pin 7): Power Good Feedback. The PG pin pulls high if PGFB increases beyond 300mV on its rising edge, with 7mV hysteresis on its falling edge. Connecting an external resistor divider between OUT, PGFB and GND sets the programmable power good threshold with the following transfer function: 0.3V • (1 + RPG2/RPG1). As discussed in the Applications Information section, PGFB also activates the fast start-up circuitry. Tie PGFB to IN if power good and fast start-up functionalities are not needed, and if reverse input protection is additionally required, tie the anode of a 1N4148 diode to IN and its cathode to PGFB. See the Typical Applications section for details. A parasitic substrate diode exists between PGFB and GND pins of the LT3045; do not drive PGFB more than 0.3V below GND during normal operation or during a fault condition. SET (Pin 7/Pin 8): SET. This pin is the inverting input of the error amplifier and the regulation set-point for the LT3045. SET sources a precision 100µA current that flows through an external resistor connected between SET and GND. The LT3045’s output voltage is determined by VSET = ISET • RSET. Output voltage range is from zero to 15V. Adding a capacitor from SET to GND improves noise, PSRR and transient response at the expense of increased start-up time. For optimum load regulation, Kelvin connect the ground side of the SET pin resistor directly to the load. A parasitic substrate diode exists between SET and GND pins of the LT3045; do not drive SET more than 0.3V below GND during normal operation or during a fault condition. GND (Pin 8, Exposed Pad Pin 11/Pin 9, Exposed Pad Pin 13): Ground. The exposed backside is an electrical connection to GND. To ensure proper electrical and thermal performance, solder the exposed backside to the PCB ground and tie it directly to the GND pin. Rev. B 12 For more information www.analog.com LT3045 PIN FUNCTIONS OUTS (Pin 9/Pin 10): Output Sense. This pin is the noninverting input to the error amplifier. For optimal transient performance and load regulation, Kelvin connect OUTS directly to the output capacitor and the load. Also, tie the GND connections of the output capacitor and the SET pin capacitor directly together. A parasitic substrate diode exists between OUTS and GND pins of the LT3045; do not drive OUTS more than 0.3V below GND during normal operation or during a fault condition. OUT (Pin 10/Pins 11, 12): Output. This pin supplies power to the load. For stability, use a minimum 10µF output capacitor with an ESR below 20mΩ and an ESL below 2nH. Large load transients require larger output capacitance to limit peak voltage transients. Refer to the Applications Information section for more information on output capacitance. A parasitic substrate diode exists between OUT and GND pins of the LT3045; do not drive OUT more than 0.3V below GND during normal operation or during a fault condition. Rev. B For more information www.analog.com 13 LT3045 BLOCK DIAGRAM VIN EN/UV CIN IN CURRENT REFERENCE 2mA 100µA – + ENABLE COMPARATOR + – + V – FAST START-UP 1.24V – 300mV INPUT UVLO V + – – COUT INTERNAL CURRENT LIMIT – + RPG GND 215Ω + – 300mV + V PG VOUT RL 1.5V PROGRAMMABLE CURRENT LIMIT SET-TO-OUTS PROTECTION CLAMP RPG2 QPWR OUT V INPUT UVLO CURRENT LIMIT THERMAL SHDN DROPOUT FAST START-UP DISABLE LOGIC PGFB QP + – + THERMAL SHDN – + + QC DRIVER OUTPUT OVERSHOOT RECOVERY BIAS PROGRAMMABLE POWER GOOD V ERROR AMPLIFIER SET RSET OUTS CSET – 300mV ILIM RILIM RPG1 3045 BD Rev. B 14 For more information www.analog.com LT3045 APPLICATIONS INFORMATION The LT3045 is a high performance low dropout linear regulator featuring LTC’s ultralow noise (2nV/√Hz at 10kHz) and ultrahigh PSRR (76dB at 1MHz) architecture for powering noise sensitive applications. Designed as a precision current source followed by a high performance rail-to-rail voltage buffer, the LT3045 can be easily paralleled to further reduce noise, increase output current and spread heat on the PCB. The device additionally features programmable current limit, fast start-up capability and programmable power good. The LT3045 is easy to use and incorporates all of the protection features expected in high performance regulators. Included are short-circuit protection, safe operating area protection, reverse battery protection, reverse current protection, and thermal shutdown with hysteresis. Output Voltage The LT3045 incorporates a precision 100µA current source flowing out of the SET pin, which also ties to the error amplifier’s inverting input. Figure 1 illustrates that connecting a resistor from SET to ground generates a reference voltage for the error amplifier. This reference voltage is simply the product of the SET pin current and the SET pin resistor. The error amplifier’s unity-gain configuration produces a low impedance version of this voltage on its noninverting input, i.e. the OUTS pin, which is externally tied to the OUT pin. The LT3045’s rail-to-rail error amplifier and current reference allows for a wide output voltage range from 0V (using a 0Ω resistor) to VIN minus dropout — up to 15V. A PNP-based input pair is active for 0V to 0.6V output and an VIN 5V ±5% LT3045 IN 100µA 4.7µF – + EN/UV OUT PGFB VOUT, 3.3V IOUT(MAX), 500mA OUTS SET GND ILIM 10µF PG 3045 F01 0.47µF 33.2k NPN-based input pair is active for output voltages greater than 1.3V, with a smooth transition between the two input pairs from 0.6V to 1.3V output. While the NPN-based input pair is designed to offer the best overall performance, refer to the Electrical Characteristics Table for details on offset voltage, SET pin current, output noise and PSRR variation with the error amp input pair. Table 1 lists many common output voltages and their corresponding 1% RSET resistors. Table 1. 1% Resistor for Common Output Voltages VOUT (V) RSET (kΩ) 2.5 24.9 3.3 33.2 5 49.9 12 121 15 150 The benefit of using a current reference compared with a voltage reference as used in conventional regulators is that the regulator always operates in unity gain configuration, independent of the programmed output voltage. This allows the LT3045 to have loop gain, frequency response and bandwidth independent of the output voltage. As a result, noise, PSRR and transient performance do not change with output voltage. Moreover, since none of the error amp gain is needed to amplify the SET pin voltage to a higher output voltage, output load regulation is more tightly specified in the hundreds of microvolts range and not as a fixed percentage of the output voltage. Since the zero TC current source is highly accurate, the SET pin resistor can become the limiting factor in achieving high accuracy. Hence, it should be a precision resistor. Additionally, any leakage paths to or from the SET pin create errors in the output voltage. If necessary, use high quality insulation (e.g., Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and other residues may be required. High humidity environments may require a surface coating at the SET pin to provide a moisture barrier. Minimize board leakage by encircling the SET pin with a guard ring operated at a potential close to itself — ideally tied to the OUT pin. Guarding both sides of the circuit board is recommended. Bulk leakage reduction depends Figure 1. Basic Adjustable Regulator Rev. B For more information www.analog.com 15 LT3045 APPLICATIONS INFORMATION on the guard ring width. Leakages of 100nA into or out of the SET pin creates a 0.1% error in the reference voltage. Leakages of this magnitude, coupled with other sources of leakage, can cause significant errors in the output voltage, especially over wide operating temperature range. Figure 2 illustrates a typical guard ring layout technique. IN VIN LT3045 100µA CIN EN/UV PGFB OUT PG 1 10 2 9 3 11 VOUT IOUT(MAX): 500mA OUTS SET OUT DEMO BOARD PCB LAYOUT ILLUSTRATES 4-TERMINAL CONNECTION TO COUT GND COUT ILIM 8 4 7 5 6 SET RSET CSET 3045 F02 3045 F03 Figure 2. DFN Guard Ring Layout Figure 3. COUT and CSET Connections for Best Performance Since the SET pin is a high impedance node, unwanted signals may couple into the SET pin and cause erratic behavior. This is most noticeable when operating with a minimum output capacitor at heavy load currents. Bypassing the SET pin with a small capacitance to ground resolves this issue — 10nF is sufficient. the GND side of CSET directly to the GND side of COUT, as well as keep the GND sides of CIN and COUT reasonably close. Refer to the LT3045 demo board manual for more information on the recommended layout that meets these requirements. While the LT3045 is robust enough not to oscillate if the recommended layout is not followed, depending on the actual layout, phase/gain margin, noise and PSRR performance may degrade. For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven by an external voltage source capable of sinking 100µA. Connecting a precision voltage reference to the SET pin eliminates any errors present in the output voltage due to the reference current and SET pin resistor tolerances. Output Sensing and Stability The LT3045’s OUTS pin provides a Kelvin sense connection to the output. The SET pin resistor’s GND side provides a Kelvin sense connection to the load’s GND side. Additionally, for ultrahigh PSRR, the LT3045 bandwidth is made quite high (~1MHz), making it very close to a typical 10µF (1206 case size) ceramic output capacitor’s self-resonance frequency (~1.6MHz). Therefore, it is very important to avoid adding extra impedance (ESR and ESL) outside the feedback loop. To that end, as shown in Figure 3, minimize the effects of PCB trace and solder inductance by tying the OUTS pin directly to COUT and Stability and Output Capacitance The LT3045 requires an output capacitor for stability. Given its high bandwidth, LTC recommends low ESR and ESL ceramic capacitors. A minimum 10µF output capacitance with an ESR below 20mΩ and an ESL below 2nH is required for stability. Given the high PSRR and low noise performance attained using a single 10µF ceramic output capacitor, larger values of output capacitor only marginally improves the performance because the regulator bandwidth decreases with increasing output capacitance — hence, there is little to be gained by using larger than the minimum 10µF output capacitor. Nonetheless, larger values of output capacitance do decrease peak output deviations during a load transient. Note that bypass capacitors used to decouple individual components powered by the LT3045 increase the effective output capacitance. Rev. B 16 For more information www.analog.com LT3045 APPLICATIONS INFORMATION X5R and X7R dielectrics result in more stable characteristics and are thus more suitable for LT3045. The X7R dielectric has better stability across temperature, while the X5R is less expensive and is available in higher values. Nonetheless, care must still be exercised when using X5R and X7R capacitors. The X5R and X7R codes only specify operating temperature range and the maximum capacitance change over temperature. While capacitance change due to DC bias for X5R and X7R is better than Y5V and Z5U dielectrics, it can still be significant enough to drop capacitance below sufficient levels. As shown in Figure 6, capacitor DC bias characteristics tend to improve as component case size increases, but verification of expected capacitance at the operating voltage is highly recommended. Due to its good voltage coefficient in small case sizes, LTC recommends using Murata’s GJ8 series ceramic capacitors. 20 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF 0 CHANGE IN VALUE (%) X5R –20 –40 –60 Y5V –80 –100 0 2 4 14 6 12 8 10 DC BIAS VOLTAGE (V) 16 3045 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF 20 CHANGE IN VALUE (%) Give extra consideration to the type of ceramic capacitors used. They are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitance in the small packages, but they tend to have stronger voltage and temperature coefficients as shown in Figure 4 and Figure 5. When used with a 5V regulator, a 16V 10µF Y5V capacitor can exhibit an effective value as low as 1µF to 2µF for the DC bias voltage applied over the operating temperature range. X5R 0 –20 –40 Y5V –60 –80 –100 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 3045 F05 Figure 5. Ceramic Capacitor Temperature Characteristics 20 Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress upon it, similar to how a piezoelectric microphone works. For a ceramic capacitor, this stress can be induced by mechanical vibrations within the system or due to thermal transients. LT3045 applications in high vibration environments have three distinct piezoelectric noise generators: ceramic output, input, and SET pin capacitors. However, due to LT3045’s very low output impedance over a wide frequency range, negligible output noise is generated using CHANGE IN VALUE (%) 0 High Vibration Environments –20 –40 –60 –80 –100 MURATA: 25V,10%, X7R/X5R, 10µF CERAMIC 1 5 10 15 DC BIAS (V) 25 20 3045 F06 GRM SERIES, 0805, 1.45mm THICK GRM SERIES, 1206, 1.8mm THICK GRM SERIES, 1210, 2.2mm THICK GJ8 SERIES, 1206, 1.9mm THICK Figure 6. Capacitor Voltage Coefficient for Different Case Sizes Rev. B For more information www.analog.com 17 LT3045 APPLICATIONS INFORMATION a ceramic output capacitor. Similarly, due to LT3045’s ultrahigh PSRR, negligible output noise is generated using a ceramic input capacitor. Nonetheless, given the high SET pin impedance, any piezoelectric response from a ceramic SET pin capacitor generates significant output noise – peak-to-peak excursions of hundreds of µVs. However, due to the SET pin capacitor’s high ESR and ESL tolerance, any non-piezoelectrically responsive (tantalum, electrolytic, or film) capacitor can be used at the SET pin – although electrolytic capacitors tend to have high 1/f noise. In any case, use of a surface mount capacitor is highly recommended. Stability and Input Capacitance The LT3045 is stable with a minimum 4.7µF IN pin capacitor. LTC recommends using low ESR ceramic capacitors. In cases where long wires connect the power supply to the LT3045’s input and ground terminals, the use of low value input capacitors combined with a large load current can result in instability. The resonant LC tank circuit formed by the wire inductance and the input capacitor is the cause and not because of LT3045’s instability. The self-inductance, or isolated inductance, of a wire is directly proportional to its length. The wire diameter, however, has less influence on its self-inductance. For example, the self-inductance of a 2-AWG isolated wire with a diameter of 0.26" is about half the inductance of a 30-AWG wire with a diameter of 0.01". One foot of 30-AWG wire has 465nH of self-inductance. Several methods exist to reduce a wire’s self-inductance. One method divides the current flowing towards the LT3045 between two parallel conductors. In this case, placing the wires further apart reduces the inductance; up to a 50% reduction when placed only a few inches apart. Splitting the wires connect two equal inductors in parallel. However, when placed in close proximity to each other, their mutual inductance adds to the overall self inductance of the wires — therefore a 50% reduction is not possible in such cases. The second and more effective technique to reduce the overall inductance is to place the forward and return current conductors (the input and ground wires) in close proximity. Two 30-AWG wires separated by 0.02" reduce the overall inductance to about one-fifth of a single wire. If a battery mounted in close proximity powers the LT3045, a 4.7µF input capacitor suffices for stability. However, if a distantly located supply powers the LT3045, use a larger value input capacitor. Use a rough guideline of 1µF (in addition to the 4.7µF minimum) per 6" of wire length. The minimum input capacitance needed to stabilize the application also varies with the output capacitance as well as the load current. Placing additional capacitance on the LT3045’s output helps. However, this requires significantly more capacitance compared to additional input bypassing. Series resistance between the supply and the LT3045 input also helps stabilize the application; as little as 0.1Ω to 0.5Ω suffices. This impedance dampens the LC tank circuit at the expense of dropout voltage. A better alternative is to use a higher ESR tantalum or electrolytic capacitor at the LT3045 input in parallel with a 4.7µF ceramic capacitor. PSRR and Input Capacitance For applications utilizing the LT3045 for post-regulating switching converters, placing a capacitor directly at the LT3045 input results in ac current (at the switching frequency) to flow near the LT3045. This relatively highfrequency switching current generates a magnetic field that couples to the LT3045 output, thereby degrading its effective PSRR. While highly dependent on the PCB, the switching pre-regulator, the input capacitance, amongst other factors, the PSRR degradation can be easily over 30dB at 1MHz. This degradation is present even if the LT3045 is de-soldered from the board, because it effectively degrades the PSRR of the PC board itself. While negligible for conventional low PSRR LDOs, LT3045’s ultrahigh PSRR requires careful attention to higher order parasitics in order to extract the full performance offered by the regulator. To mitigate the flow of high-frequency switching current near the LT3045, the LT3045 input capacitor can be entirely removed -- as long as the switching converter’s output capacitor is located more than an inch away from the LT3045. Magnetic coupling rapidly decreases with increasing distance. Nonetheless, if the switching pre-regulator is placed too far away (conservatively more than a couple inches) from the LT3045, with no input capacitor present, as with any regulator, the LT3045 input will oscillate at the Rev. B 18 For more information www.analog.com LT3045 APPLICATIONS INFORMATION parasitic LC resonance frequency. Besides, it is generally a very common (and a preferred) practice to bypass regulator input with some capacitance. So this option is fairly limited in its scope and not the most palatable solution. To that end, LTC recommends using the LT3045 demo board layout for achieving the best possible PSRR performance. The LT3045 demo board layout utilizes magnetic field cancellation techniques to prevent PSRR degradation caused by this high-frequency current flow—while utilizing the input capacitor. Filtering High Frequency Spikes For applications where the LT3045 is used to post-regulate a switching converter, its high PSRR effectively suppresses any “noise” present at the switcher’s switching frequency — typically 100kHz to 4MHz. However, the very high frequency (hundreds of MHz) “spikes” — beyond the LT3045’s bandwidth — associated with the switcher’s power switch transition times will almost directly pass through the LT3045. While the output capacitor is partly intended to absorb these spikes, its ESL will limit its ability at these frequencies. A ferrite bead or even the inductance associated with a short (e.g. 0.5”) PCB trace between the switcher’s output and the LT3045’s input can serve as an LC-filter to suppress these very high frequency spikes. Output Noise The LT3045 offers many advantages with respect to noise performance. Traditional linear regulators have several sources of noise. The most critical noise sources for a traditional regulator are its voltage reference, error amplifier, noise from the resistor divider network used for setting output voltage and the noise gain created by this resistor divider. Many low noise regulators pin out their voltage reference to allow for noise reduction by bypassing the reference voltage. Unlike most linear regulators, the LT3045 does not use a voltage reference; instead, it uses a 100µA current reference. The current reference operates with typical noise current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz bandwidth). The resultant voltage noise equals the current noise multiplied by the resistor value, which in turn is RMS summed with the error amplifier’s noise and the resistor’s own noise of √4kTR — whereby k = Boltzmann’s constant 1.38 • 10–23J/K and T is the absolute temperature. One problem that conventional linear regulators face is that the resistor divider setting the output voltage gains up the reference noise. In contrast, the LT3045’s unity-gain follower architecture presents no gain from the SET pin to the output. Therefore, if a capacitor bypasses the SET pin resistor, then the output noise is independent of the programmed output voltage. The resultant output noise is then set just by the error amplifier’s noise — typically 2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz to 100kHz bandwidth using a 4.7µF SET pin capacitor. Paralleling multiple LT3045s further reduces noise by √N, for N parallel regulators. Refer to the Typical Performance Characteristics section for noise spectral density and RMS integrated noise over various load currents and SET pin capacitances. Set Pin (Bypass) Capacitance: Noise, PSRR, Transient Response and Soft-Start In addition to reducing output noise, using a SET pin bypass capacitor also improves PSRR and transient performance. Note that any bypass capacitor leakage deteriorates the LT3045’s DC regulation. Capacitor leakage of even 100nA is a 0.1% DC error. Therefore, LTC recommends the use of a good quality low leakage ceramic capacitor. Using a SET pin bypass capacitor also soft-starts the output and limits inrush current. The RC time constant, formed by the SET pin resistor and capacitor, controls soft-start time. Ramp-up rate from 0 to 90% of nominal VOUT is: tSS ≈ 2.3 • RSET • CSET (Fast Start-Up Disabled) Fast Start-Up For ultralow noise applications that require low 1/f noise (i.e. at frequencies below 100Hz), a larger value SET pin capacitor is required, up to 22µF. While this would normally significantly increase the regulator’s start-up time, the LT3045 incorporates fast start-up circuitry that increases the SET pin current to about 2mA during start-up. As shown in the Block Diagram, the 2mA current source remains engaged while PGFB is below 300mV, unless the Rev. B For more information www.analog.com 19 LT3045 APPLICATIONS INFORMATION regulator is in current limit, dropout, thermal shutdown or input voltage is below minimum VIN. If fast start-up capability is not used, tie PGFB to IN or to OUT for output voltages above 300mV. Note that doing so also disables power good functionality. ENABLE/UVLO The EN/UV pin is used to put the regulator into a micropower shutdown state. The LT3045 has an accurate 1.24V turn-on threshold on the EN/UV pin with 130mV of hysteresis. This threshold can be used in conjunction with a resistor divider from the input supply to define an accurate undervoltage lockout (UVLO) threshold for the regulator. The EN/UV pin current (IEN) at the threshold from the Electrical Characteristics table needs to be considered when calculating the resistor divider network: ⎞ ⎛ R VIN(UVLO) = 1.24V • ⎜ 1+ EN2 ⎟ +IEN • R EN2 ⎝ R EN1 ⎠ The EN/UV pin current (IEN) can be ignored if REN1 is less than 100k. If unused, tie EN/UV pin to IN. Programmable Power Good As illustrated in the Block Diagram, power good threshold is user programmable using the ratio of two external resistors, RPG2 and RPG1: ⎞ ⎛ R VOUT(PG _ THRESHOLD) = 0.3V • ⎜ 1+ PG2 ⎟ +IPGFB • R PG2 ⎝ R PG1 ⎠ If the PGFB pin increases above 300mV, the open-collector PG pin de-asserts and becomes high impedance. The power good comparator has 7mV hysteresis and 5µs of deglitching. The PGFB pin current (IPGFB) from the Electrical Characteristics table must be considered when determining the resistor divider network. The PGFB pin current (IPGFB) can be ignored if RPG1 is less than 30k. If power good functionality is not used, float the PG pin. Please note that programmable power good and fast start-up capabilities are disabled for output voltages below 300mV. Externally Programmable Current Limit The ILIM pin’s current limit threshold is 300mV. Connecting a resistor from ILIM to GND sets the maximum current flowing out of the ILIM pin, which in turn programs the LT3045’s current limit. With a 150mA • kΩ programming scale factor, the current limit can be calculated as follows: Current Limit = 150mA • kΩ RILIM For example, a 1kΩ resistor programs the current limit to 150mA and a 2kΩ resistor programs the current limit to 75mA. For good accuracy, Kelvin connect this resistor to the LT3045’s GND pin. In cases where IN-to-OUT differential is greater than 12V, the LT3045’s foldback circuitry decreases the internal current limit. As a result, internal current limit may override the externally programmed current limit level to keep the LT3045 within its safe-operating-area (SOA). See the Internal Current Limit vs Input-to-Output Differential graph in the Typical Performance Characteristics section. As shown in the Block Diagram, the ILIM pin sources current proportional (1:500) to output current; therefore, it also serves as a current monitoring pin with a 0V to 300mV range. If external current limit or current monitoring is not used, tie ILIM to GND. Output Overshoot Recovery During a load step from full load to no load (or light load), the output voltage overshoots before the regulator responds to turn the power transistor OFF. Given that there is no load (or very light load) present at the output, it takes a long time to discharge the output capacitor. As illustrated in the Block Diagram, the LT3045 incorporates an overshoot recovery circuitry that turns on a current sink to discharge the output capacitor in the event OUTS is higher than SET. This current is typically about 4mA. No load recovery is disabled for input voltages less than 2.5V or output voltages less than 1.5V. Rev. B 20 For more information www.analog.com LT3045 APPLICATIONS INFORMATION VIN 5V ±5% If OUTS is externally held above SET, the current sink turns ON in an attempt to restore OUTS to its programmed voltage. The current sink remains ON until the external circuitry releases OUTS. LT3045 IN 100µA 10µF – + EN/UV OUT PGFB 20mΩ OUTS SET GND ILIM PG VOUT 3.3V IOUT(MAX) 1A LT3045 IN 100µA – + EN/UV OUT PGFB 20mΩ OUTS SET GND ILIM PG 10µF 3045 F07 16.5k Direct Paralleling for Higher Current 10µF 0.47µF Figure 7. Parallel Devices Higher output current is obtained by paralleling multiple LT3045s. Tie all SET pins together and all IN pins together. Connect the OUT pins together using small pieces of PCB trace (used as a ballast resistor) to equalize currents in the LT3045s. PCB trace resistance in milliohms/inch is shown in Table 2. Table 2. PC Board Trace Resistance WEIGHT (oz) 10mil WIDTH 20mil WIDTH 1 54.3 27.1 2 27.1 13.6 Trace resistance is measured in mΩ/in. The small worst-case offset of 2mV for each paralleled LT3045 minimizes the required ballast resistor value. Figure 7 illustrates that two LT3045s, each using a 20mΩ PCB trace ballast resistor, provide better than 20% accurate output current sharing at full load. The two 20mΩ external resistors only add 10mV of output regulation drop with a 1A maximum current. With a 3.3V output, this only adds 0.3% to the regulation accuracy. As has been discussed previously, tie the OUTS pin directly to the output capacitor. More than two LT3045s can also be paralleled for even higher output current and lower output noise. Paralleling multiple LT3045s is also useful for distributing heat on the PCB. For applications with high input-to-output voltage differential, an input series resistor or resistor in parallel with the LT3045 can also be used to spread heat. PCB Layout Considerations Given the LT3045’s high bandwidth and ultrahigh PSRR, careful PCB layout must be employed to achieve full device performance. Figure 8 shows a recommended layout that delivers full performance of the regulator. Refer to the LT3045’s DC2491A demo board manual for further details. Figure 8. Recommended DFN Layout Rev. B For more information www.analog.com 21 LT3045 APPLICATIONS INFORMATION Thermal Considerations Table 3. Measured Thermal Resistance for DFN Package The LT3045 has internal power and thermal limiting circuits that protect the device under overload conditions. The thermal shutdown temperature is nominally 165°C with about 8°C of hysteresis. For continuous normal load conditions, do not exceed the maximum junction temperature (125°C for E- and I-grades and 150°C for H- and MP-Grades). It is important to consider all sources of thermal resistance from junction to ambient. This includes junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. Additionally, consider all heat sources in close proximity to the LT3045. The undersides of the DFN and MSOP packages have exposed metal from the lead frame to the die attachment. Both packages allow heat to directly transfer from the die junction to the PCB metal to limit maximum operating junction temperature. The dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of the PCB. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PCB and its copper traces. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by the regulator. Tables 3 and 4 list thermal resistance as a function of copper area on a fixed board size. All measurements were taken in still air on a 4 layer FR-4 board with 1oz solid internal planes and 2oz top/bottom planes with a total board thickness of 1.6mm. The four layers were electrically isolated with no thermal vias present. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. For more information on thermal resistance and high thermal conductivity test boards, refer to JEDEC standard JESD51, notably JESD51-7 and JESD51-12. Achieving low thermal resistance necessitates attention to detail and careful PCB layout. COPPER AREA TOP SIDE* BOTTOM SIDE BOARD AREA THERMAL RESISTANCE 2500mm2 2500mm2 2500mm2 34°C/W 1000mm2 2500mm2 2500mm2 34°C/W 225mm2 2500mm2 2500mm2 35°C/W 100mm2 2500mm2 2500mm2 36°C/W *Device is mounted on topside Table 4. Measured Thermal Resistance for MSOP Package COPPER AREA TOP SIDE* BOTTOM SIDE BOARD AREA THERMAL RESISTANCE 2500mm2 2500mm2 2500mm2 33°C/W 1000mm2 2500mm2 2500mm2 33°C/W 225mm2 2500mm2 2500mm2 34°C/W 100mm2 2500mm2 2500mm2 35°C/W *Device is mounted on topside Calculating Junction Temperature Example: Given an output voltage of 3.3V and input voltage of 5V ± 5%, output current range from 1mA to 500mA, and a maximum ambient temperature of 85°C, what is the maximum junction temperature? The LT3045’s power dissipation is: IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX) where: IOUT(MAX) = 500mA VIN(MAX) = 5.25V IGND (at IOUT = 500mA and VIN = 5.25V) = 12.5mA thus: PDISS = 0.5A • (5.25V – 3.3V) + 12.5mA • 5.25V = 1W Using a DFN package, the thermal resistance is in the range of 34°C/W to 36°C/W depending on the copper area. Therefore, the junction temperature rise above ambient approximately equals: 1W • 35°C/W = 35°C The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient: TJMAX = 85°C + 35°C = 120°C 22 For more information www.analog.com Rev. B LT3045 TYPICAL APPLICATIONS Overload Recovery Protection Features Like many IC power regulators, the LT3045 incorporates safe-operating-area (SOA) protection. The SOA protection activates at input-to-output differential voltages greater than 12V. The SOA protection decreases the current limit as the input-to-output differential increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltages up to the LT3045’s absolute maximum ratings. The LT3045 provides some level of output current for all values of input-to-output differentials. Refer to the Current Limit curves in the Typical Performance Characteristics section. When power is first applied and input voltage rises, the output follows the input and keeps the input-to-output differential low to allow the regulator to supply large output current and start-up into high current loads. The LT3045 incorporates several protection features for battery-powered applications. Precision current limit and thermal overload protection protect the LT3045 against overload and fault conditions at the device’s output. For normal operation, do not allow the junction temperature to exceed 125°C (E-grade, I-grade) or 150°C (H-grade, MP-Grade). Due to current limit foldback, however, at high input voltages a problem can occur if the output voltage is low and the load current is high. Such situations occur after the removal of a short-circuit or if the EN/UV pin is pulled high after the input voltage has already turned ON. The load line in such cases intersects the output current profile at two points. The regulator now has two stable operating points. With this double intersection, the input power supply may need to be cycled down to zero and brought back up again to make the output recover. Other linear regulators with foldback current limit protection (such as the LT1965 and LT1963A) also exhibit this phenomenon, so it is not unique to the LT3045. To protect the LT3045’s low noise error amplifier, the SETto-OUTS protection clamp limits the maximum voltage between SET and OUTS with a maximum DC current of 20mA through the clamp. So for applications where SET is actively driven by a voltage source, the voltage source must be current limited to 20mA or less. Moreover, to limit the transient current flowing through these clamps during a transient fault condition, limit the maximum value of the SET pin capacitor (CSET) to 22µF. The LT3045 also incorporates reverse input protection whereby the IN pin withstands reverse voltages of up to –20V without causing any input current flow and without developing negative voltages at the OUT pin. The regulator protects both itself and the load against batteries that are plugged-in backwards. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to GND, pulled to some intermediate voltage, or left opencircuit. In all of these cases, the reverse current protection circuitry prevents current flow from output to the input. Nonetheless, due to the OUTS-to-SET clamp, unless the SET pin is floating, current can flow to GND through the SET pin resistor as well as up to 15mA to GND through the output overshoot recovery circuitry. This current flow through the output overshoot recovery circuitry can be significantly reduced by placing a Schottky diode between OUTS and SET pins, with its anode at the OUTS pin. Rev. B For more information www.analog.com 23 LT3045 TYPICAL APPLICATIONS 12VIN to 3.3VOUT with 0.8µVRMS Integrated Noise LT3045 IN VIN 12V ±5% 4.7µF 100µA – + EN/UV 200k VOUT 3.3V IOUT 200mA OUT PG OUTS GND SET ILIM 10µF PGFB 453k 33.2k 4.7µF 750Ω 49.9k 3045 TA02 Low Noise CC/CV Lab Power Supply LT3045 IN VIN Ultralow Noise Current Source for RF Biasing Applications 4.7µF VIN 1.8V to 20V 100µA EN/UV OUT PG VOUT OUTS 0.47µF ROUT = R1 + RLOAD EN/UV PGFB SET 100µA 4.7µF – + LT3045 IN GND RSET OUT PGFB OUTS PG ILIM 10µF SET GND ILIM VOUT(MAX): 15V R1 I : 200mA 1Ω OUT 10µF RLOAD 4.7µF RIOUT 3045 TA03 RSET 2k 3045 TA04 OUTPUT CURRENT NOISE = 0.8µVRMS/ROUT INCREASE R1 (AND RSET) TO REDUCE CURRENT NOISE VOUT(MAX) = 100μA • RSET IOUT(MAX) =  150mA • kΩ RIOUT Rev. B 24 For more information www.analog.com LT3045 TYPICAL APPLICATIONS Programming Undervoltage Lockout VIN 4V Turn-ON 3.4V Turn-OFF 4.7µF ⎛ 110k ⎞ VIN(UVLO)RISING =1.24V • ⎜1+ ⎟ ⎝ 49.9k ⎠ LT3045 IN 100µA PGFB REN2 110k PG – + VOUT 3.3V IOUT(MAX) 500mA OUT EN/UV REN1 49.9k OUTS SET 10µF GND ILIM 3045 TA05 0.47µF 33.2k Ratiometric Tracking LT3045 IN 100µA – + EN/UV PGFB VIN 5.5V TO 20V PG LT3045 IN SET EN/UV 0.1µF PGFB OUT PG OUTS SET 0.1µF GND ILIM 10µF VOUT 5V OUTS 100µA 10µF OUT 16.9k GND 10µF ILIM 3045 TA06 VOUT 3.3V MIN LOAD 200µA 33.2k Rev. B For more information www.analog.com 25 LT3045 TYPICAL APPLICATIONS Ultralow 1/f Noise Reference Buffer VIN 6V ±5% LT3045 IN 100µA 4.7µF – + EN/UV PGFB 1,2 PG 6,7 LTC6655-5 OUTS SET 3,4,5 VOUT = 5V IOUT(MAX) 500mA OUT GND 10µF ILIM 1k 3045 TA07 10µF 49.9k 4.7µF Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop LT3045 IN 10µF LT3045 100µA EN/UV VOUT = 3.3V IOUT(MAX) = 1A PGFB OUT PG OUTS SET IN 100µA – + GND ILIM + – VIN 5V ±5% OUT 20mΩ 10µF 20mΩ 10µF RILIM 287Ω EN/UV PGFB PG OUTS ILIM GND SET 287Ω 3045 TA08 1µF 16.5k N = NUMBER OF DEVICES IN PARALLEL RCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR RILIM = CURRENT LIMIT PROGRAMMING RESISTOR RBALLAST = BALLAST RESISTOR ILIM = OUTPUT CURRENT LIMIT RCDC 5Ω RILIM = 150mA • kΩ/ILIM – RCDC • N = 287Ω (FOR 500mA ILIM PER REGULATOR) RCDC = RBALLAST • 500/N = 5Ω Rev. B 26 For more information www.analog.com LT3045 TYPICAL APPLICATIONS Paralleling Multiple LT3045s for 2A Output Current LT3045 IN VIN 5V ±5% 22µF LT3045 100µA IN 100µA – + 200k OUT PG OUT 20mΩ OUTS SET ILIM GND + – EN/UV PGFB 20mΩ 10µF EN/UV PGFB PG OUTS ILIM 10µF GND SET 453k 49.9k VOUT = 3.3V IOUT(MAX) = 2A DROPOUT = 300mV 0.8µVRMS 4 = 0.4µVRMS OUTPUT NOISE =  LT3045 IN LT3045 100µA 100µA – + PGFB OUT PG OUT 20mΩ OUTS SET GND + – EN/UV IN ILIM 10µF 4.7µF 20mΩ 10µF EN/UV PGFB PG OUTS ILIM GND SET 8.25k 3045 TA09 Rev. B For more information www.analog.com 27 LT3045 TYPICAL APPLICATIONS Low Noise Wheatstone Bridge Power Supply LT1763 NOISE: 20µVRMS (10Hz TO 100kHz) LT3045 NOISE: 0.8µVRMS (10Hz TO 100kHz) LT3045 IN VIN 5V ±5% 4.7µF 100µA EN/UV 200k – + OUT PG RESISTOR TOLERANCE BRIDGE PSRR NOISE AT VBRIDGE USING LT1763 NOISE AT VBRIDGE USING LT3045 PERFECT MATCHING INFINITE – – 1% 40dB 200nVRMS 8nVRMS 5% 26dB 1000nVRMS 42.5nVRMS VOUT: 3.3V AND IOUT(MAX): 500mA R1 OUTS SET GND ILIM PGFB 10µF R3 VBRIDGE 453k + R2 4.7µF – R4 49.9k 33.2k 3045 TA10 PGFB Disabled without Reverse Input Protection LT3045 IN VIN 4.7µF PGFB Disabled with Reverse Input Protection 4.7µF 100µA – + EN/UV – + 1N4148 OUT PG 0.47µF 100µA EN/UV PGFB OUT VOUT PGFB OUTS SET LT3045 IN VIN GND ILIM PG 10µF RSET 0.47µF 3045 TA11 VOUT OUTS SET GND ILIM 10µF RSET 3045 TA12 Rev. B 28 For more information www.analog.com LT3045 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. B For more information www.analog.com 29 LT3045 PACKAGE DESCRIPTION MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 5.10 (.201) MIN 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 6 1 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 3.20 – 3.45 (.065 ±.004) (.126 – .136) 12 0.65 0.42 ±0.038 (.0256) (.0165 ±.0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 ±0.076 (.016 ±.003) REF 12 11 10 9 8 7 DETAIL “A” 0° – 6° TYP 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 1 2 3 4 5 6 0.22 – 0.38 (.009 – .015) TYP 0.650 NOTE: (.0256) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MSE12) 0213 REV G Rev. B 30 For more information www.analog.com LT3045 REVISION HISTORY REV DATE DESCRIPTION A 10/17 Added H-grade options Modified Quiescent Current in Shutdown specs B 10/19 PAGE NUMBER 2, 23 4 Modified Note 9 5 Modified PGFB description 12 Added MP-Grade option 2, 3, 4, 5, 22, 23 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 31 LT3045 TYPICAL APPLICATION Parallel Devices VIN 5V ±5% LT3045 IN 100µA 10µF – + EN/UV OUT PGFB 20mΩ OUTS SET GND ILIM PG 10µF VOUT 3.3V IOUT(MAX) 1A LT3045 IN 100µA – + EN/UV OUT PGFB 20mΩ OUTS SET GND ILIM PG 10µF 3045 TA13 16.5k 0.47µF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V, TSOT-23 Package LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN = 1.8V to 20V, 4mm × 3mm DFN and SO-8 Packages LT3042 200mA, Ultralow Noise and Ultrahigh PSRR LDO 0.8μVRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V, 350mV Dropout Voltage, Programmable Current Limit and Power Good, 3mm × 3mm DFN and MSOP Packages LT3055 500mA LDO with Diagnostics and Precision Current Limit 340mV Dropout Voltage, Low Noise: 25μVRMS, VIN = 1.8V to 45V, 4mm × 3mm DFN and MSOP Packages LT3065 500mA Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 25μVRMS, VIN = 1.8V to 45V, 3mm × 3mm DFN and MSOP Packages LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors; TO-220, DD-Pak, SOT-223, MSOP and 3mm × 3mm DFN-8 Packages; LT3080-1 Version Has Integrated Internal Ballast Resistor LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages Rev. B 32 10/19 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2016–2019