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LT3050MPMSE#TRPBF

LT3050MPMSE#TRPBF

  • 厂商:

    AD(亚德诺)

  • 封装:

    TSSOP12

  • 描述:

    IC REG LIN POS ADJ 100MA 12MSOP

  • 数据手册
  • 价格&库存
LT3050MPMSE#TRPBF 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 TPS74701 500-mA Low-Dropout Linear Regulator With Programmable Soft-Start 1 Features 3 Description • • • • The TPS74701 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. Userprogrammable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and wellsuited for powering many different types of processors and ASICs. The enable input and power good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements. 1 • • • • • • VOUT Range: 0.8 V to 3.6 V Ultralow VIN Range: 0.8 V to 5.5 V VBIAS Range 2.7 V to 5.5 V Low Dropout: 50 mV Typically at 500 mA, VBIAS = 5V Power Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies 2% Accuracy Over Line, Load, and Temperature Programmable Soft-Start Provides Linear Voltage Start-Up VBIAS Permits Low VIN Operation With Good Transient Response Stable With Any Output Capacitor ≥ 2.2 μF Available in a Small 3-mm × 3-mm × 1-mm 10-Pin Package A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified from –40°C to 125°C. The TPS74701 is offered in a small 3-mm × 3-mm SON-10 package for compatibility with the TPS74801. 2 Applications • • • • • Device Information(1) FPGA Applications DSP Core and I/O Voltages Post-Regulation Applications Applications With Special Start-Up Time or Sequencing Requirements Hot-Swap and Inrush Controls PART NUMBER PACKAGE TPS74701 VSON (10) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit (Adjustable) Turnon Response CSS = 0nF CSS = 560pF VIN IN CIN PG EN VBIAS TPS74701 R1 GND CSS VOUT VOUT OUT SS CBIAS CSS = 5600pF 0.5V/div R3 BIAS COUT FB 3.8V R2 1V/div VEN 1.8V Time (2ms/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Typical Characteristics: VEN = VIN ............................ 7 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V......................................................................... 10 Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 11 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 17 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 18 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... Power Dissipation ................................................. Estimating Junction Temperature ........................ 18 18 18 19 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (November 2010) to Revision G • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision E (August, 2010) to Revision F • Page Page Corrected equation for Table 3............................................................................................................................................. 14 Changes from Revision D (April, 2009) to Revision E Page • Revised Power Dissipation section ...................................................................................................................................... 18 • Deleted (previously numbers) Figure 28 through Figure 30................................................................................................. 18 • Added section ....................................................................................................................................................................... 19 2 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 5 Pin Configuration and Functions DRC Package 10-Pin SON Top View IN 1 10 OUT 9 OUT IN 2 PG 3 BIAS 4 EN 5 Thermal Pad 8 FB 7 SS 6 GND Pin Functions PIN I/O DESCRIPTION NAME NO. IN 1, 2 I Input to the device. EN 5 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. SS 7 — BIAS 4 I Bias input voltage for error amplifier, reference, and internal control circuits. Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs. PG 3 O Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pullup resistor from 10 kΩ to 1 MΩ should be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary. FB 8 I Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. OUT 9, 10 O Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability. NC N/A I No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. GND 6 I Ground Thermal Pad — I Should be soldered to the ground plane for increased thermal performance. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 3 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND. (1) MIN MAX UNIT VIN, VBIAS Input voltage –0.3 6 V VEN Enable voltage –0.3 6 V VPG Power good voltage –0.3 6 V IPG PG sink current 0 1.5 mA VSS Soft-start voltage –0.3 6 V VFB Feedback voltage –0.3 6 V VOUT Output voltage –0.3 VIN + 0.3 V IOUT Maximum output current Internally limited Output short-circuit duration Indefinite PDISS Continuous total power dissipation TJ Operating junction temperature –40 125 °C Tstg Storage temperature –55 150 °C (1) See Thermal Information Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VOUT + VDO (VIN) VOUT + 0.3 5.5 V 0 VIN 5.5 V VOUT + VDO (VBIAS) (2) VOUT + 1.4 (2) 5.5 V VIN Input supply voltage VEN Enable supply voltage VBIAS (1) BIAS supply voltage VOUT Output voltage 0.8 3.3 V IOUT Output current 0 500 mA COUT Output capacitor 2.2 µF CIN Input capacitor (3) 1 µF CBIAS Bias capacitor 0.1 TJ Operating junction temperature –40 (1) (2) (3) 4 1 µF 125 °C BIAS supply is required when VIN is below VOUT + 1.62 V. VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 6.4 Thermal Information TPS74701 THERMAL METRIC (1) (2) DRC (VSON) (3) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 41.5 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 78 °C/W Junction-to-board thermal resistance N/A °C/W ψJT Junction-to-top characterization parameter 0.7 °C/W ψJB Junction-to-board characterization parameter 11.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.6 °C/W (1) (2) (3) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRC package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 3×2 thermal via array. (b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inches × 3-inches copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 5 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 6.5 Electrical Characteristics At VEN = 1.1 V, VIN = VOUT + 0.3V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, and TJ = –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range VBIAS Bias pin voltage range VREF Internal reference (Adjustable) TJ = 25°C Output voltage range VIN = 5 V, IOUT = 500 mA VREF Accuracy (1) 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 500 mA –2% VOUT/VIN Line regulation VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5 V 0.03 %/V VOUT/IOUT Load regulation 50 mA ≤ IOUT ≤ 500 mA 0.09 %/A VOUT VIN dropout voltage VDO (2) ICL Current limit VOUT = 80% × VOUT (NOM) IBIAS Bias pin current ISHDN Shutdown supply current (IGND) IFB Feedback pin current Power-supply rejection (VBIAS to VOUT) V 2.7 5.5 V 0.804 V 3.6 V IOUT = 500 mA, VBIAS – VOUT (NOM) ≥ 1.62 V (3) IOUT = 500 mA, VIN = VBIAS PSRR 5.5 0.796 VBIAS dropout voltage (2) Power-supply rejection (VIN to VOUT) VOUT + VDO 0.8 ±0.5% 50 120 mV 1.31 1.39 V 800 VEN ≤ 0.4 V –1 2% 1350 mA 1 2 mA 1 50 μA 0.150 1 μA 1 kHz, IOUT = 500 mA, VIN = 1.8 V, VOUT = 1.5 V 60 300 kHz, IOUT = 500 mA, VIN = 1.8 V, VOUT = 1.5 V 30 1 kHz, IOUT = 500 mA, VIN = 1.8 V, VOUT = 1.5 V 50 300 kHz, IOUT = 500 mA, VIN = 1.8 V, VOUT = 1.5 V 30 dB dB Noise Output noise voltage 100 Hz to 100 kHz, IOUT = 500 mA, CSS = 0.001 μF tSTR Minimum start-up time RLOAD for IOUT = 1 A, CSS = open 200 μs ISS Soft-start charging current VSS = 0.4 V 440 nA μVRMS 25 × VOUT VEN, HI Enable input high level VEN, LO Enable input low level VEN, HYS Enable pin hysteresis 50 mV VEN, DG Enable pin deglitch time 20 μs IEN Enable pin current VEN = 5 V VIT PG trip threshold VOUT decreasing VHYS PG trip hysteresis VPG, LO PG output low voltage IPG = 1 mA (sinking), VOUT < VIT IPG, LKG PG leakage current VPG = 5.25 V, VOUT > VIT TJ Operating junction temperature TSD Thermal shutdown temperature (1) (2) (3) 6 1.1 5.5 0 0.4 85 V V 0.1 1 μA 90 94 %VOUT 3 0.1 –40 Shutdown, temperature increasing 165 Reset, temperature decreasing 140 %VOUT 0.3 V 1 μA 125 °C °C Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account. Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% less than nominal. 1.62 V is a test condition of this device and can be adjusted by referring to Figure 6. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 6.6 Typical Characteristics: VEN = VIN 0.20 0.5 0.15 0.4 0.3 0.10 Change in VOUT (%) Change in VOUT (%) At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. -40°C 0.05 0 +25°C -0.05 +125°C -0.01 0.2 -40°C 0.1 0 -0.1 +125°C -0.2 +25°C -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.5 5.0 1.0 1.5 2.0 VIN - VOUT (V) 2.5 3.0 3.5 4.0 VBIAS - VOUT (V) Figure 1. VIN Line Regulation Figure 2. VBIAS Line Regulation 1.2 0.5 0.4 0.3 Change in VOUT (%) Change in VOUT (%) 1.0 0.8 0.6 0.4 0.2 +125°C 0.1 0 -0.1 -40°C +25°C -0.2 -0.3 0.2 -0.4 0 -0.5 0 10 20 30 40 0 50 100 500 Figure 4. Load Regulation 200 90 180 80 160 VDO (VIN - VOUT) (mV) VDO (VIN - VOUT) (mV) Figure 3. Load Regulation 70 60 50 40 +125°C +25°C 20 400 IOUT (mA) 100 30 300 200 IOUT (mA) IOUT = 0.5A 140 120 100 +25°C 80 +125°C 60 40 10 -40°C 20 -40°C 0 0 100 200 300 400 0 500 0 IOUT (mA) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS - VOUT (V) Figure 5. Dropout Voltage vs IOUT and Temperature (TJ) Figure 6. Dropout Voltage vs (VBIAS – VOUT) and Temperature (TJ) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 7 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: VEN = VIN (continued) At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. 2200 Power-Supply Rejection Ratio (dB) 90 VDO (VBIAS - VOUT) (mV) 2000 1800 1600 1400 +125°C 1200 1000 +25°C -40°C 800 600 80 IOUT = 0.1A 70 60 50 40 IOUT = 0.5A 30 VIN = 1.8V VOUT = 1.2V VBIAS = 5V CSS = 1nF 20 10 0 0 100 300 200 400 500 10 100 1k IOUT (mA) Figure 7. VBIAS Dropout Voltage vs IOUT and Temperature (TJ) 60 IOUT = 100mA 50 40 30 VIN = 1.8V VOUT = 1.2V COUT = 10mF CSS = 1nF 20 10 100 IOUT = 500mA Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 70 10 10M 80 1kHz 70 60 10kHz 50 40 100kHz 30 500kHz 20 VOUT = 1.2V IOUT = 500mA CSS = 1nF 10 0 1k 10k 100k 1M 0 10M 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 VIN - VOUT (V) Frequency (Hz) Figure 9. VIN PSRR vs Frequency Figure 10. VIN PSRR vs (VIN – VOUT) 2.0 IOUT = 100mA VOUT = 1.2V 1.8 +125°C 1.6 1.4 IBIAS (mA) Output Spectral Noise Density (mV/ÖHz) 1M 90 80 0 CSS = 0nF 0.1 CSS = 10nF 1.2 1.0 0.8 +25°C 0.6 CSS = 1nF -40°C 0.4 0.2 0 0.01 100 1k 10k 100k 0 100 200 300 400 500 IOUT (mA) Frequency (Hz) Figure 11. Noise Spectral Density 8 100k Figure 8. VBIAS PSRR vs Frequency 90 1 10k Frequency (Hz) Figure 12. BIAS Pin Current vs IOUT and Temperature (TJ) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 Typical Characteristics: VEN = VIN (continued) At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. 2.0 500 1.8 475 +125°C 1.6 450 1.2 ISS (nA) IBIAS (mA) 1.4 +25°C 1.0 0.8 425 400 375 0.6 -40°C 0.4 350 325 0.2 300 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 0 -25 VBIAS (V) Figure 13. BIAS Pin Current vs VBIAS and Temperature (TJ) 50 75 100 125 Figure 14. Soft-Start Charging Current (ISS) vs Temperature (TJ) 1.0 1.5 0.9 1.4 0.8 1.3 0.7 1.2 Current Limit (A) VOL Low-Level PG Voltage (V) 25 Junction Temperature (°C) 0.6 0.5 0.4 0.3 +125°C 1.1 1.0 -40°C 0.9 +25°C 0.8 0.2 0.7 0.1 0.6 0 VOUT = 0.8V 0.5 0 2 4 6 8 10 12 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VBIAS - VOUT (V) PG Current (mA) Figure 15. Low-Level PG Voltage vs Current Figure 16. Current Limit vs (VBIAS – VOUT) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 9 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 6.7 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. CSS = 1nF COUT = 2.2mF (Ceramic) COUT = 2.2mF (Ceramic) 50mV/div 50mV/div CSS = 1nF 3.8V 5.0V 1V/div 1V/div 1V/ms 3.3V 1V/ms 1.8V Time (50ms/div) Time (50ms/div) Figure 17. VBIAS Line Transient Figure 18. VIN Line Transient CSS = 0nF COUT = 470mF (OSCON) 100mV/div CSS = 560pF CSS = 1nF CSS = 5600pF 0.5V/div VOUT 100mV/div COUT = 10mF (Ceramic) 100mV/div 3.8V COUT = 2.2mF (Ceramic) 1V/div 500mA/div VEN 1.8V 1A/ms 50mA Time (50ms/div) Time (2ms/div) Figure 19. Output Load Transient Response Figure 20. Turnon Response 1V/div VIN = VBIAS = VEN VOUT VPG Time (20ms/div) Figure 21. Power Up and Power Down 10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 7 Detailed Description 7.1 Overview The TPS74701 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74701 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications. The TPS74701 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits start-up inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often present in processor-intensive systems. 7.2 Functional Block Diagram IN Current Limit BIAS UVLO OUT Thermal Limit 0.44mA VOUT R1 SS CSS Soft-Start Discharge 0.8V Reference FB PG EN Hysteresis and Deglitch R2 0.9 ´ VREF GND 7.3 Feature Description 7.3.1 Programmable Soft-Start The TPS74701 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus. To achieve a linear and monotonic soft-start, the TPS74701 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be calculated using Equation 1: Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 11 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com Feature Description (continued) tSS = (VREF ´ CSS) ISS (1) If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up time. In this case, the start-up time is given by Equation 2: (VOUT(NOM) ´ COUT) tSSCL = ICL(MIN) where • • • VOUT(NOM) is the nominal output voltage COUT is the output capacitance ICL(MIN) is the minimum current limit for the device (2) In applications where monotonic start-up is required, the soft-start time given by Equation 1 should be set greater than Equation 2. The maximum recommended soft-start capacitor is 0.015 μF. Larger soft-start capacitors can be used, and they do not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-start capacitor when enabled. Soft-start capacitors larger than 0.015 μF could be a problem in applications where it is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. CSS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. See Table 3 for suggested soft-start capacitor values. 7.3.2 Enable and Shutdown The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the TPS74701 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the VEN signal. The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V and 1.1-V limits. If precise turnon timing is required, a fast rise-time signal must be used to enable the TPS74701. If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit. 7.3.3 Power Good The power good (PG) pin is an open-drain output and can be connected to any 5.5 V or lower rail through an external pullup resistor. This pin requires at least 1.1 V on VBIAS to have a valid output. The PG output is highimpedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the opendrain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of the PG pin sink current is up to 1 mA, so the pullup resistor for PG should be in the range of 10 kΩ to 1 MΩ. If output voltage monitoring is not needed, the PG pin can be left floating. 7.3.4 Internal Current Limit The TPS74701 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 1 A and maintain regulation. The current limit responds in about 10 μs to reduce the current during a short-circuit fault. The internal current limit protection circuitry of the TPS74701 is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS74701 above the rated current degrades device reliability. 12 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 Feature Description (continued) 7.3.5 Thermal Shutdown Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS74701 is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS74701 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: • • • • The input voltage and bias voltage are both at least at the respective minimum specifications. The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold. The output current is less than the current limit. The device junction temperature is less than the maximum specified junction temperature. 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: • The input or bias voltages are below the respective minimum specifications. • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. • The device junction temperature is greater than the thermal shutdown temperature. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VEN VBIAS IOUT TJ Normal mode VIN > VOUT(nom) + VDO (VIN) VEN > VEN, HI VBIAS ≥ VOUT + 1.39 V I OUT < ICL T J < 125°C Dropout mode VIN < VOUT(nom) + VDO (VIN) VEN > VEN, HI VBIAS < VOUT + 1.39 V — TJ < 125°C VIN < VIN(min) VEN < VEN, LO VBIAS < VBIAS(min) — TJ > 165°C Disabled mode (any true condition disables the device) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 13 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information R1 and R2 can be calculated for any output voltage using the formula shown in Figure 25. See Table 2 for sample resistor values of common output voltages. To achieve the maximum accuracy specifications, R2 should be less than or equal to 4.99 kΩ. Table 2. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 × (1 + R1/R2). Table 3. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) CSS SOFT-START TIME Open 0.1 ms 270 pF 0.5 ms 560 pF 1 ms 2.7 nF 5 ms 5.6 nF 10 ms 0.01 μF 18 ms VREF × CSS 0.8V × CSS(F) = 0.44mA ISS where tSS(s) = soft-start time in seconds. 8.1.1 Input, Output, and Bias Capacitor Requirements The device is designed to be stable for all available types and values of output capacitors greater than or equal to 2.2 μF. The device is also stable with multiple capacitors in parallel, which can be of any type or value. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1 μF. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 μF. Good quality, low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimum performance. 14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 8.1.2 Transient Response The TPS74701 was designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; see Figure 19 in the Typical Characteristics: VEN = VIN section. Because the TPS74701 is stable with output capacitors as low as 2.2 μF, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output. 8.1.3 Dropout Voltage The TPS74701 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS74701 allows the device to be used in place of a DC-DC converter and still achieve good efficiency. This feature provides designers with the power architecture for their applications to achieve the smallest, simplest, and lowest cost solution. There are two different specifications for dropout voltage with the TPS74701. The first specification (shown in Figure 22) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 1.39 V (2) above VOUT, which is the case for VBIAS when powered by a 3.3-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT +1.39 V(1), VIN dropout is less than specified. BIAS IN VBIAS = 5V ±5% VIN = 1.8V VOUT = 1.5V IOUT = 500 mA Efficiency = 83% OUT Reference VOUT COUT FB Simplified Block Diagram Figure 22. Typical Application of the TPS74701 Using an Auxiliary Bias Rail VIN BIAS IN VBIAS = 3.3V ±5% VIN = 3.3V ± 5V VOUT = 1.5V Reference IOUT = 500 mA Efficiency = 45% OUT VOUT COUT FB Simplified Block Diagram Figure 23. Typical Application of the TPS74701 Without an Auxiliary Bias Rail (2) 1.62 V is a test condition of this device and can be adjusted by referring to Figure 6. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 15 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com The second specification (shown in Figure 23) is referred to as VBIAS Dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.39-V above VOUT. Because of this usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC package. 8.1.4 Sequencing Requirements VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the softstart function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN. If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor. Figure 24 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and VBIAS are present. NOTE When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of current from OUT. Although this condition does not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10 kΩ. VIN IN VOUT OUT R1 CIN BIAS TPS74701 FB EN SS COUT R2 R VBIAS CBIAS C GND CSS Figure 24. Soft-Start Delay Using an RC Circuit to Enable the Device 8.1.5 Output Noise The TPS74701 provides low-output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF soft-start capacitor, the output noise is reduced by half and is typically 30 μVRMS for a 1.2-V output (10 Hz to 100 kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-μF soft-start capacitor is given in Equation 3: ( VN(mVRMS) = 25 mVRMS V )x V OUT(V) (3) The low-output noise of the TPS74701 makes it a good choice for powering transceivers, PLLs, or other noisesensitive circuitry. 16 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 8.2 Typical Application Figure 25 illustrates the typical application circuit for the TPS74701 adjustable output device. VIN IN CIN 1mF PG R3 BIAS EN VBIAS TPS74701 R1 SS CBIAS 1mF VOUT OUT COUT 10mF FB GND CSS R2 ( VOUT = 0.8 ´ 1 + R1 R2 ) Figure 25. Typical Application Circuit for the TPS74701 (Adjustable) 8.2.1 Design Requirements Table 4 shows the design parameters for this application. Table 4. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VIN 1.8 V ± 10% VBIAS 3.3 V ±10% VOUT 1.5 V ± 3% IOUT 500 mA Start-up time < 2 ms 8.2.2 Detailed Design Procedure 1. Select R1 and R2 based on the required output voltage. Table 2 gives example calculations for many common output voltages. 2. Select CSS to be the highest capacitance while still achieving the desired start-up time. Table 3 gives examples of this calculation. 3. Select a minimum of a 2.2-µF ceramic output capacitor. Increased output capacitance will help the output load transient response. Figure 27 gives examples of the load transient response with different output capacitor values and types. 8.2.3 Application Curves CSS = 0nF COUT = 470mF (OSCON) 100mV/div CSS = 560pF CSS = 1nF CSS = 5600pF 0.5V/div VOUT 100mV/div COUT = 10mF (Ceramic) 100mV/div 3.8V COUT = 2.2mF (Ceramic) 1V/div 500mA/div VEN 1.8V 1A/ms 50mA Time (50ms/div) Time (2ms/div) Figure 26. Output Load Transient Response Figure 27. Turnon Response Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 17 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 9 Power Supply Recommendations The TPS74701 is designed to operate from an input voltage up to 5.5 V, provided the bias rail is at least 1.39-V higher than the input supply and dropout requirements are met. The bias rail and the input supply should both provide adequate headroom and current for the device to operate normally. Connect a low-output impedance power supply directly to the IN pin of the TPS74701. This supply must have at least 1 μF of capacitance near the IN pin for optimal performance. A supply with similar requirements must also be connected directly to the bias rail with a separate 1-μF or larger capacitor. If the IN pin is tied to the bias pin, a minimum 4.7 μF of capacitance is needed for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead before the input capacitor. 10 Layout 10.1 Layout Guidelines An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN, OUT and BIAS as close as possible to the device. If BIAS is connected to IN, connect BIAS as close to the input supply as possible. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turnon response. 10.2 Layout Example CIN Input GND Plane IN 1 10 OUT Vin CBIAS IN 2 9 OUT PG 3 8 FB BIAS 4 7 SS EN 5 6 GND Vout COUT R1 Css R2 Output GND Plane Note: CIN, COUT,and CBIAS are 0603 case size capacitors, while CSS, R1, and R2 are 0402 case size. Figure 28. TPS547 Layout Recommendation 10.3 Power Dissipation An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 25 should be connected as close as possible to the load. If BIAS is connected to IN, TI recommends connecting BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turnon response. Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: PD = (VIN - VOUT) ´ IOUT (4) 18 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 Power Dissipation (continued) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the SON (DRC) package, the primary conduction path for heat is through the exposed pad to the printedcircuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: (+125°C - TA) RqJA = PD (5) Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 29. 140 120 qJA (°C/W) 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 θJA value at board size of 9in2 (that is, 3 inches × 3 inches) is a JEDEC standard. Figure 29. θJA vs Board Size Figure 29 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as explained in the section. 10.4 Estimating Junction Temperature Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD YJB: TJ = TB + YJB · PD where • • • PD is the power dissipation shown by Equation 5. TT is the temperature at the center-top of the IC package. TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 31 shows). Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 (6) 19 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com Estimating Junction Temperature (continued) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. By looking at Figure 30, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 12 YJB YJT and YJB (°C/W) 10 8 6 4 2 YJT 0 0 1 2 3 4 5 6 7 9 8 10 Board Copper Area (in2) Figure 30. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, see application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, see application report SPRA953, Semiconductor and IC Package Thermal Metrics, also available on the TI website. TT on top of IC surface TB TB on PCB TT 1mm 1mm Figure 31. Measuring Points for TT and TB 20 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 TPS74701 www.ti.com SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Module An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS74701. The TPS74701EVM-177 evaluation module (and related user guide) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for TPS74701 is available through the product folders under Simulation Models. 11.1.2 Device Nomenclature Table 5. Device Nomenclature (1) PRODUCT TPS747xx yyy z (1) (2) (3) VOUT (2) xx is nominal output voltage (for example, 12 = 1.2 V, 15 = 1.5 V, 01 = Adjustable). (3) YYY is the package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Fixed output voltages from 0.8 V to 3.3 V are available; minimum order quantities may apply. Contact factory for details and availability. For fixed 0.8-V operation, tie FB to OUT. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Using New Thermal Metrics, SBVA025 • Semiconductor and IC Package Thermal Metrics, SPRA953 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 21 TPS74701 SBVS099G – NOVEMBER 2007 – REVISED OCTOBER 2015 www.ti.com 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: TPS74701 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS74701DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEG TPS74701DRCRG4 ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEG TPS74701DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEG TPS74701DRCTG4 ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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