FEATURES
LT3055 Series
500mA, Linear Regulator
with Precision Current Limit
and Diagnostics
DESCRIPTION
n
n
n
n
n
n
The LT®3055 series are micropower, low noise, low dropout
voltage (LDO) linear regulators. The devices supply 500mA
of output current with a dropout voltage of 350mV. A 10nF
bypass capacitor reduces output noise to 25μVRMS in a
10Hz to 100kHz bandwidth and soft starts the reference.
The LT3055’s ±45V input voltage rating combined with its
precision current limit and diagnostic functions make the
IC an ideal choice for robust, high reliability applications.
n
n
n
n
n
n
n
n
Output Current: 500mA
Dropout Voltage: 350mV
Input Voltage Range: 1.6V to 45V
Programmable Precision Current Limit: ±10%
Output Current Monitor: 1/500th of IOUT
Programmable Minimum IOUT Monitor
Temperature Monitor: 10mV/°C
FAULT Indicator: Current Limit, Thermal Limit or
Minimum IOUT
Low Noise: 25μVRMS (10Hz to 100kHz)
Adjustable Output (VREF = VOUT(MIN) = 0.6V)
Output Tolerance: ±2% Over Load, Line and Temperature
Stable with Low ESR, Ceramic Output Capacitors
(3.3μF Minimum)
Shutdown Current: (VOUT-500mV), the IMON mirror PNP collector is VIMON + VDSSAT (500mV at 500mA). Early voltage
effects increase the IOUT to IMON ratio as VIMON increases.
Rev. B
14
For more information www.analog.com
LT3055 Series
OPERATION
If the open-circuit detection function is not needed, the
IMIN pin must be left floating (unconnected). A small decoupling capacitor (10nF minimum) from IMIN to GND is
required to improve IMIN pin power supply rejection and to
prevent FAULT1 pin glitches. See the Typical Performance
Characteristics section for additional information.
525
IOUT:IIMON RATIO (mA/mA)
520
515
EARLY VOLTAGE
EFFECTS
510
505
500
495
490
485
480
475
IMAX Pin Operation
VIN = 6V
VIMON = 2.5V
IOUT = 500mA (IN CURRENT LIMIT)
1
0
3
2
VOUT (V)
The IMAX pin is the collector of a PNP which mirrors the
LT3055 output PNP at a ratio of 1:500 (see Block Diagram).
The IMAX pin is also the input to the precision current limit
amplifier. If the output load increases to the point where it
causes the IMAX pin voltage to reach 0.6V, the current limit
amplifier takes control of the output regulation so that the
IMAX pin regulates at 0.6V, regardless of the output voltage.
The current limit threshold (ILIMIT) is set by connecting a
resistor (RIMAX) from IMAX to GND:
5
4
3055 F03a
Figure 3a. IOUT:IIMON Ratio vs VOUT
525
VIN = 6V
VOUT = 5V
IOUT = 500mA
IOUT:IIMON RATIO (mA/mA)
520
515
IMON MIRROR
PNP SATURATING
510
505
500
EARLY VOLTAGE
EFFECTS
495
490
480
0
1
2
3
VIMON (V)
4
5
6
3055 F03b
Figure 3. (b) IOUT:IIMON Ratio vs VIMON
In addition, if VIN – VIMON < 1V, the IMON mirror PNP
saturates at high loads, causing the IOUT-to-IMON ratio
to increase quickly. The IMON mirror ratio is affected by
power dissipation in the LT3055; it increases at a rate of
approximately 0.5 percent per watt.
Open-Circuit Detection (IMIN Pin)
The IMIN pin is the collector of a PNP which mirrors
the LT3055 output PNP at a ratio of 1:2000 (see Block
Diagram). The IMIN fault comparator asserts the FAULT1
pin if the IMIN pin voltage is below 0.6V. This low output
current fault threshold voltage (IOPEN) is set by attaching
a resistor from IMIN to GND:
R IMIN = 2000 •
0.6V
IOPEN
0.6V
ILIMIT
In cases where the IN to OUT differential voltage exceeds
10V, fold-back current limit lowers the internal current
limit level, possibly causing it to override the external
programmable current limit. See the Internal Current Limit
vs VIN-VOUT graph in the Typical Performance Characteristics section.
485
475
R IMAX = 500 •
The IMAX pin requires a 22nF decoupling capacitor. If the
external programmable current limit is not needed, the
IMAX pin must be connected to GND. The IMAX threshold
is affected by power dissipation in the LT3055; it increases
at a rate of approximately 0.5 percent per watt.
FAULT Pins Operation
The FAULT1 and FAULT2 pins are open-drain high voltage
NMOS digital outputs. The FAULT1 pin asserts during a low
current fault (open circuit). The FAULT2 pin asserts during
a current limit fault (internal or externally programmed).
Both FAULT1 and FAULT2 assert during thermal shutdown.
There is no internal pull-up on the FAULT pins; an external
pull-up resistor is required. The FAULT pins sink up to
50μA of pull-down current. Off state logic may be as high
as 45V, regardless of the input voltage used.
Rev. B
For more information www.analog.com
15
LT3055 Series
OPERATION
Table 1. FAULT Pins Truth Table
STATUS
Open Circuit
Current Limit
Thermal Shutdown
FAULT1
Low
High
Low
FAULT2
High
Low
Low
Depending on the IMIN capacitance, BYP capacitance,
and OUT capacitance, the FAULT pins may assert during
start-up. Consideration should be given to masking the
fault signals during start-up. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above IN pin.
PWRGD Pin Operation
The PWRGD pin is an open-drain high voltage NMOS
digital output. The PWRGD pin deasserts and becomes
high impedance if the output rises above 90% of its
nominal value. If the output falls below 89% of its nominal
value for more than 25μs, the PWRGD pin asserts low.
The PWRGD comparator has 1% hysteresis and 25μs
of deglitching. The PWRGD comparator has a dedicated
reference that does not soft-start when a capacitor is
added to the REF/BYP pin.
The use of a feed-forward capacitor, CFF, as shown in Figure 5, can result in the ADJ pin being pulled artificially high
during start- up transients, which causes the PWRGD flag
to assert early. To avoid this problem, ensure that the REF/
BYP capacitor is significantly larger than the feed-forward
capacitor, causing REF/BYP time constant to dominate over
the time constant of the resistor divider network.
Operation in Dropout
There may be some degradation of the current mirror accuracy for output currents less than 50mA when operating
in dropout.
APPLICATIONS INFORMATION
The LT3055 is a micropower, low noise and low dropout voltage, 500mA linear regulator with micropower shutdown,
programmable current limit, and diagnostic functions. The
device supplies up to 500mA at a typical dropout voltage
of 350mV and operates over a 1.6V to 45V input range.
A single external capacitor provides low noise reference
performance and output soft-start functionality. For example, connecting a 10nF capacitor from the REF/BYP
pin to GND lowers output noise to 25μVRMS over a 10Hz
to 100kHz bandwidth. This capacitor also soft starts the
reference and prevents output voltage overshoot at turn-on.
The LT3055’s quiescent current is merely 65μA but provides
fast transient response with a minimum low ESR 3.3μF
ceramic output capacitor. In shutdown, quiescent current is
less than 1μA and the reference soft-start capacitor is reset.
The LT3055 optimizes stability and transient response
with low ESR, ceramic output capacitors. The regulator
does not require the addition of ESR as is common with
other regulators. The LT3055 typically provides 0.1% line
regulation and 0.1% load regulation. Internal protection
circuitry includes reverse battery protection, reverse output
protection, reverse current protection, current limit with
fold-back and thermal shutdown.
This “bullet-proof” protection set makes it ideal for use
in battery-powered, automotive and industrial systems.
In battery backup applications where the output is held
up by a backup battery and the input is pulled to ground,
the LT3055 acts like it has a diode in series with its output
and prevents reverse current flow.
Rev. B
16
For more information www.analog.com
LT3055 Series
APPLICATIONS INFORMATION
Adjustable Operation
+
The adjustable LT3055 has an output voltage range of
0.6V to 40V. The output voltage is set by the ratio of
two external resistors, as shown in Figure 4. The device
servos the output to maintain the ADJ pin voltage at 0.6V
referenced to ground. The current in R1 is then equal to
0.6V/R1, and the current in R2 is the current in R1 minus
the ADJ pin bias current.
The ADJ pin bias current, 16nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure 4. The value of R1 should be
no greater than 62k to provide a minimum 10μA load current so that output voltage errors, caused by the ADJ pin
bias current, are minimized. Note that in shutdown, the
output is turned off and the divider current is zero. Curves
of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typical Performance
Characteristics section.
The LT3055 is tested and specified with the ADJ pin tied
to the OUT pin, yielding VOUT = 0.6V. Specifications for
output voltages greater than 0.6V are proportional to the
ratio of the desired output voltage to 0.6V: VOUT/0.6V. For
example, load regulation for an output current change of
1mA to 500mA is 0.5mV (typical) at VOUT = 0.6V. At VOUT
= 12V, load regulation is:
12V
0.6V
• ( 0.5mV) = 10mV
Table 2 shows 1% resistor divider values for some common
output voltages with a resistor divider current of 10μA.
Table 2. Output Voltage Resistor Divider Values
VOUT (V)
1.2
1.5
1.8
2.5
3
3.3
5
R1 (kΩ)
60.4
59
59
60.4
59
61.9
59
R2 (kΩ)
60.4
88.7
118
191
237
280
432
IN
VIN
VOUT
OUT
LT3055
SHDN
R2
ADJ
GND
R1
3055 F04
R2
VOUT = 0.6V 1+ – (IADJ •R2)
R1
VADJ = 0.6V
IADJ = 16nA AT 25°C
OUTPUT RANGE = 0.6V TO 40V
Figure 4. Adjustable Operation
Bypass Capacitance and Output Voltage Noise
The LT3055 regulator provides low output voltage
noise over a 10Hz to 100kHz bandwidth while operating at full load with the addition of a bypass capacitor
(CREF/BYP) from the REF/BYP pin to GND. A high quality
low leakage capacitor is recommended. This capacitor
bypasses the internal reference of the regulator, providing a low frequency noise pole for the internal reference.
With the use of 10nF for CREF/BYP, output voltage noise
decreases to as low as 25μVRMS when the output voltage
is set for 0.6V. For higher output voltages (generated by
using a feedback resistor divider), the output voltage noise
gains up proportionately when using CREF/BYP.
To lower the higher output voltage noise, include a feedforward capacitor (CFF) from VOUT to the ADJ pin. A high
quality, low leakage capacitor is recommended. This
capacitor bypasses the error amplifier of the regulator,
providing an additional low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 25μVRMS when the output voltage is
set to 5V by a 10μA feedback resistor divider. If the current in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise can occur if care
is not exercised with regard to circuit layout and testing.
Crosstalk from nearby traces induces unwanted noise
onto the LT3055’s output. Power supply ripple rejection
Rev. B
For more information www.analog.com
17
LT3055 Series
APPLICATIONS INFORMATION
must also be considered. The LT3055 regulator does not
have unlimited power supply rejection and passes a small
portion of the input noise through to the output.
Start-up time is also affected by the presence of a feedforward capacitor. Start-up time is directly proportional to
the size of the feedforward capacitor and the output voltage, and is inversely proportional to the feedback resistor
divider current, slowing to 15ms with a 10nF feedforward
capacitor and a 10μF output capacitor for an output voltage
set to 5V by a 10μA feedback resistor divider.
Output Capacitance and Transient Response
The LT3055 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stability,
most notably with small capacitors. Use a minimum output
capacitor of 3.3μF with an ESR of 1Ω or less to prevent
oscillations. If a feedforward capacitor is used with output
voltages set for greater than 24V, use a minimum output
capacitor of 10μF. The LT3055 is a micropower device and
output load transient response is a function of output capacitance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used to
decouple individual components powered by the LT3055,
increase the effective output capacitor value. For applications with large load current transients, a low ESR ceramic
IN
OUT
LT3055
SHDN
ADJ
GND REF/BYP
R2
CFF
VOUT
COUT
R1
CREF/BYP
3055 F05
CFF ≥
10nF
• IFB _ DIVIDER
10µA
(
IFB _ DIVIDER =
)
VOUT
R1+R2
Figure 5. Feedforward Capacitor for Fast Transient Response
0
VOUT
100mV/DIV
During start-up, the internal reference soft-starts when
a bypass capacitor is present. Regulator start-up time is
directly proportional to the size of the bypass capacitor
(See Start-Up Time vs REF/BYP Capacitor in the Typical
Performance Characteristics section). The reference bypass capacitor is actively pulled low during shutdown to
reset the internal reference.
VIN
FEEDFORWARD
CAPACITOR, CFF
Using a feedforward capacitor (CFF) from VOUT to the
ADJ pin has the added benefit of improving transient
response for output voltages greater than 0.6V. With no
feedforward capacitor, the settling time increases as the
output voltage increases above 0.6V. Use the equation in
Figure 5 to determine the minimum value of CFF to achieve
a transient response that is similar to the 0.6V output
voltage performance regardless of the chosen output voltage (See Figure 6 and Transient Response in the Typical
Performance Characteristics section).
+
100pF
1nF
10nF
LOAD CURRENT
500mA/DIV
100µs/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 10µA
3055 F06
Figure 6. Transient Response vs Feedforward Capacitor
capacitor in parallel with a bulk tantalum capacitor often
provides an optimally damped response.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients,
as shown in Figure 7 and Figure 8. When used with a 5V
regulator, a 16V 10μF Y5V capacitor can exhibit an effective
value as low as 1μF to 2μF for the DC bias voltage applied,
and over the operating temperature range. The X5R and
X7R dielectrics yield much more stable characteristics and
are more suitable for use as the output capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
be exercised when using X5R and X7R capacitors; the X5R
Rev. B
18
For more information www.analog.com
LT3055 Series
APPLICATIONS INFORMATION
20
0
CHANGE IN VALUE (%)
of noise. A ceramic capacitor produced the trace in
Figure 9 in response to light tapping from a pencil. Similar
vibration induced behavior can masquerade as increased
output voltage noise.
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
–20
–40
–60
Y5V
–80
–100
VOUT
1mV/DIV
0
2
4
14
8
6
10 12
DC BIAS VOLTAGE (V)
16
3055 F07
Figure 7. Ceramic Capacitor DC Bias Characteristics
VOUT = 5V
COUT = 10µF
CREF/BYP = 10nF
40
CHANGE IN VALUE (%)
20
–20
Stability and Input Capacitance
–40
Y5V
–60
–80
3055 F09
Figure 9. Noise Resulting from Tapping On a Ceramic Capacitor
X5R
0
10ms/DIV
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
–100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3055 F08
Figure 8. Ceramic Capacitor Temperature Characteristics
and X7R codes only specify operating temperature range
and maximum capacitance change over temperature.
Capacitance change due to DC bias with X5R and X7R
capacitors is better than Y5V and Z5U capacitors, but can
still be significant enough to drop capacitor values below
appropriate levels. Capacitor DC bias characteristics tend
to improve as component case size increases, but expected
capacitance at operating voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress is induced
by vibrations in the system or thermal transients. The
resulting voltages produced cause appreciable amounts
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, applications connecting a power supply to an LT3055 circuit’s
IN and GND pins with long input wires combined with a
low ESR, ceramic input capacitors are prone to voltage
spikes, reliability concerns and application-specific board
oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic input
capacitor, forms a high QLC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of
LT3055 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not
a major factor on its self-inductance. For example, the
self-inductance of a 2-AWG isolated wire (diameter =
0.26") is about half the self-inductance of a 30-AWG wire
(diameter = 0.01"). One foot of 30-AWG wire has approximately 465nH of self-inductance.
Rev. B
For more information www.analog.com
19
LT3055 Series
APPLICATIONS INFORMATION
Two methods can reduce wire self-inductance. One method
divides the current flowing towards the LT3055 between
two parallel conductors. In this case, the farther apart the
wires are from each other, the more the self-inductance is
reduced; up to a 50% reduction when placed a few inches
apart. Splitting the wires connects two equal inductors in
parallel, but placing them in close proximity creates mutual
inductance adding to the self-inductance. The second and
most effective way to reduce overall inductance is to place
both forward and return current conductors (the input and
GND wires) in very close proximity. Two 30-AWG wires
separated by only 0.02”, used as forward- and returncurrent conductors, reduce the overall self-inductance
to approximately one-fifth that of a single isolated wire.
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
LC tank circuit at the expense of dropout voltage. A better
alternative is to use higher ESR tantalum or electrolytic capacitors at the LT3055 input in place of ceramic capacitors.
If a battery, mounted in close proximity, powers the LT3055,
a 10µF input capacitor suffices for stability. However, if a
distant supply powers the LT3055, use a larger value input
capacitor. Use a rough guideline of 1µF (in addition to the
10µF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3055’s output also
helps. However, this requires an order of magnitude more
capacitance in comparison with additional LT3055 input
bypassing. Series resistance between the supply and the
LT3055 input also helps stabilize the application; as little
In Figure 10, this is implemented using inexpensive 2N3904
NPN devices. Precision 1k resistors provide 1V emitter
degeneration at full load to guarantee good current mirror
matching. The feedback resistors of the slave LT3055 are
split into sections to ensure adequate headroom for the
slave 2N3904. A 1nF capacitor added to the IMON pin of
the slave device frequency compensates the feedback loop.
REF
+
–
+
–
This circuit architecture is scalable to as many LT3055s
as are needed simply by extending the current mirror and
adding slave LT3055 devices.
600mV
500x
1x
IMON
REF
+
–
+
–
600mV
VOUT
5V
1A
OUT
ADJ
440k
500x
10µF
60k
LT3055 (SLAVE)
IN
10µF
Higher output current is obtained by paralleling multiple
LT3055 together. Tie the individual OUT pins together
and tie the individual IN pins together. An external NPN
or NMOS current mirror is used in combination with the
LT3055 IMON pins to create a simple amplifier. This amplifier injects current into or out of the feedback divider of
the slave LT3055 in order to ensure that the IMON currents
from each LT3055 are equal.
LT3055 (MASTER)
IN
VIN
5.6V
Paralleling Devices
1x
IMON
1nF
OUT
ADJ
300k
140k
60k
2N3904
1k
1k
3055 F10
Figure 10. Parallel Devices
20
For more information www.analog.com
Rev. B
LT3055 Series
APPLICATIONS INFORMATION
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output differential is high.
Overload Recovery
Like many IC power regulators, the LT3055 has safe operating area protection. The safe area protection decreases
current limit as input-to-output voltage increases, and
keeps the power transistor inside a safe operating region
for all values of input-to-output voltage. The LT3055 provides some output current at all values of input-to-output
voltage up to the device breakdown.
When power is first applied, the input voltage rises and the
output follows the input; allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a
high input voltage, a problem can occur wherein the removal
of an output short will not allow the output to recover. Other
regulators, such as the LT1083/LT1084/ LT1085 family and
LT1764A also exhibit this phenomenon, so it is not unique
to the LT3055. The problem occurs with a heavy output load
when the input voltage is high and the output voltage is low.
Common situations are immediately after the removal of a
short circuit or if the shutdown pin is pulled high after the
input voltage is already turned on. The load line intersects
the output current curve at two points. If this happens, there
are two stable output operating points for the regulator. With
this double intersection, the input power supply needs to be
cycled down to zero and back up again to recover the output.
Thermal Considerations
The LT3055’s maximum rated junction temperature of
125°C (E-, I-grades) or 150°C (MP-, H-grades) limits its
power handling capability. Two components comprise the
power dissipated by the device:
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed above.
The LT3055 regulator has internal thermal limiting that
protects the device during overload conditions. For continuous normal conditions, do not exceed the maximum
junction temperature of 125°C (E-, I-grades) or 150°C
(MP-, H-grades). Carefully consider all sources of thermal
resistance from junction-to-ambient including other heat
sources mounted in proximity to the LT3055.
The undersides of the LT3055 DFN and MSE packages have
exposed metal from the lead frame to the die attachment.
These packages allow heat to directly transfer from the
die junction to the printed circuit board metal to control
maximum operating junction temperature. The dual-inline pin arrangement allows metal to extend beyond the
ends of the package on the topside (component side) of a
PCB. Connect this metal to GND on the PCB. The multiple
IN and OUT pins of the LT3055 also assist in spreading
heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
power devices.
Table 3 and Table 4 list thermal resistance as a function
of copper area in a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes, and 2oz external trace planes with a
total board thickness of 1.6mm. For further information
on thermal resistance and using thermal information, refer
to JEDEC standard JESD51, notably JESD51-12.
Table 3. MSOP Measured Thermal Resistance
COPPER AREA
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
1. Output current multiplied by the input/output voltage
difference:
IOUT • (VIN – VOUT), and
2500 sq mm 2500 sq mm 2500 sq mm
35°C/W
1000 sq mm 2500 sq mm 2500 sq mm
36°C/W
2. GND pin current multiplied by the input voltage:
225 sq mm 2500 sq mm 2500 sq mm
37°C/W
100 sq mm 2500 sq mm 2500 sq mm
39°C/W
IGND • VIN
TOPSIDE
BACKSIDE
Rev. B
For more information www.analog.com
21
LT3055 Series
APPLICATIONS INFORMATION
Table 4. DFN Measured Thermal Resistance
COPPER AREA
TOPSIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm
2500 sq mm
36°C/W
1000 sq mm
2500 sq mm
37°C/W
225 sq mm
2500 sq mm
38°C/W
100 sq mm
2500 sq mm
40°C/W
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 12V ±5%, a maximum output current range of
75mA and a maximum ambient temperature of 85°C, what
is the maximum junction temperature?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = 75mA
VIN(MAX) = 12.6V
IGND at (IOUT = 75mA, VIN = 12V) = 3.5mA
So:
P = 75mA • (12.6V – 5V) + 3.5mA • 12.6V = 0.614W
Using a DFN package, the thermal resistance ranges from
36°C/W to 40°C/W depending on the copper area. So the
junction temperature rise above ambient approximately
equals:
limiting, the device also protects against reverse input
voltages, reverse output voltages and reverse output-toinput voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. For normal operation, do not
exceed a junction temperature of 125°C (E-, I-grades) or
150°C (MP-, H-grades).
The LT3055 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 1μA (typically less
than 25nA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The LT3055 incurs no damage if its output is pulled below
ground. If the input is left open circuit or grounded, the
output can be pulled below ground by 50V. No current
flows through the pass transistor from the output. However,
current flows in (but is limited by) the feedback resistor
divider that sets the output voltage. Current flows from
the bottom resistor in the divider and from the ADJ pin’s
internal clamp through the top resistor in the divider to
the external circuitry pulling OUT below ground. If the
input is powered by a voltage source, the output sources
current equal to its current limit capability and the LT3055
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
1.0
0.614W • 40°C/W = 24.6°C
VIN = 0
0.9
TJMAX = 85°C + 24.6°C = 110°C
Protection Features
0.8
OUTPUT CURRENT (µA)
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction temperature rise above ambient or:
0.7
0.6
0.5
0.4
0.3
0.2
The LT3055 incorporates several protection features that
make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
0.1
0
0
5
10
15
20 25
VOUT (V)
30
35
40
3055 F11
Figure 11. Reverse Output Current
Rev. B
22
For more information www.analog.com
LT3055 Series
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
0.305 ±0.038
(.0120 ±.0015)
TYP
16
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
Rev. B
For more information www.analog.com
23
LT3055 Series
PACKAGE DESCRIPTION
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.45 BSC
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
9
R = 0.115
TYP
0.40 ±0.10
16
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE16) DFN 0806 REV Ø
8
0.200 REF
1
0.23 ±0.05
0.45 BSC
0.75 ±0.05
3.15 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
Rev. B
24
For more information www.analog.com
LT3055 Series
REVISION HISTORY
REV
DATE
DESCRIPTION
A
6/14
Modified Minimum VIN to 1.8V
Added 3.3V and 5V options, related specs, Typical Performance Characteristics and Pin Functions
B
10/18
PAGE NUMBER
1
Throughout
Added specification for absolute maximum SENSE pin voltage
2
Modified Pinouts to accommodate new fixed voltage options
2
Modified Note 7
5
Modified PWRGD applications section
16
Changed Typical Minimum Input Voltage from 1.8V to 1.6V
1, 4, 16, 26
Added Note 17 to Electrical Characteristics regarding Minimum Input Voltage
4, 5
Added new Typical Performance Curve TEMP Pin Minimum Input Voltage
11
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
more by
information
www.analog.com
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
25
LT3055 Series
TYPICAL APPLICATION
Cable Drop Compensation
VIN
7V
LT3055
IN
10µF
REF
+
–
+
–
600mV
1x 500x
RCABLE/2
OUT
IMON
ADJ
100nF
10µF
RCABLE • 500
RCABLE/2
440k – RCABLE • 500
2N3904
1k
1k
+
5V, COMPENSATED
10µF FOR DROP ALONG
RCABLE/2 RESISTORS
–
10nF
60k
3055 TA02FF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, ThinSOT™ Package
LT1762
150mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, SO-8 Package
LT1962
300mA, Low Noise LDO
270mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1964
200mA, Low Noise, Negative LDO
340mV Dropout Voltage, Low Noise: 30μVRMS, VIN: –1.8V to –20V, ThinSOT Package
LT1965
1.1A, Low Noise, Low Dropout Linear
Regulator
290mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V,
Stable with Ceramic Capacitors, TO-220, DDPak, MSOP and 3mm × 3mm DFN
Packages
LT3008
20mA, 45V, 3µA IQ Micropower LDO
300mV Dropout Voltage, Low IQ = 3μA, VIN: 2.0V to 45V, VOUT: 0.6V to 39.5V,
ThinSOT and 2mm × 2mm DFN-6 Packages
LT3009
20mA, 3µA IQ Micropower LDO
280mV Dropout Voltage, Low IQ = 3μA, VIN: 1.6V to 20V, 2mm × 2mm DFN-6 and
SC-70 Packages
LT3010
50mA, High Voltage, Micropower LDO
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 30μA, ISD < 1μA,
Low Noise:
工商网监
湘ICP备2023018690号
