LT3072
Dual, Low Noise, 2.5A
Programmable Output, 80mV
Low Dropout Linear Regulator
DESCRIPTION
FEATURES
Dual, Independent 2.5A Outputs
Dropout Voltage: 80mV
Low Output Noise: 12µVRMS (10Hz to 100kHz)
Digitally Programmable VOUT: 0.6V to 2.5V
Output Tolerance: ±1.25%/±1.5% Over Load, Line and
Temperature
n Analog Output Margining: ±10% Range
n Parallel Multiple Devices for Higher Current
n Programmable Precision Current Limit: ±7%
n Output Current Monitor: I
MON = IOUT/3000
n High Frequency PSRR: 30dB at 1MHz
n Stable with Ceramic Output Capacitors (10µF Minimum)
n VIOC Pin Controls Buck Converter to Maintain Low
Power Dissipation and Optimize Efficiency
n PWRGD/UVLO Flags
n Current Limit and Thermal Shutdown Protection
n Temperature Monitor
n 36-Lead 4mm × 7mm QFN Package
n
n
n
n
n
APPLICATIONS
n
n
n
n
FPGA, DSP and Microprocessor Power Supplies
Low Noise RF Power Supplies
High-Speed Servers and Storage Devices
Post Buck Regulation and Supply Isolation
The LT®3072 is a low voltage, UltraFast™ transient
response, dual channel linear regulator. The device
supplies up to 2.5A per channel with a typical dropout
voltage of 80mV. A 0.1µF reference bypass capacitor
decreases output voltage noise to 12µVRMS. The wide
bandwidth and high PSRR permit the use of small ceramic
capacitors, saving bulk capacitance and cost. The LT3072
is ideal for high performance FPGAs, microprocessors
and sensitive RF communication supply applications.
Independent output voltages are digitally selectable
in 50mV increments from 0.6V to 1.2V and in 100mV
increments from 1.2V to 2.5V. Output current monitors
provide diagnostics and program the precision current
limit. The LT3072 incorporates a unique tracking feature (VIOC) to control the upstream buck regulator(s)
powering the inputs. VIOC adaptively servos the buck
regulator to maintain the LT3072 input-to-output voltage
differential to 300mV at maximum load and 450mV at
light load, minimizing power dissipation with less input
capacitance. Internal protection circuitry includes UVLO,
OVLO, reverse-current protection, current limiting and
thermal shutdown. The LT3072 is available in a low profile
(0.75mm) 36-lead 4mm × 7mm QFN package.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dropout Voltage vs Load Current
2.5V/0.6V, 2.5A Regulators
VIN1
2.7V TO
3.45V
47µF
0.1µF
NC
1nF
VIN2
0.8V TO
3.45V
100
PWRGD
4.7µF
47µF
0.1µF
NC
1nF
BIAS
BIAS
EN1
PWRGD1
IN1
OUT1
VO1B2
SENSE1
VO1B1
VO1B0
REF/BYP1 IMON/LIM1
MARGA1
VIOC1
LT3072
EN2
PWRGD2
IN2
OUT2
VO2B2
SENSE2
VO2B1
VO2B0
REF/BYP2 IMON/LIM2
MARGA2
VIOC2
GND
TEMP
VIN = VOUT(NOMINAL)
VOUT = 0.6V & 2.5V
VBIAS = 5V
49.9k
10µF*
1k
10µF*
VOUT1
2.5V
2.5A
VMON1
833.3mV AT 2.5A FULL-SCALE
1V AT 3A CURRENT LIMIT
VOUT2
0.6V
2.5A
1k
VTEMP
10mV/°C
25°C = 250mV
VMON2
833.3mV AT 2.5A FULL-SCALE
1V AT 3A CURRENT LIMIT
DROPOUT VOLTAGE (mV)
VBIAS
5V
80
60
40
20
0
*X5R OR X7R CAPACITORS
3072 TA01a
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3072 TA01b
Rev. 0
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1
LT3072
MARGA1
IMON/LIM1
TEMP
VO1B0
VO1B1
TOP VIEW
VO1B2
36 35 34 33 32 31
EN1
1
30 REF/BYP1
BIAS
2
29 GND
PWRGD1
3
28 GND
VIOC1
4
27 SENSE1
IN1
5
IN1
6
IN2
7
IN2
8
23 OUT2
VIOC2
9
22 SENSE2
26 OUT1
25 OUT1
37
GND
24 OUT2
PWRGD2 10
21 GND
BIAS 11
20 GND
19 REF/BYP2
EN2 12
MARGA2
IMON/LIM2
NC
13 14 15 16 17 18
VO2B0
IN1, 2 Pin Voltage...................................... –0.3V to 3.6V
OUT1, 2 Pin Voltage................................... –0.3V to 3.6V
SENSE1, 2 Pin Voltage............................... –0.3V to 3.6V
BIAS Pin Voltage........................................ –0.3V to 5.5V
VO1,2B2, VO1,2B1, VO1,2B0 Pin Voltage.........–0.3V to BIAS
EN1, 2 Pin Voltage......................................–0.3V to BIAS
VIOC1, 2 Pin Voltage..................................–0.3V to BIAS
PWRGD1, 2 Pin Voltage.............................–0.3V to BIAS
IMON/LIM1,2 Pin Voltage..............................–0.3V to BIAS
TEMP Pin Voltage......................................... –0.3V to 2V
REF/BYP1, 2 Pin Voltage............................... –0.3V to 2V
MARGA1, 2 Pin Voltage................................. –0.3V to 2V
Output Short-Circuit Duration........................... Indefinite
Operating Junction Temperature (Note 2)
E-Grade, I-Grade................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
VO2B2
(Note 1)
VO2B1
ABSOLUTE MAXIMUM RATINGS
UFF PACKAGE
36-LEAD (4mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 32°C/W
EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB
Rev. 0
2
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LT3072
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3072EUFF#PBF
LT3072EUFF#TRPBF
3072
36-Lead (4mm × 7mm) Plastic QFN
–40°C to 125°C
LT3072IUFF#PBF
LT3072IUFF#TRPBF
3072
36-Lead (4mm × 7mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. RMON = 1kΩ, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
IN Pin Voltage
l
BIAS Pin Voltage (Note 5)
l
2.375
TYP
MAX
UNITS
3.45
V
5.25
V
Regulated Output Voltage (Note 4)
VOUT = 0.6V, 10mA ≤ IOUT ≤ 2.5A, 0.90V ≤ VIN ≤ 1.05V
VOUT = 1.0V, 10mA ≤ IOUT ≤ 2.5A, 1.3V ≤ VIN ≤ 1.45V
VOUT = 1.2V, 10mA ≤ IOUT ≤ 2.5A, 1.5V ≤ VIN ≤ 1.65V
VOUT = 1.5V, 10mA ≤ IOUT ≤ 2.5A, 1.8V ≤ VIN ≤ 1.95V
VOUT = 1.8V, 10mA ≤ IOUT ≤ 2.5A, 2.1V ≤ VIN ≤ 2.25V
VOUT = 2.5V, 10mA ≤ IOUT ≤ 2.5A, 2.8V ≤ VIN ≤ 2.95V
l
l
l
l
l
l
0.591
0.985
1.1850
1.4812
1.7775
2.4687
0.600
1.000
1.200
1.500
1.800
2.500
0.609
1.015
1.2150
1.5188
1.8225
2.5313
V
V
V
V
V
V
Regulated Output Voltage Margining
MARGA = 1.2V
MARGA = 0V
l
l
9
–11
10
–10
11
–9
%
%
Line Regulation to VIN
VOUT = 0.6V, ∆VIN = 0.9V to 3.45V, VBIAS = 5.0V, IOUT = 10mA
VOUT = 1.2V, ∆VIN = 1.5V to 3.45V, VBIAS = 5.0V, IOUT = 10mA
l
l
0.02
0.02
1
2
mV
mV
Line Regulation to VBIAS
VOUT = 0.6V, ∆VBIAS = 2.375V to 5.25V, VIN = 0.9V, IOUT = 10mA
VOUT = 1.2V, ∆VBIAS = 2.4V to 5.25V, VIN = 1.5V, IOUT = 10mA
l
l
0.2
0.2
1.5
3
mV
mV
Load Regulation
∆IOUT = 10mA to 2.5A
(Note 5)
VBIAS = 2.375V, VIN = 0.9V, VOUT = 0.6V
1.2
2.4
3.6
mV
mV
2
4
6
mV
mV
1.3
2.5
3.7
mV
mV
1.9
3.7
5.6
mV
mV
2.6
5.1
7.7
mV
mV
1
mA
19
25
35
mV
mV
38
50
70
mV
mV
80
125
175
mV
mV
l
VBIAS = 2.375V, VIN = 1.3V, VOUT = 1.0V
l
VBIAS = 2.4V, VIN = 1.5V, VOUT = 1.2V
l
VBIAS = 3V, VIN = 2.1V, VOUT = 1.8V
l
VBIAS = 3.7V, VIN = 2.8V, VOUT = 2.5V
l
Minimum Load Current (Note 11)
Dropout Voltage
VIN = VOUT(NOMINAL)
VBIAS ≥ VOUT + 1.2V
(Note 8)
IOUT = 0.5A
l
IOUT = 1A
l
IOUT = 2.5A
l
Rev. 0
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3
LT3072
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. RMON = 1kΩ, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SENSE Pin Current
(Note 5)
VIN = 0.9V, VOUT = 0.6V (Unity Gain)
VIN = 0.95V, VOUT = 0.65V
VIN = 1.45V, VOUT = 1.15V
VIN = 1.5V, VOUT = 1.2V (Unity Gain)
VIN = 2.1V, VOUT = 1.8V
VIN = 2.8V, VOUT = 2.5V
l
l
l
l
l
l
–1.5
7
82
–1.5
90
194
0
12.5
137.5
0
150
325
1.5
20
215
1.5
235
508
µA
µA
µA
µA
µA
µA
Ground Pin Current
(Both Channels Enabled) (Note 9)
VIN = 1.3V, VOUT = 1.0V, IOUT1 = IOUT2 =10mA
VIN = 1.3V, VOUT = 1.0V, IOUT1 = 10mA, IOUT2 = 2.5A
l
l
2.6
3.2
5.2
6.4
mA
mA
BIAS Pin Current,
VIN = 1.3V,
VOUT = 1.0V
(Note 4)
IOUT = 10mA
IOUT = 100mA
IOUT = 500mA
IOUT = 1A
IOUT = 2.5A
l
l
l
l
l
2.8
3.5
4.6
5.3
7
4.7
5.7
7.3
8.4
10.8
mA
mA
mA
mA
mA
BIAS Pin Current in Dropout (Notes 4, 8)
VBIAS = 5.25V, IOUT = 2.5A
l
36
mA
BIAS Pin Nap Mode Current
VBIAS = 5.25V, EN = 0V
l
1.4
2.4
mA
Reverse Output Current (Note 10)
EN = VBIAS
VBIAS = 2.375V, VIN = 0V, VOUT = 0.6V
VBIAS = 5.25V, VIN = 0V, VOUT = 2.5V
l
l
0.02
0.45
0.2
1
mA
mA
IMON Output Current
IOUT = 2.5A, VIN – VOUT = 0.3V
IOUT = 0.5A, VIN – VOUT = 0.3V
l
l
791.7
137.5
833.3
166.7
875
195.8
µA
µA
Adjustable Current Limit (Notes 6)
RMON = 1kΩ
RMON = 2kΩ
RMON = 6kΩ
l
l
l
2.79
1.37
0.4
3.0
1.5
0.5
3.21
1.63
0.6
A
A
A
Internal Current Limit (Notes 6, 12)
VIN = 0.9V, VOUT = 0V
VIN – VOUT = 0.3V, ∆VOUT = 100mV
l
l
2.8
3.3
4.2
A
A
PWRGD VOUT Threshold
Percentage of VOUT(NOMINAL), VOUT Rising
Percentage of VOUT(NOMINAL), VOUT Falling
l
l
90
85
93.5
88.5
97
92
%
%
PWRGD VOL
IPWRGD = 200µA (Fault Condition)
l
100
mV
l
1
µA
PWRGD VOH Leakage
VPWRGD = VBIAS = 5.25V
TEMP Voltage (Note 3)
TJ = 25°C
TJ = 125°C
TEMP Error (Note 3)
0°C < TJ ≤ 125°C
VBIAS Undervoltage Lockout
VBIAS Rising
VBIAS Falling
l
l
1.75
VIN Undervoltage Lockout
VIN Rising
l
0.43
VIN – VBIAS Overvoltage Lockout
EN = VBIAS = 3.3V, VIN Rising
EN = VBIAS = 3.3V, VIN Falling
l
l
150
60
VIN – VOUT Servo Voltage: VIOC
(Note 7)
IOUT = 10mA, VOUT ≥ 0.7V
IOUT = 10mA, VOUT ≤ 0.65V
IOUT = 2.5A, VOUT ≥ 0.7V
IOUT = 2.5A, VOUT ≤ 0.65V
l
l
l
l
400
400
250
250
VIOC Maximum Output Current
VIN = VOUT + 20mV, VIOC Pin Sources Current
VIN = VOUT + 900mV, VIOC Pin Sinks Current
l
l
170
170
l
0.27
l
0.45
0.25
1.25
–0.09
VIN Undervoltage Lockout Hysteresis
V
V
0.09
V
2.15
2.05
2.37
V
V
0.50
0.59
V
320
180
mV
mV
450
450
300
300
500
550
370
420
mV
mV
mV
mV
270
310
390
390
µA
µA
0.08
VIOC Transconductance
VIN = VOUT + 450mV
VIL Input Threshold (Logic-0 State)
VOUTB2, VOUTB1, VOUTB0
Input Falling
VIZ Input Range (Logic-Z State)
VOUTB2, VOUTB1, VOUTB0
V
0.88
mA/V
0.33
V
0.66
V
Rev. 0
4
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LT3072
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. RMON = 1kΩ, unless otherwise noted.
PARAMETER
CONDITIONS
VIH Input Threshold (Logic-1 State)
VOUTB2, VOUTB1, VOUTB0
Input Rising
MIN
Input Hysteresis
VOUTB2, VOUTB1, VOUTB0
VIL Input Rising
VIH Input Falling
Input Pin Current High
VOUTB2, VOUTB1, VOUTB0
VIH = VBIAS = 5.25V, Current Sinks Into Pin
l
17
26
µA
Input Pin Current Low
VOUTB2, VOUTB1, VOUTB0
VIL = 0V, VBIAS = 5.25V, Current Sources Out of Pin
l
13
20
µA
EN Pin Threshold
VOUT = OFF to ON
VOUT = ON to OFF
l
l
0.3
0.85
0.5
1.1
V
V
EN Pin Logic—High Current
VEN = VBIAS = 5.25V
l
7
12
20
µA
l
l
TYP
MAX
0.86
1
65
90
UNITS
V
mV
mV
EN Pin Logic—Low Current
VEN = 0V
VBIAS Ripple Rejection (Note 4)
VBIAS = 2.7V (Avg), VIN = 1.5V, VOUT = 1.2V, IOUT = 2.5A,
VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz
54
70
dB
VIN Ripple Rejection (Notes 4, 5, 6)
VBIAS = 2.5V, VIN = 1.65V (Avg), VOUT = 1.2V, IOUT = 2.5A,
VRIPPLE = 300mVP-P, fRIPPLE = 120Hz
60
74
dB
Channel Isolation (Notes 4, 5, 6)
(Opposing Channel VOUT Ripple)
VBIAS = 2.5V, VIN = 1.5V, VOUT = 1.2V, IOUT1 = IOUT2 = 2.5A,
VRIPPLE = 50mVP-P, fRIPPLE = 120Hz
80
dB
Output Voltage Noise (Note 4)
VOUT = 1.2V, IOUT = 2.5A, CREF/BYP = 100nF,
BW = 10Hz to 100kHz, COUT = 10µF
12
µVRMS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3072 regulators are tested and specified under pulse
load conditions such that TJ = TA. The LT3072E is 100% tested at
TA = 25°C and performance is guaranteed from 0°C to 125°C.
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3072I is
guaranteed over the –40°C to 125°C operating junction temperature range.
Note 3: The TEMP output voltage represents the average temperature
of the LT3072’s power devices. Due to power dissipation, temperature
gradients and thermal time constants across the die, the TEMP output
voltage measurement is not guaranteed to precisely track transient power
excursions in the power device. The internal thermal shutdown sensors,
embedded in each power device, are designed to keep the LT3072 within
its safe operating area.
Note 4: Electrical Test performed with both channels enabled, the channel
under test at the specified load current and the other channel at 10mA.
Note 5: To maintain proper performance and regulation, the BIAS supply
voltage must be higher than both IN supply voltages. For both VOUT
voltages, the BIAS voltage must satisfy the following conditions:
2.375V ≤ VBIAS ≤ 5.25V and VBIAS ≥ (VOUT + 1.2V).
1
µA
Note 6: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification does not apply
for all possible combinations of input voltage and output current. When
operating at maximum output current, limit the input voltage range to
VIN ≤ VOUT + 300mV.
Note 7: VIOC input-to-output voltage control incorporates a power
adaptive feature that maximizes VIN under light loads at VIN – VOUT =
450mV, and reduces VIN – VOUT to 300mV near max load.
Note 8: Dropout voltage, VDO, is the minimum input-to-output voltage
differential at a specified output current. In dropout, the output voltage
equals VIN – VDO.
Note 9: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a
current source load.
Note 10: Reverse output current is tested with the IN pins grounded and
the OUT + SENSE pins forced to the rated output voltage. This is measured
as current into the OUT + SENSE pins.
Note 11: The LT3072 requires a minimum load current to ensure proper
regulation and stability. This parameter is guaranteed by design and is not
production tested.
Rev. 0
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5
LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage (2.5A)
VOUT = 1.2V, VBIAS = 2.5V
VOUT = 0.6V, VBIAS = 2.5V
VOUT = 2.5V, VBIAS = 5V
75
50
25
0
VVIN
IN == VVOUT(NOMINAL)
OUT(NOMINAL)
IOUT = 2.5A
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
100
75
50
0
–50 –25
2.5
60
125
VOUT = 1.2V, VBIAS = 2.5V
VOUT = 0.6V, VBIAS = 2.5V
VOUT = 2.5V, VBIAS = 5V
25
VIN = VOUT(NOMINAL)
Dropout Voltage (1A)
70
0
200
VIN = VOUT(NOMINAL)
IOUT = 0.5A
20
15
10
0
–50 –25
VOUT = 1.2V, VBIAS = 2.5V
VOUT = 0.6V, VBIAS = 2.5V
VOUT = 2.5V, VBIAS = 5V
0
160
140
60
VIN = VOUT(NOMINAL)
IOUT = 2.5A
1.212
1.209
0.997
0.994
2.5
3.0 3.5 4.0 4.5
BIAS VOLTAGE (V)
5.0
0.597
25 50 75 100 125 150
TEMPERATURE (°C)
Output Voltage (1.5V)
VBIAS = 2.5V
VIN = 1.5V
IOUT = 10mA
1.5141
1.200
1.197
1.194
0.988
1.188
25 50 75 100 125 150
TEMPERATURE (°C)
0
3072 G06
1.5188
1.203
1.191
0
0.599
0.591
–50 –25
5.5
1.206
0.991
0.985
–50 –25
0.601
0.593
OUTPUT VOLTAGE (V)
VBIAS = 2.5V
VIN = 1.3V
IOUT = 10mA
1.000
VBIAS = 2.5V
VIN = 0.9V
IOUT = 10mA
0.603
Output Voltage (1.2V)
1.003
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G05
1.215
1.006
0
0.595
40
0
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.009
0.605
80
20
25 50 75 100 125 150
TEMPERATURE (°C)
0.607
100
Output Voltage (1.0V)
1.012
VOUT = 1.2V, VBIAS = 2.5V
VOUT = 0.6V, VBIAS = 2.5V
VOUT = 2.5V, VBIAS = 5V
3072 G03
0.609
120
3072 G04
1.015
20
Output Voltage (0.6V)
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.6V
180
25
5
30
Dropout Voltage vs VBIAS
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
30
40
3072 G02
Dropout Voltage (0.5A)
35
50
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G01
VIN = VOUT(NOMINAL)
IOUT = 1A
10
OUTPUT VOLTAGE (V)
100
150
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
175
DROPOUT VOLTAGE (mV)
Dropout Voltage vs IOUT
125
1.185
–50 –25
VBIAS = 3.3V
VIN = 1.8V
IOUT = 10mA
1.5094
1.5047
1.5000
1.4953
1.4906
1.4859
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G07
3072 G08
1.4812
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G09
Rev. 0
6
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LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
VBIAS = 3.3V
VIN = 2.1V
IOUT = 10mA
OUTPUT VOLTAGE (V)
1.8090
1.8045
1.8000
1.7955
1.7910
1.7865
2.5156
VBIAS = 5V
VIN = 2.8V
IOUT = 10mA
2.4922
2.4844
2.4688
–50 –25
2.1
0
3.0
2.5
2.0
1.5
2.5A
1A
500mA
100mA
10mA
1.0
0.5
0
–50 –25
0
VEN1 = VEN2 = 0V
2.1
1.5
1.2
0.9
0.6
2.5
3.0 3.5 4.0 4.5 5.0
BIAS PIN VOLTAGE (V)
BIAS PIN CURRENT (mA)
4
3
VOUT = 2.5V, VBIAS = 5.0V
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 0.6V, VBIAS = 2.5V
1
0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
OPPOSING CHANNEL 10mA
VOUT = 1.2V
10 VIN = 1.5V
9 VBIAS = 2.5V
11
5
2.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
8
5.5
1.5
1.2
0.9
0.6
0
–50 –25
6.0
VBIAS = 5V
VBIAS = 3.3V
VBIAS = 2.5V
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G15
BIAS Pin Undervoltage Lockout
Threshold
2.5A
1A
500mA
100mA
10mA
7
6
5
4
3
2
1
0
–50 –25
0
2.5
VEN1 = VEN2 = 0V
3072 G14
12
6
0.5
1.8
BIAS Pin Current
7
0
0.3
0
2.0
25 50 75 100 125 150
TEMPERATURE (°C)
8
VOUT1 = VOUT2 = 2.5V, VBIAS = 5V
VOUT1 = VOUT2 = 1.8V, VBIAS = 3.3V
VOUT1 = VOUT2 = 1.2V, VBIAS = 2.5V
VOUT1 = VOUT2 = 0.6V, VBIAS = 2.5V
3072 G12
0.3
OPPOSING CHANNEL 10mA
VIN = VOUT + 0.3V
2
1.5
BIAS Pin Current in Nap Mode
1.8
BIAS Pin Current vs IOUT
9
2.0
2.4
3072 G13
10
2.5
0
25 50 75 100 125 150
TEMPERATURE (°C)
BIAS PIN CURRENT (mA)
BIAS PIN CURRENT (mA)
GND PIN CURRENT (mA)
3.5
3.0
BIAS Pin Current in Nap Mode
2.4
OPPOSING CHANNEL 10mA
VOUT = 1.2V
VIN = 1.5V
VBIAS = 2.5V
4.0
3.5
3072 G11
GND Pin Current
4.5
4.0
0.5
3072 G10
5.0
4.5
1.0
1.7775
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
5.0
2.5000
2.4766
0
OPPOSING CHANNEL 10mA
VIN = VOUT + 0.3V
5.5
2.5078
1.7820
BIAS PIN CURRENT (mA)
OUTPUT VOLTAGE (V)
1.8135
2.5234
6.0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G16
3072 G17
2.4
BIAS PIN UVLO THRESHOLD (V)
1.8180
GND Pin Current vs IOUT
Output Voltage (2.5V)
2.5312
GND PIN CURRENT (mA)
Output Voltage (1.8V)
1.8225
2.3
VBIAS RISING
2.2
2.1
VBIAS FALLING
2.0
1.9
1.8
1.7
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G18
Rev. 0
For more information www.analog.com
7
LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
IN Pin Undervoltage Lockout
Threshold
VIN – VBIAS Overvoltage Lockout
Threshold
VIN RISING
0.47
0.44
0.41
VIN FALLING
0.38
0.35
0.32
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G19
VBIAS = 5.25V
16
125°C
14
25°C
12
10
–40°C
8
6
4
2
0
1.0
0.9
0.8
0.7
LOGIC HIGH TO Hi–Z (INPUT FALLING)
0.6
0.5
0.4
0.3
0.2
LOGIC LOW TO Hi–Z (INPUT RISING)
LOGIC Hi–Z TO LOW (INPUT FALLING)
0.1
0
–50 –25
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
EN PIN VOLTAGE (V)
SENSE PIN CURRENT (µA)
SENSE PIN CURRENT (µA)
450
16
VOUT = 0.65V
12
10
8
6
4
2
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
EN FALLING
0.4
0.3
0.2
0.1
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G21
28
24
400
350
VOUT = 2.5V
300
250
200
VOUT = 1.8V
150
50
–50 –25
VOUT = 1.15V
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G25
VBIAS = 5.25V
125°C
20
25°C
16
–40°C
12
8
CURRENT FLOWS
INTO THE PIN
4
0
CURRENT FLOWS
OUT OF THE PIN
–4
–8
–12
–16
–20
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VO1,2B0,1,2 PIN VOLTAGE (V)
3072 G24
PWRGD Threshold
SENSE TIED TO OUT
CURRENT FLOWS INTO THE PIN
100
VOUT = 0.6V AND 1.2V
0
0.5
SENSE Pin Current
500
SENSE TIED TO OUT
CURRENT FLOWS INTO THE PIN
14
0.6
3072 G23
SENSE Pin Current
18
0.7
VO1,2B0,1,2 Pin Input Current
LOGIC Hi–Z TO HIGH (INPUT RISING)
3072 G22
20
0.8
VO1,2B0,1,2 Pin Thresholds
1.1
OUTPUT VOLTAGE SELECT THRESHOLD (V)
EN PIN INPUT CURRENT (µA)
18
EN RISING
0.9
3072 G20
EN Pin Input Current
20
1.0
OUTPUT VOLTAGE SELECT INPUT CURRENT (µA)
0.50
EN Pin Threshold
1.1
PWRGD THRESHOLD OF VOUT(NOMINAL) (%)
0.53
IN–TO–BIAS OVLO THRESHOLD (mV)
IN PIN UVLO THRESHOLD (V)
0.56
320
300
280
260
VIN – VBIAS RISING
240
220
200
180
160
140
120
VIN – VBIAS FALLING
100
80
60
–50 –25 0
25 50 75 100 125 150
TEMPERATURE (°C)
EN PIN THRESHOLD (V)
0.59
3072 G26
97
96
95
VOUT RISING
94
93
92
91
90
89
88
VOUT FALLING
87
86
85
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G27
Rev. 0
8
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LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
PWRGD VOL Threshold
80
70
60
50
40
30
20
10
0
–50 –25
0
500
45
40
VOH TO VOL
35
30
25
20
15
10
VOL TO VOH
5
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
VIOC IN–TO–OUT SERVO VOLTAGE (mV)
PWRGD INTERNAL TIME DELAY (µs)
90
PWRGD VOL VOLTAGE (mV)
50
IPWRGD = 200µA
0
3072 G28
340
320
300
260
240
–50 –25
VOUT = 0.60V, VBIAS = 2.5V
VOUT = 0.65V, VBIAS = 2.5V
VOUT = 0.70V, VBIAS = 2.5V
VOUT = 2.50V, VBIAS = 3.7V
0
430
420
410
370
350
330
310
290
270
250
VBIAS = 5.25V
VBIAS = 2.375V
230
210
3300
8
3250
VIN – VOUT = 0.02V
CURRENT FLOWS OUT OF THE PIN
3200
IOUT/IMON RATIO (A/A)
0
–2
–4
–6
0
–40°C
3150
310
290
270
250
210
VIN – VOUT = 0.9V
CURRENT FLOWS INTO THE PIN
170
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G33
IMON/LIM External Current Limit
Threshold
IMON = VMON/RMON
RMON = 1kΩ
VIN = VOUT + 0.3V
VBIAS = VOUT + 1.2V
3050
3000
25°C
2950
2900
2850
–8
2750
–10
2700
150
VBIAS = 5.25V
VBIAS = 2.375V
230
190
3100
2800
125
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G32
10
2
0
330
IOUT/IMON Ratio
4
VOUT = 0.60V, VBIAS = 2.5V
VOUT = 0.65V, VBIAS = 2.5V
VOUT = 0.70V, VBIAS = 2.5V
VOUT = 2.50V, VBIAS = 3.7V
VIOC Output Current (Sinking)
350
170
–50 –25
6
TEMP PIN ERROR (°C)
440
370
190
25 50 75 100 125 150
TEMPERATURE (°C)
50
75
100
TEMPERATURE (°C)
450
390
TEMP Pin Error
25
460
390
3072 G31
0
470
3072 G30
VIOC OUTPUT CURRENT (µA)
VIOC OUTPUT CURRENT (µA)
VIOC IN–TO–OUT SERVO VOLTAGE (mV)
360
280
480
VIOC Output Current (Sourcing)
VIN = VOUT + 0.3V
380
VIN = VOUT + 0.3V
3072 G29
VIOC VIN – VOUT Servo Voltage,
IOUT = 2.5A
400
490
400
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
125°C
0
0.5
1.05
1.04
IMON/LIM PIN THRESHOLD (V)
100
VIOC VIN – VOUT Servo Voltage,
IOUT = 10mA
PWRGD Internal Time Delay
VBIAS = VOUT + 1.2V
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3072 G34
3.0
3072 G35
0.95
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G36
Rev. 0
For more information www.analog.com
9
LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
BIAS Pin Ripple Rejection,
1.2V/2.5A
Internal Current Limit
3.6
3.4
3.2
3.0
2.8
–50 –25
VBIAS = 5.25V
VBIAS = 2.375V
0
90
80
80
70
60
50
40
VIN = 1.5V
COUT = 10µF
VTEMP = 0.25V
30
20
VBIAS = 5V + 50mVRMS RIPPLE
VBIAS = 3.3V + 50mVRMS RIPPLE
VBIAS = 2.5V + 50mVRMS RIPPLE
10
0
25 50 75 100 125 150
TEMPERATURE (°C)
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
3072 G37
70
60
50
40
COUT = 10µF + 2× 47µF
COUT = 10µF
1M
10M
100kHz
20 VIN = 1.5V
COUT = 10µF
500kHz
V
=
0.25V
10 TEMP
1MHz
50mVRMS RIPPLE ON VBIAS
2MHz
0
1
1.5
2
2.5
3
3.5
4
BIAS–TO–OUT VOLTAGE DIFFERENTIAL (V)
3072 G39
90
60
50
40
30
COUT = 10µF + 2× 47µF
COUT = 10µF
20
VIN = 1.5V + 50mVRMS RIPPLE
10 VBIAS = 2.5V
VTEMP = 0.25V
0
10
100
1k
10k 100k
FREQUENCY (Hz)
50mVRMS RIPPLE ON VIN
80 VBIAS = 2.5V
COUT = 10µF
70 VTEMP = 0.25V
60
50
40
30
10
1M
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
IN–TO–OUT VOLTAGE DIFFERENTIAL (V)
10M
3072 G42
Channel-to-Channel Isolation
60
50
40
30
100kHz
500kHz
1MHz
2MHz
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
IN–TO–OUT VOLTAGE DIFFERENTIAL (V)
CHANNEL–TO–CHANNEL ISOLATION (dB)
100
50mVRMS RIPPLE ON VIN
80 VBIAS = 2.5V
COUT = 10µF
70 VTEMP = 0.25V
100kHz
500kHz
1MHz
2MHz
20
3072 G41
90
IN PIN RIPPLE REJECTION (dB)
30
10M
70
IN Pin Ripple Rejection vs
VIN – VOUT, 1.2V/1A
10
40
IN Pin Ripple Rejection vs
VIN – VOUT, 1.2V/2.5A
3072 G40
20
50
IN PIN RIPPLE REJECTION (dB)
80
IN PIN RIPPLE REJECTION (dB)
IN PIN RIPPLE REJECTION (dB)
90
80
VIN = 1.5V + 50mVRMS RIPPLE
10 VBIAS = 2.5V
VTEMP = 0.25V
0
10
100
1k
10k 100k
FREQUENCY (Hz)
60
IN Pin Ripple Rejection,
1.2V/1A
90
20
70
3072 G38
IN Pin Ripple Rejection,
1.2V/2.5A
30
BIAS PIN RIPPLE REJECTION (dB)
3.8
90
Minimum VBIAS – VOUT Voltage
CHANNEL 1
CHANNEL 2
90
80
70
60
50
40
30
20
10
0
VOUT = 1.2V
VIN = 1.5V
VBIAS = 2.5V
VTEMP = 0.25V
COUT = 10µF
IOUT1 = IOUT2 = 2.5A
50mVRMS RIPPLE ON OPPOSING CHANNEL
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
3072 G43
10M
3072 G44
MINIMUM BIAS–TO–OUT DIFFERENTIAL (V)
CURRENT LIMIT (A)
4.0
VIN = 0.9V
VOUT = 0V
BIAS PIN RIPPLE REJECTION (dB)
4.2
BIAS Pin Ripple Rejection vs
VBIAS – VOUT, 1.2V/2.5A
1.2
1.1
1.0
VIN = VOUT(NOMINAL) + 0.3V
∆VOUT = –1%
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50 –25
IOUT = 2.5A
IOUT = 1.0A
IOUT = 100mA
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G45
Rev. 0
10
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LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
LINE REGULATION TO BIAS VOLTAGE (mV)
VIN = VOUT(NOMINAL) + 0.3V
∆IOUT = 10mA TO 2.5A
–1.0
–1.5
–2.0
–2.5
–3.0
–4.0
–4.5
–5.0
–50 –25
VOUT = 0.6V, VBIAS = 2.5V
VOUT = 1.2V, VBIAS = 2.5V
VOUT = 1.8V, VBIAS = 3.3V
VOUT = 1V, VBIAS = 2.5V
VOUT = 2.5V, VBIAS = 5V
0
VOUT = 1.2V, ∆VBIAS = 2.4V TO 5.25V
VOUT = 0.6V, ∆VBIAS = 2.375V TO 5.25V
1.4
VIN = VOUT(NOMINAL) + 0.3V
IOUT = 10mA
1.2
1.0
0.8
0.6
0.4
0.2
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
0.60
0.15
IOUT
0.12
0.09
25°C
0.06
ISENSE
0.03
0
0.50
0.45
0.40
ISENSE
0.35
0.30
125°C
0.25
0.20
IOUT
25°C
0.15
0.10
0.05
0
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
OUTPUT VOLTAGE (V)
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
OUTPUT VOLTAGE (V)
3072 G49
CREF/BYP = 1µF
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
36
OUTPUT NOISE VOLTAGE (µVRMS)
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
CREF/BYP = 100nF
0.1
0.01
0.04
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G48
10
VOUT = 2.5V
VOUT = 1.8V
1
CREF/BYP = 100nF
IOUT = 2.5A
COUT = 10µF
VTEMP = 0.5V
0.1 VOUT = 1.2V
VOUT = 0.6V
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
f = 10Hz TO 100kHz
32 VBIAS = 4.5V
COUT = 10µF
28 VTEMP = 0.25V
RMS Output Noise vs CREF/BYP
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.6V
24
20
16
12
8
4
0
0.01
0.1
1
OUTPUT CURRENT (A)
3072 G52
1M
3072 G51
RMS Output Noise vs Load
Current CREF/BYP =100nF
VOUT = 0.6V
IOUT = 2.5A
COUT = 10µF
VTEMP = 0.5V
1
0.08
3072 G50
Output Noise Spectral Density
vs CREF/BYP
10
0.12
Output Noise Spectral Density
vs VOUT
CURRENT FLOWS THROUGH PINS TO GND
OUT SET FOR 2.5V
0.55
0.18
VBIAS = 5V
IOUT = 10mA
0.16
Reverse Output Current (2.5V)
REVERSE OUTPUT CURRENT (mA)
REVERSE OUTPUT CURRENT (mA)
0.21
VOUT = 1.2V, ∆VIN = 1.5V TO 3.45V
VOUT = 0.6V, ∆VIN = 0.9V TO 3.45V
3072 G47
Reverse Output Current (0.6V)
CURRENT FLOWS THROUGH PINS TO GND
OUT SET FOR 0.6V
125°C
Line Regulation to VIN
0.20
25 50 75 100 125 150
TEMPERATURE (°C)
3072 G46
0.24
0.24
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
–3.5
Line Regulation to VBIAS
10
3072 G53
80
OUTPUT NOISE VOLTAGE (µVRMS)
–0.5
LOAD REGULATION (mV)
1.6
LINE REGULATION TO IN VOLTAGE (mV)
Load Regulation
0
70
60
f = 10Hz TO 100kHz
VBIAS = 4.5V
IOUT = 2.5A
COUT = 10µF
VTEMP = 0.25V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 0.6V
50
40
30
20
10
0
10n
100n
REF/BYP CAPACITOR (F)
1µ
3072 G54
Rev. 0
For more information www.analog.com
11
LT3072
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Noise
Start-Up Time
START–UP TIME (ms)
100
VOUT
50µV/DIV
AC-COUPLED
10
1
3072 G55
1ms/DIV
CREF/BYP = 100nF
VTEMP = 0.25V
f = 10Hz TO 100kHz
SETTLING TO 1%
IOUT = 10mA
VOUT = 1.2V
COUT = 10µF
IOUT = 2.5A
0.1
10
100
REF/BYP PIN CAPACITANCE (nF)
1000
3072 G56
Start-Up Response
Load Transient Response
VOUT
500mV/DIV
VEN
1V/DIV
VOUT
50mV/DIV
AC-COUPLED
COUT = 10µF
VOUT
50mV/DIV
AC-COUPLED
COUT = 10µF + 2× 47µF
IOUT = 250mA TO 2.5A
IOUT
2A/DIV
1ms/DIV
VOUT(NOMINAL) = 1.2V VIN = 1.5V
COUT = 10µF
VBIAS = 2.5V
RLOAD = 120Ω
CREF/BYP = 10nF
3072 G57
20µs/DIV
VOUT(NOMINAL) = 1.2V
VIN = 1.5V
VBIAS = 2.5V
VIN Line Transient Response
VBIAS Line Transient Response
VOUT
1mV/DIV
AC-COUPLED
VIN
50mV/DIV
AC-COUPLED
3072 G58
VOUT
5mV/DIV
AC-COUPLED
∆VIN = 1.5V TO 1.55V
20µs/DIV
VOUT(NOMINAL) = 1.2V
VBIAS = 2.5V
IOUT = 10mA
COUT = 10µF
VBIAS
500mV/DIV
AC-COUPLED
3072 G59
∆VBIAS = 2.5V TO 3V
20µs/DIV
VOUT(NOMINAL) = 1.2V
VBIAS = 1.5V
IOUT = 10mA
COUT = 10µF
3072 G60
Rev. 0
12
For more information www.analog.com
LT3072
PIN FUNCTIONS
VO1,2B0, VO1,2B1 and VO1,2B2 (Pins 34, 15, 35, 14,
36,13): Output Voltage Select. These three-state pins
combine to select a nominal output voltage from 0.6V
to 2.5V. An input logic low state is guaranteed with less
than 270mV referenced to GND and a logic high state
is guaranteed with greater than 1V referenced to GND.
The range between 0.45V and 0.66V defines the logic
Hi-Z (input floating) state. See Table 1 in the Applications
Information section that defines the VOUT versus VOB2,
VOB1 and VOB0 settings.
EN1, EN2 (Pins 1, 12): Channel Enable. These pins
enable/disable the channel output. Pulling the EN pin
low pulls down the channel reference, and disables the
output transistor and auxiliary functions. When disabled,
the output is shunted to GND via the nominal feedback
resistor network and an internal 32k load resistor. When
VBIAS is above its UVLO threshold, an additional 8k load
resistor will be present on either IN or OUT, whichever
has the lower voltage. Drive the EN pin with either a digital logic port or an open-collector NPN or an open-drain
NMOS terminated with a pull-up resistor to VBIAS. The
pull-up resistor must be less than 182kΩ to meet the VIH
condition of the EN pin.
BIAS (Pins 2, 11): Bias Supply. These pins supply current
to most of the internal control circuitry and the output
stage driving the pass transistor. The LT3072 requires a
minimum 2.2µF bypass capacitor on each BIAS pin for
stability and proper operation. To ensure proper operation, the BIAS voltage must conform to the equation:
• VBIAS is less than its undervoltage lockout threshold.
• VIN is less than its undervoltage lockout threshold.
• VIN is greater than VBIAS by more than its overvoltage
lockout threshold.
• The OUT-over-IN voltage detector is activated.
• VBIAS is less than 1V higher than VOUT and VIN.
• Thermal shutdown is triggered.
See the Applications Information section for more information on PWRGD fault modes.
VIOC1, VIOC2 (Pins 4, 9): Voltage for IN-to-OUT Control.
VIOC is a unique tracking function to control a buck regulator powering the LT3072 input. The VIOC pin is the output of this tracking function that drives an external buck
regulator to maintain the input voltage at VOUT + 300mV
at maximum load and VOUT + 450mV at light load, or a
minimum of 0.85V, whichever is greater. This function
maximizes efficiency and minimizes power dissipation.
See the Applications Information section for more information on proper control of the buck regulator.
When not used, terminate the VIOC pin to GND with a
small capacitor (1nF) to avoid oscillations. The VIOC pin
can be tied to GND if additional quiescent current is not
a concern during low input-to-output voltage differential
conditions.
• VOUT is less than 93.5% of VOUT(NOMINAL) on the rising
edge of VOUT.
IN1, IN2 (Pins 5, 6, 7, 8): Input Supply. These pins supply power to the high current pass transistor. Tie both
IN1 pins together and both IN2 pins together for proper
performance. The LT3072 requires a bypass capacitor
at IN to maintain stability and low input impedance over
frequency. A 22μF input bypass capacitor on each channel
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low VIN-VOUT differential
voltages with large, fast load transients will have much
higher input capacitor requirements to prevent the input
supply from drooping and allowing the regulator to enter
dropout. See the Applications Information section for
more information on input capacitor requirements.
• VOUT drops below 88.5% of VOUT(NOMINAL) for more
than 35µs.
NC: (Pin 16): Unused Pin in the Package. Connect to
ground or any adjacent pin.
VOUT + 1.2V ≤ VBIAS ≤ 5.25V
Both BIAS pins must be tied together on the PCB. Power
sequence BIAS first before toggling the enable and output
voltage select pins.
PWRGD1, PWRGD2 (Pins 3, 10): Power Good. The
PWRGD pins are open-drain NMOS outputs that are active
low when the channel is enabled and any one of these fault
modes is detected:
Rev. 0
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13
LT3072
PIN FUNCTIONS
GND: (Pins 20, 21, 28, 29, Exposed Pad 37): Ground.
The exposed pad is an electrical connection to GND. To
ensure proper electrical and thermal performance, solder
the back tab to the PCB ground and tie to all GND pins
of the package. These GND pins are fused to the internal
die attach paddle and the exposed pad to optimize heat
sinking and thermal resistance characteristics. See the
Applications Information section for thermal considerations and calculating junction temperature.
OUT1, OUT2 (Pins 25, 26, 23, 24): Output. These pins
supply power to the load. Tie both OUT1 pins together
and both OUT2 pins together for proper performance.
A minimum output capacitance of 10μF is required for
stability. ADI recommends low ESR, X5R or X7R dielectric ceramic capacitors for best performance. Large load
transient applications require larger output capacitors to
limit peak voltage transients. The LT3072 requires a 1mA
minimum load current to ensure proper regulation and
stability.
See the Applications Information section for more information on output capacitor requirements.
SENSE1, SENSE2 (Pins 27, 22): Kelvin Sense for OUT.
Optimum regulation is obtained when the SENSE pin connects to the OUT pin of the regulator. In critical applications, the resistance (RP) of PCB traces between the
regulator and the load cause small voltage drops, creating
a load regulation error at the point of load. Connecting the
SENSE pin at the load instead of directly to OUT eliminates
this voltage error. Figure 1 illustrates this Kelvin-Sense
connection method. Note that the voltage drop across
the external PCB traces adds to the dropout voltage of
the regulator. The SENSE pin input bias current depends
on the selected output voltage. SENSE pin input current
varies from 12.5μA typical at VOUT = 0.65V, to 325μA
typical at VOUT = 2.5V.
REF/BYP1, REF/BYP2 (Pins 30, 19): Reference Filter. This
pin is the output of a 66.7µA current reference feeding
an impedance of approximately 18kΩ. This pin must not
be externally loaded. Bypassing the REF/BYP pin to GND
with at least a 10nF capacitor filters the chopper stabilized
reference, decreases output voltage noise and provides a
+
VBIAS
VIN
+
BIAS BIAS
ENn
PWRGDn
INn
SENSEn
VOnB0
OUTn
VOnB1
LT3072
VOnB2
MARGAn
VIOCn
IMON/LIMn
REF/BYPn
RP
LOAD
GND
RP
3072 F01
Figure 1. Kelvin Sense
soft-start function to each channel reference. ADI recommends the use of a high quality, low leakage capacitor. See
the Applications Information section for related information about output noise and output voltage margining.
MARGA1, MARGA2 (Pins 31, 18): Analog Margining.
This input pin selects the value of margining by injecting
offset into the internal reference. Grounding this pin will
offset the channel output by –10%. Pulling this pin to
1.2V will offset the output by 10%. Note: the 1.2V REF/
BYP pin will not drive the MARGA pin to 10%. An external
reference is required.
TEMP (Pin 33): Output indicator of average die temperature scaled at 10mV/°C to a reference level of 0.25V at
25°C. The TEMP output is active when VBIAS is above
its undervoltage lockout threshold. Since the TEMP pin
output impedance is typically 1kΩ, use a resistor divider
greater than 100kΩ for applications requiring the attenuation of the TEMP pin voltage.
IMON/LIM1, IMON/LIM2 (Pins 32, 17): Output Current
Monitor and Adjustable Current Limit Pin. When the
channel is enabled, this pin sources an output current
proportional to the channel load current scaled to 333.3µA
per 1A load current. Current limit activates when this pin
rises to 1V. ILIM = 3000/RMON where RMON is the terminating resistor to ground. When current limiting to less
than 500mA, a series 10k – 10nF network on the IMON/LIM
pin will compensate the presence of parasitic series
inductance to the load.
Rev. 0
14
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LT3072
BLOCK DIAGRAM
INn
BIAS
LDO
gm = 16.7m
160k
–
MARGAn
HIREFn (1.2V)
ERROR
AMP
EN
+
OUTn ≥ 1.2V
4k
REFn
10.1k
LOREFn (0.6V)
SENSEn
IDEAL
DIODE
OUTn ≥ 1.15V
81k
10.1k
–
+
INT_ENn
12µA FOR ENn > 1.8V
150k FOR ENn < 1.8V
INn–BIAS_OVLO
+
–
BIAS_UVLO
INn_UVLO
TLIMIT
REV_DETECT
PWRGDn
35µs DELAY
ON SENSEn
FALLING EDGE
+
BIAS_UVLO
INT_ENn
+
–
0.85V
60k
0.55V
CH_ENn
ENn
32k
INn
0.2V
+
2.15V
–
BIAS
+
0.5V
–
INn
–
93.5%
REFn
EN
–
VIOCn
VIOC
+
–
81k
CH_ENn
OUTn
66mV
+
REF/BYPn
INTERNAL
ILIMIT
+ILIMIT
2V
20mΩ
–
EXTERNAL
240k
CHOPPER
STABILIZED
66.7µA
REV_DETECT
+
–
IOUTn
3000
ILIM = 3000
RMON
IMON =
8k
CURRENT
MONITOR
–
IMON/LIMn
OUT-over-IN
DETECTION
BUF
2V INTERNAL
SUPPLY
–
PWRGDn VIOCn
+
ENn
0.45V =
IOUTn
16.67A
TEMP
MONITOR
10mV/°C
25°C = 250mV
+
TLIMIT
3.692k
TO ∞
TEMP
–
1.68V
OUTPUT VOLTAGE SELECTION
+
5% HYST
VOn B 2
GND
VOn B 1
VOn B 0
OUTPUT VOLTAGE SELECTION TRI-STATE LOGIC PINS
BIAS
VOnB2, VOnB1, VOnB0
1.1V
80k FOR VOn Bx < 1.1V
∞ FOR VOn Bx > 1.1V
120k FOR VOn Bx < 2V
16.7µA FOR VOn Bx > 2V
0.86V
90mV HYST
–
+
–
0.33V
+
LOGIC-1 STATE
LOGIC-Z STATE
LOGIC-0 STATE
65mV HYST
3072 BD02
Rev. 0
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15
LT3072
APPLICATIONS INFORMATION
Introduction
Current generation FPGA and ASIC processors place
stringent demands on the power supplies that power the
core, I/O, and transceiver channels. These microprocessors may cycle load current from near zero to amps in
nanoseconds. Output voltage specifications, especially in
the 1V range, require tight tolerances including transient
response as part of the requirement. Some ASIC processors require only a single output voltage from which the
core and I/O circuitry operate. Some high performance
FPGA processors require separate power supply voltages for the processor core, the I/O and the transceivers.
Often, these supply voltages must be low noise and high
bandwidth to achieve the lowest bit-error rates. These
requirements mandate the need for very accurate, low
noise, high current, very high speed regulator circuits that
operate at low input and output voltages.
The LT3072 is a dual channel, low voltage, UltraFast transient response linear regulator. The device supplies up to
2.5A of output current per channel with a typical dropout voltage of 80mV. A 0.1µF reference bypass capacitor decreases output noise to 12µVRMS (BW = 10Hz to
100kHz). The LT3072's high bandwidth provides UltraFast
transient response using low ESR ceramic output capacitors (10μF minimum), saving bulk capacitance, PCB area
and cost.
The LT3072 features permit state-of-the-art linear regulator performance. The LT3072 is ideal for high performance FPGAs, microprocessors, sensitive communication supplies and high current logic applications that also
operate over low input and output voltages.
The LT3072 provides dedicated control pins for both channels. Output voltage is digitally selectable in 50mV increments over the 0.6V to 1.2V range and 100mV increments
over the 1.2V to 2.5V range. An analog margining pin
allows the user to check system tolerance to the LT3072
output voltage continuously over a range of ±10%. The
LT3072 also incorporates enable/disable control.
The IC incorporates a unique tracking function, which
if enabled by the user, controls the upstream regulator
powering the LT3072 input (see Figure 2). This tracking
function drives the buck regulator to maintain the LT3072
input voltage to VOUT + 450mV under light loads and VOUT
+ 300mV near maximum load. This input-to-output voltage control allows the user to change the LT3072 programmed output voltage, and have the switching regulator powering the LT3072 input track to the optimum
input voltage with no component changes. Adapting for
load current allows for the reduction in input capacitance
requirements. This combines the efficiency of a switching
regulator with superior linear regulator response. It also
permits thermal management of the system even with a
maximum 2.5A output load.
FPGA system designers can now correlate their power
estimates with direct measurements of load current
through the IMON/LIM pin. This feature provides 333.3µA
per 1A of load current as a scaled dynamic representation
of output current. A termination resistor programs the
precision current limit to when the IMON/LIM pin voltage
reaches 1V.
The LT3072 provides temperature monitoring that is typically 10mV/°C where 250mV = 25°C. Additional LT3072
internal protection includes input undervoltage lockout
(UVLO), reverse current protection, current limit and
thermal shutdown. The LT3072 regulator is available in a
thermally enhanced 36-lead, 4mm × 7mm QFN package.
The LT3072 architecture drives an internal N-channel
power MOSFET as a source follower. This configuration permits a user to realize an extremely low dropout,
UltraFast transient response regulator with excellent high
frequency PSRR performance. The LT3072 achieves
superior regulator bandwidth and transient load performance and eliminates expensive bulk tantalum or electrolytic capacitors, even in the most modern and demanding
microprocessor applications. Users realize significant cost
savings as all additional bulk capacitance is removed. The
additional savings of insertion cost, purchasing/inventory
cost and board space is readily apparent. Precision incremental output voltage control accommodates legacy or
future microprocessor power supply voltages.
Often, the high frequency ceramic decoupling capacitors required by these various FPGA and ASIC processors are sufficient to stabilize the system (see Stability
and Output Capacitance section). This regulator design
Rev. 0
16
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LT3072
APPLICATIONS INFORMATION
provides ample bandwidth and responds to transient load
changes in a few hundred nanoseconds versus regulators
that respond in many microseconds.
Table 1. VOUT Selection Matrix
VOUTn (V)
VOnB2
VOnB1
VOnB0
0.60
0
0
0
0.65
0
0
Z
0.70
0
0
1
0.75
0
Z
0
0.80
0
Z
Z
0.85
0
Z
1
0.90
0
1
0
0.95
0
1
Z
1.00
0
1
1
1.05
Z
0
0
1.10
Z
0
Z
Three tri-level input pins, VOn B2, VOn B1 and VOn B0, select
the value of output voltage. Table 1 illustrates the three-bit
digital word to output voltage relationship resulting from
setting these pins high, low or allowing them to float.
1.15
Z
0
1
1.20
Z
Z
0
1.30
Z
Z
Z
1.40
Z
Z
1
An input logic low state is guaranteed with less than
270mV referenced to GND and a logic high state is guaranteed with greater than 1V. The range between 450mV
to 660mV defines the logic Hi-Z (input floating) state.
1.50
Z
1
0
1.60
Z
1
Z
1.70
Z
1
1
1.80
1
0
0
1.90
1
0
Z
2.00
1
0
1
2.10
1
Z
0
2.20
1
Z
Z
2.30
1
Z
1
2.40
1
1
0
2.50
1
1
Z
2.50
1
1
1
As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the
LT3072 offers superior regulation and an appreciable
component cost savings. The LT3072 steps to the next
level of performance for the latest generation FPGAs,
DSPs and microprocessors. The simple versatility and
benefits derived from these circuits satisfy the power supply needs of today’s high performance microprocessors.
Programming Output Voltage
These pins may be tied high by either pin strapping them
to VBIAS or driving them with digital ports. Pins that float
may either actually float or require logic that has Hi-Z
output capability. This allows output voltage to be dynamically changed if necessary.
0 = Low, Z = Hi-Z (Float), 1 = High
Rev. 0
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17
LT3072
APPLICATIONS INFORMATION
REF/BYP—Voltage Reference
The REF/BYP pin is the buffered output of the internal 66.7µA current reference feeding an impedance of
approximately 18kΩ. The internal reference is chopper
stabilized at 125kHz with spread spectrum. A 100nF REF/
BYP capacitor to GND creates a low pass pole at 88Hz,
which decreases reference voltage noise to about 5μVRMS
and soft-starts the individual channel references at enable.
Soft-start time is determined by the value of REF/BYP
capacitor used. Output voltage noise is predominantly
the RMS sum of the reference voltage noise in addition
to the amplifier noise.
The REF/BYP pin must not be DC loaded by anything
except for applications that parallel other LT3072 regulators for higher output currents. Consult the Paralleling for
Higher Output Current section for further details.
Output Voltage Margining
An analog input pin, MARGA, selects the amount of output
voltage margining. Margining is employed by offsetting
the internal reference and likewise the output. Grounding
the MARGA pin offsets the output –10%. Pulling the
MARGA pin up to 1.2V offsets the output 10%.
Enable Function—Turning On and Off
The EN pins enable/disable the output and reset the independent channel references. Pulling both EN pins low
places the regulator into “nap” mode. In nap mode, the
internal overhead circuits remain active, but the outputs
are disabled and the quiescent current decreases.
Drive the EN pins with either a digital logic port or an
open-collector NPN or open-drain NMOS terminated with
a pull-up resistor to VBIAS. The pull-up resistor must be no
larger than 182k to meet the VIH condition of the EN pin
when BIAS is at its minimum voltage of 2.375V.
BIAS Undervoltage Lockout
An internal undervoltage lockout (UVLO) comparator
monitors the BIAS rail. If VBIAS drops below the UVLO
threshold, all functions shut down, the pass transistors
are gated off and output currents fall to zero. The typical
BIAS pin UVLO threshold is 2.15V on the rising edge of
VBIAS. The UVLO circuit incorporates about 100mV of
hysteresis on the falling edge of VBIAS.
VIN Undervoltage and Overvoltage Lockout
Each channel has input undervoltage and overvoltage
lockout comparators. One monitors IN relative to a 500mV
reference. The second monitors if IN exceeds VBIAS. If
either of these conditions are violated, the affected channel shuts down, the pass transistor is gated off and output
current falls to zero.
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
The VIOC (voltage input-to-output control) pin is a function to control a switching regulator and facilitate a design
solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance.
The VIOC pin is the output of an integrated transconductance amplifier that sources 270µA and sinks 310µA
of current. It typically regulates the output of most ADI
switching regulators or LTM power modules by sinking current from the ITH compensation node. The VIOC
function controls a buck regulator powering the LT3072
input by maintaining the LT3072 input voltage to VOUT
+ 450mV under light loads, and scaling back the input
voltage to VOUT + 300mV at maximum load. This VINVOUT differential voltage scale is chosen to provide fast
transient response and good high frequency PSRR while
minimizing power dissipation and maximizing efficiency.
For example, 1.5V to 1.2V conversion and 1.3V to 1.0V
conversion yield 0.75W maximum power dissipation per
channel at 2.5A full output current. The minimum input
voltage that the VIOC pin will regulate to is 0.85V typically.
Figure 2 depicts that the switcher’s feedback resistor
network sets the maximum switching regulator output
voltage if the linear regulator is disabled. However, once
the LT3072 is enabled, the feedback loop decreases the
switching regulator output voltage back to VOUT + 450mV
at light load.
Using the VIOC function creates a feedback loop between
the LT3072 and the switching regulator. As such, the
Rev. 0
18
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LT3072
APPLICATIONS INFORMATION
IN
PWM
OUT
IOUT
0.45V –
16.67A
BUCK–REF
FB
+
–
LOAD
SENSE
ITH
REF
SWITCHING REGULATOR
VIOC
LT3072 SINGLE CHANNEL
3072 F02
Figure 2. VIOC Control Block Diagram
feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many ADI ITH
pins represents a high impedance characteristic which is
the optimum circuit node to frequency compensate the
feedback loop. Figure 2 illustrates the typical frequency
compensation network used at the VIOC node to GND.
Power Good
PWRGD pin is an open-drain NMOS digital output that
actively pulls low if any one of these fault modes is
detected:
• VOUT is less than 93.5% of VOUT(NOMINAL) on the rising
edge of VOUT.
• VOUT drops below 88.5% of VOUT(NOMINAL) for more
than 35μs.
• VBIAS is less than its undervoltage lockout threshold.
• VIN is less than its undervoltage lockout threshold.
• VIN is greater than VBIAS by more than its overvoltage
lockout threshold.
• The OUT-over-IN voltage detector activates.
• Junction temperature exceeds 168°C typically.
Stability and Output Capacitance
The LT3072 feedback loop requires a minimum output
capacitance of 10μF for stability. ADI recommends mounting low ESR, X5R or X7R ceramic capacitors in close
proximity to the LT3072 OUT and GND pins. Include wide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance for
optimal load transient performance. Point-of-load applications present the best case layout scenario for extracting
full LT3072 performance.
Additional ceramic capacitors distributed beyond the
immediate decoupling capacitors are acceptable and recommended at the point of load, because the distributed
PCB inductance isolates them from the primary compensation capacitors.
Many of the applications in which the LT3072 excels,
such as FPGA, ASIC processor or DSP supplies, typically
require a high frequency decoupling capacitor network
for the device being powered. This network generally consists of many low value ceramic capacitors in parallel.
Multiple low value capacitors in parallel present a favorable frequency characteristic that reduces the parasitic
inductance of the capacitors.
Although the LT3072 is stable with a single 10µF ceramic
capacitor, typical 0603 or 0805 case-size capacitors have
an ESL of ~800pH and PCB mounting can contribute up to
~200pH. For better transient response and improved high
frequency PSRR, it may become necessary to reduce the
parasitic inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency,
fR, will form a tank circuit that can induce ringing of their
own accord. Small amounts of ESR (5mΩ to 10mΩ)
Rev. 0
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19
LT3072
APPLICATIONS INFORMATION
have some benefit in dampening the resonant loop, but
higher ESRs degrade the capacitor response to transient
load steps with rise/fall times less than 1μs. The most
area efficient parallel capacitor combination is a graduated 7/2/1 scale of fR of the same case size. Under these
conditions, the individual ESLs are relatively uniform, and
the resonance peaks are deconstructively spread beyond
the regulator bandwidth. The recommended parallel combination that approximates 10μF is 6.8μF + 2.2μF + 1µF.
Capacitors with case sizes larger than 0805 have higher
ESL and lower ESR (
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