LT3462/LT3462A
Inverting 1.2MHz/2.7MHz
DC/DC Converters with
Integrated Schottky
DESCRIPTION
FEATURES
Integrated Schottky Rectifier
nn Fixed Frequency 1.2MHz/2.7MHz Operation
nn Very Low Noise: 1mV
P-P Output Ripple
nn Low V
CESAT Switch: 270mV at 250mA
nn –5V at 100mA from 5V Input
nn –12V at 30mA from 3.3V Input
nn Low Input Bias Current GND Based FB Input
nn Low Impedance (40Ω) 1.265V Reference Output
nn High Output Voltage: Up to – 38V
nn Wide Input Range: 2.5V to 16V
nn Uses Tiny Surface Mount Components
nn Low Shutdown Current: ISDREF ≥ –80µA
●
1.245
FB Pin Bias Current (Note 2)
10µA > ISDREF ≥ –80µA
●
1.235
SDREF Reference Source Current
SDREF >1.2V
●
120
Supply Current
FB = –0.05V, Not Switching
SDREF = 0V, FB = Open, VIN = 5V
SDREF Minus FB Voltage
UNITS
2.5
Maximum Operating Voltage
SDREF Voltage
MAX
Error Amp Offset Voltage
1.265
1.285
V
15
50
nA
1.263
1.285
V
–12
12
180
2.9
6.5
SDREF Line Regulation
V
mV
µA
3.6
10
0.007
mA
µA
%/V
Switching Frequency (LT3462)
●
0.8
1.2
1.6
MHz
Switching Frequency (LT3462A)
●
2.0
2.7
3.5
MHz
Maximum Duty Cycle (LT3462)
●
90
Maximum Duty Cycle (LT3462A)
●
Switch Current Limit
%
77
300
%
420
mA
Switch VCESAT
ISW = 250mA
270
350
mV
Switch Leakage Current
VSW = 5V
0.01
1
µA
Rectifier Leakage Current
VD = –40V
0.03
4
µA
Rectifier Forward Drop
ISCHOTTKY = 250mA
800
1100
mV
0.20
V
3
µA
SDREF Voltage Low
●
SDREF Off-State Pull-Up Current
SDREF Turn-Off Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Current flows out of the pin.
1
2
–300
–200
µA
Note 3: The LT3462E is guaranteed to meet specifications from 0°C to
70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls.
Rev A
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3
LT3462/LT3462A
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency (LT3462)
Current Limit
1.6
480
SDREF Minus FB Pin Voltage
1.29
TA = 25°C
1.28
LT3462
1.4
1.3
1.2
360
LT3462A
SDREF MINUS FB (V)
CURRENT LIMIT (mA)
FREQUENCY (MHz)
1.5
240
120
1.0
–40 –20
40
20
60
0
TEMPERATURE (°C)
80
0
10
100
20
30
40 50 60 70
DUTY CYCLE (%)
80
3462 G01
1.25
10
3.0
QUIESCENT CURRENT (A)
FB BIAS CURRENT (nA)
–10
2.4
–15
–20
–25
–30
–35
–40
2.2
100
TA = 25°C
FB = N/C
–5
2.6
80
Quiescent Current in
Shutdown Mode
0
2.8
40
20
60
0
TEMPERATURE (°C)
3462 G03
FB Bias Current
TA = 25°C
2.0
–40 –20
1.23
–40 –20
90
3462 G02
Oscillator Frequency (LT3462A)
FREQUENCY (MHz)
1.26
1.24
1.1
3.2
1.27
8
6
4
2
–45
40
20
60
0
TEMPERATURE (°C)
80
100
–50
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
3462 G04
PIN FUNCTIONS
100
0
0
4
8
12
16
SUPPLY VOLTAGE (V)
3462 G05
3462 G06
(TSOT-23/DFN)
SW (Pin 1/Pin 4): Switch Pin. Connect to external induc‑
tor L1 and positive terminal of transfer cap.
GND (Pin 2/Pins 2, 3): Ground. Tie directly to local
ground plane.
FB (Pin 3/Pin 1): Feedback Pin. Connect resistive divider
tap here. Set R1 according to R1 = R2 • (VOUT/1.265V).
In shutdown, a proprietary shutdown bias current cancel‑
lation circuit allows the internal 3µA source to pull up the
SDREF pin, even with residual negative voltage on VOUT.
SDREF (Pin 4/Pin 8): Dual Function Shutdown and
1.265V Reference Output Pin. Pull to GND with exter‑
nal N-FET to turn regulator off. Turn-off pull-down and
a 2µA internal source will pull SDREF up to turn-on the
regulator. At turn-on, a 180µA internal source pulls the
pin to the regulation voltage. The SDREF pin can supply
up to 80µA at 1.265V to bias the feedback resistor divider.
An optional soft-start circuit capacitor connects from this
pin to –VOUT.
D (Pin 5/Pin 7): Anode Terminal of Integrated Schottky
Diode. Connect to negative terminal of transfer cap and
external inductor L2.
VIN (Pin 6/Pin 5): Input Supply Pin. Must be locally
bypassed.
Exposed Pad (NA/Pin 9): GND. The exposed pad should
be soldered to the PCB ground to achieve the rated ther‑
mal performance.
Rev A
4
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LT3462/LT3462A
BLOCK DIAGRAM
–
+
FB
SW
A1
E AMP
RC
+
CC
SHUTDOWN
BIAS CURRENT
CANCELLATION
DRIVER
A2
COMP
R
S
Q
Q1
SHUTDOWN
ISRC
–
GND
RAMP
GENERATOR
VOUT
VOUT
R1 (EXTERNAL)
*LT3462A IS 2.7MHz
FB
R2 (EXTERNAL)
–
CS1 (EXTERNAL)
SDREF
CS2 (EXTERNAL)
SDREF
Q2
1.265V
REFERENCE
LG
+
1.2MHz*
OSCILLATOR
VIN
DO
0.1Ω
OFF 3µA
ON 180µA
SDREF
–
D
+
CS1, CS2 OPTIONAL SOFT-START COMPONENTS
3462 F01
Figure 1. Block Diagram
OPERATION
The LT3462 uses a constant frequency, current mode
control scheme to provide excellent line and load regula‑
tion. Operation can be best understood by referring to the
Block Diagram in Figure 1. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch
Q1. A voltage proportional to the switch current is added
to a stabilizing ramp and the resulting sum is fed into
the positive terminal of the PWM comparator. When this
voltage exceeds the voltage at the output of the EAMP, the
SR latch is reset, turning off the power switch. The level
at the output of the EAMP is simply an amplified version
of the difference between the feedback voltage and GND.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is taken from
the output; if it decreases, less current is taken. One func‑
tion not shown in Figure 1 is the current limit. The switch
current is constantly monitored and not allowed to exceed
the nominal value of 400mA. If the switch current reaches
400mA, the SR latch is reset regardless of the output state
of the PWM comparator. This current limit cell protects
the power switch as well as various external components
connected to the LT3462.
SDREF is a dual function input pin. When driven low it
shuts the part down, reducing quiescent supply current
to less than 10µA. When not driven low, the SDREF pin
has an internal pull-up current that turns the regulator on.
Once the part is enabled, the SDREF pin sources up to
180µA nominally at a fixed voltage of 1.265V through
external resistor R2 to FB. If there is no fault condition
present, FB will regulate to 0V, and VOUT will regulate to
1.265V • (–R1/R2). An optional soft-start circuit uses the
fixed SDREF pull-up current and a capacitor from SDREF
to VOUT to set the dV/dt on VOUT. In shutdown, an FB bias
current cancellation circuit supplies up to 150µA biasing
current to external resistor R1 while VOUT is lower than
FB. This function eliminates R2 loading of SDREF during
shutdown. As a result, supply current in shutdown may
exceed 10µA by the amount of current flowing in R1.
Rev A
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5
LT3462/LT3462A
APPLICATIONS INFORMATION
Inrush Current
Capacitor Selection
The LT3462 has a built-in Schottky diode. When supply
voltage is applied to the VIN pin, the voltage difference
between VIN and VD generates inrush current flowing
from input through the inductor and the Schottky diode
to charge the flying capacitor to VIN. The maximum non‑
repetitive surge current the Schottky diode in the LT3462
can sustain is 1.5A. The selection of inductor and capaci‑
tor value should ensure the peak of the inrush current to
be below 1.5A. The peak inrush current can be calculated
as follows:
Ceramic capacitors are recommended. An X7R or X5R
dielectric should be used to avoid capacitance decreasing
severely with applied voltage and at temperature limits.
The “flying” capacitor between the SW and D pins should
be a ceramic type of value 1µF or more. When used in
the dual inductor or coupled inductor topologies the fly‑
ing capacitor should have a voltage rating that is more
than the difference between the input and output voltages.
For the charge pump inverter topology, the voltage rat‑
ing should be more than the output voltage. The output
capacitor should be a ceramic type. Acceptable output
capacitance varies from 1µF for high VOUT (–36V), to 10µF
for low VOUT (–5V). The input capacitor should be a 1µF
ceramic type and be placed as close as possible to the
LT3462/LT3462A.
⎛
⎞
⎜
V – 0.6
π ⎟
IP = IN
exp ⎜ –
⎟
L
L ⎟
⎜
2
–1
–1
⎝
C
C ⎠
where L is the inductance between supply and SW, and C
is the capacitance between SW and D.
Table 3 gives inrush peak currents for some component
selections.
Table 3. Inrush Peak Current
VIN (V)
L (µH)
C (µF)
IP (A)
5
22
1
0.70
33
1
0.60
47
1
1.40
The high speed operation of the LT3462 demands care‑
ful attention to board layout. You will not get advertised
performance with careless layout. Figure 2 shows the rec‑
ommended component placement. A ceramic capacitor
of 1µF or more must be placed close to the IC for input
supply bypassing.
C1
+
5
12
Layout Hints
GND
L1
Inductor Selection
Each of the two inductors used with LT3462 should have
a saturation current rating (where inductance is approxi‑
mately 70% of zero current inductance ) of approximately
0.25A or greater. If the device is used in the charge pump
mode, where there is only one inductor, then its rating
should be 0.35A or greater. DCR of the inductors should
be less than 1Ω. For LT3462, a value of 22µH is suitable
if using a coupled inductor such as Sumida CLS62-220.
If using two separate inductors, increasing the value to
47µH will result in the same ripple current. For LT3462A,
a value of 10µH for the coupled inductor and 22µH for
two inductors will be acceptable for most applications.
VIN
C2
1
6
2
5
3
4
L2
R2
C3
R1
C4
VOUT
3462 F02
Figure 2. Suggested Layout
Rev A
6
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LT3462/LT3462A
TYPICAL APPLICATIONS
3.3V to –12V with Soft-Start Circuit
C2
1µF
VIN
3.3V
SW
VIN
C1
4.7µF
80
L2
47µH
R1
267k
D
FB
C4
15pF
CS1
100nF
R2
27.4k
LT3462
SDREF
GND
TA = 25°C
75
OFF
M1
VIN = 3.3V
VOUT
–12V
30mA
C3
2.2µF
EFFICIENCY (%)
L1
47µH
–12V Efficiency
70
65
60
55
22nF
50
C1: TAIYO YUDEN X5R JMK212BJ475MG
C2: TAIYO YUDEN X5R EMK212BJ105MG
C3: TAIYO YUDEN EMK316BJ225
L1, L2: MURATA LQH32CN470
3462 TA02a
VOUT Reaches –12V in 750µs; Input
Current Peaks at 300mA without CS1
0
5
OFF
VOUT
10V/DIV
VOUT
10V/DIV
IIN
100mA/DIV
IIN
50mA/DIV
3462 TA02c
C2
1µF
C1
4.7µF
80
L1B
22µH
D
FB
SW
VIN
LT3462
SDREF
GND
3462 TA02d
–8V Efficiency
TA = 25°C
75
R1
267k
R2
42.2k
C1: TAIYO YUDEN X5R JMK212BJ475MG
C2: TAIYO YUDEN X5R EMK212BJ105MG
C3: TAIYO YUDEN LMK316BJ475
L1: SUMIDA CLS62-220 OR 2X MURATA LQH32CN330
C4
15pF
VOUT
–8V
C3
4.7µF
EFFICIENCY (%)
VIN
2.7V
TO 4.2V
35
3462 TA02b
2ms/DIV
Li+ to –8V Supply
L1A
22µH
30
VOUT Reaches –12V in 7.5ms; Input
Current Peaks at 125mA with CS1 = 100nF
OFF
2ms/DIV
10
15
20
25
LOAD CURRENT (mA)
VIN = 3.3V
70
65
60
55
50
3462 TA03a
0
10
20
30
40
LOAD CURRENT (mA)
50
3462 TA03b
Rev A
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7
LT3462/LT3462A
TYPICAL APPLICATIONS
3.3V to –8V (LT3462A)
C2
1µF
L1A
10µH
VIN
2.7V
TO 4.2V
C1
1µF
SW
VIN
5V to –5V Supply (LT3462A)
L1B
10µH
D
FB
LT3462A
SDREF
GND
VIN
5V
R1
267k
R2
42.2k
C1: TAIYO YUDEN JMK107BJ105MA
C2: TAIYO YUDEN EMK212BJ105MA
C3: TAIYO YUDEN LMK316BJ475
L1: WURTH 50310057-100
C4
22pF
C2
1µF
L1
22µH
VOUT
–8V
35mA
SW
VIN
C1
1µF
C3
4.7µF
L2
22µH
D
FB
LT3462A
SDREF
GND
C1: TAIYO YUDEN JMK107BJ105MA
C2: TAIYO YUDEN EMK212BJ105MA
C3: MURATA GRM219R60J106KE19B
L1, L2: MURATA LQH32CN220
3462 TA04a
R1
267k
C4
22pF
VOUT
–5V
100mA
C3
10µF
R2
68.1k
3462 TA05a
Switching Waveform
INDUCTOR
50mA/DIV
VSW
10V/DIV
VOUT
1mV/DIV
AC-COUPLED
200ns/DIV
3462 TA05b
Rev A
8
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LT3462/LT3462A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3462#packaging for the most recent package drawings.
DC8 Package
8-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1719 Rev A)
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05 0.64 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.45 BSC
1.37 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.05
TYP
2.00 ±0.10
(4 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
R = 0.115
TYP
5
8
0.40 ±0.10
0.64 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
(DC8) DFN 0409 REVA
4
0.200 REF
1
0.23 ±0.05
0.45 BSC
0.75 ±0.05
1.37 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
Rev A
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9
LT3462/LT3462A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3462#packaging for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S6 TSOT-23 0302
Rev A
10
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LT3462/LT3462A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/18
Add 2mm × 2mm 8-lead DFN package information (A-grade version only) to data sheet
PAGE NUMBER
1, 2, 4, 9
Rev A
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Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
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information
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11
LT3462/LT3462A
TYPICAL APPLICATION
12V to –36V DC/DC Converter
L1
47µH
VIN
12V
C2
0.47µF
–36V Efficiency
85
D1
TA = 25°C
VIN = 12V
80
LT3462
SDREF
GND
VOUT
–36V
36mA
C4
5pF
R2
15k
EFFICIENCY (%)
C1
1µF
D
FB
SW
VIN
R1
432k
C3
1µF
50V
70
65
100nF
C1: TAIYO YUDEN X5R EMK212BJ105
C2: MURATA GRM42-6X7R474K50
C3: MURATA GRM42-6X7R474K50 ×2
D1: CENTRAL CMSH5-4-LTN
L1: MURATA LQH32CN470
75
60
3462 TA06a
0
10
20
30
40
LOAD CURRENT (mA)
3462 TA06b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1617/LT1617-1
350mA/100mA (ISW) High Efficiency Micropower
Inverting DC/DC Converter
VIN: 1.2V to 15V, VOUT(MAX) = –34V, IQ = 20µA, ISD