Features
Wide Input Range: 4V to 36V
nn One 2.7A and Two 1.8A Output Switching
Regulators with Internal Power Switches
nn Low Dropout Linear Regulator with External
Transistor
nn Antiphase Switching Reduces Ripple
nn Independent Run, Tracking/Soft-Start, and Power
Good Indicators Ease Supply Sequencing
nn Uses Small Inductors and Ceramic Capacitors
nn Adjustable, 250kHz to 2.5MHz Switching Frequency,
Synchronizable Over the Full Range
nn User Programmable Overvoltage and Undervoltage
Lockouts
nn Thermally Enhanced, 38-Lead TSSOP and
5mm × 7mm QFN Packages
nn
Applications
Automotive
Industrial Supplies
nn Distributed Power Regulation
nn DSP Power
nn
nn
LT3507A
Triple Monolithic Step-Down
Regulator with LDO
Description
The LT®3507A is a triple, current mode, DC/DC converter
with internal power switches and a low dropout regulator.
The switching converters are step-down converters capable
of generating one 2.7A output and two 1.8A outputs. All
three converters are synchronized to a single oscillator.
The 2.7A output runs with opposite phase to the other two
converters, reducing input ripple current. Each regulator
has independent shutdown and soft-start circuits, and
generates a power good signal when its output is in regulation, easing power supply sequencing and interfacing
with microcontrollers and DSPs.
The switching frequency is set with a single resistor yielding
a range of 250kHz to 2.5MHz. The high switching frequency
allows the use of small inductors and capacitors resulting
in a very small triple output supply. The constant switching
frequency, combined with low impedance ceramic capacitors, results in low, predictable output ripple. Frequency
foldback and thermal shutdown provide protection against
fault conditions. The LT3507A provides higher output current than available with the LT3507.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
5V, 3.3V, 2.5V and 1.8V Step-Down Regulator
VIN
6V TO 36V
22µF
VIN1
VIN2
BOOST1
Start-Up Waveforms—Coincident Tracking
BOOST2
0.22µF
4.7µH
VOUT1
1.8V
2.7A
VIN3
SW1
0.22µF
18.7k
100µF
15k
25.5k
VOUT2
VOUT3
5V
1.8A
VC1
680pF
VC2
25.5k
FB3
BIAS
VC3
DRIVE
25.5k
VOUT3
VOUT4
VOUT1
11k
680pF
107k
VOUT2
1V/DIV
FB2
SW3
22µF
34.8k
LT3507A
53.6k
10.2k
VOUT2
3.3V
33µF 1.5A
680pF
0.22µF BOOST3
15µH
10µH
SW2
FB1
1ms/DIV
RT/SYNC
fSW = 450kHz
FB4
GND
24.3k
11.5k
2.2µF
3507 TA01b
VOUT4
2.5V
0.3A
3507A TA01a
3507afa
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1
LT3507A
Absolute Maximum Ratings
(Note 1)
VIN Pins....................................................... –0.3V to 36V
BOOST Pins...............................................................55V
BOOST Above SW......................................................25V
PGOOD Pins...............................................................36V
BIAS Pin.....................................................................16V
TRK/SS, VC, FB, RT/SYNC Pins....................................6V
RUN, OVLO, UVLO Pins............................................ VIN1
DRIVE Pin....................................................................5V
Operating Junction Temperature Range (Notes 2, 5)
LT3507AE, LT3507AI.......................... –40°C to 125°C
LT3507AH........................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP Only....................................................... 300°C
Pin Configuration
TOP VIEW
38 37 36 35 34 33 32
BOOST1 1
31 VIN2
VIN1 2
30 VIN2
VIN1 3
29 SW2
VINSW 4
28 SW2
OVLO 5
27 BOOST2
UVLO 6
38 SW3
2
37 BOOST3
SW1
3
36 VIN2
BOOST1
4
35 VIN2
VIN1
5
34 NC
VIN1
6
33 SW2
VINSW
7
32 BOOST2
OVLO
8
31 TRK/SS4
UVLO
9
VC1 10
25 FB4
TRK/SS1 8
TRK/SS1 11
30 FB4
39
GND
29 DRIVE
28 VC2
PGOOD2 14
25 TRK/SS2
PGOOD3 12
20 FB3
PGOOD3 15
24 FB3
13 14 15 16 17 18 19
RT/SYNC 16
23 VC3
RUN1 17
22 TRK/SS3
RUN2 18
21 BIAS
RUN3 19
20 GND
TRK/SS3
21 TRK/SS2
BIAS
26 FB2
PGOOD2 11
RUN3
PGOOD1 13
RUN2
FB1 12
22 FB2
RUN1
23 VC2
RT/SYNC
FB1 9
PGOOD1 10
VC3
24 DRIVE
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
2
1
26 TRK/SS4
39
GND
VC1 7
VIN3
SW1
BOOST3
SW3
SW3
VIN3
VIN3
SW1
SW1
TOP VIEW
27 NC
FE PACKAGE
38-LEAD PLASTIC TSSOP
θJA = 24°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
3507afa
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LT3507A
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3507AEUHF#PBF
LT3507AEUHF#TRPBF
3507A
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LT3507AIUHF#PBF
LT3507AIUHF#TRPBF
3507A
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LT3507AHUHF#PBF
LT3507AHUHF#TRPBF
3507A
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 150°C
LT3507AEFE#PBF
LT3507AEFE#TRPBF
LT3507AFE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3507AIFE#PBF
LT3507AIFE#TRPBF
LT3507AFE
38-Lead Plastic TSSOP
–40°C to 125°C
LT3507AHFE#PBF
LT3507AHFE#TRPBF
LT3507AFE
38-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Notes 2, 7)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Operating Voltage
Internal UVLO on VIN1
3.8
4
Input Quiescent Current
Not Switching, VBIAS = 3.3V
2
3.5
mA
Bias Quiescent Current
Not Switching, VBIAS = 3.3V
5
7.5
mA
Shutdown Current
VRUN1,2,3 = 0V
1
µA
Reference Voltage Line Regulation
5V < VIN1 < 36V
VC Source Current
VC Sink Current
l
V
0.01
%/V
VC = 0.6V
20
µA
VC = 0.6V
30
µA
1.8
V
VC Clamp Voltage
Switching Frequency
RT = 40.2k
Switching Phase
SW1 to SW2,3, RT = 40.2k
180
Deg
Foldback Frequency
VFB = 0V, RT = 40.2k
120
kHz
0.4
V
l
0.9
Frequency Shift Threshold on FB
RUN Threshold
1.1
MHz
1
1.5
V
PGOOD Output Voltage Low
IPGOOD = 200µA
0.2
0.4
V
PGOOD Pin Leakage
VPGOOD = 2V
10
400
nA
PGOOD Threshold Offset
VFB Rising
58
80
105
mV
788
800
812
mV
–50
–500
nA
Feedback Pin Voltage
l
Feedback Pin Bias Current
l
Error Amplifier Transconductance
330
µS
Error Amplifier Voltage Gain
500
V/V
VC Switching Threshold
0.9
Switch Leakage Current
0.01
10
µA
V
Minimum Boost Voltage Above Switch (Note 4)
1.8
2.5
V
ITRK/SS
VTRK/SS = 0V
1.25
µA
VIN1-VINSW
IVINSW = 1mA
0.35
V
Converter 1
VC1 to Switch Current Gain
6
A/V
3507afa
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3
LT3507A
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted (Notes 2, 7)
PARAMETER
CONDITIONS
MIN
TYP
MAX
Switch 1 Current Limit (Note 3)
Duty Cycle = 15%
4.3
5.1
6
Switch 1 VCESAT
BOOST1 Operating Current
ISW1 = 2A (Note 6)
400
600
mV
ISW1 = 2A
40
60
mA
l
UNITS
A
Converter 2
VC2 to Switch Current Gain
4.3
3.3
4
ISW2 = 1.5A (Note 6)
350
500
mV
ISW2 = 1.5A
40
60
mA
Switch 2 Current Limit (Note 3)
Duty Cycle = 15%
Switch 2 VCESAT
BOOST2 Operating Current
l
2.7
A/V
A
Converter 3
VC3 to Switch Current Gain
4.3
3.3
4
ISW3 = 1.5A (Note 6)
350
500
mV
ISW3 = 1.5A
40
60
mA
800
812
mV
–150
–500
nA
Switch 3 Current Limit (Note 3)
Duty Cycle = 15%
Switch 3 VCESAT
BOOST3 Operating Current
l
2.7
A/V
A
LDO Regulator
Feedback Pin Voltage
l
788
Feedback Pin Bias Current
1100
V/V
Line Regulation
Error Amplifier Voltage Gain
VIN from 5V to 36V
0.05
%/V
Load Regulation
IDRIVE from 0.1mA to 10mA
0.005
%/mA
DRIVE Output Current Limit
l
10
15
22.5
mA
Dropout Voltage, VIN1 to DRIVE
IDRIVE = 10mA, VIN = 5V
1.7
2.0
V
Dropout Voltage, BIAS to DRIVE
IDRIVE = 10mA, VIN = 5V
0.5
0.8
V
Over/Undervoltage Lockout
Undervoltage Lockout Threshold
1.15
1.20
1.25
V
Overvoltage Lockout Threhold
1.15
1.20
1.25
V
10
13
µA
–10
–13
µA
–100
–200
nA
Undervoltage Lockout Hysteresis Current
V(UVLO) < 1.2V
7
Overvoltage Lockout Hysteresis Current
V(OVLO) > 1.2V
–7
Input Bias Current (OVLO and UVLO)
V(OVLO) = 1.0V, V(UVLO) = 1.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3507AE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3507AI is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT3507AH is guaranteed over the
full –40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
4
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 6: Switch VCESAT for the FE package is guaranteed by design and/or
correlation to static test.
Note 7: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum specifications refer to absolute values.
3507afa
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LT3507A
Typical Performance Characteristics
VIN = 12V
70
VIN = 36V
60
50
40
Efficiency vs Load Current,
Channels 2 and 3, VOUT = 3.3V
VIN = 6V
0.5
80
VIN = 12V
0.4
VIN = 36V
70
0
0.3
804
80
803
70
802
60
CHANNELS 2, 3
50
CHANNEL 1
40
797
10
796
1.0
1.5
ISW (A)
2.0
0
1.8
2.5
3507A G04
0.5
1
1.5
ISW (A)
2
2.5
3
3507A G03
Frequency vs RT
2.5
2.0
1.5
1.0
0.5
795
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
3.0
0
3507A G02
799
20
0.5
1.5
800
798
0
0.9
1.2
IOUT (A)
801
30
0
0.6
FREQUENCY (MHz)
90
VFB (mV)
IBOOST (mA)
805
CHANNEL 1
0.3
VFB vs Temperature
100
CHANNELS 2 AND 3
0.1
INDUCTOR: NIC NPIM74C8R2MTRF
fSW = 450kHz
3507A G01
BOOST Pin Current vs Switch
Current, Channels 1, 2 and 3
TA = 25°C
0.2
60
40
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
IOUT (A)
0.6
90
50
0
Switch VCESAT vs Switch Current,
Channels 1, 2 and 3
VCESAT (V)
VIN = 6V
80
EFFICIENCY (%)
100
INDUCTOR: NIC NPIM74C4R7MTRF
fSW = 450kHz
EFFICIENCY (%)
90
Efficiency vs Load Current,
Channel 1, VOUT = 1.8V
0
3507A G05
0
20 40 60 80 100 120 140 160 180 200
RT (kΩ)
3507A G06
Frequency vs VFB (Foldback)
Frequency vs Temperature
1200
–0.5
–1.0
–1.5
1.28
800
ITRK/SS (µA)
0.0
ITRK/SS vs Temperature
1.30
RT = 40.2k
TA = 25°C
1000
FRERQUENCY (kHz)
FREQUENCY DEVIATION (%)
0.5
600
400
3507A G07
0
1.24
1.22
200
–2.0
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
1.26
0
0.2
0.4
0.6
VFB (V)
0.8
1
3507A G08
1.20
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
3507A G09
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5
LT3507A
Typical Performance Characteristics
RUN Threshold vs Temperature
VIN1-VINSW Voltage Drop vs IVINSW
0.40
1.2
TA = 25°C
0.35
1.0
5
0.30
0.6
0.4
CHANNEL 1
4
0.25
ILIM (A)
0.8
VIN–VINSW (V)
RUN THRESHOLD (V)
Current Limit vs Duty Cycle
6
0.20
3
CHANNELS 2 AND 3
0.15
2
0.10
0.2
1
0.05
0.00
0.0
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
0
0.2
3507A G10
0.4
0.6
IVINSW (mA)
0.8
0
1.0
1
20
40
60
DUTY CYCLE
80
100
3507A G11
3507A G12
250
Minimum On-Time vs ISW
200
MINIMUM OFF-TIME (ns)
MINIMUM ON-TIME (ns)
200
150
150°C
25°C
100
–40°C
50
0
0
1
2
ISW (A)
6
3
Minimum Off-Time vs ISW
–40°C
150
25°C
150°C
100
50
0
0
3507A G13
0.5
1
1.5
ISW (A)
2
2.5
3
3507A G14
3507afa
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LT3507A
Pin Functions
BIAS: The BIAS pin supplies the current to the LT3507A’s
internal regulator. This pin should be tied to the lowest
available voltage source above 3V (either VIN, VOUT or any
other available supply). The LDO pass transistor’s base
current is supplied from the BIAS pin if it is at least 0.8V
above the LDO DRIVE output.
BOOST1, BOOST2, BOOST3: The BOOST pins are used
to provide drive voltages, higher than the input voltage,
to the internal bipolar NPN power switches. These pins
must be tied through a diode from VOUT, VIN or another
supply greater than 2.5V.
RT/SYNC: The RT/SYNC pin requires a resistor to ground
or a clock signal to set the operating frequency of the
LT3507A.
RUN1, RUN2, RUN3: The RUN pins are used to shut
down the individual switching regulators. When all three
RUN pins are low, the LT3507A shuts down and draws
less than 1µA from VIN1.
SW1, SW2, SW3: The SW pins are the outputs of the
internal power switches. Connect these pins to the inductors and switching diodes.
FB1, FB2, FB3: The FB pins are the negative inputs of the
error amplifiers. The LT3507A regulates each feedback pin
to the lesser of 0.8V or the TRK/SS pin voltage. Connect
the feedback resistor divider taps to these pins.
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4: The TRK/SS pins
allow a regulator to track the output of another regulator.
When the TRK/SS pin is below 0.8V, the FB pin regulates
to the TRK/SS voltage. This pin souces 1.25µA and can
be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB4: The FB4 pin is the negative input to the LDO error
amplifier. It is regulated to 0.8V through the LDO feedback
resistor divider.
UVLO: The LT3507A goes into undervoltage shutdown
when this pin drops below 1.2V. If unused, the UVLO pin
should be tied to VINSW.
GND: Ground. The underside exposed pad metal of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board. The
exposed pad must be soldered to a grounded pad on the
circuit board for proper operation.
VC1, VC2, VC3: The VC pins are the outputs of the internal
error amps. The voltages on these pins control the peak
switch currents. These pins are normally used to compensate the control loops. Each switching regulator can
be shut down by pulling its respective VC pin to ground
with an NMOS or NPN transistor.
DRIVE: The DRIVE pin provides the base drive for an
external NPN transistor used for the LDO regulator.
OVLO: The LT3507A goes into overvoltage shutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
PGOOD1, PGOOD2, PGOOD3: The PGOOD pins are the
open-collector outputs of an internal comparator. PGOOD
remains low until the FB pin is within 10% of the final
regulation voltage. As well as indicating output regulation,
the PGOOD pins can sequence the switching regulators.
These pins must be left unconnected if unused. The PGOOD
outputs are valid when VIN is greater than 3.8V and any of
the RUN pins are high. They are not valid when all RUN
pins are low.
VIN1: The VIN1 pins supply power to the internal switch of
the 2.7A regulator and to the LT3507A’s internal reference
and start-up circuitry. VIN1 must be above the internal UVLO
threshold of 3.8V (typical) for any of the four channels to
operate. These pins must be locally bypassed.
VIN2/VIN3: The VIN2 and VIN3 pins supply power to the
internal switches of the 1.8A converters. These pins must
be locally bypassed.
VINSW: The VINSW pin is a switched VIN1 for the user programmable undervoltage and overvoltage detection. It is
connected to VIN1 when any of the RUN pins are pulled high,
and high impedance when all RUN pins are low or open.
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7
LT3507A
Block Diagram
VINSW
VIN1
+
BIAS
OVLO
–
RUN1
INT REG
AND REF
RUN2
MASTER
OSC
CLK1
CLK2
CLK3
1.2V
+
RUN3
RT/SYNC
–
UVLO
VIN4
DRIVE
SHDN
THERMAL
SHUTDOWN
+
+
–
0.8V
–
C1
+
+
SLOPE
C3
SLAVE
OSC
VOUTX
D1
0.4V
RC
–
CC
1.8V
+CLAMP
R2
0.8V
+
ILIMIT
+
1.25µA
C1
R1
FB
–
ERROR
–
AMP
+
VC
PGOOD
L1
SW
+
CF
D2
BOOST
R
S Q
–
–
VINX
CIN
+
0.9V
CLK
FB4
VIN
UNDERVOLTAGE
DETECTION
CHANNEL
SHUTDOWN
VOUT4
1.25µA
TRK/SS4
80mV
TRK/SS
+
GND
–
ONE OF THREE STEP-DOWN REGULATORS
3507A F01
Figure 1. LT3507A Block Diagram with Typical External Components
8
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LT3507A
Operation
The LT3507A contains three independent, constant frequency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common circuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by referring to the Block Diagram (Figure 1).
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when VFB is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. VFB is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
If the RUN pins are tied to ground, the LT3507A is shut
down and draws 1.25V. The master oscillator generates three clock signals,
with the signal for channel 1 out of phase by 180°.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, current mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets the RS flip-flop and turns on the internal NPN bipolar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at VC, current comparator
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the VC
pin controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the VC pin voltage. The threshold
for switching on the VC pin is >0.9V and an active clamp
of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
The switch drivers operate either from VIN or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will flow from VIN.
A power good comparator trips when the FB pin is at 90% of
its regulated value. The PGOOD output is an open-collector
transistor that is off when the output is in regulation, allowing an external resistor to pull the PGOOD pin high.
Power good is valid when the LT3507A is enabled and VIN
is within normal operating range.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2µF or greater.
The LDO is disabled when all three of the RUN pins are low.
The overvoltage and undervoltage detection shuts down
the LT3507A if the OVLO pin >1.2V or the UVLO pin
125°C tON(MIN) = 155ns) and tOFF(MIN) = 170ns.
fMAX1 is the frequency at which the minimum duty cycle
is exceeded. The regulator will skip ON pulses in order to
reduce the overall duty cycle at frequencies above fMAX1.
It will continue to regulate but with increased inductor
current and greatly increased output ripple. The increased
peak inductor current in pulse-skipping will also stress
the switch transistor at high voltages and high switching
frequency. If the LT3507A is allowed to pulse-skip and
the input voltage is greater than 20V, then the switching
frequency must be kept below 1.1MHz to prevent damage
to the LT3507A.
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fMAX2 is the frequency at which the maximum duty cycle
is exceeded. If there is sufficient charge on the BOOST
capacitor, the regulator will skip OFF periods to increase
the overall duty cycle at frequencies about fMAX2. It will
continue to regulate but with increased inductor current
and greatly increased output ripple.
Note that the restriction on the operating input voltage
refers to steady-state limits to keep the output in regulation; the circuit will tolerate input voltage transients up to
the absolute maximum rating.
Switching Frequency
Once the upper and lower bounds for the switching
frequency are found from the duty cycle requirements,
the frequency may be set within those bounds. Lower
frequencies result in lower switching losses, but require
larger inductors and capacitors. The user must decide
the best trade-off.
The switching frequency is set by a resistor connected
from the RT/SYNC pin to ground, or by forcing a clock
signal into RT/SYNC. The LT3507A applies a voltage of
~1.25V across this resistor and uses the current to set
the oscillator speed. The switching frequency is given by
the following formula:
fSW =
53.2
R T + 12.4
where fSW is in MHz and RT is in kΩ.
The formula will give a frequency value that is accurate to
within ±3%, for better accuracy use Table 1.
Table 1. RT for Common Frequencies
SWITCHING FREQUENCY (MHz)
RT (kΩ)
0.25
203
0.5
93.8
0.75
58.0
1.0
40.2
1.25
30.0
1.5
23.0
1.75
18.0
2.0
14.3
2.25
11.4
2.5
9.17
The frequency sync signal will support VH logic levels from
1.8V to 5V CMOS or TTL. The duty cycle is not important,
but it needs a minimum on time of 100ns and a minimum
off time of 100ns. If the sync circuit is to be powered from
one of the LT3507A outputs there may be start-up problems
if the driving gate is high impedance without a supply or
pulls high or low at some intermediate supply voltage.
The circuit shown in Figure 2 prevents these problems by
isolating the clock sync circuit until the clock is operating.
The Schottky diode should be a low leakage type such as
the BAS70 from On Semi or CMOD6263 from Central Semi.
RT should be set to provide a frequency within ±25% of
the final sync frequency.
VCC
CLOCK
SYNC
CLK
1k
LT3507A
470pF
RT/SYNC SW1
BAS70
VOUT1
RT
3507A F02
Figure 2. Clock Powered from LT3507A Output
Inductor Selection and Maximum Output Current
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peakto-peak inductor ripple current. The LT3507A limits its
switch current in order to protect itself and the system
from overload faults. Therefore, the maximum output
current that the LT3507A will deliver depends on the
switch current limit, the inductor value and the input and
output voltages.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
ΔIL = (1– DC)
VOUT + VF
L•f
where f is the switching frequency of the LT3507A and L
is the value of the inductor. The peak inductor and switch
current is:
ISWPK =ILPK =IOUT +
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ΔIL
2
3507afa
11
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To maintain output regulation, this peak current must be
less than the LT3507A’s switch current limit, ILIM. For
SW1, ILIM is typically 5.1A at low duty cycles and decreases
linearly to 3.7A at DC = 0.8. For SW2 and SW3, ILIM is
typically 3.3A for at low duty cycles and decreases linearly
to 2.4A at DC = 0.8.
The minimum inductance can now be calculated as:
LMIN =
1− DCMIN VOUT + VF
•
2•f
ILIM – IOUT
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
large output capacitors to keep output voltage ripple low.
Select an inductor greater than LMIN that keeps the ripple
current below 30% of ILIM.
The inductor’s RMS current rating must be greater than the
maximum load current and its saturation current should
be greater than ILPK. For highest efficiency, the series
resistance (DCR) should be less than 0.1Ω. Table 2 lists
several vendors and series that are suitable.
Output Capacitor Selection
The output capacitor filters the inductor current to generate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3507A’s
control loop. Because the LT3507A operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following
equations:
VRIPPLE =
and
VRIPPLE = ΔIL • ESR for electrolytic capacitors
(tantalum and aluminum)
where ΔIL is the peak-to-peak ripple current in the inductor.
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
Table 2. Inductors
MANUFACTURER
Würth
SERIES
INDUCTANCE
RANGE
CURRENT
RANGE
WE-HC
1µH to 6.5µH
6A to 15A
Coilcraft
XAL40xx
0.22µH to 15µH
3.3A to 21.5A
Sumida
CDRH103R
0.8µH to 10µH
2.8A to 8.3A
VLF
2.2µH to 10µH
3.8A to 7.7A
IHLP-2525CZ-11
1µH to 10µH
2.5A to 9.5A
TDK
Vishay
This analysis is valid for continuous mode operation
(IOUT > ILIM/2). For details of maximum output current in
discontinuous mode operation, see Linear Technology’s
Application Note AN44. Finally, for duty cycles greater
than 50% (VOUT/VIN > 0.5), a minimum inductance is
required to avoid subharmonic oscillations. This minimum
inductance is:
SW1:LMIN = ( VOUT + VF ) •
0.4
fSW
SW2, SW3:LMIN = ( VOUT + VF ) •
with LMIN in µH and fSW in MHz.
12
0.75
fSW
ΔIL
for ceramic capacitors
8 • f • COUT
IC(RMS) =
ΔIL
12
Another constraint on the output capacitor is that it must
have greater energy storage than the inductor; if the stored
energy in the inductor transfers to the output, the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
⎛I
⎞2
LIM
COUT >10 •L • ⎜
⎟
VOUT ⎠
⎝
The low ESR and small size of ceramic capacitors make
them the preferred type for LT3507A applications. Not all
ceramic capacitors are the same, however. Many of the
higher value capacitors use poor dielectrics with high
temperature and voltage coefficients. In particular, Y5V and
Z5U types lose a large fraction of their capacitance with
applied voltage and at temperature extremes. Because loop
stability and transient response depend on the value of COUT,
this loss may be unacceptable. Use X7R and X5R types.
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Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 3 lists
several capacitor vendors.
Table 3. Low ESR Surface Mount Capacitors
MANUFACTURER TYPE
SERIES
Taiyo-Yuden
Ceramic
AVX
Ceramic
Tantalum
Kemet
Ceramic
Tantalum
T494, T495
Tantalum Organic Polymer T510, T520, T525, T530
Aluminum Organic Polymer A700
Sanyo
Tantalum Organic Polymer POSCAP
Aluminum Organic Polymer OS-CON
Panasonic
Ceramic
Aluminum Organic Polymer SP CAP
TDK
Ceramic
TPM, TPS
Diode Selection
The catch diode (D1 from Figure 1) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
ID(AVG) =
IOUT ( VIN – VOUT )
VIN
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current. Peak
reverse voltage is equal to the regulator input voltage. Use
a diode with a reverse voltage rating greater than the input
voltage, but not higher than 40V. Using higher breakdown
Schottky diodes may result in undesirable behavior. The
programmable OVLO can protect the diode from excessive
reverse voltage by shutting down the regulator if the input
voltage exceeds the maximum rating of the diode. Table
4 lists several Schottky diodes and their manufacturers.
Table 4. Schottky Diodes
MANUFACTURER
PART
NUMBER
CURRENT
VF AT
OUTLINE
On Semiconductor
MBRS240
2A
0.43V
SMB
On Semiconductor
MBRS340
3A
0.5V
SMC
On Semiconductor
MBRD340
3A
0.6V
DPAK
B240A
2A
0.5V
SMA
Diodes, Inc.
Diodes, Inc.
B340
3A
0.5V
SMC
Diodes, Inc.
SMB340
3A
0.5V
Powermite 3
Central Semiconductor CMSH3-40
3A
0.5V
SMC
Central Semiconductor
3A
0.65V
DPAK
CSHD3-40
Boost Pin Considerations
The capacitor and diode tied to the BOOST pin generate a
voltage that is higher than the input voltage. In most cases,
a small ceramic capacitor and fast switching diode (such
as the CMDSH-3 or MMSD914LT1) will work well. The
capacitor value is a function of the switching frequency,
peak current, duty cycle and boost voltage; in general a
value of (0.1µF • 1MHz/fSW) works well. Figure 3 shows
three ways to arrange the boost circuit. The BOOST pin
must be more than 2.5V above the SW pin for full efficiency. For outputs of 3.3V and higher, the standard
circuit (Figure 3a) is best. For outputs between 2.8V and
3.3V, use a small Schottky diode (such as the BAT54).
For lower output voltages, the boost diode can be tied
to the input (Figure 3b). The circuit in Figure 3a is more
efficient because the BOOST pin current comes from a
lower voltage source. Finally, as shown in Figure 3c, the
anode of the boost diode can be tied to another source
that is at least 3V. For example, if you are generating 3.3V
and 1.8V and the 3.3V is on whenever the 1.8V is on, the
1.8V boost diode can be connected to the 3.3V output. In
this case, the 3.3V output cannot be set to track the 1.8V
output (see Output Voltage Tracking).
In any case, be sure that the maximum voltage at the
BOOST pin is less than 55V and the voltage difference
between the BOOST and SW pins is less than 25V.
The minimum operating voltage of an LT3507A application is limited by the internal undervoltage lockout and by
the maximum duty cycle. The boost circuit also limits the
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13
LT3507A
APPLICATIONS INFORMATION
D2
D2
C3
BOOST
VIN
VIN
C3
BOOST
LT3507A
LT3507A
VIN
VOUT
SW
VIN
VOUT
SW
GND
GND
VBOOST – VSW ≅ VIN
MAX VBOOST ≅ 2VIN
VBOOST – VSW ≅ VOUT
MAX VBOOST ≅ VIN + VOUT
(3a)
(3b)
D2
VINB > 3V
BOOST
C3
LT3507A
VIN
VIN
VOUT
SW
GND
VBOOST – VSW ≅ VINB
MAX VBOOST ≅ VINB + VIN
MINIMUM VALUE FOR VINB = 3V
3507A F03
(3c)
Figure 3. Generating the Boost Voltage
minimum input voltage for proper start-up. If the input
voltage ramps slowly, or the LT3507A turns on when
the output is already in regulation, the boost capacitor
may not be fully charged. Because the boost capacitor
charges with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly. This minimum load will depend
on input and output voltages, and on the arrangement of
the boost circuit. The minimum load current generally
goes to zero once the circuit has started. Figure 4 shows
a plot of minimum load to start and to run as a function
of input voltage. Even without an output load current, in
many cases the discharged output capacitor will present
a load to the switcher that will allow it to start.
The boost current is generally small but can become significant at high duty cycles. The required boost current is:
⎛ V ⎞⎛ I
⎞
IBOOST = ⎜ OUT ⎟⎜ OUT ⎟
⎝ VIN ⎠⎝ 40 ⎠
Converter with Backup Output Regulator
There is another situation to consider in systems where
the output will be held high when the input to the LT3507A
is absent. If the VIN and one of the RUN pins are allowed
8.0
5.5
TA = 25°C
7.5 VOUT = 5V
5.0
TA = 25°C
VOUT = 3.3V
TO START
6.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
7.0
6.0
5.5
TO RUN
5.0
4.5
TO START
4.0
TO RUN
3.5
3.0
4.5
4.0
0.001
0.010
0.100
LOAD CURRENT (A)
1.000
2.5
0.001
3507A F04a
0.010
0.100
LOAD CURRENT (A)
1.000
3507 F04b
Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
14
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to float, then the LT3507A’s internal circuitry will pull its
quiescent current through its SW pin. This is acceptable
if the system can tolerate a few mA of load in this state.
With all three RUN pins grounded, the LT3507A enters
shutdown mode and the SW pin current drops to
5% IOUT) and the loop crossover frequency is less than
fSW/5. A phase lead capacitor (CPL) across the feedback
divider may improve the transient response.
16
ERROR
AMPLIFIER
330µS
500k
GND
+
The components tied to the VC pin provide frequency
compensation. Generally, a capacitor and a resistor in
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor filters
noise at the switching frequency and is not part of the
loop compensation.
VSW
–
The LT3507A uses current mode control to regulate the
output. This simplifies loop compensation. In particular,
the LT3507A does not depend on the ESR of the output
capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size.
CURRENT MODE
POWER STAGE
gmp
OUTPUT
R1
ESR
VFB
800mV
VC
RC
CPL
FB
C1
R2
CF
C1
+
POLYMER
OR
TANTALUM
CERAMIC
CC
3507A F06
Figure 6. Loop Response Model
SHUTDOWN
The RUN pins are used to place the individual switching
regulators and the internal bias circuits in shutdown mode.
When all three RUN pins are pulled low, the LT3507A is
in shutdown mode and draws less than 1µA from the
input supply. When any RUN pin is pulled high (>1.25V)
the internal reference, the LDO and selected channel are
all turned on.
The RUN pins draw a small amount of current to power
the reference. The current is less than 3µA at 1.8V, so the
RUN pin can be driven directly from 1.8V logic. The RUN
pins are rated up to 36V and can be connected directly to
the input voltage.
A RUN pin cannot be pulled up by logic powered by its
own output, i.e., RUN1 can’t be pulled up by logic powered
by OUT1.
POWER GOOD INDICATORS
The PGOOD pin is the open-collector output of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200µA. Note that this pin will be open when the LT3507A
is in shutdown mode (all three RUN pins at ground)
regardless of the voltage at the FB pin. PGOOD is valid
when the LT3507A is enabled (any RUN pin is high) and
VIN is greater than ~3.5V.
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LT3507A
RUN1
RUN1
RUN2
RUN3
LT3507A
RUN1
TRK/SS1
RUN2
RUN2
TRK/SS2
RUN3
RUN3
TRK/SS3
RUN
LT3507A
C
RUN
RUN1
2C
VINSW
4C
PG1
RUN2
(7a)
(7b)
PG2
RUN3
LT3507A
RUN
RUN1
TRK/SS1
RUN2
PG1
RUN3
TRK/SS2
PG2
(7c)
VIN
LT3507A
RUN2
PG1
TRK/SS3
3507A F07
(7d)
(7e)
Doesn’t Work!
Figure 7. Output Sequencing
OUTPUT SEQUENCING
The LT3507A outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
each case channel 1 starts first, followed by channel 2,
then channel 3. The sequence shown is not a requirement;
the LT3507A can sequence the channels in any order. Note
that these circuits sequence the outputs during start-up.
When shut down the three channels turn off simultaneously.
The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
Another possibility is to use the soft-start feature to slow
the start-up of specific channels (Figure 7b). All three RUN
pins are tied together and the difference in soft-start capacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
required, depending on the output capacitance and load on
each channel. Make sure to test the circuit in the system
before deciding on final values for these capacitors. Also
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
The PG pins can be also used to sequence the three outputs. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The resistors pull up to VINSW so that there is no current
draw in shutdown. They should be sized to provide at least
1µA into the RUN pin. The capacitors keep channels 2 and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its final value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
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LT3507A
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VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
3507A F08
TIME
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8. Two Different Modes of Output Voltage Tracking
VOUT1
TO
TRK/SS2
PIN
VOUT2
R5
R6
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
Tracking Setup
R3
SELECTING VALUES FOR R5 AND R6
R4
R5 =
R6 =
COINCIDENT RATIOMETRIC
R3
R1
R4
R1
VOUT1/1V – 1
⎛ R1 VOUT1
R3 VOUT2 ⎞
– 1,
=
– 1⎟
⎜ =
⎝ R2 0.8
⎠
R4 0.8
Figure 9. Setup for Coincident and Ratiometric Tracking
outputs at start-up, they also disable the slaved channels
if the master channel falls out of regulation (due to a short
circuit or a collapsing input voltage).
Finally, be aware that the circuit in Figure 7e does not
work, because the power good comparators are disabled
in shutdown.
OUTPUT VOLTAGE TRACKING
The LT3507A allows the user to program how the output
ramps up by means of the TRK/SS pins. Through these
pins, any channel output can be set up to either coincidently or ratiometrically track any other channel output.
This example will show the channel 2 output tracking the
channel 1 output, as shown in Figure 8. The TRK/SS2 pin
acts as a clamp on channel 2’s reference voltage. VOUT2
is referenced to the TRK/SS2 voltage when the TRK/SS2
< 0.8V and to the internal precision reference when TRK/
SS2 > 0.8V.
To implement the coincident tracking in Figure 8a, connect an extra resistive divider to the output of channel 1
and connect its midpoint to the TRK/SS2 pin (Figure 9).
18
The ratio of this divider should be selected the same as
that of channel 2’s feedback divider (R5 = R3 and R6 =
R4). In this tracking mode, VOUT1 must be set higher than
VOUT2. To implement the ratiometric tracking in Figure 8b,
change the extra divider ratio to R5 = R1 and R6 = R2 +
ΔR. The extra resistance on R6 should be set so that the
TRK/SS2 voltage is ≥1V when VOUT1 is at its final value.
The need for this extra resistance is best understood with
the help of the equivalent input circuit shown in Figure 10.
At the input stage of the error amplifier, two common anode
diodes are used to clamp the equivalent reference voltage
and an additional diode is used to match the shifted common mode voltage. The top two current sources are of
the same amplitude. In the coincident mode, the TRK/SS2
I
I
1.25µA
TRK/SS
0.8V
FB
D1
+
D2
EA2
–
D3
3507A F10
Figure 10. Equivalent Input Circuit of Error Amplifier
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voltage is substantially higher than 0.8V at steady state and
effectively turns off D1. D2 and D3 will therefore conduct
the same current and offer tight matching between VFB2
and the internal precision 0.8V reference. In the ratiometric
mode with R6 = R2, TRK/SS2 equals 0.8V at steady state.
D1 will divert part of the bias current and make VFB2 slightly
lower than 0.8V. Although this error is minimized by the
exponential I-V characteristic of the diodes, it does impose
a finite amount of output voltage deviation. Further, when
channel 1’s output experiences dynamic excursions (under
load transient, for example), channel 2 will be affected as
well. Setting R6 to a value that pushes the TRK/SS2 voltage
to 1V at steady state will eliminate these problems while
providing near ratiometric tracking.
VIN3. This can be useful in applications regulating outputs
from a PCI Express bus, where the 12V input is power
limited and the 3.3V input has power available to drive
other outputs. In this case, tie the 12V input to VIN1 and
the 3.3V input to VIN2 and VIN3.
The example shows channel 2 tracking channel 1, however
any channel may be set up to track any other channel.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 5 lists some suitable
NPN transistors with their saturation specifications.
If a capacitor is tied from the TRK/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This results in a ramp at the output, limiting the
inductor current and therefore input current during start-up.
A good value for the soft-start capacitor is COUT/10,000,
where COUT is the value of the output capacitor.
LOW DROPOUT REGULATOR
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same 0.8V
reference as the switching regulators. It requires an external
NPN pass transistor and 2.2µF of output capacitance for
stability. The internal compensation is stable with loads
up to 300mA.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
5V – VBESAT where VBESAT is the base-emitter saturation
voltage of the pass transistor.
Table 5. Low VCESAT Transistors
MULTIPLE INPUT SUPPLIES
VIN1, VIN2 and VIN3 are independent and can be powered
with different voltages provided VIN1 is present when VIN2
or VIN3 is present. Each supply must be bypassed as close
to the VIN pins as possible.
For applications requiring large inductors due to high VIN
to VOUT ratios, a 2-stage step-down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application steps down the input voltage (VIN1)
to the highest output voltage, then uses that voltage to
power the other outputs (VIN2 and VIN3). VOUT1 must be
able to provide enough current for its output plus the
input current at VIN2 and VIN3 when VOUT2 and VOUT3 are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
For applications with multiple voltages, the LT3507A can
accommodate input voltages as low as 3V on VIN2 and
PART NUMBER
VCESAT AT
IC = 1A
OUTLINE
MANUFACTURER
ZXTN25012EZ
0.06
SOT89
ZXTN25020DG
0.075
SOT223
Zetex
www.diodes.com
NSS20201JT1G
0.22
SC-89
NSS12201LT1G
0.08
CTLT3410-M621
0.28
SOT-23
On Semiconductor
www.onsemi.com
1mm × 2mm Central Semiconductor
TLM621
www.central-semi.com
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pulling the FB4 pin up with a 30µA current source. The FB4
pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3507A outputs provided that channel
is always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
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For more information www.linear.com/LT3507A
19
LT3507A
APPLICATIONS INFORMATION
FB Resistor Network
The hysteresis voltages are:
The output voltage of the LDO regulator is programmed
with a resistor divider (Refer to Block Diagram) between the
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
VOVHYST = 10µA • R3
⎛V
⎞
R1=R2 ⎜ OUT4 −1⎟
⎝ 800mV ⎠
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
PROGRAMMABLE OVERVOLTAGE and
UNDERVOLTAGE LOCKOUT
VUVHYST = 10µA • R1
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to VINSW.
VINSW
R1
10µA
R3
UVLO
R2
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO comparator trips when the UVLO pin drops below 1.2V. These
comparators shut down all four regulators until the input
voltage recovers.
The comparators also activate current sources that generate hysteresis to eliminate chatter. The UVLO comparator
activates a 10µA current sink on the UVLO pin. The OVLO
comparator activates a 10µA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
Figure 11 shows a typical connection. The threshold
voltages are:
⎛ R3 ⎞
VOVTH = 0.3V+1.2V • ⎜1+ ⎟
⎝ R4 ⎠
UVLO
+
The LT3507A provides two input pins that allow userprogrammable overvoltage and undervoltage lockout. Both
the trip levels and hysteresis can be set by resistor values.
VINSW provides a switched VIN1 to minimize power consumption in shutdown. VINSW is connected to VIN1 when
the LT3507A is operating, with a saturation voltage of
about 0.3V. It is high impedance when the LT3507A is in
shutdown (all three RUN pins low).
–
1.2V
–
OVLO
OVLO
+
R4
10µA
3507A F11
Figure 11. Undervoltage and Overvoltage Lockout Circuit
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regulator circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components, along with the inductor and output capacitor,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of the
output capacitor C2. Additionally, keep the SW and BOOST
nodes as small as possible and away from any FB or VC
pins. Figure 13 shows an example of proper PCB layout.
⎛ R1 ⎞
VUVTH = 0.3V+1.2V • ⎜1+ ⎟
⎝ R2 ⎠
where 0.3V is the typical VIN1-VINSW voltage drop.
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For more information www.linear.com/LT3507A
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LT3507A
APPLICATIONS INFORMATION
IIN
IOUT
VIN
IOUT – IIN
IIN
SW
GND
VIN
(12a Switch On)
IOUT
IC1
(12b Switch Off)
VSW
VIN
C1
L1
SW
GND
IOUT
GND
IIN
IIN
SW
D1
(12c High Frequency Switching Loop)
C2
3507A F12
Figure 12. Subtracting the Current When the Switch Is On (12a) from the Current When the Switch Is Off (12b)
Reveals the Path of the High Frequency Switching Current (12c)
Figure 13. Power Path Components and Topside Layout
THERMAL CONSIDERATIONS
The high output current capability of the LT3507A will
require careful attention to power dissipation of all the
components to insure a safe thermal design. The PCB
must provide heat sinking to keep the LT3507A cool.
The exposed pad on the bottom of the package must be
soldered to a ground plane. This ground should be tied
to other copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3507A. Place
additional vias near the catch diodes. Adding more copper
to the top and bottom layers and tying this copper to the
internal planes with vias can reduce thermal resistance
further. With these steps, the thermal resistance from die
(or junction) to ambient can be reduced to θJA = 34°C/W
or less (QFN). With 100 LFPM airflow, this resistance can
fall by another 25%. Further increases in airflow will lead
to lower thermal resistance.
For more information www.linear.com/LT3507A
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21
LT3507A
APPLICATIONS INFORMATION
The maximum allowed power dissipation by the LT3507A
can be determined by:
PDISS(MAX) =
TJ(MAX) – TA
The boost loss in channel i is:
θJA
where TJMAX is the maximum die temperature of 125°C
(150°C for H-grade).
However, take care in determining TA since the catch diodes also dissipate power and must be located close to
the LT3507A. Another potential heat source is the LDO
pass transistor. In a compact layout the pass transistor
will be located close to the LT3507A. The inductors will
also dissipate some power due to their series resistance
and they must be close to the LT3507A. All of these heat
sources will increase the effective ambient temperature
seen by the LT3507A.
A thorough analysis of eight heat sources in a small PCB
area is beyond the scope of this data sheet, however a
number of thermal analysis programs are available to
calculate the temperature rise in each component (such as
PCAnalyze from K&K Associates or Flo Therm PCB from
Mentor). The power dissipation of each component will be
needed to accurately calculate the thermal characteristics
of the system.
The contributors to power dissipation inside the LT3507A
are switch DC loss, switch AC loss, boost current, quiescent current and LDO drive current. The total dissipation
within the LT3507A can be expressed as:
3
PDISS = ∑ (PSWDCi + PSWACi + PBSTi ) + PQ + PLDO
⎛I
⎞
VOUTi ( VBOOSTi ) ⎜ OUTi +0.02A ⎟
⎝ 50
⎠
PBSTi =
VINi
The quiescent loss is:
PQ = VIN1(IQ(VIN1)) + VBIAS(IQ(BIAS))
If the BIAS pin does not have a voltage of at least 3V applied, then VIN1 must replace VBIAS in the equation. Also,
IQ(VIN1) can be reduced by 0.2mA (typ) if the LDO is shut
off (see the LDO section).
The LDO drive loss is:
⎛ IOUT(LDO) ⎞
PLDO =(VBIAS −VLDO(OUT) −0.7V)⎜
⎟,
⎝ βPASS ⎠
if VBIAS ≥ VLDO(OUT) +1.5V
or
⎛ IOUT(LDO) ⎞
PLDO =(VIN1 −VLDO(OUT) −0.7V)⎜
⎟,
⎝ βPASS ⎠
if VBIAS
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