LT3688
Dual 800mA Step-Down
Switching Regulator with
Power-On Reset and
Watchdog Timer
DESCRIPTION
FEATURES
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Wide Input Range:
Operation from 3.8V to 36V
Low Ripple ( 125°C). As the switching frequency
is increased above fSW(MAX), the part is required to switch
for shorter periods to maintain the same duty cycle. Delays
associated with turning off the power switch dictate the
minimum on-time of the part. When the required on-time
decreases below the minimum on-time of 140ns, the switch
pulse width remains fixed at 140ns (instead of becoming
narrower) to accommodate the same duty cycle requirement. The inductor current ramps up to a value exceeding
the load current and the output ripple increases. The part
then remains off until the output voltage dips below the
programmed value before it begins switching again.
Maximum Operating Voltage Range
The maximum input voltage for LT3688 applications
depends on switching frequency, the absolute maximum
ratings of the VIN and BST pins, and by the minimum
duty cycle (DCMIN). The LT3688 can operate from input
voltages up to 36V.
DCMIN = tON(MIN) • fSW
where tON(MIN) is equal to 140ns and fSW is the switching
frequency. Running at a lower switching frequency allows
a lower minimum duty cycle. The maximum input voltage
before pulse-skipping occurs depends on the output voltage and the minimum duty cycle:
V
+ VF
VIN(PS) = OUT
– VF + VSW
DCMIN
Example: f = 2.1MHz, VOUT = 3.3V
DCMIN = 140ns • 2.1MHz = 0.294
3.3V + 0.5V
VIN(PS) =
– 0.5V + 0.3V = 12.7V
0.294
3688f
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LT3688
APPLICATIONS INFORMATION
The LT3688 will regulate the output voltage at input voltages greater than VIN(PS). For example, an application
with an output voltage of 3.3V and switching frequency
of 2.1MHz has a VIN(PS) of 12.7V, as shown in Figure 1.
Figure 2 shows operation at 27V. Output ripple and peak
inductor current have significantly increased. A saturating
inductor may further reduce performance. In pulse skip
mode, the LT3688 skips switching pulses to maintain
output regulation. The LT3688 will also skip pulses at very
low load currents. VIN(PS) vs load current is plotted in the
Typical Performance section.
Unlike many fixed frequency regulators, the LT3688 can
extend its duty cycle by remaining on for multiple cycles.
The LT3688 will not switch off at the end of each clock
cycle if there is sufficient voltage across the boost capacitor
(C3 in the Block Diagram). Eventually, the voltage on the
boost capacitor falls and requires refreshing. Circuitry
detects this condition and forces the switch to turn off,
allowing the inductor current to charge up the boost
capacitor. This places a limitation on the maximum duty
cycle as follows:
DCMAX = 90%
This leads to a minimum input voltage of:
V
+ VF
VIN(MIN) = OUT
– VF + VSW
DCMAX
VOUT
50mV/DIV
(AC)
IL
500mA/DIV
2μs/DIV
3688 F01
where VF is the forward voltage drop of the catch diode
(~0.4V) and VSW is the voltage drop of the internal switch
(~0.3V at maximum load).
Example: ISW=0.8A and VOUT = 3.3V
Figure 1. Operation Below Pulse-Skipping
Voltage. VOUT = 3.3V and fSW = 2.1MHz
3.3V + 0.4V
– 0.4 + 0.3V = 4V
90%
For best performance in dropout, use a 1μF or larger
boost capacitor.
VIN(MIN) =
VOUT
50mV/DIV
(AC)
IL
500mA/DIV
Inductor Selection and Maximum Output Current
2μs/DIV
3688 F02
Figure 2. Operation Above VIN(ps). VIN = 27V,
VOUT = 3.3V and fSW = 2.1MHz. Output Ripple
and Peak Inductor Current Increase
Minimum Operating Voltage Range
The minimum input voltage is determined either by the
LT3688’s minimum operating voltage of ~3.6V or by its
maximum duty cycle. The duty cycle is the fraction of
time that the internal switch is on and is determined by
the input and output voltages:
DC =
VOUT + VF
VIN – VSW + VF
A good first choice for the inductor value is
L = ( VOUT + VF ) •
1.8MHz
fSW
where VF is the voltage drop of the catch diode (~0.4V),
fSW is in MHz, and L is in μH. The inductor’s RMS current
rating must be greater than the maximum load current
and its saturation current should be at least 30% higher.
For robust operation in fault conditions (start-up or shortcircuit) and high input voltage (>30V), use an 8.2μH or
greater inductor with a saturation rating of 2.2A, or higher.
For highest efficiency, the series resistance (DCR) should
be less than 0.1Ω. Table 2 lists several vendors and types
that are suitable.
3688f
14
LT3688
APPLICATIONS INFORMATION
Table 2. Inductor Vendors
VENDOR
Murata
TDK
Toko
Sumida
PART SERIES
TYPE
URL
LQH55D
Open
SLF7045
SLF10145
Shielded
Shielded
www.component.tdk.com
DC62CB
D63CB
D75C
D75F
Shielded
Shielded
Shielded
Open
www.toko.com
CR54
CDRH74
CDRH6D38
CR75
Open
Shielded
Shielded
Open
www.sumida.com
www.murata.com
The optimum inductor for a given application may differ
from the one indicated by this simple design guide. A larger
value inductor provides a higher maximum load current,
and reduces the output voltage ripple. If your load is lower
than the maximum load current, then you can relax the
value of the inductor and operate with higher ripple current.
This allows you to use a physically smaller inductor, or
one with a lower DCR resulting in higher efficiency. Be
aware that if the inductance differs from the simple rule
above, then the maximum load current will depend on
input voltage. In addition, low inductance may result in
discontinuous mode operation, which further reduces
maximum load current. Discontinuous operation occurs
when IOUT is less than ΔIL / 2. For details of maximum
output current and discontinuous mode operation, see
Linear Technology’s Application Note AN44. Finally, for
duty cycles greater than 50% (VOUT/VIN > 0.5), a minimum
inductance is required to avoid sub-harmonic oscillations:
1.2MHz
LMIN = ( VOUT + VF ) •
fSW
where VF is the voltage drop of the catch diode (~0.4V),
fSW is in MHz, and LMIN is in μH.
The current in the inductor is a triangle wave with an average
value equal to the load current. The peak switch current
is equal to the output current plus half the peak-to-peak
inductor ripple current. The LT3688 limits its switch current in order to protect itself and the system from overload
faults. Therefore, the maximum output current that the
LT3688 will deliver depends on the switch current limit,
the inductor value, and the input and output voltages.
When the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. This
gives the peak-to-peak ripple current in the inductor
ΔIL =
(1– DC) ( VOUT + VF )
L•f
where f is the switching frequency of the LT3688 and L is the
value of the inductor. The peak inductor and switch current is
ΔI
ISW(PK) = IL(PK) = IOUT + L
2
To maintain output regulation, this peak current must be
less than the LT3688’s switch current limit ILIM . ILIM is at
least 1.25A for at low duty cycles and decreases linearly
to 0.9A at DC = 0.9. The maximum output current is a
function of the chosen inductor value:
IOUT(MAX) = ILIM –
ΔIL
2
= 1.25A • (1– 0.3DC) –
ΔIL
2
Choosing an inductor value so that the ripple current is
small will allow a maximum output current near the switch
current limit.
One approach to choosing the inductor is to start with the
simple rule given above, look at the available inductors, and
choose one to meet cost or space goals. Then use these
equations to check that the LT3688 will be able to deliver
the required output current. Note again that these equations
assume that the inductor current is continuous.
Input Capacitor
Bypass the input of the LT3688 circuit with a ceramic
capacitor of an X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. A 2.2μF to 4.7μF ceramic capacitor
is adequate to bypass the LT3688 and will easily handle
the ripple current. Note that larger input capacitance
is required when a lower switching frequency is used.
If the input power source has high impedance, or there
is significant inductance due to long wires or cables,
3688f
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LT3688
APPLICATIONS INFORMATION
additional bulk capacitance may be necessary. This can be
provided with a lower performance electrolytic capacitor.
Step-down regulators draw current from the input supply
in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT3688 input and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 2.2μF capacitor is capable of this task, but only if it is
placed close to the LT3688 and the catch diode (see the
PCB Layout section). A second precaution regarding the
ceramic input capacitor concerns the maximum input
voltage rating of the LT3688. A ceramic input capacitor
combined with trace or cable inductance forms a high
quality (under damped) tank circuit. If the LT3688 circuit
is plugged into a live supply, the input voltage can ring to
twice its nominal value, possibly exceeding the LT3688’s
voltage rating. See Linear Technology’s Application Note
88 for details.
High performance electrolytic capacitors can be used for
the output capacitor. Low ESR is important, so choose one
that is intended for use in switching regulators. The ESR
should be specified by the supplier and should be 0.1Ω
or less. Such a capacitor will be larger than a ceramic
capacitor and will have a larger capacitance because the
capacitor must be large to achieve low ESR. Table 3 lists
several capacitor vendors.
Table 3. Capacitor Vendors
VENDOR
PART SERIES
COMMENTS
Panasonic
Ceramic
Polymer
Tantalum
EEEF Series
Kemet
Ceramic
Tantalum
Sanyo
Ceramic
Polymer
Tantalum
Murata
Ceramic
AVX
Ceramic
Tantalum
Taiyo Yuden
Ceramic
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by the
LT3688 to produce the DC output. In this role it determines
the output ripple, and low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3688’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
COUT =
50
VOUT • fSW
where fSW is in MHz and COUT is the recommended output
capacitance in μF. Use X5R or X7R types, which will
provide low output ripple and good transient response.
Transient performance can be improved with a high value
capacitor, but a phase lead capacitor across the feedback
resistor R1 may be required to get the full benefit (see the
Compensation section).
T494, T495
POSCAP
TPS Series
Catch Diode
The catch diode conducts current only during switch-off
time. Average forward current in normal operation can
be calculated from:
ID(AVG) =
IOUT ( VIN – VOUT )
VIN
where IOUT is the output load current. The only reason to
consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition
of shorted output. The diode current will then increase to
the typical peak switch current limit. Peak reverse voltage
is equal to the regulator input voltage. Use a Schottky
diode with a reverse voltage rating greater than the input
voltage. Table 4 lists several Schottky diodes and their
manufacturers.
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LT3688
APPLICATIONS INFORMATION
IAVE
(A)
MBR0520L
20
0.5
MBR0540
40
0.5
620
MBRM120E
20
1
530
MBRM140
40
1
550
B0530W
30
0.5
B120
20
1
500
500
Part Number
VF at 1A
(mV)
On Semiconductor
Diodes Inc.
B130
30
1
B140HB
40
1
DFLS140
40
1.1
510
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT3688 due to their piezoelectric
nature. When in Burst Mode operation, the LT3688’s
switching frequency depends on the load current, and
at very light loads the LT3688 can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since the LT3688 operates at a lower current limit during
Burst Mode operation, the noise is typically very quiet. If
this is unacceptable, use a high performance tantalum or
electrolytic capacitor at the output.
With the recommended output capacitor, the loop crossover occurs above the RCCC zero. This simple model works
well as long as the value of the inductor is not too high
and the loop crossover frequency is much lower than the
switching frequency. With a larger ceramic capacitor (very
low ESR), crossover may be lower and a phase lead capacitor (CPL) across the feedback divider may improve the
phase margin and transient response. At minimum, use a
10pF phase lead capacitor to reduce noise injection to the
FB pin. If the output capacitor is different than the recommended capacitor, stability should be checked across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Figure 4
shows the transient response when the load current is
stepped from 300mA to 600mA and back to 300mA.
LT3688
0.7V
CURRENT MODE
POWER STAGE
–
gm =
OUT
+1.6A/V
FB
+
VR
(V)
–
Table 4. Capacitor Vendors
800mV
R1
CPL
gm =
300μA/V
VC
RC
80k
CC
100pF
3M ERROR
AMPLIFIER
ESR
C1
+
C1
R2
GND
TANTALUM OR CERAMIC
ELECTROLYTIC
3688 F03
Figure 3. Model for the Loop Response
Frequency Compensation
The LT3688 uses current mode control to regulate the
output, which simplifies loop compensation. In particular,
the LT3688 does not require the ESR of the output capacitor for stability, allowing the use of ceramic capacitors to
achieve low output ripple and small circuit size. Figure 3
shows an equivalent circuit for the LT3688 control loop. The
error amp is a transconductance amplifier with finite output
impedance. The power section, consisting of the modulator,
power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to
the voltage at the VC node. Note that the output capacitor,
C1, integrates this current, and that the capacitor on the
VC node (CC) integrates the error amplifier output current,
resulting in two poles in the loop. RC provides a zero.
VOUT
100mV/DIV
ILOAD
200mA/DIV
50μs/DIV
3688 F04
Figure 4. Transient Load Response of the LT3688
Front Page Application as the Load Current is
Stepped from 300mA to 600mA
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LT3688
APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation
To enhance efficiency at light loads, the LT3688 operates
in low ripple Burst Mode operation that keeps the output
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode operation, the LT3688 delivers single cycle bursts of current
to the output capacitor followed by sleep periods where
the output power is delivered to the load by the output
capacitor. Because the LT3688 delivers power to the
output with single, low current pulses, the output ripple
is kept below 25mV for a typical application. In addition,
VIN and BIAS quiescent currents are reduced to typically
65μA and 155μA, respectively, during the sleep time. As
the load current decreases towards a no-load condition,
the percentage of time that the LT3688 operates in sleep
mode increases and the average input current is greatly
reduced, resulting in high efficiency even at very low loads
(see Figure 5). At higher output loads the LT3688 will be
running at the frequency programmed by the RT resistor,
and will be operating in standard PWM mode. The transition between PWM and low ripple Burst Mode operation
is seamless, and will not disturb the output voltage. The
front page application circuit will switch at full frequency
at output loads higher than about 60mA.
three ways to arrange the boost circuit. The BST pin must
be more than 2.3V above the SW pin for best efficiency.
For outputs of 3V and above, the standard circuit (Figure
6a) is best. For outputs between 2.8V and 3V, use a 1μF
boost capacitor. A 2.5V output presents a special case
because it is marginally adequate to support the boosted
drive stage while using the internal boost diode. For reliable
BST pin operation with 2.5V outputs, use a good external
Schottky diode (such as the ON semi MBR0540), and a
1μF boost capacitor (see Figure 6b). For lower output
voltages, the boost diode can be tied to the input (Figure
6c), or to another supply greater than 2.8V. The circuit in
Figure 6a is more efficient because the BST pin current
and BIAS pin quiescent current comes from a lower voltVOUT
BIAS
BST
VIN
VIN LT3688
C3
SW
4.7μF
GND
(6a) For VOUT > 2.8V
VOUT
D2
BIAS
BST
IL
0.2A/DIV
VIN
VSW
5V/DIV
4.7μF
VIN LT3688
GND
C3
SW
VOUT
10mV/DIV
(6b) For 2.5V < VOUT < 2.8V
5μs/DIV
3688 F05
VOUT
Figure 5. Burst Mode Operation
BIAS
BST
VIN
VIN LT3688
C3
BST and BIAS Pin Considerations
Capacitor C3 and the internal boost Schottky diodes (see
the Block Diagram) are used to generate boost voltages
that are higher than the input voltage. In most cases, a
0.22μF capacitor will work well. For the best performance
in dropout, use a 1μF or larger capacitor. Figure 6 shows
4.7μF
GND
SW
3688 F06
(6c) For VOUT < 2.5V; VIN(MAX) = 30V
Figure 6. Three Circuits for Generating the Boost Voltage
3688f
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LT3688
APPLICATIONS INFORMATION
age source. However, the full benefit of the BIAS pin is not
realized unless it is at least 3V. Ensure that the maximum
voltage ratings of the BST and BIAS pins are not exceeded.
There is one particular issue to note if sequencing is
used. If the BIAS pin is tied to VOUT2, it will be low during
the startup of VOUT1. This will prevent the boost circuit
from working on VOUT1 until it has risen to 90% of its
programmed value, increasing the required startup voltage. Using circuit in Figure 6b for VOUT1 will reduce the
startup voltage to its normal value. An alternative is to tie
BIAS to VOUT1, if it is greater than 2.8V.
Soft-Start and Individual Channel Shutdown
The RUN/SS (Run/Soft-Start) pins are used to place the
individual switching regulators in shutdown mode. They
also provide a soft-start function. To shut down either
VOUT = 5V
TO START
INPUT VOLTAGE (V)
7
6.5
6
TO RUN
5.5
5
4.5
4
1
10
100
1000
LOAD (mA)
3688 F07a
7.0
VOUT = 3.3V
6.5
6.0
INPUT VOLTAGE (V)
The minimum operating voltage of an LT3688 application
is limited by the minimum input voltage (3.6V) and by the
maximum duty cycle, as outlined in a previous section. For
proper start-up, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3688 is turned on with its EN/UVLO pin when the
output is already in regulation, then the boost capacitor may
not be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages, and on the arrangement of the boost
circuit. The minimum load generally goes to zero once the
circuit has started. Figure 7 shows a plot of minimum load
to start and to run as a function of input voltage. In many
cases, the discharged output capacitor will present a load
to the switcher, which will allow it to start. The plots show
the worst-case situation where VIN is ramping very slowly.
For lower start-up voltage, the boost diode can be tied to
VIN ; however, this restricts the input range to one-half of the
absolute maximum rating of the BST pin. At light loads, the
inductor current becomes discontinuous and the effective
duty cycle can be very high. This reduces the minimum input
voltage to approximately 300mV above VOUT. At higher load
currents, the inductor current is continuous and the duty
cycle is limited by the maximum duty cycle of the LT3688,
requiring a higher input voltage to maintain regulation.
8
7.5
TO START
5.5
5.0
4.5
4.0
TO RUN
3.5
3.0
1
10
100
1000
LOAD (mA)
3688 F07b
Figure 7. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
regulator, pull the RUN/SS pin to ground with an opendrain or collector. Note that if CONFIG is tied high or low
(not open), shutting down Channel 1 will also shut down
Channel 2 because of the sequencing function (See the
Configuration and Sequencing section for more details).
2.5μA current sources pull up on each pin. If the RUN/SS
pin reaches ~0.2V, the channel will begin to switch
If a capacitor is tied from the RUN/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This voltage clamps the VC pin, limiting the peak
switch current and therefore input current during start up.
A good value for the soft-start capacitor is COUT/10,000,
where COUT is the value of the output capacitor.
The RUN/SS pins can be left floating if the Soft-Start feature
is not used. They can also be tied together with a single
capacitor providing soft-start. The internal current sources
3688f
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LT3688
APPLICATIONS INFORMATION
will charge these pins to ~2V. The RUN/SS pins provide
a soft-start function that limits peak input current to the
circuit during start-up. This helps to avoid drawing more
current than the input source can supply or glitching the
input supply when the LT3688 is enabled. The RUN/SS pins
do not provide an accurate delay to start or an accurately
controlled ramp at the output voltage, both of which depend
on the output capacitance and the load current.
Synchronization
Synchronizing the LT3688 oscillator to an external frequency can be done by connecting a square wave (with
positive and negative pulse width > 150ns) to the SYNC
pin. The square wave amplitude should have valleys that
are below 0.4V and peaks that are above 1.3V (up to 6V).
The LT3688 may be synchronized over a 350kHz to 2.5MHz
range. The RT resistor should be chosen to set the LT3688
switching frequency 20% below the lowest synchronization
input. For example, if the synchronization signal will be
350kHz and higher, RT should be chosen for 280kHz. To
assure reliable and safe operation, the LT3688 will only
synchronize when the output voltage is above 90% of its
regulated voltage. It is therefore necessary to choose a
large enough inductor value to supply the required output
current at the frequency set by the RT resistor (see the
Inductor Selection section). It is also important to note
that the slope compensation is set by the RT value. When
the sync frequency is much higher than the one set by
RT, the slope compensation will be significantly reduced,
which may require a larger inductor value to prevent
subharmonic oscillation.
Shutdown and Undervoltage Lockout
Figure 8 shows how to add undervoltage lockout (UVLO)
to the LT3688. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions.
UVLO prevents the regulator from operating at source
voltages where the problems might occur. An internal
comparator will force the part into shutdown below the
minimum VIN of 3.5V. This feature can be used to prevent
excessive discharge of battery-operated systems. If an
adjustable UVLO threshold is required, the EN/UVLO pin
can be used. The threshold voltage of the EN/UVLO pin
comparator is 1.25V. Current hysteresis is added above the
EN threshold. This can be used to set voltage hysteresis
of the UVLO using the following:
R3 =
VH – VL
3.7μA
R4 =
R3 • 1.25V
VH – 1.25V – R3 • 0.3μA
Example: switching should not start until the input is above
4.40V, and is to stop if the input falls below 4V.
VH = 4.40V, VL = 4V
R3 =
4.40V – 4V
= 107k
3.7μA
R4 =
107k • 1.25V
= 43.2k
4.40V – 1.25V – 107k • 0.3μA
LT3688
VIN
1.25V
–
VC
R3
EN/UVLO
C1
+
RUN/SS
R4
0.3μA
3.7μA
3688 F08
Figure 8. Undervoltage Lockout
Keep the connection from the resistor to the EN/UVLO pin
short and make sure the interplane or surface capacitance
to switching nodes is minimized. If high resistor values
are used, the EN/UVLO pin should be bypassed with a
1nF capacitor to prevent coupling problems from the
switch node.
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LT3688
APPLICATIONS INFORMATION
Output Voltage Monitoring
The LT3688 provides power supply monitoring for
microprocessor-based systems. The features include
power-on reset (POR) and watchdog timing.
A precise internal voltage reference and glitch immune
precision POR comparator circuits monitor the LT3688
output voltages. Each channel’s output voltage must be
above 90% of the programmed value for RST not to be
asserted (refer to the Timing Diagram). The LT3688 will
assert RST during power-up, power-down and brownout
conditions. Once the output voltage rises above the RST
threshold, the adjustable reset timer is started and RST is
released after the reset timeout period. On power-down,
once the output voltage drops below RST threshold, RST
is held at a logic low. The reset timer is adjustable using
external capacitors. This capability helps hold the microprocessor in a stable shutdown condition. The RST pin
has weak pull-up to the BIAS pin.
The above discussion is concerned only with the DC
value of the monitored supply. Real supplies also have
relatively high-frequency variation, from sources such as
load transients, noise, and pickup. These variations should
not be considered by the monitor in determining whether
a supply voltage is valid or not. The variations may cause
spurious outputs at RST, particularly if the supply voltage
is near its trip threshold.
Two techniques are used to combat spurious reset without
sacrificing threshold accuracy. First, the timeout period
helps prevent high-frequency variation whose frequency is
above 1/ tRST from appearing at the RST output. When the
voltage at FB goes below the threshold, the RST pin asserts
low. When the supply recovers past the threshold, the reset
timer starts (assuming it is not disabled), and RST does not
go high until it finishes. If the supply becomes invalid any
time during the timeout period, the timer resets and starts
fresh when the supply next becomes valid. While the reset
timeout is useful for preventing toggling of the reset output
in most cases, it is not effective at preventing nuisance
resets due to short glitches (due to load transients or other
effects) on a valid supply. To reduce sensitivity to these
short glitches, the comparator has additional anti-glitch
circuitry. Any transient at the input of the comparator needs
to be of sufficient magnitude and duration (tUV) before it
can change the monitor state. The combination of the reset
timeout and anti-glitch circuitry prevents spurious changes
in output state without sacrificing threshold accuracy.
Watchdog Timer
The LT3688 includes an adjustable watchdog timer that
monitors a μP’s activity. If a code execution error occurs
in a μP, the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a μP.
The watchdog circuitry is triggered by negative edges on
the WDI pin. The window mode restricts the WDI pin’s
negative going pulses to appear inside a programmed
time window (see the Timing Diagram) to prevent WDO
from going low. If more than two pulses are registered
in the window’s fast period, the WDO is forced to go low.
The WDO also goes low if no negative edge is supplied
to the WDI pin in the window’s slow timer period. During
a code execution error, the microprocessor will output
WDI pulses that would be either too fast or too slow. This
condition will assert WDO and force the microprocessor
to reset the program. In window mode, the WDI signal
frequency is bounded by an upper and lower limit for
normal operation. The WDI input frequency period should
be higher than the window mode’s fast period and lower
than the window mode’s slow period to keep WDO high
under normal conditions. The window mode’s fast and slow
times have a fixed ratio of 16 between them. These times
can be increased or decreased by adjusting an external
capacitor on the CWDT pin.
When WDO is asserted, a timer is enabled for a time
equivalent to 1/8th of the watchdog window upper
boundary. Any WDI pulses that appear while the reset
timer is running are ignored. When the timer expires, the
WDO is allowed to go high again. Therefore, if no input
is applied to the WDI pin, then the watchdog circuitry
produces a train of pulses on the WDO pin. The high
time of this pulse train is equal to the watchdog window
upper boundary, and low time is equal to the 1/8th of the
watchdog window upper boundary.
3688f
21
LT3688
APPLICATIONS INFORMATION
If WDO is low and RST goes low, then WDO will go
high. The WDE pin allows the user to turn on and off the
watchdog function. Leaving this pin open is okay and
will automatically enable the watchdog. It has an internal
weak pull-down to ground. The WDI pin has an internal
weak pull-up that keeps the WDI pin high. If watchdog is
disabled, leaving this pin open is acceptable.
VOUT1 (10V/DIV)
VOUT2 (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
Configuration and Sequencing
10ms/DIV
Use the CONFIG pin to adjust the sequencing and the
behavior of the power-on reset and watchdog timers. The
table below shows all of the configuration options.
Channel 1 starts before Channel 2
CONFIG
RST1 (5V/DIV)
HIGH LOW OPEN
RST2 (5V/DIV)
×
×
WDO (5V/DIV)
Channel 1 and Channel 2 start simultaneously
×
Watchdog operates only if Reset 1 Expires
×
Watchdog operates only if Reset 1 and Reset
2 Expire
×
×
WDI (10V/DIV)
×
10ms/DIV
×
RST1 and RST2 high only if Timer 1 Expires
RST1 and RST2 use independent timers
Figure 9a. CONFIG = HIGH
VOUT1 (10V/DIV)
VOUT2 (10V/DIV)
Table 5. Configuration Options
CONDITION
3688 F09a
3688 F09b
Figure 9b. CONFIG = LOW
×
With the CONFIG pin tied high, VOUT1 will rise first, as
shown in Figure 9a. After VOUT1 reaches VUV, VOUT2 will
start increasing. In addition, the reset timer for Channel 1
starts. Once VOUT2 reaches VUV, the reset timer for Channel 2
starts. Once the reset timers for both Channel 1 and Channel
2 have expired, the Watchdog will start operation.
With the CONFIG pin tied low, VOUT1 will rise first. After
VOUT1 reaches VUV, VOUT2 will start increasing. The reset
timer will only start if both VOUT1 and VOUT2 are above VUV,
as shown in Figure 9b. Once the reset timer programmed
by CPOR1 expires, both RST1 and RST2 can pull high,
and the Watchdog will start operation. In this mode, tie
CPOR2 to GND.
With the CONFIG pin open, VOUT1 and VOUT2 can rise
simultaneously, as shown in figure 9c. After VOUT1 reaches
VUV the reset timer for Channel 1 starts. Once VOUT2
reaches VUV, the reset timer for Channel 2 starts. Once
the reset timer for Channel 1 has expired, the Watchdog
will start operation.
VOUT1 (10V/DIV)
VOUT2 (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
10ms/DIV
3688 F09c
Figure 9c. CONFIG = OPEN
Figure 9. Startup Waveforms with the
Three Configuration Settings
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
The reset timeout period, tRST, is adjusted by connecting
a capacitor, CPOR, between the CPOR pin and ground. The
value of this capacitor is determined by:
3688f
22
LT3688
APPLICATIONS INFORMATION
⎛ pF ⎞
CPOR = t RST • 200 ⎜ ⎟
⎝ ms ⎠
This equation is accurate for reset timeout periods of 1ms,
or greater. To program faster timeout periods, see the
Reset Timeout Period vs Capacitance graph in the Typical
Characteristics section. Leaving the CPOR pin unconnected
will generate a minimum reset timeout of approximately
65μs. Maximum reset timeout is limited by the largest
available low leakage capacitor. The accuracy of the
timeout period will be affected by capacitor leakage (the
nominal charging current is 2.5μA), capacitor tolerance
and temperature coefficient. A low leakage, low tempco,
capacitor is recommended.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog window
upper boundary, tWDU is adjusted by connecting a capacitor,
CWDT, between the CWDT pin and ground. Given a specified
watchdog timeout period, the capacitor is determined by:
⎛ pF ⎞
CWDT = t WDU • 50 ⎜ ⎟
⎝ ms ⎠
The window lower boundary (tWDL) and the watchdog
timeout (tWDTO) have a fixed relationship to tWDU for a
given capacitor. The window lower boundary is related to
tWDU by the following:
1
t WDL =
• t WDU
16
The watchdog timeout is related to tWDU by the following:
1
tWDTO = •tWDU
8
Leaving the CWDT pin unconnected will generate a minimum
watchdog window upper boundary of approximately 200μs.
Maximum window upper boundary is limited by the largest
available low leakage capacitor. The timing accuracy of the
reset and watchdog signals depends on the initial accuracy
and stability of the programing capacitors. Use capacitors
with specified accuracy, leakage and voltage and temperature
coefficients. For surface mount ceramic capacitors C0G and
NP0 types are superior to alternatives such as X5R and X7R.
Shorted and Reversed Input Protection
If an inductor is chosen to prevent excessive saturation, the
LT3688 will tolerate a shorted output. When operating in
short-circuit condition, the LT3688 will reduce its frequency
until the valley current is at a typical value of 1.2A (see Figure
12). There is another situation to consider in systems where
the output will be held high when the input to the LT3688 is
absent. This may occur in battery charging applications or
in battery backup systems where a battery or some other
supply is diode ORed with the LT3688’s output. If the VIN
pin is allowed to float and the EN/UVLO pin is held high
(either by a logic signal or because it is tied to VIN), then
the LT3688’s internal circuitry will pull its quiescent current
through its SW pin. This is fine if the system can tolerate a
few mA in this state. If the EN/UVLO pin is grounded, the
SW pin current will drop to essentially zero.
However, if the VIN pin is grounded while the output is
held high, then parasitic diodes inside the LT3688 can
pull large currents from the output through the SW pin
and the VIN pin. Figure 13 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
VSW
10V/DIV
IL
500mA/DIV
5μs/DIV
3688 F12
Figure 12. The LT3688 Reduces Its Frequency to Below
70kHz to Protect Against Shorted Output with 36V Input
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 14 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT3688’s VIN, DA and SW pins, the catch diode
(D1) and the input capacitor (C1). The loop formed by
3688f
23
LT3688
APPLICATIONS INFORMATION
D4
VIN
VIN
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3688 to additional ground planes within the circuit
board and on the bottom side.
BIAS
BOOST
LTC3688
VOUT
SW
DA
EN/UVLO
GND
FB
+
High Temperature Considerations
3688 F13
Figure 13. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output; It Also Protects the Circuit
from a Reversed Input. The LT3688 Runs Only When the Input
Is Present
3688 F14
Figure 14. Top Layer PCB Layout in the LT3688
Demonstration Board
these components should be as small as possible. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board.
Place a local, unbroken ground plane below these components. The SW and BST nodes should be as small as
possible. Finally, keep the FB node small so that the ground
traces will shield them from the SW and BST nodes.
The exposed pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
The PCB must provide heat sinking to keep the LT3688
cool. The exposed pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3688. Placing
additional vias can reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
to ambient can be reduced to θJA = 40°C/W or less. With
100 LFPM airflow, this resistance can fall by another 25%.
Further increases in airflow will lead to lower thermal resistance. Because of the large output current capability of
the LT3688, it is possible to dissipate enough heat to raise
the junction temperature beyond the absolute maximum
of 125°C (150°C for H Grade). When operating at high
ambient temperatures, the maximum load current should
be derated as the ambient temperature approaches 125°C
(150°C for H Grade). Power dissipation within the LT3688
can be estimated by calculating the total power loss from
an efficiency measurement and subtracting the catch diode
loss. The die temperature is calculated by multiplying the
LT3688 power dissipation by the thermal resistance from
junction-to-ambient. Thermal resistance depends on the
layout of the circuit board, but values from 30°C/W to
60°C/W are typical. Die temperature rise was measured
on a 4-layer, 5cm • 7.5cm circuit board in still air at a load
current of 0.8A (fSW = 800kHz). For a 12V input to 3.3V
output the die temperature elevation above ambient was
14°C; for 12VIN to 5VOUT the rise was 15°C and for 12VIN
to 5VOUT and 3.3VOUT the rise was 30°C.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
3688f
24
LT3688
TYPICAL APPLICATIONS
VIN
6V TO 36V
C1
4.7μF
ON OFF
L1
18μH
VOUT1
5V
800mA
C2
0.22μF
R1
523k
C6
10pF
C4
22μF
VIN
EN/UVLO
BST1
BIAS
BST2
SW1
SW2
LT3688
D1
DA2
FB2
CONFIG
CWDT
CPOR1
CPOR2
RT
SYNC
WDE
I/O
I/O
RESET
WDI
WDO
RST1
RST2
C9
1nF
C7
10pF
VOUT2
3.3V
800mA
C5
22μF
R4
100k
RUN/SS2
RUN/SS1
μP
R3
316k
D2
DA1
FB1
C8
1nF
R2
100k
L2
12μH
C3
0.22μF
GND
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
C10
4.7nF
R5
110k
C12
1nF
C11
4.7nF
3688 TA02
fSW = 500kHz
5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
VIN
8V TO 36V
C1
4.7μF
R6
475k
VIN
EN/UVLO
R7
100k L1
10μH
VOUT
1.8V
800mA
C6
10pF
C4
47μF
C2
0.22μF
C8
1nF
R2
150k
BIAS
BST1
BST2
SW1
SW2
DA1
FB1
WDI
WDO
RST1
RST2
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
C7
10pF
R3
316k
C9
1nF
VOUT2
3.3V
800mA
C5
22μF
R4
100k
RUN/SS2
WDE
I/O
I/O
RESET
L2
12μH
D2
DA2
FB2
RUN/SS1
μP
C3
0.22μF
LT3688
D1
R1
187k
CONFIG
GND
CWDT
CPOR1
CPOR2
RT
SYNC
C10
4.7nF
R5
110k
C11
4.7nF
C12
1nF
3688 TA02
fSW = 500kHz
3.3V and 1.8V Regulator with Power-On Reset and Watchdog Timers
and Input Under Voltage Lockout
3688f
25
LT3688
TYPICAL APPLICATIONS
VIN
6V TO 36V
C1
4.7μF
ON OFF
L1
8.2μH
VOUT1
5V
800mA
C6
10μF
C4
10μF
C2
0.1μF
VIN
EN/UVLO
BST1
BIAS
BST2
SW1
SW2
LT3688
D1
R1
523k
CONFIG
WDE
I/O
I/O
RESET
WDI
WDO
RST1
RST2
C9
1nF
C7
10pF
VOUT2
3.3V
800mA
C5
22μF
R4
100k
RUN/SS2
RUN/SS1
μP
R3
316k
D2
DA2
FB2
DA1
FB1
C8
1nF
R2
100k
L2
8.2μH
C3
0.1μF
GND
CWDT
CPOR1
CPOR2
RT
SYNC
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
C10
4.7nF
R5
20k
C12
1nF
C11
4.7nF
3688 TA04
fSW = 2MHz: 8V < VIN < 16V, TJ < 85°C
2MHz Switching Frequency, 5V and 3.3V Regulator with
Power-On Reset and Watchdog Timers
VIN
4V TO 36V
C1
4.7μF
ON OFF
L1
8.2μH
VOUT1
1.2V
800mA
C6
10pF
C4
100μF
C2
0.22μF
EN/UVLO
BST1
BIAS
BST2
SW1
SW2
C8
1nF
I/O
CONFIG
RESET
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
R3
316k
C9
1nF
C7
10pF
VOUT2
3.3V
800mA
C5
22μF
R4
100k
RUN/SS2
WDE
WDI
WDO
RST1
RST2
L2
15μH
D2
DA2
FB2
DA1
FB1
RUN/SS1
WATCHDOG DEFEAT
μP
C3
0.22μF
LT3688
D1
R1
90.9k
R2
182k
VIN
GND
CWDT
CPOR1
CPOR2
RT
SYNC
C10
4.7nF
R5
143k
C11
4.7nF
C12
1nF
3688 TA05
fSW = 400kHz: VIN < 25V
3.3V and 1.2V Regulator with Power-On Reset Timer and
Defeatable Watchdog, Timing Error Resets Microprocessor
3688f
26
LT3688
PACKAGE DESCRIPTION
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev Ø)
Variation AA
7.70 – 7.90*
(.303 – .311)
3.25
(.128)
3.25
(.128)
24 23 22 21 20 19 18 17 16 15 14 13
6.60 p0.10
2.74
(.108)
4.50 p0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 p0.05
1.05 p0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
1.20
(.047)
MAX
0o – 8o
0.65
(.0256)
BSC
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE24 (AA) TSSOP 0208 REV Ø
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
4.00 ± 0.10
(4 SIDES)
0.70 ±0.05
0.75 ± 0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
2.45 ± 0.10
(4-SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
(UF24) QFN 0105
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3688f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3688
TYPICAL APPLICATION
VIN
6V TO 36V
C1
4.7μF
ON OFF
L1
18μH
VOUT1
5V
800mA
C6
10pF
C4
22μF
C2
0.22μF
R1
523k
VIN
EN/UVLO
BST1
BIAS
BST2
SW1
SW2
LT3688
D1
C8
1nF
R2
100k
DA2
FB2
CONFIG
WDI
WDO
RST1
RST2
R3
340k
C9
1nF
R4
100k
C7
10pF
VOUT2
3.3V
800mA
C5
22μF
RUN/SS2
WDE
I/O
I/O
RESET
L2
12μH
D2
DA1
FB1
RUN/SS1
μP
C3
0.22μF
GND
CWDT
CPOR1
CPOR2
RT
SYNC
C1-C5: X5R OR X7R
D1, D2: DFLS140
C10
4.7nF
R5
49.9k
C11
4.7nF
C12
1nF
3688 TA06
fSW = 1MHz: 7V < VIN < 21V
1MHz 5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3640
35V, 55V MAX, Dual (1.3A, 1.1A), 2.5MHz High Efficiency StepDown DC/DC Converter with POR Reset and Watchdog Timer
VIN Min = 4V, VIN Max = 35V, Transient to 55V, VOUT(MIN) = 0.6V,
IQ =
