LT3689/LT3689-5
700mA Step-Down
Regulator with Power-On Reset
and Watchdog Timer
DESCRIPTION
FEATURES
Wide Input Range:
Operation from 3.6V to 36V
Overvoltage Lockout Protects Circuits through
60V Transients
n 85µA I at 12V to 3.3V
Q
IN
OUT
n Low Ripple Burst Mode® Operation Allows Output
Ripple 38V (typical),
the LT3689 will stop switching, allowing the output to fall
out of regulation.
DCMIN = tON(MIN) • fSW
where tON(MIN) is equal to 130ns (for TJ > 125°C tON(MIN)
is equal to 150ns) and fSW is the switching frequency.
Running at a lower switching frequency allows a lower
minimum duty cycle. The maximum input voltage before
pulse-skipping occurs depends on the output voltage and
the minimum duty cycle:
VIN(PS) =
VOUT + VD
– VD + VSW
DCMIN
Minimum Operating Voltage Range
The minimum input voltage is determined either by the
LT3689’s minimum operating voltage of ~3.4V or by its
maximum duty cycle. The duty cycle is the fraction of
time that the internal switch is on and is determined by
the input and output voltages:
DC =
Example: fSW = 790kHz, VOUT = 3.3V,
DCMIN = 130ns • 790kHz = 0.103
VIN(PS) =
with an output voltage of 1.8V and switching frequency
of 1.5MHz has a VIN(PS) of 11.3V, as shown in Figure 1.
Figure 2 shows operation at 24V. Output ripple and peak
inductor current have significantly increased. A saturating
inductor may further reduce performance. For input voltages over 30V, there are restrictions on the inductor size
and saturation rating. See the Inductor Selection section
for more details. In pulse-skipping mode, the LT3689 skips
switching pulses to maintain output regulation. Above 38V
(typical) switching will stop. Transients of up to 60V are
acceptable, regardless of switching frequency.
3.3V + 0.4V
– 0.4V + 0.4V = 36V
0.103
The LT3689 will regulate the output current at input voltages greater than VIN(PS). For example, an application
VOUT + VD
VIN – VSW + VD
Unlike many fixed frequency regulators, the LT3689 can
extend its duty cycle by remaining on for multiple cycles.
The LT3689 will not switch off at the end of each clock cycle
if there is sufficient voltage across the boost capacitor (C3
in the Block Diagram). Eventually, the voltage on the boost
capacitor falls and requires refreshing. Circuitry detects
VOUT
50mV/DIV
(AC)
VOUT
50mV/DIV
(AC)
IL
0.5A/DIV
IL
0.5A/DIV
5µs/DIV
3689 F01
Figure 1. Operation Below VIN(PS). VIN = 10V,
VOUT = 1.8V and fSW = 1.5MHz
5µs/DIV
3689 F02
Figure 2. Operation Above VIN(PS). VIN = 24V,
VOUT = 1.8V and fSW = 1.5MHz. Output Ripple
and Peak Inductor Current Increase
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this condition and forces the switch to turn off, allowing
the inductor current to charge up the boost capacitor.
This places a limitation on the maximum duty cycle. The
maximum duty cycle that the LT3689 can sustain is 90%.
From this DCMAX number, the minimum operating voltage
can be calculated using the following equation:
VOUT + VD
− VD + VSW
0.90
Example: VOUT = 3.3V
VIN(MIN) =
VIN(MIN) =
3.3V + 0.4V
– 0.4V + 0.4V = 4.1V
0.90
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
L = (VOUT + VF ) •
2.2MHz
fSW
where VF is the voltage drop of the catch diode (~0.4V),
fSW is the switching frequency in MHz, and L is in µH. The
inductor’s RMS current rating must be greater than the
maximum load current and its saturation current should
be at least 30% higher. For robust operation in fault conditions (start-up or short-circuit) and high input voltage
(>30V), use an 8.2µH or greater inductor (for TJ > 125°C,
use 10µH or larger) with a saturation rating of 2.5A, or
higher. To keep the efficiency high, the series resistance
(DCR) should be less than 0.15Ω and the core material should be intended for high frequency applications.
Table 2 lists several vendors and suitable types.
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-topeak inductor ripple current. The LT3689 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3689 will deliver depends on the switch current
limit, the inductor value, and the input and output voltages. Also, if the inductor current’s bottom peak exceeds
the DA current limit (ILIM(DA)) at high output currents
then the DA current comparator will regulate the bottom
peak to ILIM(DA). This will result in higher inductor ripple
current and will further limit the max output current. The
DA current limit consists of a DC and an AC component.
The nominal DC component is fixed at 1.2A. The AC
component depends on the output voltage, inductor size
and a fixed time delay between the DA comparator turning off and switch turning on. Therefore, the DA current
limit ILIM(DA) will increase as the output voltage collapses
under overload conditions.
ILIM(DA) = 1.2A −
( VOUT + VD ) • 0.25µs
L
Table 2. Inductor Vendors
VENDOR
URL
Sumida
www.sumida.com
Toko
www.toko.com
Würth Elektronik
www.we-online.com
PART SERIES
INDUCTANCE RANGE
(µH)
SIZE
(mm)
CDRH4D28
CDRH5D28
1.2 to 4.7
2.5 to 10
4.5 × 4.5
5.5 × 5.5
A916CY
D585LC
2 to 12
1.1 to 39
6.3 × 6.2
8.1 × 8
WE-TPC(M)
WE-PD2(M)
1 to 10
2.2 to 22
4.8 × 4.8
5.2 × 5.8
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Choose an inductor using the previous inductor selection
equation to guarantee 700mA of output current. If using
a smaller inductor, check the DA current limit equation to
verify that the DA circuitry will not lower the switching
frequency.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
∆IL =
(1− DC)(VOUT + VD )
L • fSW
where fSW is the switching frequency of the LT3689 and L
is the value of the inductor. The peak inductor and switch
current is:
load is lower than 0.7A, decrease the value of the inductor
and operate with a higher ripple current. This allows the
use of a physically smaller inductor, or one with a lower
DCR resulting in higher efficiency. There are graphs in
the Typical Performance Characteristics section of this
data sheet that show the maximum load current as a
function of input voltage for several popular output voltages. Low inductance may result in discontinuous mode
operation, which is okay but further reduces maximum
load current. For details of maximum output current and
discontinuous mode operation, see Linear Technology
Application Note 44. Finally, for duty cycles greater than
50% (VOUT / VIN > 0.5), a minimum inductance is required
to avoid subharmonic oscillations:
L MIN =
(
1.4 VOUT + VD
∆I
ISW(PK) = IL(PK) = IOUT + L
2
To maintain output regulation, this peak current must be
less than the LT3689’s switch current limit ILIM. ILIM is at
least 1.5A for at low duty cycles and decreases linearly
to 0.87A at DC = 85%. The maximum output current is a
function of the chosen inductor value.
Input Capacitor
IOUT(MAX) = ILIM −
∆IL
2
∆IL
2
Choosing an inductor value so that the ripple current is
small will allow a maximum output current near the switch
current limit.
= 1.15A • (1− 0.28 • DC) −
One approach to choosing the inductor is to start with the
preceding simple rule, determine the available inductors,
and choose one to meet cost or space goals. Next, use
these equations to check that the LT3689 will be able to
deliver the required output current. Note again that these
equations assume that the inductor current is continuous. Discontinuous operation occurs when IOUT is less
than ∆IL /2.
Of course, such a simple design guide will not always
result in the optimum inductor for the application. A larger
value inductor provides a slightly higher maximum load
current and will reduce the output voltage ripple. If the
where LMIN
is in MHz.
)
fSW
is in µH, VOUT and VD are in volts, and fSW
Bypass the input of the LT3689 circuit with a ceramic
capacitor of an X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. The minimum value of input capacitance depends on the switching frequency. Use an input
capacitor of 1µF or more for switching frequencies between 1MHz to 2.2MHz, and 2.2µF or more for frequencies lower than 1MHz. If the input power source has high
impedance, or there is significant inductance due to long
wires or cables, additional bulk capacitance may be necessary. This can be provided with a lower performance
electrolytic capacitor. Step-down regulators draw current
from the input supply in pulses with very fast rise and
fall times. The input capacitor is required to reduce the
resulting voltage ripple at the LT3689 input and to force
this very high frequency switching current into a tight local
loop, minimizing EMI. A ceramic capacitor is capable of
this task, but only if it is placed close to the LT3689 and
the catch diode (see the PCB Layout section). A second
precaution regarding the ceramic input capacitor concerns
the maximum input voltage rating of the LT3689. A ceramic
input capacitor combined with trace or cable inductance
forms a high quality (under damped) tank circuit. If the
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LT3689 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding
the LT3689’s voltage rating. For a complete discussion,
see Linear Technology’s Application Note 88.
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by the
LT3689 to produce the DC output. In this role it determines
the output ripple, and low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3689’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
COUT =
50
VOUT fSW
where fSW is in MHz, and COUT is the recommended output capacitance in µF. Use X5R or X7R types, which will
provide low output ripple and good transient response.
Transient performance can be improved with a high value
capacitor, but a phase lead capacitor across the feedback
resistor R1 may be required to get the full benefit (see the
Frequency Compensation section).
High performance electrolytic capacitors can be used for
the output capacitor. Low ESR is important, so choose one
that is intended for use in switching regulators. The ESR
should be specified by the supplier and should be 0.1Ω
or less. Such a capacitor will be larger than a ceramic
capacitor and will have a larger capacitance because the
capacitor must be large to achieve low ESR. Table 3 lists
several capacitor vendors.
Table 3. Capacitor Vendors
VENDOR
PHONE
URL
Panasonic
(714) 373-7366
www.panasonic.com
Kemet
(864) 963-6300
www.kemet.com
Sanyo
(408) 749-9714
www.sanyovideo.com
Murata
(408) 436-1300
www.murata.com
(864) 963-6300
www.taiyo-yuden.com
AVX
www.avxcorp.com
Taiyo Yuden
Catch Diode
The catch diode conducts current only during switch-off
time. Average forward current in normal operation can
be calculated from:
ID(AVG) =
IOUT (V IN − VOUT )
V IN
where IOUT is the output load current. The only reason to
consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition
of shorted output. The diode current will then increase to
the typical peak switch current limit. Peak reverse voltage
is equal to the regulator input voltage. Use a Schottky
diode with a reverse voltage rating greater than the input
voltage. The overvoltage protection feature in the LT3689
will keep the switch off when VIN > 38V (typical), which
allows the use of a 40V rated Schottky even when VIN
ranges up to 60V. Table 4 lists several Schottky diodes
and their manufacturers.
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Frequency Compensation
Table 4. Diode Vendors
PART NUMBER
VR
(V)
IAVE
(A)
VF AT IAVE
(mV)
On Semiconductor
MBRM120E
MBRM140
20
40
1
1
530
550
Diodes Inc.
B120
B130
B140
B0540W
B140HB
20
30
40
40
40
1
1
1
0.5
1
500
500
500
510
530
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT3689 due to their piezoelectric
nature. When in Burst Mode operation, the LT3689’s
switching frequency depends on the load current, and at
very light loads the LT3689 can excite the ceramic capacitor at audio frequencies, generating audible noise. Since
the LT3689 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet. If this
noise is unacceptable, use a high performance tantalum
or electrolytic capacitor at the output.
LT3689
0.7V
The LT3689 uses current mode control to regulate the
output, which simplifies loop compensation. In particular,
the LT3689 does not require the ESR of the output capacitor for stability, allowing the use of ceramic capacitors to
achieve low output ripple and small circuit size. Figure 3
shows an equivalent circuit for the LT3689 control loop.
The error amp is a transconductance amplifier with finite
output impedance. The power section, consisting of the
modulator, power switch and inductor, is modeled as a
transconductance amplifier generating an output current
proportional to the voltage at the VC node. Note that the
output capacitor, C1, integrates this current, and that the
capacitor on the VC node (CC) integrates the error amplifier output current, resulting in two poles in the loop. RC
provides a zero. With the recommended output capacitor,
the loop crossover occurs above the RCCC zero. This simple
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. With a larger ceramic
capacitor (very low ESR), crossover may be lower and a
phase lead capacitor (CPL) across the feedback divider may
improve the phase margin and transient response. Large
electrolytic capacitors may have an ESR large enough to
create an additional zero, and the phase lead may not be
necessary.
CURRENT MODE
POWER STAGE
–
gm =
OUT
+1.2A/V
R1
CPL
FB
–
gm =
300µA/V
RC
37k
CC
100pF
ERROR
AMPLIFIER
3M
+
VC
ESR
800mV
+
C1
C1
R2
GND
3689 F03
Figure 3. Model for the Loop Response
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Most applications running at VIN greater than 20V will
require a small phase lead capacitor, ranging from 2pF to
about 30pF, between the FB pin and VOUT for good transient
response. The circuits in the Typical Applications section
use the appropriate phase lead capacitors and are stable
at all input voltages.
If the output capacitor is different than the recommended
capacitor, stability should be checked across all operating
conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough
discussion of loop compensation and describes how to
test the stability using a transient load. Figure 4 shows
the transient response when the load current is stepped
from 360mA to 720mA and back to 360mA.
Low Ripple Burst Mode Operation and Pulse-Skipping
Mode
The LT3689 is capable of operating in either low ripple Burst
Mode operation or pulse-skipping mode, which is selected
using the SYNC pin. See the Synchronization section for
details. To enhance efficiency at light loads, the LT3689
can be operated in low ripple Burst Mode operation that
keeps the output capacitor charged to the proper voltage
while minimizing the input quiescent current. During Burst
Mode operation, the LT3689 delivers single cycle bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. Because the LT3689 delivers power to the
output with single, low current pulses, the output ripple is
kept below 15mV for a typical application. The LT3689-5
has a slightly higher output ripple of 25mV. This higher
ripple can be reduced by using a larger output capacitor.
In addition, VIN and OUT quiescent currents are reduced
to typically 50µA and 75µA, respectively, during the sleep
time. As the load current decreases towards a no-load
condition, the percentage of time that the LT3689 operates
in sleep mode increases and the average input current is
greatly reduced, resulting in high efficiency even at very
low loads (see Figure 5).
At higher output loads (above approximately 60mA at
VIN = 12V for the front page application) the LT3689 will be
running at the frequency programmed by the RT resistor,
and will be operating in standard PWM mode. The transition between PWM and low ripple Burst Mode operation
is seamless, and will not disturb the output voltage. If low
quiescent current is not required, the LT3689 can operate in pulse-skipping mode. The benefit of this mode is
that the LT3689 will enter full frequency standard PWM
operation at a lower output load current than when in
Burst Mode operation. The front page application circuit
will switch at full frequency at output loads higher than
about 15mA at 12VIN.
VOUT
10mV/DIV
VOUT
50mV/DIV
IL
0.2A/DIV
IL
250mA/DIV
VSW
5V/DIV
10µs/DIV
3689 F04
Figure 4. Transient Load Response of the LT3689 Front
Page Application as the Load Current is Stepped from
360mA to 720mA. VOUT = 3.3V, VIN = 12V
5µs/DIV
VIN = 12V, FRONT PAGE APPLICATION
ILOAD = 8mA
3689 F05
Figure 5. Burst Mode Operation
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BST and OUT Pin Considerations
Capacitor C3 and the internal boost Schottky diode (see
the Block Diagram) are used to generate a boost voltage
that is higher than the input voltage. In most cases, a 0.1µF
capacitor will work well. Figure 6 shows three ways to arrange the boost circuit. The BST pin must be more than
2.3V above the SW pin for best efficiency. For outputs of
3V and above, the standard circuit (Figure 6a) is best. For
outputs between 2.8V and 3V, use a 0.47µF boost capacitor. A 2.5V output presents a special case because it is
marginally adequate to support the boosted drive stage
while using the internal boost diode. For reliable BST pin
operation with 2.5V outputs, use a good external Schottky
diode (such as ON Semiconductor’s MBR0540), and a
0.47µF boost capacitor (see Figure 6b). For lower output
voltages, the boost diode can be tied to the input (Figure 6c),
or to another supply greater than 2.8V. The circuit in
Figure 6a is more efficient because the BST pin current
and OUT pin quiescent current comes from a lower
voltage source. Ensure that the maximum voltage ratings
of the BST and OUT pins are not exceeded.
The minimum operating voltage of an LT3689 application
is limited by the minimum input voltage (3.7V) and by the
maximum duty cycle, as outlined in the Minimum Operating
Voltage Range section. For proper start-up, the minimum
input voltage is also limited by the boost circuit. If the input
voltage is ramped slowly, or the LT3689 is turned on with
its EN/UVLO pin when the output is already in regulation,
then the boost capacitor may not be fully charged. Because
the boost capacitor is charged with the energy stored in
the inductor, the circuit will rely on some minimum load
current to get the boost circuit running properly. This
minimum load will depend on input and output voltages,
and on the arrangement of the boost circuit. The minimum
load generally goes to zero once the circuit has started.
For lower start-up voltage, the boost diode can be tied to
VIN ; however, this restricts the input range to one-half of
the absolute maximum rating of the BST pin.
VOUT
VOUT
BST
BST
VIN
VIN
LT3689
VIN
C3
VIN
LT3689
SW
2.2µF
D2
OUT
OUT
GND
GND
2.2µF
(6a) For VOUT > 2.8V
C3
SW
(6b) For 2.5V < VOUT < 2.8V
VOUT
OUT
BST
VIN
2.2µF
VIN
LT3689
GND
C3
SW
3689 F06
(6c) For VOUT < 2.5V; VIN(MAX) = 30V
Figure 6. Three Circuits for Generating the Boost Voltage
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Another way to lower the start-up voltage is by using a
resistor divider on the EN/UVLO pin (see the Shutdown
and Undervoltage Lockout section). A resistor divider on
EN/UVLO pin programs the turn-on threshold to slightly
higher than the minimum VIN voltage required to run at full
load. Below the EN/UVLO high voltage, the part will stay
shut off and the output cap will remain discharged during
the worse case slow VIN ramp. When the EN/UVLO pin
crosses the EN/UVLO high threshold, the part will turn on
and the empty output capacitor will provide enough load
to bring the output voltage in regulation. This technique
significantly lowers the start-up voltage of the circuit. The
plot in Figure 7 depicts the minimum load required to start
and run (as a function of input voltage). It also depicts the
benefit of programming the EN/UVLO threshold to lower
the start-up voltage at low load currents. At light loads, the
inductor current becomes discontinuous and the effective
8.0
duty cycle can be very high. This reduces the minimum input
voltage to approximately 300mV above VOUT. At higher load
currents, the inductor current is continuous and the duty
cycle is limited by the maximum duty cycle of the LT3689,
requiring a higher input voltage to maintain regulation.
Soft-Start
The LT3689 has an internal soft-start that gradually ramps
up the switch current limit from about 100mA to the switch’s
maximum current limit in typical value of 150µs, as shown
in Figure 8. This feature limits the inrush current during
start-up and prevents the switch current from spiking when
the EN/UVLO pin crosses the UVLO threshold. A soft-start
sequence is also initiated right after a VIN overvoltage/
undervoltage lockout, or thermal shutdown fault in order
to prevent the switch current from suddenly jumping to
its maximum current limit.
6.0
TO START:
EN/UVLO TIED TO VIN
7.5
TO START: EN/UVLO HIGH
THRESHOLD = 4.85V
5.0
6.5
VIN (V)
VIN (V)
7.0
TO START: EN/UVLO HIGH
THRESHOLD = 6.15V
4.5
6.0
4.0
5.5
3.5
5.0
TO START:
EN/UVLO TIED TO VIN
5.5
TO RUN
1
10
100
LOAD (mA)
VOUT = 5V
L = 8.2µH
3.0
1000
TO RUN
1
10
100
LOAD (mA)
3589 F07a
fSW = 800KHz
TA = 25°C
1000
3589 F07b
VOUT = 3.3V fSW = 800KHz
L = 8.2µH
TA = 25°C
Figure 7. LT3689 Minimum VIN to Start and Run vs Load
VOUT
2V/DIV
IL
0.5A/DIV
IVIN
0.2A/DIV
VIN = 12V
VOUT = 5V
20µs/DIV
3689 F08
f = 2MHz
CIN = 1µF CERAMIC + 100µF ELECTROLYTIC
Figure 8. Internal Soft-Start
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Synchronization
To select low ripple Burst Mode operation, tie the SYNC pin
below 0.3V (this can be ground or a logic output). Synchronizing the LT3689 oscillator to an external frequency can
be done by connecting a square wave (with positive and
negative pulse width >80ns) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.3V
and peaks that are above 1V (up to 6V).
The LT3689 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will skip pulses to maintain regulation.
The LT3689 may be synchronized over a 350kHz to 2.5MHz
range. The RT resistor should be chosen to set the LT3689
switching frequency 20% below the lowest synchronization
input. For example, if the synchronization signal will be
350kHz and higher, the RT should be chosen for 280kHz.
To assure reliable and safe operation, the LT3689 will only
synchronize when the output voltage is above 90% of its
regulated voltage. It is therefore necessary to choose a
large enough inductor value to supply the required output
current at the frequency set by the RT resistor (see the
Inductor Selection section). It is also important to note
that the slope compensation is set by the RT value. When
the sync frequency is much higher than the one set by
RT, the slope compensation will be significantly reduced,
which may require a larger inductor value to prevent
subharmonic oscillation. The minimum inductor value
should be calculated using the RT programmed frequency
to avoid subharmonic oscillation.
Shutdown and Undervoltage Lockout
Figure 9 shows how to add undervoltage lockout (UVLO)
to the LT3689. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where the problems might occur. An internal comparator
will force the part into shutdown below the minimum VIN
of 3.4V. This feature can be used to prevent excessive
discharge of battery-operated systems. If an adjustable
UVLO threshold is required, the EN/UVLO pin can be used.
The threshold voltage of the EN/UVLO pin comparator is
1.26V. Current hysteresis is added above the EN threshold.
This can be used to set voltage hysteresis of the UVLO
using the following:
R3 =
R4 =
V H VL
4µA
VH
LT3689
VIN
1.25V
R3
C1
EN/UVLO
–
4k
1.26V
1.26V
R3
4µA
VC
+
R4
SS
4µA
3689 F09
Figure 9. Undervoltage Lockout
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Example: switching should not start until the input is above
4.40V, and is to stop if the input falls below 4V.
V H = 4.40V,V L = 4V
R3 =
4.40V − 4V
− 4k = 95.3k
4µA
Characteristics section). This prevents spurious resets
caused by output voltage transients such as load steps
or short brownout conditions without sacrificing the DC
reset threshold accuracy.
Watchdog
1.26V
= 43.2k
R4 =
4.40V −1.26V
– 4µA (Nearest 1% Resistor)
95.3k
Keep the connection from the resistor to the EN/UVLO
pin short and make sure the interplane or surface capacitance to switching nodes is minimized. If high resistor
values are used, the EN/UVLO pin should be bypassed with
a 1nF capacitor to prevent coupling problems from the
switch node.
Output Voltage Monitoring
The LT3689 provides power supply monitoring for microprocessor-based systems. The features include power-on
reset (POR) and watchdog timing.
A precise internal voltage reference and glitch immune
precision POR comparator circuit monitor the LT3689
output voltage. The switcher’s output voltage must be
above 90% of programmed value for RST not to be asserted
(refer to the Timing Diagram). The LT3689 will assert RST
during power-up, power-down and brownout conditions.
Once the output voltage rises above the RST threshold,
the adjustable reset timer is started and RST is released
after the reset timeout period. On power-down, once the
output voltage drops below RST threshold, RST is held
at a logic low. The reset timer is adjustable using external
capacitors. The RST pin has a weak pull-up to the OUT pin.
The POR comparator is designed to be robust against FB
pin noise, which could potentially false trigger the RST pin.
The POR comparator lowpass filters the first stage of the
comparator. This filter integrates the output of the comparator before asserting the RST. The benefit of adding this filter
is that any transients at the buck regulator’s output must
be of sufficient magnitude and duration before it triggers
a logic change in the output (see the Typical Transient vs
POR Comparator Overdrive in the Typical Performance
The LT3689 includes an adjustable watchdog timer that
monitors a µP’s activity. If a code execution error occurs
in a µP, the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a microprocessor.
The watchdog is operated either in timeout or window
mode. In timeout mode, the microprocessor needs to
toggle the WDI pin before the watchdog timer expires, to
keep the WDO pin high. If no WDI pulse (either positive or
negative) appears during the programmed timeout period,
then the circuitry will pull WDO low. During normal operation, the WDI input signal’s high to low, and low to high
transition periods should be set lower than the watchdog’s
programmed time to keep WDO inactive.
In window mode, the watchdog circuitry is triggered by
negative edges on the WDI pin. The window mode restricts
the WDI pin’s negative going pulses to appear inside a
programmed time window (see the Timing Diagram) to
prevent WDO from going low. If more than two pulses are
registered in the watchdog lower boundary period, the WDO
is forced to go low. The WDI edges are ignored while the
CWDT capacitor charges from 0V to 200mV right after a
low to high transition on the WDO or RST pin. The WDO
also goes low if no negative edge is supplied to the WDI
pin in the watchdog upper boundary period. During a code
execution error, the microprocessor will output WDI pulses
that would be either too fast or too slow. This condition
will assert WDO and force the microprocessor to reset the
program. In window mode, the WDI signal frequency is
bounded by an upper and lower limit for normal operation.
The WDI input frequency period should be higher than the
tWDL period, and lower than the tWDU period, to keep WDO
high under normal conditions. The window mode’s tWDL
and tWDU times have a fixed ratio of 31 between them.
These times can be increased or decreased by adjusting
an external capacitor on the CWDT pin.
3689fe
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23
LT3689/LT3689-5
APPLICATIONS INFORMATION
In both watchdog modes, when WDO is asserted, the reset
timer is enabled. Any WDI pulses that appear while the
reset timer is running are ignored. When the reset timer
expires, the WDO is allowed to go high again. Therefore,
if no input is applied to the WDI pin, then the watchdog
circuitry produces a train of pulses on the WDO pin. The
high time of this pulse train is equal to the timeout period,
and low time is equal to the reset period. Also, WDO and
RST cannot be logic low simultaneously. If WDO is low
and RST goes low, then WDO will go high.
The WDE pin allows the user to turn on and off the watchdog function. Do not leave this pin open. Tie it high or
low to turn watchdog off or on, respectively. The W/T pin
enables/disables the window/timeout mode. Leaving this
pin open is fine and will put the watchdog in window mode.
It has a weak pull-down to ground. The WDI pin has an
internal 2µA weak pull-up that keeps the WDI pin high. If
watchdog is disabled, leaving this pin open is acceptable.
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to accommodate a variety of microprocessor applications. The
reset timeout period, (tRST), is adjusted by connecting a
capacitor, CPOR , between the CPOR pin and ground. The
value of this capacitor is determined by:
CPOR = t RST • 432
pF
ms
This equation is accurate for reset timeout periods of
5ms, or greater. To program faster timeout periods, see
the Reset Timeout Period vs Capacitance graph in the
Typical Performance Characteristics section. Leaving the
CPOR pin unconnected will generate a minimum reset
timeout of approximately 25µs. Maximum reset timeout
is limited by the largest available low leakage capacitor.
The accuracy of the timeout period will be affected by
WDI
5V/DIV
VOUT
2V/DIV
CWDT = 10nF, tWDL = 5.8ms
WDO
2V/DIV
RST
2V/DIV
CWDT
1V/DIV
tRST = 165ms
CPOR = 71nF
CPOR
1V/DIV
50ms/DIV
CPOR
1V/DIV
3689 F10
5ms/DIV
Figure 10. Reset Timer Waveforms
WDI
5V/DIV
WDO
2V/DIV
CWDT
1V/DIV
3689 F11
Figure 11. Window Watchdog Waveforms (W/T = Low)
tRST = 165ms, CPOR = 71nF
tWDU = 180ms, CWDT = 10nF
CPOR
1V/DIV
100ms/DIV
3689 F12
Figure 12. Timeout Watchdog Waveforms (W/T = High)
3689fe
24
For more information www.linear.com/LT3689
LT3689/LT3689-5
APPLICATIONS INFORMATION
capacitor leakage (the nominal charging current is 2µA)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog upper
boundary timeout period, tWDU is adjusted by connecting a capacitor, CWDT, between the CWDT pin and ground.
Given a specified watchdog timeout period, the capacitor
is determined by:
C WDT = t WDU • 55
pF
ms
This equation is accurate for upper boundary periods of
20ms, or greater. The watchdog lower boundary period
(tWDL) has a fixed relationship to tWDU for a given capacitor. The tWDL period is related to tWDU by the following:
t WDL =
1
• t WDU
31
In addition, the following equation can be used to calculate
the watchdog lower boundary period for a given CWDT
capacitor value.
C WDT = t WDL •
1.7nF
ms
These lower boundary period equations are accurate for a
tWDL of 3ms, or greater. To program faster tWDU and tWDL
periods, see the Watchdog Upper and Lower Boundary
Periods vs Capacitance graphs in the Typical Performance
Characteristics section.
Leaving the CWDT pin unconnected will generate a minimum
watchdog timeout of approximately 200µs. Maximum
timeout is limited by the largest available low leakage
capacitor. The accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current
is 2µA) and capacitor tolerance. A low leakage ceramic
capacitor is recommended.
Time Charts for the Power-On-Reset and
Watch Dog Timers
The watchdog timer monitors proper operation of the
microprocessor. During the start-up sequence of the microprocessor, there are fixed requirements for the watch
dog input (WDI) in order to keep the WDO pin from flagging a fault.
Requirements for the watch dog input in window mode
(W/T = Low) are best understood by looking at Figure 13.
In window mode, the WDI pin detects falling edges. These
edges are ignored until the power-on-reset timer expires,
and the CWDT pin has risen above 0.2V for the first time,
as shown in Figure 13a. After that time, there must be a
falling edge on the WDI pin before the watchdog timer
expires, which will happen within tWDU (a minimum of
17ms while using 1000pF for CWDT). After this first valid
falling edge, subsequent edges must follow the timing
sequence outlined in Figure 13b. Each subsequent edge
must occur after tWDL (a maximum of 785µs while using
1000pF for CWDT) and before tWDU.
If there is a timing fault, the WDO pin will flag low, and will
initiate a restart sequence using the power-on-reset timer,
as shown in Figure 13c. The RST pin will remain high,
however. WDI edges are ignored until the power-on-reset
timer expires, and the CWDT pin has risen above 0.2V. After
that time, there must be a falling edge on the WDI pin before the watchdog timer expires, which will happen within
tWDU. After this first valid falling edge, subsequent edges
must follow the timing sequence outlined in Figure 13b.
Requirements for the watch dog input in timer mode (W/T
= High) are best understood by looking at Figure 14. In
timer mode, the WDI pin detects rising and falling edges.
These edges are ignored until the power-on-reset timer
expires, and the CWDT pin has risen above 0.2V for the
first time, as shown in Figure 14a. After that time, there
must be an edge on the WDI pin before the watchdog
timer expires, which will happen within tWDU (a minimum
of 17ms while using 1000pF for CWDT). After this first
edge, subsequent edges must follow the timing sequence
outlined in Figure 14b. Each subsequent edge must occur
before tWDU.
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25
LT3689/LT3689-5
APPLICATIONS INFORMATION
FB
0.72V
CPOR
RST COUNTER
1
3
2
4
tRST
RST
tWDU
CWTD
•••
0.2V
WDT COUNTER
1
WATCH DOG INPUT
IS IGNORED
WDO
2
0.2V
30
31
WATCH DOG INPUT MUST
TRANSITION LOW AT LEAST ONCE
IN THIS PERIOD
32
3689 F13a
(13a) W/T = Low. The First Valid Negative Edge on WDI Must Occur Before the Watchdog Timer Expires
tWDU
tWDL
WDI
•••
CWDT
1
2
30
0.2V
32
31
WATCH DOG INPUT
MUST TRANSITION LOW
AT LEAST ONCE IN
THIS PERIOD
WDO
3689 F13b
(13b) W/T = Low. Subsequent Negative Edges Must Occur Within a Fixed Time Window
CPOR
RST COUNTER
1
2
3
4
tRST
CWTD
•••
0.2V
1
WDT COUNTER
WDO
tWDU
WATCH DOG INPUT
IS IGNORED
2
30
0.2V
31
WATCH DOG INPUT MUST
TRANSITION LOW AT LEAST ONCE
IN THIS PERIOD
32
3689 F13c
(13c) W/T = Low. Restart Sequence After a Timing Fault
Figure 13. W/T = Low. Time Charts for the Power-On-Reset and Watchdog Timer in Window Mode
3689fe
26
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LT3689/LT3689-5
APPLICATIONS INFORMATION
FB
0.72V
CPOR
1
RST COUNTER
3
2
4
tRST
RST
tWDU
•••
CWTD
0.2V
1
WDT COUNTER
WDO
WATCH DOG INPUT
IS IGNORED
2
30
0.2V
31
WATCH DOG INPUT MUST
TRANSITION LOW AT LEAST
ONCE IN THIS PERIOD
32
3689 F14a
(14a) W/T = High. The First Valid Negative Edge on WDI Must Occur Before the Watchdog Timer Expires
tWDU
WDI
•••
CWDT
1
WDT COUNTER
2
30
0.2V
32
31
WATCH DOG INPUT MUST
TRANSITION LOW AT LEAST
ONCE IN THIS PERIOD
WDO
3689 F14b
(14b) W/T = High. Subsequent Edges Must Occur Before the Timer Expires
CPOR
RST COUNTER
1
2
3
4
tRST
CWTD
0.2V
1
WDT COUNTER
WDO
tWDU
WATCH DOG INPUT
IS IGNORED
•••
2
30
0.2V
31
WATCH DOG INPUT MUST
TRANSITION LOW AT LEAST
ONCE IN THIS PERIOD
32
3689 F14c
(14c) W/T = Low. Restart Sequence After a Timing Fault
Figure 14. W/T = High. Time Charts for the Power-On-Reset and Watchdog Timer in Timer Mode
3689fe
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27
LT3689/LT3689-5
APPLICATIONS INFORMATION
If there is a timing fault, the WDO pin will flag, low, and
will initiate a restart sequence using the power-on-reset
timer, as shown in Figure 14c. The RST pin will remain
high, however. WDI edges are ignored until the power-onreset timer expires, and the CWDT pin has risen above
0.2V for the first time. After that time, there must be an
edge on the WDI pin before the watchdog timer expires,
which will happen within tWDU. After this first falling edge,
subsequent edges must follow the timing sequence outlined in Figure 14b.
Shorted and Reversed Input Protection
If an inductor is chosen to prevent excessive saturation,
the LT3689 will tolerate a shorted output. When operating in short-circuit condition, the LT3689 will reduce
its frequency until the valley current is at a typical value of
1.2A (see Figure 15). There is another situation to consider
in systems where the output will be held high when the
input to the LT3689 is absent. This may occur in battery
charging applications or in battery backup systems where
a battery or some other supply is diode ORed with the
LT3689’s output. If the VIN pin is allowed to float and the
EN/UVLO pin is held high (either by a logic signal or because it is tied to VIN), then the LT3689’s internal circuitry
will pull its quiescent current through its SW pin. This is
fine if the system can tolerate a few mA in this state. If the
EN/UVLO pin is grounded, the SW pin current will drop to
essentially zero. However, if the VIN pin is grounded while
the output is held high, then parasitic diodes inside the
LT3689 can pull large currents from the output through
the SW pin and the VIN pin. Figure 16 shows a circuit that
will run only when the input voltage is present and that
protects against a shorted or reversed input.
VIN
VIN
OUT
LT3689
BST
DA
EN/UVLO
GND
VOUT
SW
FB
+
3689 F16
Figure 16. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output; It Also
Protects the Circuit from a Reversed Input. The LT3689
Runs Only When the Input Is Present
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 17 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT3689’s VIN and SW pins, the catch
diode (D1) and the input capacitor (C1). The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board. Place a local, unbroken ground plane below these
components. The SW and BST nodes should be as small
as possible. Finally, keep the FB node small so that the
VSW
20V/DIV
IL
0.5A/DIV
10µs/DIV
3689 F15
Figure 15. The LT3689 Reduces its Frequency to Below
100kHz to Protect Against Shorted Output with 36V Input
Figure 17. Example Layout for QFN Package.
A Good PCB Layout Ensures Proper Low EMI Operation
3689fe
28
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LT3689/LT3689-5
APPLICATIONS INFORMATION
ground traces will shield them from the SW and BOOST
nodes. The Exposed Pad on the bottom of the package
must be soldered to ground so that the pad acts as a heat
sink. To keep thermal resistance low, extend the ground
plane as much as possible, and add thermal vias under
and near the LT3689 to additional ground planes within
the circuit board and on the bottom side.
be derated as the ambient temperature approaches 125°C
(150°C for H-grade). A board measuring 5cm × 7.5cm with
a top layer layout similar to Figure 15 was evaluated in
still air at 3.3VOUT, 700kHz switching frequency. At 700mA
load, the temperature reached approximately 12°C above
ambient for input voltages equal to 12V and 24V. Power
dissipation within the LT3689 can be estimated by calculating the total power loss from an efficiency measurement
and subtracting the catch diode loss. The die temperature
is calculated by multiplying the LT3689 power dissipation
by the thermal resistance from junction-to-ambient.
High Temperature Considerations
The PCB must provide heat sinking to keep the LT3689
cool. The Exposed Pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3689.
Placing additional vias can reduce thermal resistance
further. Because of the large output current capability of
the LT3689, it is possible to dissipate enough heat to raise
the junction temperature beyond the absolute maximum
of 125°C (150°C for H-grade). When operating at high
ambient temperatures, the maximum load current should
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
TYPICAL APPLICATIONS
5V Step-Down Converter
VIN
6.3V TO 36V
TRANSIENT
TO 60V
C1
1µF
WINDOW TIMEOUT
WATCHDOG_DEFEAT
µP
EN/UVLO
OUT
BST
VIN
W/T
WDE
I/O
WDI
I/O
WDO
LT3689
SW
C6
10nF
tWDU = 182ms
CPOR
C5
68nF
tRST = 157ms
R1
536k
DA
FB
RT
SYNC
CWDT
R2
102k
GND
fSW = 1MHz
L1
12µH
C4
5.6pF
D1
RST
RESET
C2
0.1µF
5V
700mA
C3
10µF
RT
12.7k
3689 TA02
L1: CDR125NP-12MC
D1: MBRM140
C1, C2, C3: X7R or X5R
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For more information www.linear.com/LT3689
29
LT3689/LT3689-5
TYPICAL APPLICATIONS
3.3V Step-Down Converter
VIN
4.5V TO 36V
TRANSIENT
TO 60V
C1
2.2µF
WINDOW TIMEOUT
WATCHDOG_DEFEAT
µP
EN/UVLO
OUT
BST
VIN
W/T
WDE
I/O
WDI
I/O
WDO
LT3689
SW
C6
10nF
tWDU = 182ms
R1
316k
DA
FB
RT
SYNC
CWDT
CPOR
R2
100k
GND
C5
68nF
tRST = 157ms
L1
12µH
C4
10pF
D1
RST
RESET
C2
0.1µF
3.3V
700mA
C3
22µF
RT
20.5k
fSW = 700kHz
3689 TA03
L1: CDR125NP-12MC
D1: MBRM140
C1, C2, C3: X7R or X5R
5V, 2MHz Step-Down Converter
VIN
6.3V TO 18V
TRANSIENT
TO 60V
C1
1µF
WINDOW TIMEOUT
WATCHDOG_DEFEAT
µP
VIN
W/T
EN/UVLO
OUT
BST
WDE
I/O
WDI
I/O
WDO
LT3689-5
SW
D1
RST
RESET
CPOR
C5
68nF
tRST = 157ms
5V
700mA
C3
4.7µF
GND
fSW = 2MHz
L1
10µH
C4
2.7pF
DA
FB
RT
SYNC
CWDT
C6
10nF
tWDU = 182ms
C2
0.1µF
RT
4.02k
3689 TA04
C1, C2, C3: X7R OR X5R
D1: MBRM140
3689fe
30
For more information www.linear.com/LT3689
LT3689/LT3689-5
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
(.112 ± .004)
5.23
(.206)
MIN
2.845 ± 0.102
(.112 ± .004)
0.889 ± 0.127
(.035 ± .005)
8
1
1.651 ± 0.102
(.065 ± .004)
1.651 ± 0.102 3.20 – 3.45
(.065 ± .004) (.126 – .136)
0.305 ± 0.038
(.0120 ± .0015)
TYP
16
0.50
(.0197)
BSC
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ± 0.076
(.011 ± .003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE16) 0910 REV C
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31
LT3689/LT3689-5
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
15
PIN 1
TOP MARK
(NOTE 6)
16
0.40 ± 0.10
1
1.45 ± 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
3689fe
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LT3689/LT3689-5
REVISION HISTORY
REV
DATE
DESCRIPTION
A
4/10
Added LT3689-5 Fixed Output Voltage Option
PAGE NUMBER
B
9/10
Revised conditions for tSW(OFF) and VOL in Electrical Characteristics section.
3
C
10/10
Removed connection from OUT to GND in 5V, 2MHz Step-Down Converter drawing in Typical Applications section.
28
D
2/11
Replaced Figure 12 in the Applications Information section.
24
E
3/13
Clarified Switching Frequency limits, Foldback Resistor values
Clarified Watchdog Timing graphs
1–32
3
25-28
3689fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3689
33
LT3689/LT3689-5
TYPICAL APPLICATION
1.8V Step-Down Converter with System Reset Generated by
Watchdog Timing or Output Voltage Failure
VIN
3.6V TO 16V
TRANSIENT TO 27V
C1
1µF
WINDOW TIMEOUT
WATCHDOG_DEFEAT
µP
I/O
WDE
WDI
WDO
L1: WE-PD2: 7447745047
D1: MBRM140
C1, C2, C3: X7R OR X5R
LT3689
SW
C5
68nF
tRST = 157ms
L1
4.7µH
C2
0.1µF
DA
FB
RT
SYNC
CWDT
CPOR
GND
fSW = 900kHz
1.8V
700mA
C4
15pF
D1
RST
RESET
C6
10nF
tWDU = 182ms
EN/UVLO
OUT
BST
VIN
W/T
R1
127k
RT
14.7k
R2
102k
C3
47µF
3689 TA05
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1766
60V, 1.2A (IOUT), 200kHz, High Efficiency Step-Down DC/DC
Converter
VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA, ISD = 25µA, TSSOP-16
and TSSOP-16E Packages
LT1936
36V, 1.4A (IOUT), 500kHz High Efficiency Step-Down DC/DC
Converter
VIN: 3.6V to 36V, VOUT(MIN) = 1.2V, IQ = 1.9mA, ISD
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