LT3742
Dual, 2-Phase Step-Down
Switching Controller
Features
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Description
Wide Input Voltage Range: 4V to 30V
Wide Output Voltage Range: 0.8V to VIN
Low Shutdown IQ: 20µA
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
0.8V ±1.5% Voltage Reference
500kHz Current Mode Fixed Frequency Operation
Internal Boost Converter Provides Bias Rail for
N-channel MOSFET Gate Drive
Power Good Voltage Monitor for Each Output
Programmable Soft-Start
24-Lead 4mm × 4mm × 0.75mm Package
The LT®3742 is a dual step-down DC/DC switching regulator
controller that drives high side N-channel power MOSFETs.
A 500kHz fixed frequency current mode architecture provides fast transient response with simple loop compensation components and cycle-by-cycle current limiting. The
output stages of the two controllers operate 180° out of
phase to reduce the input ripple current, minimizing the
noise induced on the input supply, and allowing less input
capacitance.
An internal boost regulator generates a bias rail of VIN + 7V
to provide gate drive for the N-channel MOSFETs allowing
low dropout and 100% duty cycle operation. The LT3742
can be used for applications where both controllers need
to operate independently, or where both controllers are
used to provide a single higher current output.
Applications
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Satellite and Cable TV Set-Top Boxes
Distributed Power Regulation
Automotive Systems
Super Capacitor Charger
The device is available in a thermally enhanced 4mm ×
4mm QFN package.
L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and Burst Mode are registered
trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
8V and 5V Dual Step-Down Converter
10µH
45.3k
1µF
4.7µF
5VOUT
SWB BIAS
VIN
UVLO
20.0k
LT3742
VIN
VIN
10µF
VOUT1
8V
4A
G1
0.010Ω
G2
6.5µH
47µF
0.010Ω
SW2
SENSE2+
SENSE2–
FB2
SW1
SENSE1+
SENSE1–
FB1
1.05k
RUN1
VOUT2
5V
4A
47µF
200Ω
200Ω
PG1
1nF
1000pF
30k
PG1
RUN/SS1
VC1
PG2
RUN/SS2
VC2
GND
80
70
60
10µF
6.5µH
1.8k
8VOUT
90
EFFICIENCY (%)
VIN
14V
Efficiency vs Load Current
100
50
40
0
0.5
1
2.5 3
1.5 2
LOAD CURRENT (A)
3.5
4
3742 TA01b
PG2
20k
1000pF
1nF
RUN2
3742 TA01a
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LT3742
pIN CONFIGURATION
VIN Voltage.................................................................30V
UVLO Voltage.............................................................30V
PG1, PG2 Voltage.......................................................30V
SWB, BIAS Voltage....................................................40V
SENSE1+, SENSE2+ Voltage.......................................30V
SENSE1–, SENSE2– Voltage.......................................30V
RUN/SS1, RUN/SS2 Voltage........................................6V
FB1, FB2 Voltage..........................................................6V
VC1, VC2 Voltage...........................................................6V
Junction Temperature............................................ 125°C
Operating Junction Temperature Range
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
FB1
SENSE1–
SENSE1+
NC
NC
SW1
TOP VIEW
24 23 22 21 20 19
G1 1
18 VC1
VIN 2
17 PG1
UVLO 3
16 RUN/SS1
25
BIAS 4
15 RUN/SS2
SWB 5
14 PG2
G2 6
13 VC2
FB2
SENSE2–
9 10 11 12
SENSE2+
8
NC
7
NC
(Note 1)
SW2
Absolute Maximum Ratings
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 36°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3742EUF#PBF
LT3742EUF#TRPBF
3742
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C (Note 2)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise specified.
PARAMETER
CONDITIONS
Minimum Operating Input Voltage
VUVLO = 1.5V
Quiescent Current
MIN
TYP
MAX
3.5
4.0
V
VRUN/SS1 = VRUN/SS2 = VFB1 = VFB2 = 1V
5.0
7.0
mA
Shutdown Current
VRUN/SS1 = VRUN/SS2 = 0V
20
35
µA
UVLO Pin Threshold
UVLO Pin Voltage Rising
1.25
1.28
V
UVLO Pin Hysteresis Current
VUVLO = 1V, Current Flows Into Pin
1.8
3
4
µA
0.2
0.5
0.5
1
1.5
µA
0.788
0.800
0.812
V
l
l
RUN/SS Pin Threshold
RUN/SS Pin Charge Current
VRUN/SS = 0V
FB Pin Voltage
FB Pin Voltage Line Regulation
l
VIN = 5V to 30V
1.20
0.01
UNITS
V
%/V
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LT3742
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise specified.
PARAMETER
CONDITIONS
FB Pin Bias Current
VFB = 0.8V, VC = 0.4V
MIN
FB Pin Voltage Matching
–4
TYP
MAX
UNITS
50
200
nA
0
4
mV
Error Amplifier Transconductance
250
µmho
Error Amplifier Voltage Gain
500
V/V
VC Pin Source Current
VFB = 0.6V
15
µA
VC Pin Sink Current
VFB = 1V
15
µA
Controller Switching Frequency
440
Switching Phase
Maximum Current Sense Voltage
500
560
180
– = 3.3V
VSENSE
l
Current Sense Matching
Between Controllers
Current SENSE Pins Total Current
SENSE–, SENSE+ = 0V
SENSE–, SENSE+ = 3.3V
Gate Rise Time
50
60
kHz
Deg
70
mV
±5
%
–1.0
40
mA
µA
CLOAD = 3300pF
40
ns
Gate Fall Time
CLOAD = 3300pF
60
ns
Gate On Voltage (VG – VSW)
VBIAS = 12V
Gate Off Voltage (VG – VSW)
VBIAS = 12V
PG Pin Voltage Low
IPG = 100µA
0.20
0.5
V
Lower PG Trip Level (Relative to VFB)
VFB Increasing
–7
–10
–13
%
Lower PG Trip Level (Relative to VFB)
VFB Decreasing
–10
–13
–16
%
Upper PG Trip Level (Relative to VFB)
VFB Increasing
7
10
13
%
Upper PG Trip Level (Relative to VFB)
VFB Decreasing
4
7
10
%
0.1
µA
200
500
µA
VIN + 6.6
VIN + 7
VIN + 7.7
250
340
500
mA
0.01
1
µA
1.0
1.12
PG Pin Leakage Current
VPG = 2V
PG Pin Sink Current
VPG = 0.5V
Bias Pin Voltage
SWB Pin Current Limit
SWB Pin Leakage Current
6.0
VSWB = 12V
Bias Supply Switching Frequency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
0.88
6.7
7.0
V
0.4
0.75
V
V
MHz
Note 2: The LT3742E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature range. Specifications
over the – 40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls.
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LT3742
Typical Performance Characteristics
IQ-SHDN vs Temperature
Controller Current Sense Voltage
vs Temperature
IQ-Running vs Temperature
10
50
70
8
CURRENT (mA)
CURRENT (µA)
40
SENSE VOLTAGE (mV)
9
30
7
6
5
20
65
60
55
4
10
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
3
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
100
50
–50
125
–25
75
0
25
50
TEMPERATURE (°C)
Internal UVLO vs Temperature
VFB vs Temperature
UVLO Threshold vs Temperature
5
125
3742 G03
3742 G02
3742 G01
100
3.0
830
2.5
820
2.0
810
3
VFB (mV)
UVLO (V)
VIN (V)
4
1.5
800
1.0
790
0.5
780
2
1
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
3742 G04
125
770
–50 –25
50
25
75
0
TEMPERATURE (°C)
RUN/SS Current vs Temperature
3.0
125
3742 G06
3742 G05
1.8
100
UVLO IHYST vs Temperature
1.2
IHYST (µA)
RUN/SS CURRENT (µA)
2.8
2.6
2.4
0.6
2.2
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3742 G07
2.0
–50
–25
50
0
75
25
TEMPERATURE (°C)
100
125
3742 G08
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LT3742
Typical Performance Characteristics
Controller Frequency
vs Temperature
PG Threshold vs Temperature
450
75
0
25
50
TEMPERATURE (°C)
100
125
POWER GOOD
0.8
8
6
0.7
0.6
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
4
–50
75
0
25
50
TEMPERATURE (°C)
–25
3742 G10
3742 G09
100
125
3742 G11
RUN/SS Threshold
vs Temperature
SWB Current Limit
vs Temperature
1.0
380
360
RUN/SS VOLTS (V)
–25
0.9
(VBIAS – VIN) (V)
FEEDBACK VOLTS RISING (V)
500
SWB CURRENT LIMIT (mA)
FREQUENCY (kHz)
550
400
–50
VBIAS – VIN vs Temperature
10
1.0
600
340
0.7
0.4
320
300
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
3742 G12
0.1
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3742 G13
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LT3742
Pin Functions
G1, G2 (Pins 1, 6): Gate Drives. These pins provide high
current gate drive for the external N-channel MOSFETs.
These pins are the outputs of floating drivers whose voltage swings between the BIAS and SW pins.
VIN (Pin 2): Input Voltage. This pin supplies current to the
internal circuitry of the LT3742. This pin must be locally
bypassed with a capacitor.
UVLO (Pin 3): Undervoltage Lockout. Do not leave this
pin open ; connect it to VIN if not used. A resistor divider
connected to VIN is tied to this pin to program the minimum input voltage at which the LT3742 will operate. When
this pin is less than 1.25V, the controllers are disabled
(the RUN/SS pins are still used to turn on each switching
regulator). Once this pin drops below 1.25V, a 3µA current
sink draws current into the pin to provide programmable
hysteresis for UVLO.
BIAS (Pin 4): Bias for Gate Drive. This pin provides a bias
voltage higher than the input voltage to drive the external
N-channel MOSFETs. The voltage on this pin is regulated
to VIN + 7V.
SWB (Pin 5): Bias Regulator Switch. This is the collector of an internal NPN switch used to generate the bias
voltage to provide gate drive for the external N-channel
MOSFETs.
RUN/SS1, RUN/SS2 (Pins 16, 15): Run/Soft-Start Pins.
These pins are used to shut down each controller. They
also provide a soft-start function with the addition of an
external capacitor. To shut down any regulator, pull the
RUN/SS pin to ground with an open-drain or open-collector device. If neither feature is used, leave these pins
unconnected.
PG1, PG2 (Pins 17, 14): Power Good. These pins are
open-collector outputs of internal comparators. PG remains
low until the FB pin is within 90% of the final regulation
voltage. As well as indicating output regulation, the PG
pins can be used to sequence the switching regulators.
The PG outputs are valid when VIN is greater than 4V
and either of the RUN/SS pins is high. The power good
comparators are disabled in shutdown. If not used, these
pins should be left unconnected.
VC1, VC2 (Pins 18, 13): Control Voltage and Compensation
Pins for Internal Error Amplifiers. Connect a series RC
from these pins to ground to compensate each switching
regulator loop.
FB1, FB2 (Pins 19, 12): Feedback Pins. The LT3742
regulates these pins to 800mV. Connect the feedback
resistors to this pin to set the output voltage for each
switching regulator.
SENSE1–, SENSE2– (Pins 20, 11): Negative Current Sense
Inputs. These pins (along with the SENSE+ pins) are used to
sense the inductor current for each switching regulator.
SENSE1+, SENSE2+ (Pins 21, 10): Positive Current Sense
Inputs. These pins (along with the SENSE– pins) are used to
sense the inductor current for each switching regulator.
SW1, SW2 (Pins 24, 7): Switch Nodes. These pins connect
to the source of the external N-channel MOSFETs and to
the external inductors and diodes.
Exposed Pad (Pin 25): Ground. The Exposed Pad of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board. The
Exposed Pad must be soldered to the circuit board to
ensure proper operation.
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LT3742
Block Diagram
SWB
BIAS
25 GND
VIN
2 VIN
3
UVLO
GATE DRIVE BIAS
BOOST REGULATOR
1.25V
+
–
VIN
5
4
BIAS
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
3µA
UVLO
VREF
INTERNAL
SUPPLY
ENABLE
COMPARATOR
–
+
+
≈0.5V
1.25V
0.88V
0.80V
0.72V
ENABLE
ENABLE
1MHz MASTER
OSCILLATOR
D
Q
Q
PHASE SYNC FOR
DC/DC CONTROLLERS
TO
RUN/SS1
RUN/SS2
LT3742 CONTROLLER 1 AND 2
PHASE SYNC
G
GATE
DRIVER
TO ENABLE
COMPARATOR
RUN/SS
SHDN
1µA
Σ
+
–
CURRENT
SENSE
AMPLIFIER
ERROR
AMPLIFIER
SS
SW
VOUT
SENSE+
+
–
+
+
–
500kHz SLAVE
OSCILLATOR
PWM
COMPARATOR
VIN
BIAS
R
Q
S
SENSE–
FB
0.80V
VC
POWER GOOD
COMPARATORS
+
–
PG
+
–
PGOOD
0.88V
FB
0.72V
3742 BD1
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LT3742
Operation
The LT3742 is a dual, constant frequency, current mode
DC/DC step-down controller. The two controllers in each
device share some common circuitry including protection circuitry, the internal bias supply, voltage reference,
master oscillator and the gate drive boost regulator. The
Block Diagram shows the shared common circuitry and
the independent circuitry for both DC/DC controllers.
A power good comparator pulls the PG pin low whenever
the FB pin is not within ±10% of the 800mV internal
reference voltage. PG is the open-collector output of an
NPN that is off when the FB pin is in regulation, allowing
an external resistor to pull the PG pin high. This power
good indication is valid only when the device is enabled
(RUN/SS is high) and VIN is 4V or greater.
Important protection features included in the LT3742 are
undervoltage lockout and thermal shutdown. When either
of these conditions exist, the gate drive bias regulator and
both DC/DC controllers are disabled and both RUN/SS pins
are discharged to 0.5V to get ready for a new soft-start
cycle. Undervoltage lockout (UVLO) is programmed using
two external resistors. When the UVLO pin drops below
1.25V, a 3µA current sink is activated to provide programmable hysteresis for the UVLO function. A separate, less
accurate, internal undervoltage lockout will disable the
LT3742 when VIN is less than 2.5V.
The LT3742 enables each controller independently when its
RUN/SS pin is above 0.5V and each controller generates
its own soft-start ramp. During start-up, the error amplifier compares the FB pin to the soft-start ramp instead of
the precision 800mV reference, which slowly raises the
output voltage until it reaches its resistor programmed
regulation point. Control of the inductor current is strictly
maintained until the output voltage is reached. The LT3742
is ideal for applications where both DC/DC controllers need
to operate separately.
The gate drive boost regulator is enabled when all internal
fault conditions have been cleared. This regulator uses
both an internal NPN power switch and Schottky diode to
generate a voltage at the BIAS pin that is 7V higher than
the input voltage. Both DC/DC controllers are disabled until
the BIAS voltage has reached ~90% of its final regulation
voltage. This ensures that sufficient gate drive to fully
enhance the external MOSFETs is present before the driver
is allowed to turn on.
The master oscillator runs at 1MHz and clocks the gate
drive boost regulator at this frequency. The master oscillator also generates two 500kHz clocks, 180° out of phase,
for the DC/DC controllers.
A pulse from the 500kHz oscillator sets the RS flip-flop
and turns on the external N-channel MOSFET. Current in
the switch and the external inductor begins to increase.
When this current reaches a level determined by the control
voltage (VC), the PWM comparator resets the flip-flop,
turning off the MOSFET. The current in the inductor then
flows through the external Schottky diode and begins to
decrease. This cycle begins again at the next set pulse from
the slave oscillator. In this way, the voltage at the VC pin
controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the VC pin voltage. Direct control
of the peak inductor current on a cycle-by-cycle basis is
managed by the current sense amplifier. Because the inductor current is constantly monitored, the devices inherently
provide excellent output short-circuit protection.
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LT3742
Applications Information
Soft-Start and Shutdown
The RUN/SS (Run/Soft-Start) pins are used to enable each
controller independently, and to provide a user-programmable soft-start function that reduces the peak input
current and prevents output voltage overshoot during
start-up. To disable either controller, pull its RUN/SS pin
to ground with an open-drain or open-collector device.
If both RUN/SS pins are pulled to ground, the LT3742
is placed in shutdown mode, and quiescent current is
reduced to 20µA. Internal 1µA current sources pull up on
each RUN/SS pin, and when either pin reaches 0.5V, that
controller is enabled, along with the internal bias supply,
gate drive boost regulator, voltage reference and master
oscillator. If both outputs are always enabled together,
one soft-start capacitor can be used with both RUN/SS
pins tied together.
The Benefits of Soft-Start
When a capacitor is tied from the RUN/SS pin to ground,
the internal 1µA pull-up current source generates a voltage ramp on this pin. During start-up, the error amplifier
VOUT
5V/DIV
compares the FB pin to this ramp instead of to the 800mV
reference; this slowly and smoothly increases the output
voltage to its final value, while maintaining control of the
inductor current. Always check the inductor current and
output voltage waveforms to ensure that the programmed
soft-start time is long enough. A new soft-start cycle will
be initiated whenever VIN drops low enough to trigger
undervoltage lockout (programmed using the UVLO pin),
or the LT3742 die temperature exceeds thermal shutdown.
A typical value for the soft-start capacitor is 1nF.
Soft-start is strongly recommended for all LT3742 applications, as it provides the least amount of stress on the
external power MOSFET and catch diode. Without soft-start,
both of these components will see the maximum current
limit every start-up cycle. Figures 1a and 1b show startup waveforms with and without soft-start for the circuit
on the front page. Notice the large inductor current spike
and the output voltage overshoot when soft-start is not
used. While this may be acceptable for some systems, the
addition of a single capacitor dramatically improves the
start-up behavior of each DC/DC controller.
VOUT
5V/DIV
IL
2A/DIV
IL
2A/DIV
0.5ms/DIV
3742 F01a
Figure 1a. Start-Up Waveforms Without Soft-Start
0.5ms/DIV
3742 F01b
Figure 1b. Start-Up Waveforms with 1nF Soft-Start Capacitor
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LT3742
Applications Information
Power Good Indicators
Output Sequencing and Tracking
The PG pin is the open-collector output of an internal
window comparator that is pulled low whenever the FB
pin is not within ±10% of the 800mV internal reference
voltage. Tie the PG pin to any supply less than 30V with
a pull-up resistor that will supply less than 200µA. This
pin will be open when the LT3742 is placed in shutdown
mode regardless of the voltage at the FB pin. The power
good indication is valid only when the LT3742 is enabled
(RUN/SS is high) and VIN is 4V or greater.
The RUN/SS and PG pins can be used together to sequence
the two outputs of the LT3742. Figure 3 shows three
circuits to do this. For the first two cases, controller 1
starts first.
LT3742
RUN/SS1
SHDN
4.7nF
PG1
RUN/SS2
4.7nF
In Figure 2a, controller 2 turns on only after controller
1 has reached within 10% of its final regulation voltage.
A larger value for the soft-start capacitor on RUN/SS2
will provide additional delay between the outputs. One
SHDN (REFERENCE)
VOUT1
5V/DIV
VOUT2
10V/DIV
5ms/DIV
3742 F02a
Figure 2a. Supply Sequencing with Controller 2 Delayed Until After Controller 1 is in Regulation
LT3742
RUN/SS1
SHDN
4.7nF
RUN/SS2
10nF
SHDN (REFERENCE)
VOUT1
5V/DIV
VOUT2
10V/DIV
5ms/DIV
3742 F02b
Figure 2b. Supply Sequencing with Controller 2 Having a Fixed Delay Relative to Controller 1
LT3742
RUN/SS1
SHDN
10nF
RUN/SS2
SHDN (REFERENCE)
VOUT1
5V/DIV
VOUT2
10V/DIV
5ms/DIV
3742 F02c
Figure 2c. Both Conditions Start Up Together with Ratiometic Tracking
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LT3742
Applications Information
characteristic to notice about this method is that if the
output of controller 1 goes out of regulation enough
to trip the power good comparator, controller 2 will be
disabled.
tie it to VIN if not used. A separate, less accurate, internal
undervoltage lockout will disable the LT3742 when VIN is
less than 2.5V.
The UVLO resistor values are chosen to give the desired
minimum operating voltage (VIN(MIN)) and the desired
amount of hysteresis (VHYST). The LT3742 will turn on
when the input voltage is above (VIN(MIN) + VHYST), and
once on, will turn off when VIN drops below VIN(MIN). Select
the value for RUV1 first, then select the value for RUV2.
In Figure 2b, a slightly larger capacitor on RUN/SS2 delays
the turn-on of controller 2 with respect to controller 1. The
start-up waveforms for this method look very similar to
the one shown in Figure 6a, but here controller 2 is not
disabled if controller 1 goes out of regulation.
In Figure 2c, both RUN/SS pins share a single capacitor
and start up at the same time. By sharing the same softstart signal, this method provides ratiometric tracking of
the two outputs.
RUV1 =
Undervoltage Lockout (UVLO)
RUV1
RUV2
UVLO
2
1.25V
VIN(MIN) – 1.25V
The minimum input voltage is determined by either the
LT3742’s minimum operating voltage of 4V, UVLO or by
the output voltages of a given application. The LT3742 can
operate at 100% duty cycle, so if the input voltage drops
close to or equal to one of the output voltages, the controller will go into low dropout operation (100% duty cycle).
The duty cycle is the fraction of the time the N-channel
MOSFET is on every switch cycle, and is determined by
the input and output voltages:
During a UVLO event, both controllers and the gate drive
boost regulator are disabled. For the LT3742, all RUN/SS
pins are discharged to get ready for a new soft-start cycle.
For each controller that is enabled, it’s RUN/SS pin will
be held to 500mV until the input voltage rises above the
upper UVLO trip voltage. The UVLO function is only active
when one or more of the controllers are enabled using the
RUN/SS pin. The UVLO pin can not be used to directly
start the part. Do not leave the UVLO pin unconnected;
VIN
RUV2 = RUV1 •
Input Voltage Range
An external resistor divider can be used to accurately
set the minimum input voltage at which the LT3742 will
operate. Figure 3 shows the basic UVLO operation. Once
the UVLO pin drops below 1.25V, an undervoltage lockout event is signaled, turning on a 3µA current source to
provide hysteresis.
VIN
VHYST
3µA
⎛ V
+V ⎞
DC = ⎜ OUT D ⎟
⎝ VIN – VDS + VD ⎠
where VD is the forward drop of the catch diode (~0.4V)
and VDS is the typical MOSFET voltage drop (~0.1V).
1.25V
+
UVLO
–
3
3µA
3742 F03
Figure 3. Undervoltage Lockout
3742fa
11
LT3742
Applications Information
The maximum input voltage is determined by the absolute
maximum ratings of the VIN and BIAS pins (30V and 40V, respectively) and by the minimum duty cycle, DCMIN = 15%.
⎛V
+V ⎞
VIN(MAX) = ⎜ OUT D ⎟ + VSW – VD
⎝ DCMIN ⎠
The formula above calculates the maximum input voltage
that allows the part to regulate without pulse-skipping,
and is mainly a concern for applications with output voltages lower than 3.3V. For example, for a 2.5V output, the
maximum input voltage is:
⎛ 2.5V + 0.4V ⎞
VIN(MAX) = ⎜
⎟ + 0.1V – 0.4V = 19V
⎝
⎠
0.15
If an input voltage higher than 19V is used, the 2.5V output
will still regulate correctly, but the part must pulse-skip
to do so. Pulse skipping does not damage the LT3742,
but it will result in erratic inductor current waveforms
and higher peak currents. Note that this is a restriction
on the operating input voltage only for a specific output
voltage; the circuit will tolerate inputs up to the absolute
maximum rating.
Single Phase
Dual Controller
The Benefits of 2-Phase Operation
Traditionally, dual controllers operate with a single phase.
This means that both power MOSFETs are turned on at
the same time, causing current pulses of up to twice the
amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the RMS current flowing in the input capacitor,
require the use of larger and more expensive input capacitors, increase EMI, and causes increased power losses in
the input capacitor and input power supply.
The two controllers of the LT3742 are guaranteed by design
to operate 180° out of phase. This assures that the current
in each power MOSFET will never overlap, always presenting a significantly low peak and RMS current demand to
the input capacitor. This allows the use of a smaller, less
expensive input capacitor, improving EMI performance
and real world operating efficiency.
Figure 4 shows example waveforms for a single phase dual
controller versus a 2-phase LT3742 system. In this case,
5V and 3.3V outputs, each drawing a load current of 2A,
are derived from a 12V supply. In this example, 2-phase
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
IL1
IL2
IIN
3742 F04
Figure 4. Example Waveforms for a Single Phase Dual Controller vs the 2-Phase LT3742
3742fa
12
LT3742
Applications Information
operation would reduce the RMS input capacitor current
from ~1.8ARMS to ~0.8ARMS. While this is an impressive
reduction by itself, remember that power losses are proportional to IRMS2, meaning that the actual power wasted
due to the input capacitor is reduced by a factor of ~4.
Figure 5 shows the reduction in RMS ripple current for a
typical application.
The reduced input ripple current also means that less
power is lost in the input power path. Improvements in
both conducted and radiated EMI also directly accrue as
a result of the reduced RMS input current and voltage.
Significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower
RMS current-rated input capacitors.
Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two
controllers, which in turn, are dependent upon the input
voltage (DC ≈ VOUT/VIN).
It can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in
fact extend over a wide region. A good rule of thumb for
most applications is that 2-phase operation will reduce the
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
Inductor Value Selection
The inductor value directly affects inductor ripple current,
IRIPPLE, and maximum output current, IOUT(MAX). Lower
ripple current reduces core losses in the inductor, ESR
losses in the output capacitors and output voltage ripple.
Too large of a value, however, will result in a physically
large inductor. A good trade-off is to choose the inductor
ripple current to be ~30% of the maximum output current.
This will provide a good trade off between the inductor
size, maximum output current, and the amount of ripple
current. Note that the largest ripple current occurs at the
highest the input voltage, so applications with a wide VIN
range should consider both VIN(TYP) and VIN(MAX) when
calculating the inductor value:
L≥
VIN – VOUT
V
1
• OUT •
0.3 • IOUT(MAX) VIN 500kHz
This equation provides a good starting point for picking the inductor value. Most systems can easily tolerate
ripple currents in the range of 10% to 50%, so deviating
slightly from the calculated value is acceptable for most
applications. Pick a standard value inductor close to the
3.0
SINGLE PHASE
DUAL CONTROLLER
INPUT RMS CURRENT (A)
2.5
2.0
1.5
2-PHASE
DUAL CONTROLLER
1.0
0.5
0
VO1 = 5V/3A
VO2 = 3.3V/3A
0
10
20
30
INPUT VOLTAGE (V)
40
3742 F05
Figure 5. RMS Input Current Comparison
3742fa
13
LT3742
Applications Information
value calculated above, and then recheck the amount of
ripple current:
IRIPPLE
V – VOUT VOUT
1
= IN
•
•
L
VIN 500kHz
The DC resistance (DCR) of the inductor can have a significant impact on total system efficiency, as it causes an
I2RDCR power loss. Consider inductance value, DCR, and
current rating when choosing an inductor. Table 1 shows
several recommended inductor vendors. Each offers
numerous devices in a wide variety of values, current
ratings, and package sizes.
Table 1. Recommended Inductor Manufacturers
VENDOR
WEBSITE
Sumida
www.sumida.com
Toko
www.toko.com
Würth
www.we-online.com
NEC-Tokin
www.nec-tokinamerica.com
TDK
www.tdk.com
Maximum Output Current (RSENSE Value Selection)
Maximum output current is determined largely by the
values of the current sense resistor, RSENSE (which sets
the inductor peak current), and the inductor (which sets
the inductor ripple current). The LT3742 current comparator has a guaranteed minimum threshold of 50mV, which
does not vary with duty cycle. The maximum output current is calculated:
IOUT(MAX) =
50mV IRIPPLE
–
RSENSE
2
Rearranging the equation above to solve for RSENSE
gives:
RSENSE =
50mV
⎛I
⎞
IOUT(MAX) + ⎜ RIPPLE ⎟
⎝ 2 ⎠
Inductor, Catch Diode and MOSFET Current Rating
Once the inductor and RSENSE values have been chosen, the
current ratings of the inductor, catch diode and MOSFET
can then be determined. The LT3742 current comparator
has a guaranteed maximum threshold of 70mV, and there
is a small amount of current overshoot resulting from
the response time of the current sense comparator. The
components should be rated to handle:
IRATED ≥
⎞
70mV ⎛ VIN
+⎜
• 100ns⎟
⎠
RSENSE ⎝ L
Schottky Catch Diode Selection
During output short-circuits, the diode will conduct current
most of the time, so it is important to choose a device
with a sufficient current rating. In addition, the diode must
have a reverse voltage rating greater than the maximum
input voltage. Many surface mount Schottky diodes are
available in very small packages. Read their data sheets
carefully as they typically must be temperature derated.
Basically, excessive heating prevents them from being
used effectively at their rated maximum current. A few
recommended diodes are listed in Table 2.
Table 2. Recommended Schottky Diodes
VENDOR
DEVICE
Diodes, Inc.
www.diodes.com
PDS540 (5A, 40V)
SBM1040 (10A, 40V)
Microsemi
www.microsemi.com
UPS340 (3A, 40V)
UPS840 (8A, 40V)
On Semiconductor
www.onsemi.com
MBRD320 (3A, 20V)
MBRD340 (3A, 40V)
Power MOSFET Selection
There are several important parameters to consider when
choosing an N-channel power MOSFET: drain current
(maximum ID); breakdown voltage (maximum VDS and
VGS); threshold voltage (VGS(TH)); on-resistance (RDS(ON));
reverse transfer capacitance (CRSS); and total gate charge
3742fa
14
LT3742
Applications Information
(QG). A few simple guidelines will make the selection
process easier.
provide higher efficiency. The power loss in the MOSFET
can be approximated by:
The maximum drain current must be higher than the
maximum rated current, IRATED, calculated on the previous
page. Note that the ID specification is largely temperature
dependent (lower ID at higher ambient temperatures), so
most data sheets provide a graph or table of ID versus
temperature to show this.
Ensure that the VDS breakdown voltage is greater than the
maximum input voltage and that the VGS breakdown voltage is 8V or greater. The peak-to-peak gate drive for each
MOSFET is ~7V, so also ensure that the device chosen will
be fully enhanced with a VGS of 7V. This may preclude the
use of some MOSFETs with a 20V VGS rating, as some have
too high of a threshold voltage. A good rule of thumb is that
the maximum threshold voltage should be VGS(TH)(MAX) ≤
3V. 4.5V MOSFETs will work as well.
⎛V
⎞
OUT + VD
2
⎜
PLOSS ≈ ⎜
• IOUT RDS(ON) • ρT ⎟⎟
V
+
V
D
⎝ IN
⎠
(2 • V
M1: ID = 11.5A, VGS = 12V, RDS(ON) = 10mΩ, CRSS = 230pF
M2: ID = 6.5A, VGS = 20V, RDS(ON) = 50mΩ, CRSS = 45pF
Power loss is calculated for both devices over a wide input
voltage range (4V ≤ VIN ≤ 30V), and shown in Figure 6 (as
a percentage of the 10W total power). Note that while the
low RDS(ON) device power loss is 5× lower at low input
0.6
0.6
0.4
0.3
TRANSITION
0.2
0.1
0
0
5
20
15
10
INPUT VOLTAGE (V)
0.5
0.4
0.3
TOTAL =
OHMIC + TRANSITION
0.2
OHMIC
0.1
OHMIC
)
The trade-off in RDS(ON) and CRSS can easily be seen in an
example using real MOSFET values. To generate a 3.3V,
3A (10W) output, consider two typical N-channel power
MOSFETs, both rated at VDS = 30V and both available in
the same SO-8 package, but having ~5x differences in
on-resistance and reverse transfer capacitance:
0.7
TOTAL =
OHMIC + TRANSITION
• IOUT • CRSS • f
where f is the switching frequency (500kHz) and ρT is a
normalizing term to account for the on-resistance change
due to temperature. For a maximum ambient temperature
of 70°C, using ρT ≈ 1.3 is a reasonable choice.
0.7
0.5
2
IN
MOSFET POWER LOSS (W)
MOSFET POWER LOSS (W)
Power losses in the N-channel MOSFET come from two
main sources: the on-resistance, RDS(ON), and the reverse
transfer capacitance, CRSS. The on-resistance causes
ohmic losses (I2RDS(ON)) which typically dominate at
input voltages below ~15V. The reverse transfer capacitance results in transition losses which typically dominate
for input voltages above ~15V. At higher input voltages,
transition losses rapidly increase to the point that the use
of a higher RDS(ON) device with lower CRSS will actually
PLOSS = (ohmic loss) + ( transition loss)
TRANSITION
25
30
3742 F06a
Figure 6a. Power Loss Example for M1 (10mΩ, 230pF)
0
0
5
20
15
10
INPUT VOLTAGE (V)
25
30
3742 F06b
Figure 6b. Power Loss Example for M2 (50m, 45pF)
3742fa
15
LT3742
Applications Information
voltages, it is also 3× higher at high input voltages when
compared to the low CRSS device.
Total gate charge, QG, is closely related to CRSS. Low
gate charge corresponds to a small value of CRSS. Many
manufacturers have MOSFETs advertised as “low gate
charge” devices (which means they are low CRSS devices)
that are specifically designed for low transition loss, and
are ideal for high input voltage applications.
Input Capacitor Selection
For most applications, 10µF to 22µF of input capacitance
per channel will be sufficient. A small 1µF bypass capacitor
between the VIN and ground pins of the LT3742, placed
close to the device, is also suggested for optimal noise
immunity. Step-down regulators draw current from the
input supply in pulses with very fast rise and fall times.
The input capacitor is required to reduce the resulting
voltage ripple at the LT3742 and to force this very high
frequency switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at
the switching frequency to do this effectively, and it must
have an adequate ripple current rating. With two controllers operating at the same frequency but with different
phases and duty cycles, calculating the input capacitor
RMS current is not simple. However, a conservative value
is the RMS input current for the channel that is delivering
the most power (VOUT • IOUT):
IRMS(CIN) =
IOUT
• VOUT • ( VIN – VOUT )
VIN
IRMS(CIN) is largest (IOUT/2) when VIN = 2VOUT (at DC =
50%). As the second, lower power channel draws input
current, the input capacitor’s RMS current actually decreases as the out-of-phase current cancels the current
drawn by the higher power channel, so choosing an input
capacitor with an RMS ripple current rating of IOUT,MAX/2
is sufficient.
The combination of small size and low impedance (low
equivalent series resistance, or ESR) of ceramic capacitors
make them the preferred choice. The low ESR results in
very low input voltage ripple and the capacitors can handle
plenty of RMS current. They are also comparatively robust
and can be used at their rated voltage. Use only X5R or
X7R types because they retain their capacitance over wider
voltage and temperature ranges than other ceramics.
An alternative to a high value ceramic capacitor is a lower
value (1µF) along with a larger value (10µF to 22µF) electrolytic or tantalum capacitor. Because the input capacitor
is likely to see high surge currents when the input source
is applied, tantalum capacitors should always be surge
rated. The manufacturer may also recommend operation
below the rated voltage of the capacitor. Be sure to place
the 1µF ceramic as close as possible to the N-channel
power MOSFET.
Output Capacitor Selection
A good starting value for output capacitance is to provide
10µF of COUT for every 1A of output current. For lower
output voltages (under 3.3V) and for applications needing
the best possible transient performance, the ratio should
be 20µF to 30µF of COUT for every 1A of output current.
X5R and X7R ceramics are an excellent choice for the
output capacitance. Aluminum electrolytics can be used,
but typically the ESR is too large to deliver low output
voltage ripple. Tantalum and newer, lower ESR organic
electrolytic capacitors are also possible choices, and the
manufactures will specify the ESR. Because the volume of
the capacitor determines the ESR, both the size and value
will be larger than a ceramic capacitor that would give you
similar output ripple voltage performance.
The output capacitor filters the inductor ripple current to
generate an output with low ripple. It also stores energy
in order to satisfy transient loads and to stabilize the
3742fa
16
LT3742
Applications Information
LT3742’s control loop. Output ripple can be estimated
with the following equation:
The output voltage for each controller is programmed
with a resistor divider between the output and the FB pin.
Always use 1% resistors (or better) for the best output
voltage accuracy. The value of RA should be 8k or less,
and the value of R1 should be chosen according to:
⎛
⎞
1
VRIPPLE = ΔIL ⎜
+ ESR ⎟
⎝ 8 • fSW • COUT
⎠
⎛V
⎞
RB = RA • ⎜ OUT – 1⎟
⎝ 0.8V ⎠
where ΔIL is the inductor ripple current and fSW is the
switching frequency (500kHz). The ESR is so low for
ceramic capacitors that it can be left out of the above
calculation. The output voltage ripple will be highest at
maximum input voltage (ΔIL increases with input voltage).
Table 3 shows several low-ESR capacitor manufacturers.
Output Short-Circuit Protection
Because the LT3742 constantly monitors the inductor current, both devices inherently providing excellent output
short-circuit protection. The N-channel MOSFET is not
allowed to turn on unless the inductor current is below the
threshold of the current sense comparator. This guarantees that the inductor current will not “run away” and the
controller will skip cycles until the inductor current has
dropped below the current sense threshold.
Table 3. Low ESR Surface Mount Capacitors
VENDOR
TYPE
SERIES
Taiyo Yuden
www.t-yuden.com
Ceramic X5R, X7R
Murata
www.murata.com
Ceramic X5R, X7R
Kemet
www.kemet.com
Tantalum
Ta Organic
Al Organic
T491, T494, T495
T520
A700
Sanyo
www.sanyo.com
Ta or Al Organic
POSCAP
Panasonic
www.panasonic.com
Al Organic
SP CAP
TDK
www.tdk.com
Ceramic X5R, X7R
Nippon Chemicon
www.chemi-con.co.jp
Ceramic X5R, X7R
Loop Compensation
An external resistor and capacitor connected in series from
the VC pin to ground provides loop compensation for each
controller. Sometimes a second, smaller valued capacitor
is placed in parallel to filter switching frequency noise from
the VC pin. Loop compensation determines the stability
and transient performance of each controller.
A practical approach is to start with values of RC = 10k
and CC = 330pF, then tune the compensation network to
optimize the performance. When adjusting these values,
change only one value at a time (RC or CC), then see how
the transient response is affected. The simplest way to
check loop stability is to apply a load current step while
observing the transient response at the output. Stability
should then be checked across all operating conditions,
including load current, input voltage, and temperature to
ensure a robust design.
Setting Output Voltage
The output of a bipolar controller requires a minimum load
to prevent current sourced from the switch pin charging
the output capacitor above the desired output voltage.
This current, approximately 5mA, may be accounted for
in the feedback string or the user may choose to force a
minimum load in their application.
VOUT1
R1B
VOUT2
LT3742
VFB1
R2B
VFB2
R1A
R2A
3742 F07
Figure 7. Setting Output Voltage with the FB Pin
3742fa
17
LT3742
Applications Information
Bias Supply Considerations
The LT3742 uses an internal boost regulator to provide a
bias rail for enhancement of the external MOSFETs. This
bias rail is regulated to VIN + 7V and must be in regulation before either controller is allowed to start switching.
As this is a high speed switching regulator, standard
procedures must be followed regarding placement of the
external components. The SWB node should be kept small
to reduce EMI effects and the bias decoupling capacitor
(CBIAS) should be kept close to the BIAS pin and VIN. A
slight surplus of power is available from this supply and
it can be tapped after stringent engineering evaluation.
PC Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
• Place the power components close together with short
and wide interconnecting traces. The power components consist of the top MOSFETs, catch diodes and
the inductors CIN and COUT. One way to approach this
is to simply place them on the board first.
• Similar attention should be paid to the power components that make up the boost converter. They should also
be placed close together with short and wide traces.
• Always use a ground plane under the switching regulator
to minimize interplane coupling.
• Minimize the parasitic inductance in the loop of CIN,
MOSFET and catch diode, which carry large switching
currents.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI low.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low. Unused areas
can be filled with copper and connect to any DC node
(VIN, VOUT, GND).
• Place CB close to BIAS pin and input capacitor.
• Keep the high dv/dt nodes (SW1, SW2, G1, G2, CIN1,
CIN2, SWB) away from sensitive small-signal nodes.
Demo board gerber files are available to assist with a
reliable layout. It will be difficult to achieve data sheet
performance specifications with improper layout.
3742fa
18
LT3742
Applications Information
VIN
VOUT1
VIN
SHDN
RUN1
SYSTEM
GROUND
SHDN
VIN
RUN2
VOUT2
3742 F08
VIAS TO LOCAL GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation
3742fa
19
LT3742
Typical Applications
Supercap Charger Plus a DC/DC Buck Converter
L3
22µH
VIN
5.5V TO 30V
2
R7
357k
C5
1µF
C6
4.7µF
3
VIN
UVLO
5
4
SWB BIAS
R8
124k
LT3742
VIN
VOUT1
5V
4A
C1
6.8µF
RS1
0.010Ω
1
M1
L1
4.7µH
24
21
R1
1.05k
C2
150µF
20
19
R2
200Ω
SENSE1+
SENSE1–
SENSE2+
SENSE2–
FB1
FB2
7
16
C7
1nF
CC1
680pF
M2
L2
47µH
RS2
0.030Ω
C3
6.8µF
VIN
SUPERCAP
CHARGER
OUTPUT
10
11
C4
47µF
12
150mF
D2
17
M3
SW2
SW1
6
D1
PG1
RUN1
G2
G1
18
RC1
51k
D1, D2: DIODES INC. PDS1040
M1, M2: SILICONIX Si7884DP
PG1
PG2
RUN/SS1
VC1
RUN/SS2
GND
25
VC2
14
PG2
15
13
C8
1nF
M4
RUN2
CC2
1000pF
3742 TA02
3742fa
20
LT3742
Typical Applications
8V and 5V Dual Step-Down Converter
L3
22µH
VIN
14V
2
R1
45.3k
C5
1µF
C6
2.2µF
3
VIN
UVLO
5
4
SWB BIAS
R1
20k
LT3742
VIN
VOUT1
8V
4A
C1
10µF
RS1
0.01Ω
1
M1
L1
6.5µH
24
21
R1
1.8k
C2
47µF
20
19
R2
200Ω
SENSE1+
SENSE1–
SENSE2+
SENSE2–
FB1
FB2
M2
L2
6.5µH
7
16
C7
1nF
CC1
1000pF
RS2
0.01Ω
C3
10µF
18
RC1
30k
PG1
PG2
RUN/SS1
VC1
C2, C4: MURATA GRM32ER71A476K
D1, D2: DIODES INC. PDS1040
L1, L2: WÜRTH ELEKTRONIK 744314650
M1, M2: FAIRCHILD FDS4470
RUN/SS2
GND
25
VC2
VIN
10
R3
1.05k
11
12
VOUT2
5V
4A
C4
47µF
R4
200Ω
D2
17
M3
SW2
SW1
6
D1
PG1
RUN1
G2
G1
14
PG2
15
13
RC2
20k
C8
1nF
M4
RUN2
CC2
1000pF
3742 TA03
3742fa
21
LT3742
Typical Applications
5V and 3.3V Dual Step-Down Converter
L3
22µH
VIN
14V
348k
1µF
2.2µF
SWB BIAS
VIN
UVLO
130k
LT3742
VIN
VIN
10µF
VOUT1
3.3V
4A
10mΩ
G1
L1
3.3µH
G2
SW2
SENSE2+
SENSE2–
FB2
SW1
SENSE1+
SENSE1–
FB1
619Ω
220µF
L2
4.7µH
10µF
10mΩ
1.05k
150µF
200Ω
D2
200Ω
PG1
1nF
680pF
51k
PG1
RUN/SS1
VC1
PG2
RUN/SS2
VC2
PG2
51k
GND
68pF
VOUT2
5V
4A
D1, D2: DIODES INC. PDS1040
L1: VISHAY IHLP2525CZER3R3
L2: VISHAY IHLP2525CZER4R7
L3: COILCRAFT: ME3220-223KL
M1, M2: VISHAY Si7848DP-T1-E3
1nF
680pF
3742 TA04a
Efficiency vs Load Current
90
5VOUT
EFFICIENCY (%)
80
3.3VOUT
70
60
50
0
1
2
3
4
LOAD CURRENT (A)
3742 TA04b
3742fa
22
LT3742
Typical Applications
High Current, Low Ripple 12V Step-Down Converter
L3 10µH
VIN
24V
R7
124k
C5
1µF
C6
4.7µF
SWB BIAS
VIN
UVLO
R8
20.0k
LT3742
VIN
C1
10µF
RS1
0.010Ω
VOUT1
12V
8A
G1
M1
G2
L2
8.2µH
L1
8.2µH
SW2
SENSE2+
SENSE2–
FB2
SW1
SENSE1+
SENSE1–
D1
PG1
C7
1nF CC1
680pF
RC1
51k
PG1
FB1
RUN/SS1
VC1
RS2
0.010Ω
PG2
RUN/SS2
VC2
PG2
GND
COUTA
100µF
20V
COUTA-COUTD: KEMET T495E107K020E060
D1, D2: DIODES INC. PDS1040
L1, L2: NEC/TOKIN PLC12458R2
M1, M2: ROHM RSS065N03
VIN
C3
10µF
D2
R1
2.8k
R2
200Ω
M2
COUTB
100µF
20V
COUTC
100µF
20V
COUTD
100µF
20V
3742 TA05a
12VOUT Efficiency vs Load Current
100
EFFICIENCY (%)
90
85
70
60
0
1
2
5
6
3
4
LOAD CURRENT (A)
7
8
3742 TA05b
3742fa
23
LT3742
Package Description
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3742fa
24
LT3742
Revision History
REV
DATE
DESCRIPTION
A
5/11
Revised Conditions in the Electrical Characteristics section.
PAGE NUMBER
2, 3
Revised the title of curve G04 in the Typical Performance Characteristics section.
4
Updated the PG1, PG2 pin description in the Pin Functions section.
6
Updated values in the Block Diagram, Operation, and Applications Information sections.
7-12
3742fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LT3742
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