LT3744
High Current Synchronous
Step-Down LED Driver
Features
Description
Ideal for Driving Up to 40A LEDs
n Up to 3000:1 PWM Dimming
n 20:1 Analog Dimming
n ±3% Current Regulation Accuracy
n ±3% Voltage Regulation Accuracy
n Unique Inverting Buck-Boost Topology Allows
Grounded Heat Sink to Be Used for RGB LEDs
n 3.3V to 36V Input Voltage Range
n Peak Current Mode with DC LED Current Sensing
n Open and Shorted LED Protection and Fault Reporting
n Floating LED Driver Allows Single Power Solution
to Drive Multicolor LEDs or Single LED with Three
Different Regulated Currents
n Thermally Enhanced 5mm × 6mm QFN 36-Lead
Package
The LT®3744 is a fixed frequency synchronous step-down
DC/DC controller designed to drive a LED load at up to 20A
continuous or 40A pulsed. The peak current mode controller
will maintain ±3% LED current regulation over a wide output
voltage range, from VEE to VIN. By allowing VEE to float
to negative voltages, several LEDs in series can be driven
from a single Li-Ion battery with a simple, single step-down
output stage. PWM dimming is achieved with the PWM pins.
The regulated LED current is set with analog voltages at the
CTRL pins. Regulated voltage and overvoltage protection
are set with a voltage divider from the output to the FB pin.
The switching frequency is programmable from 100kHz to
1MHz through an external resistor on the RT pin.
n
Applications
LED Driver for DLP Projectors
Heads-Up Displays
n High Power LED
n
n
Additional features include an accurate external reference
voltage, a control input for thermally derating regulation
current, an accurate EN/UVLO pin, an open-drain output
fault flag, OVLO, frequency synchronization, and thermal
shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7199560, 7321203, 8120335 and 8901904.
Typical Application
LED Driver for DLP Projectors
EN/UVLO
EN/UVLO
PWM1
PWM2
PWM3
CTRL1
CTRL2
CTRL3
VIN
TG
20µF
2.2µF
VREF
INTVCC
100k
45.3k
FAULT
BG
CTRLT
VEE
ISP
ISN
SGND
680k
1nF
82.5k
4.7nF
4.7nF
4.7nF
51k
51k
51k
0.47µH
22µF
VC2
1mΩ
20A MAXIMUM
330µF
330µF
PWM1
5V/DIV
PWM2
5V/DIV
PWM3
5V/DIV
ILED
6.7A/DIV
330µF
51k
GREEN
10µF
SYNC
PWM_OUT1
SS
RT
PWM_OUT2
VFNEG
VEE
PWM_OUT3
VC1
VIN
3.3V TO 12V
VEE
220nF
BOOST
SW
LT3744
2V
220µF
LED Current Waveforms
(2000:1) 0A to 6.7A to 13.3A to 20A
25µsec/DIV
LED_ISP
LED_ISN
FB
3744 TA01b
3mΩ
10k
VC3
3744 TA01a
VEE
3744fa
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1
LT3744
Absolute Maximum Ratings
(Note 1)
Relative to VEE (Tested with VEE = 0V and SGND = 20V):
VIN.........................................................................36V
EN/UVLO...............................................................36V
CTRL1, CTRL2, CTRL3...........................................23V
CTRLT....................................................................23V
ISP, ISN..................................................................36V
LED_ISP, LED_ISN...................................................3V
VC1, VC2, VC3............................................................3V
VFNEG..........................................................–15V to 3V
BOOST................................................................... 41V
FAULT, SYNC..........................................................23V
PWM1, PWM2, PWM3..........................................25V
FB............................................................................3V
SW.........................................................................36V
INTVCC, RT, BG, TG, PWM_OUT1, PWM_OUT2,
PWM_OUT3, VREF, SS.......................................Note 4
Relative to SGND (Tested with VEE = 0V and SGND = 0V):
VIN .........................................................................36V
EN/UVLO ...............................................................36V
CTRL1, CTRL2, CTRL3 .............................................3V
CTRLT .....................................................................3V
ISP, ISN ..................................................................36V
LED_ISP, LED_ISN ...................................................3V
VC1, VC2, VC3 ............................................................3V
VFNEG...........................................................–15V to 3V
BOOST................................................................... 41V
FAULT, SYNC............................................................3V
PWM1, PWM2, PWM3.............................................5V
FB ............................................................................3V
SW.........................................................................36V
Storage Temperature Range................. –65°C to 150°C
Pin Configuration
TG
SW
BOOST
BG
VEE
INTVCC
VEE
VIN
TOP VIEW
36 35 34 33 32 31 30 29
EN/UVLO 1
28 VEE
CTRL1 2
27 PWM_OUT1
VREF 3
26 VEE
CTRL2 4
25 PWM_OUT2
CTRL3 5
24 VFNEG
37
VEE
CTRLT 6
23 PWM_OUT3
PWM1 7
22 ISP
PWM2 8
21 ISN
PWM3 9
20 VC1
19 VC2
SYNC 10
VC3
FB
LED_ISP
LED_ISN
SS
RT
SGND
FAULT
11 12 13 14 15 16 17 18
UHE PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
θJA = 34°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 37) IS VEE, MUST BE SOLDERED TO PCB
3744fa
2
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LT3744
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3744EUHE#PBF
LT3744EUHE#TRPBF
3744
36-Lead (5mm × 6mm) Plastic QFN
–40°C to 125°C
LT3744IUHE#PBF
LT3744IUHE#TRPBF
3744
36-Lead (5mm × 6mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 2V, SGND = VEE = 0V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Input Voltage Range
(Note 2)
3.3
VIN Pin Quiescent Current (Note 3)
Non-Switching Operation
Shutdown Mode
VEN/UVLO = 2V, Not Switching
VEN/UVLO = 0V
TYP
1.225
EN/UVLO Hysteresis
UNITS
36
V
2.2
2.6
1
mA
µA
1.3
1.375
l
EN/UVLO Pin Threshold (Rising)
MAX
V
–65
mV
4.8
μA
EN/UVLO Pin Current
EN/UVLO = 1.0V
PWM1, PWM2, PWM3 Input High
Referenced to SGND
PWM1, PWM2, PWM3 Input Low
Referenced to SGND
PWM1, PWM2, PWM3 Pin Currents
PWM1, PWM2, PWM3 = 2.0V
CTRL1, CTRL2, CTRL3 Control Range
Referenced to SGND
CTRL1, CTRL2, CTRL3, Pin Currents
CTRL1, CTRL2, CTRL3, = 1.5V
100
nA
CTRLT Pin Current
CTRLT = 1.5V
100
nA
2.0
V
0.8
100
0
V
nA
1.5
V
Reference
Reference Voltage (VREF Pin)
Referenced to SGND
l
1.96
2
2.04
V
CTRL1 = 1.5V, PWM1 = 2V, PWM2 and PWM3 = 0V
l
58.2
60.0
61.8
mV
l
–3.0
l
2
LED and Inductor Current Sensing
Full Range LED_ISP to LED_ISN
Current Regulation Accuracy, Full Range
3
3.0
%
4
mV
1/20 Range LED_ISP to LED_ISN
CTRL1 = 0.075V, PWM1 = 2V, PWM2 and PWM3 = 0V
LED_ISP and LED_ISN Pin Current
CTRL1 = 1.5V, PWM1 = 2V,
PWM2, PWM3, LED_ISP and LED_ISN = 0V
65
μA
ISN and ISP Pin Current at 0V
ISN = ISP = 0V, PWM1 = 2V, PWM2 and PWM3 = 0V
390
μA
ISN and ISP Pin Current at 0V, Dimming
ISN = ISP = 0V, PWM1 = 0V, PWM2 and PWM3 = 0V
1
μA
ISN and ISP Pin Current at 5V
ISN = ISP = 5V, PWM1 = 2V, PWM2 and PWM3 = 0V
10
μA
ISN and ISP Pin Current at 5V, Dimming
ISN = ISP = 5V, PWM1 = 0V, PWM2 and PWM3 = 0V
1
μA
OC Inductor Threshold, Rising (ISP-ISN)
ISN = 3V
110
mV
OC Inductor Threshold, Falling (ISP-ISN)
ISN = 3V
75
mV
Internal VCC Regulator (INTVCC Pin)
4.75
Regulation Voltage
Current Limit (INTVCC Short)
INTVCC = 0V
5
50
5.25
V
mA
3744fa
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3
LT3744
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 2V, SGND = VEE = 0V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NMOS FET Drivers
Non-Overlap Time TG to BG
Non-Overlap Time BG to TG
50
ns
50
ns
Minimum On-Time BG
(Note 3)
50
ns
Minimum On-Time TG
(Note 3)
160
ns
Top Gate Driver Switch RON
Gate Pull Up
Gate Pull Down
VBOOST – VSW = 5V
3
1.5
Ω
Ω
Bottom Gate Driver Switch RON
Gate Pull Up
Gate Pull Down
VINTVCC = 5V
2.5
1.5
Ω
Ω
5
1.65
Ω
Ω
175
80
ns
ns
PWM Out Drivers
PWM_OUT Switch RON
Gate Pull Up
Gate Pull Down
VINTVCC = 5V, VFNEG = –15V
PWMX High To PWM_OUTX High Delay
PWMX Low To PWM_OUTX Low Delay
Oscillator
Switching Frequency Range
100
RT Pin Current Limit
1000
66
SYNC Input High
Referenced to SGND
SYNC Input Low
Referenced to SGND
SYNC Pin Current
SYNC = 2.0V
SYNC Range
Tested at 190kHz and 1.1MHz with RT = 422kΩ
kHz
μA
2.0
V
0.8
25
90
V
nA
900
kHz
Switching Frequency
fSW
RT = 40.2kΩ
RT = 422kΩ
l
950
95
1000
104
1050
120
kHz
kHz
PWM1 = 2V, SS, PWM2 and PWM3 = 0V
l
4.8
5
5.2
μA
l
240
250
260
mV
l
1.06
1.100
Soft-Start
Charge Current
Fault
Lower Fault Falling VFB Threshold
Lower Fault Rising VFB Hysteresis
30
Upper Fault Rising VFB Threshold
Upper Fault Falling VFB Hysteresis
Fault Voltage Low
–30
IFAULT = 2mA
Fault Leakage Current
mV
1.14
V
mV
0.1
V
50
nA
3744fa
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LT3744
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 2V, SGND = VEE = 0V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Regulation Amplifier
FB Pin Current
VFB = 1.2V
1.2
µA
600
gm
Feedback Regulation Voltage
l
1.169
1.205
μA/V
1.241
V
LED Current Control Loop gm Amplifier
Input Bias Current (LED_ISP and LED_ISN)
CTRL1 = 1.5V, PWM1 = 2V, PWM2, PWM3, LED_ISP
and LED_ISN = 0V
65
μA
Output Impedance
25
MΩ
gm
200
μA/V
5
kV/V
Differential Gain
C/10 Comparator
Falling Threshold
LED_ISN = 0V, Threshold = LED_ISP-LED_ISN,
CTRL1 = CTRL2 = CTRL3 = 2V
Rising Hysteresis
LED_ISN = 0V, Threshold = LED_ISP-LED_ISN,
CTRL1 = CTRL2 = CTRL3 = 2V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for an extended periods may affect device
reliability and lifetime.
Note 2: The LT3744E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
4.0
6
3.0
8.0
mV
mV
characterization and correlation with statistical process controls. The
LT3744I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 3: The minimum on and off times are guaranteed by design and are
not tested.
Note 4: Do not apply a positive or negative voltage to INTVCC, RT, VREF,
SS, TG, BG, PWM_OUT1, PWM_OUT2, or PWM_OUT3 pins, otherwise
permanent damage may occur.
3744fa
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5
LT3744
Typical Performance Characteristics
EN/UVLO Threshold (Falling)
EN/UVLO Hysteresis
EN/UVLO Pin Current
12
200
1.5
1.35
1.3
1.25
1.2
1.15
1.1
VIN = 3.3V
VIN = 12V
VIN = 36V
1.05
1.0
–50
–25
50
0
25
75
TEMPERATURE (°C)
100
160
120
80
40
0
–50
125
VIN = 3.3V
VIN = 12V
VIN = 36V
–25
0
25
75
50
TEMPERATURE (°C)
100
IQ (mA)
IQ (µA)
2
1.0
0.8
0.4
1.5
30
0
36
0
4
8
12
16 20
VIN (V)
3744 G04
VREF UVLO
24
28
32
1.97
–50
36
VIN = 3.3V
VIN = 12V
VIN = 36V
–25
0
50
75
25
TEMPERATURE (°C)
1.7
5
100
125
3744 G06
VREF Current Limit
6
125
1.99
3744 G05
1.8
100
2.0
1.98
T = 125°C
T = 25°C
T = –50°C
0.5
0.2
24
50
0
25
75
TEMPERATURE (°C)
2.01
1.0
0.6
–25
VREF
2.0
1.2
18
VIN (V)
4
2.02
2.5
1.4
12
6
3744 G03
VREF PIN VOLTAGE (V)
1.6
6
8
0
–50
125
3.0
T = 150°C
T = 25°C
T = –50°C
1.8
0
10
Quiescent Current
(Non-Switching)
IQ in Shutdown
2.0
VEN/UVLO = 1.2V
3744 G02
3744 G01
0
EN/UVLO PIN CURRENT (µA)
1.4
EN/UVLO HYSTERESIS (mV)
EN/UVLO THRESHOLD (V)
1.45
Soft-Start Pin Current
6.0
1.5
1.4
VIN = 3.3V
VIN = 12V
VIN = 36V
1.3
1.2
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3744 G07
4
3
2
T = 125°C
T = 25°C
T = –50°C
1
0
3
6
9 12 15 18 21 24 27 30 33 36
VIN (V)
3744 G08
SOFT START PIN CURRENT (µA)
VREF (V)
1.6
VREF CURRENT LIMIT (mA)
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
VIN = 3.3V
VIN = 12V
VIN = 36V
4.2
4.0
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
3744 G09
3744fa
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LT3744
Typical Performance Characteristics
VBOOST - VSW UVLO
(Falling Threshold)
3.5
2.95
3.4
2.9
3.3
2.85
3.2
2.8
2.75
2.7
2.65
2.6
2.55
2.5
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
1.2
3.1
3.0
2.9
2.8
VIN = 3.3V
VIN = 12V
VIN = 36V
2.6
2.5
–50
125
–25
0
50
75
25
TEMPERATURE (°C)
3744 G10
0.6
0.4
0.2
0.0
–50
125
65
5
0.8
60
4
0.4
INTVCC (V)
1.0
0
55
50
T = 125°C
T = 25°C
T = –50°C
0
100
200
300
400
FB PIN VOLTAGE (mV)
500
40
–50
VIN = 3.3V
VIN = 12V
VIN = 36V
–25
0
50
75
25
TEMPERATURE (°C)
3744 G13
INTVCC Current Limit
30
20
0
–50
VIN = 3.3V
VIN = 12V
VIN = 36V
–25
0
50
75
25
TEMPERATURE (°C)
0
125
100
125
3744 G16
0
10
20
30
40
50
INTVCC (mA)
1.2
290
1.18
280
1.16
270
1.14
260
250
240
230
VIN = 3.3V
VIN = 12V
VIN = 36V
210
200
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
70
Upper FAULT Threshold (Rising)
300
220
60
3744 G15
VFB PIN VOLTAGE (V)
VFB VOLTAGE (mV)
40
10
100
T = 130°C
T = 25°C
T = –50°C
1
Lower FAULT Threshold (Falling)
60
125
3
3744 G14
70
100
2
45
600
50
0
50
75
25
TEMPERATURE (°C)
INTVCC Load Regulation
RT Pin Current Limit
6
0.2
–25
3744 G12
70
IRT (µA)
NORMALIZED OSCILLATOR FREQUENCY
0.8
3744 G11
Frequency Foldback
INTVCC PIN CURRENT (mA)
100
1.0
1.2
0.6
200kHz
1MHz
1.4
2.7
VIN = 3.3V
VIN = 12V
VIN = 36V
Oscillator Frequency
FREQUENCY (MHz)
3.0
VBOOST - VSW (V)
INTVCC (V)
INTVCC UVLO (Falling Threshold)
125
3744 G17
VLED_ISP - VLED_ISN < 6mV
1.12
1.1
1.08
1.06
1.04
VIN = 3.3V
VIN = 12V
VIN = 36V
1.02
1.0
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
3744 G18
3744fa
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7
LT3744
Typical Performance Characteristics
Regulated Sense Voltage
ANALOG DIMMING LIMITED TO
VCTRLX = 75mV (20:1)
60
VLED_ISP - VLED_ISN (mV)
LED Current Regulation Accuracy
100
90
80
NUMBER OF UNITS
50
40
30
20
380 TYPICAL UNITS
VCTRL1 = 1.5V
70
60
50
40
30
380 TYPICAL UNITS
VCTRL1 = 0V
200
150
100
50
10
0
0
0.25 0.5 0.75 1.0 1.25 1.50 1.75 2.0
VCTRLx (V)
0
59
59.4
59.8
60.2
60.6
61
REGULATED VLED_ISP - VLED_ISN VOLTAGE (mV)
Feedback Voltage
3744 G21
VFB Load Regulation
SS "Finished” Threshold
4.00
1.0
NORMALIZED LOAD CURRENT (A/A)
1.225
VFB (V)
1.22
1.215
1.21
1.205
1.2
1.195
–50
–25
0
25
75
50
TEMPERATURE (°C)
100
3.90
3.80
0.8
SS PIN VOLTAGE (V)
1.235
1.23
0.6
0.4
3.30
3.00
–50
140
60
120
40
30
20
VIN = 3.3V
VIN = 12V
VIN = 36V
100
125
3744 G24
–25
50
0
25
75
TEMPERATURE (°C)
125°C
25°C
–45°C
125
Overcurrent Threshold
120
380 TYPICAL UNITS
110
RISING THRESHOLD
100
100
80
60
90
80
60
20
50
4.4 4.8 5.2 5.6 6.0 6.4 6.8 7.2
VLED_ISP - VLED_ISN C/10 THRESHOLD (mV)
3744 G25
FALLING THRESHOLD
70
40
0
100
3744 G23a
VISP - VISN (mV)
70
NUMBER OF UNITS
160
25
0
50
75
TEMPERATURE (°C)
3.40
Falling C/10 Threshold
80
–25
3.50
3744 G23
Average Current Regulation
During Start-Up
0
–50
3.60
3.10
3744 G22
10
3.70
3.20
0.2
0
1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235
VFB (V)
125
50
–300 –200 –100
0
100
200
300
REGULATED VLED_ISP - VLED_ISN VOLTAGE (µV)
3744 G20
3744 G19
VISP - VISN (mV)
125°C
25°C
–45°C
250
20
10
0
125°C
25°C
–45°C
LED Current Regulation Accuracy
300
NUMBER OF UNITS
70
40
–50
–25
25
0
50
75
TEMPERATURE (°C)
100
125
3744 G26
3744fa
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LT3744
Typical Performance Characteristics
1.5
1.52
1.4
RISING THRESHOLD
1.48
FALLING THRESHOLD
1.46
1.44
VPWMx PIN VOLTAGE (V)
1.54
1.5
VFB (V)
PWM1, PWM2, PWM3 Threshold
1.6
1.42
SYNC Threshold
1.6
1.5
RISING THRESHOLD
1.3
FALLING THRESHOLD
1.2
1.1
1
VSYNC PIN VOLTAGE (V)
OVLO Threshold
1.56
0.9
1.4
–50
–25
25
0
50
75
TEMPERATURE (°C)
100
–25
25
0
50
75
TEMPERATURE (°C)
100
3744 G27
PWM Driver RDS(ON)
1
–25
25
0
50
75
TEMPERATURE (°C)
100
125
3744 G29
Bottom Gate Driver RDS(ON)
Top Gate Driver RDS(ON)
2.5
3.5
PMOSRDS(ON)
PMOSRDS(ON)
PMOSRDS(ON)
3.0
2
2.5
4
3
NMOSRDS(ON)
1.5
RDS(ON) (Ω)
RDS(ON) (Ω)
RDS(ON) (Ω)
1.1
0.8
–50
125
5
NMOSRDS(ON)
1.0
2
2.0
1.5
NMOSRDS(ON)
1.0
0.5
1
–25
0
50
75
25
TEMPERATURE (°C)
100
0.5
0
–50
125
–25
0
50
75
25
TEMPERATURE (°C)
100
3744 G30
Non-Overlap PWM Signal Delay
55
NON-OVERLAP TIME (nsec)
220
200
190
180
170
160
25
0
50
75
TEMPERATURE (°C)
100
125
3744 G33
125
TG Minimum On-Time
50
HG TO LG DELAY
45
40
LG TO HG DELAY
35
30
20
–50
100
300
25
–25
25
0
50
75
TEMPERATURE (°C)
3744 G32
BG and TG Non-Overlap Time
60
210
–25
3744 G31
230
150
–50
0
–50
125
–25
25
0
50
75
TEMPERATURE (°C)
100
125
3744 G34
MINIMUM ON AND OFF TIME (nsec)
0
–50
DELAY (nsec)
FALLING THRESHOLD
1.2
3744 G28
7
6
1.3
0.9
0.8
–50
125
RISING THRESHOLD
1.4
250
200
MINIMUM ON-TIME
150
100
MINIMUM OFF-TIME
50
0
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
3744 G35
3744fa
For more information www.linear.com/LT3744
9
LT3744
Typical Performance Characteristics
LED Current Waveforms
(0A to 20A) 2000:1
LED Current Waveforms
(0A to 6.7A to 13.3A to 20A) 2000:1
ILED
16.7A/DIV
PWM1
5V/DIV
SW
5V/DIV
2.5µs/DIV
PWM1
5V/DIV
PWM2
5V/DIV
PWM3
5V/DIV
PWM1
5V/DIV
PWM2
5V/DIV
PWM3
5V/DIV
ILED
6.7A/DIV
ILED
6.67A/DIV
3744 G36
25µsec/DIV
LED Current Waveforms
(0A to 5A) 2000:1 Inverting
Buck-Boost Regulator
3744 G37
25µsec/DIV
PWM1
5V/DIV
PWM2
5V/DIV
SW
10V/DIV
IANODE
5A/DIV
VSW
5V/DIV
ILED
1.67A/DIV
VSW
10V/DIV
ILED
5A/DIV
IL
20A/DIV
VEE
5V/DIV
3744 G39
10µs/DIV
Voltage Regulation
3744 G38
LED Current Waveforms
(5000:1) 0A TO 20A Flicker-Free
Performance
LED Current Waveforms (0A to
10A) 1000:1 Inverting Regulator
PWM1
5V/DIV
2.5µs/DIV
LED Current Waveforms
(0A to 6.7A to 13.3A to 20A) 5000:1
3744 G41
3744 G40
1µsec/DIV - 5 MINUTE PERSISTENCE
LED_ISP – LED_ISN
Overvoltage Protection
Overcurrent
VSW
5V/DIV
VBG
5V/DIV
VSW
20V/DIV
VOUT
2V/DIV
IL
50A/DIV
ISENSE
33.3A/DIV
IL
5A/DIV
SW
5V/DIV
100µs/DIV
3744 G42
25µs/DIV
3744 G43
20µs/DIV
3744 G44
3744fa
10
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LT3744
Pin Functions
EN/UVLO (Pin 1): The EN/UVLO pin acts as a precision
enable and turns on the internal current bias core and
subregulators with a rising threshold of 1.30V and a falling threshold of 1.235V. The pin has a 4.8μA pull-down
current when below 1.235V. For normal operation, this
pin requires a voltage bias. Full shutdown occurs at approximately 0.5V and low IQ operations is guaranteed
below 0.3V. This pin is referenced to SGND.
CTRL1, CTRL2, CTRL3 (Pin 2, 4, 5): The voltage at the
CTRL pins set the regulated LED current. When PWM1
is high and PWM2 and PWM3 are low, CTRL1 is used.
When PWM2 is high and PWM3 is low, CTRL2 is used.
Whenever PWM3 is high, CTRL3 is used. The maximum
analog control is 1.5V providing 60mV regulated voltage
across the LED_ISP and LED_ISN sense resistor. The
analog dimming range using the CTRL pins is 20:1. This
means the lowest CTRL input for guaranteed operation is
75mV. At this VCTRL, the voltage between the LED_ISP and
LED_ISN pins will be regulated at 3mV ±500µV (±17%).
All CTRL pins are referenced to SGND.
VREF (Pin 3): VREF is a buffered 2.0V reference capable of
0.5mA drive. This pin is referenced to SGND. A minimum
capacitance of 2.2µF to SGND is required on this pin.
CTRLT (Pin 6): The voltage at the CTRLT pin limits the
regulated LED current whenever CTRLT is lower than
CTRL1, CTRL2 or CTRL3. This pin may be used for thermally limiting the LED current using an NTC resistor. The
CTRLT pin is referenced to SGND.
PWM1, PWM2, PWM3 (Pins 7, 8, 9): Pins PWM1, PWM2
and PWM3 are digital input pins that determine which of
the CTRL voltages are used to regulate the LED current
and which LEDs and/or capacitors are connected to the
output. All PWM input pins are referenced to SGND.
SYNC (Pin 10): Frequency Synchronization Pin. This pin
allows the switching frequency to be synchronized to an
external clock. The RT resistor should be chosen to operate the internal clock at 10% slower than the SYNC pulse
frequency. This pin should be grounded when not in use.
The SYNC pin is referenced to SGND.
FAULT (Pin 11): The FAULT pin indicates either an
overvoltage or shorted output. At FB voltages less than
250mV and greater than 1.1V (with VLED_ISP - VLED_ISN
less than 6mV), the FAULT pin is pulled low to SGND. The
pull-down impedance is 50Ω. The FAULT pin is referenced
to SGND.
SGND (Pin 12): System/Board Ground. All input pins are
referenced to SGND. VSGND-VEE may have a potential
difference of up to 20V. The voltage at the VEE pin should
never be higher than the voltage at the SGND pin. For
proper operation when configured as an inverting buckboost regulator, use a low VF Schottky diode between
VEE and SGND.
RT (Pin 13): A resistor to ground sets the switching frequency between 100kHz and 1.0MHz. This pin is current
limited to 66μA. Connect this pin through a resistor to
VEE only. Do not connect to SGND and do not leave this
pin open.
SS (Pin 14): Soft-Start Pin. Place a capacitor from this pin
to VEE to limit the start-up voltage ramp. The SS pin has
a 5μA charging current and is referenced to VEE.
LED_ISN (Pin 15): LED_ISN is the noninverting input
of the LED current sensing error amplifier. Connect this
pin to the lower terminal of an external current sense
resistor in series with the LED cathode or the source of
the LED disconnect FET (LED_ISN must be connected to
VEE). The voltage drop between LED_ISP and LED_ISN
is regulated to the current determined by the voltage of
the CTRL1, CTRL2 and CTRL3 pins. The LED_ISN pin is
referenced to VEE.
LED_ISP (Pin 16): LED_ISP is the inverting input of the
LED current sensing error amplifier. Connect this pin to the
upper terminal of the sense resistor in series with the LED
cathode. The voltage drop between LED_ISP and LED_ISN
is regulated to the current determined by the voltage at
the CTRL pins. The LED_ISP pin is referenced to VEE.
3744fa
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11
LT3744
Pin Functions
FB (Pin 17): Feedback Pin. The feedback regulation voltage
is 1.205V. The LT3744 will go into frequency foldback
at feedback voltages less than 0.4V and foldback to a
minimum of 10% of the normal switching frequency. If
the voltage between LED_ISP and LED_ISN is less than
6mV while the voltage on FB is greater than 1.1V, FAULT
is pulled low to SGND. Also, if the voltage on the FB pin
is less than 250mV, the FAULT pin is again pulled low
to SGND. If the FB voltage is less than 100mV, the BG
signal is disabled during overcurrent events. The FB pin
is referenced to VEE.
VC3, VC2, VC1 (Pins 18, 19, 20): VC3, VC2 and VC1 provide
the necessary compensation for the peak current loop
stability. Typical compensation values are 20kΩ to 40kΩ
for the resistor and 2.2nF to 10nF for the capacitor. The
VC pins are referenced to VEE.
ISN (Pin 21): ISN is the inverting input of the inductor
current sense gm amplifier. This pin is connected to an
external current sense resistor in series with the inductor.
The inductor current sense amplifier provides inductor
current information to the LT3744. The amplifier senses
inductor current with a common mode range of 0V to a
maximum of 36V. ISN and ISP are independent of VIN and
may go to a higher voltage than the supply of the LT3744.
ISP (Pin 22): ISP is the noninverting input of the inductor
current sense gm amplifier. This pin is connected to an
external current sense resistor in series with the inductor.
Inductor overcurrent is set at 110mV between the ISP and
ISN pins and has –35mV of hysteresis.
PWM_OUT3, PWM_OUT2, PWM_OUT1 (Pins 23, 25,
27): The PWM_OUT pins drive the gates of a external
NMOS FETs connected in series with output capacitors
or LED cathodes.
VFNEG (Pin 24): VFNEG is the negative supply voltage to
the PWM_OUT drivers. It is used with diodes to control
the gate of the PWM dimming FETs when the FETs are off.
The voltage at this pin may go to –15V below VEE.
VEE (Pins 26, 28, 33, 35, Exposed Pad Pin 37): VEE is
the LT3744 internal ground. All internal and driver output
signals are referenced to VEE. VEE and SGND may have a
voltage difference of up to –20V. The voltage at the VEE
pin should never be higher than the voltage at the SGND
pin. For step-down applications, connect VEE to SGND. For
inverting buck-boost applications, do not connect SGND
and VEE.The VEE exposed pad must be soldered to the
PCB. If VEE and SGND are isolated, the exposed pad must
not be on the same ground plane as SGND.
TG (Pin 29): TG is the top FET gate drive signal that controls
the state of the high side external power FET. The driver
pull-up impedance is 3Ω and pull-down impedance is 1.5Ω.
SW (Pin 30): The SW pin is used internally as the lower
supply rail for the floating high side driver. Externally,
this node connects the two power FETs and the inductor.
BOOST (Pin 31): The BOOST pin provides a floating 5V
regulated supply for the high side FET driver. An external
Schottky diode is required from the INTVCC pin to the
BOOST pin to charge the BOOST capacitor when the switch
pin is near ground.
BG (Pin 32): BG is the bottom FET gate drive signal that
controls the state of the low side external power FET. The
driver pull-up impedance is 2.5Ω and pull-down impedance is 1.5Ω.
INTVCC (Pin 34): A regulated 5V output (referenced to VEE)
for charging the BOOST capacitor. INTVCC also provides the
power for the digital and switching sub-circuits. INTVCC is
current limited to 50mA. Shutdown operation disables the
output voltage drive. Use a minimum of 10μF to bypass
this pin to VEE.
VIN (Pin 36): Input Supply Pin. Must be locally bypassed
with at least a 1μF low ESR capacitor to ground.
3744fa
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For more information www.linear.com/LT3744
LT3744
Block Diagram
VIN
402k
1
VIN
EN/UVLO
2.2µF
3
VREF
2V
REFERENCE
RESET
INTERNAL
REGULATOR
AND UVLO
1.5V
HIGH SIDE
DRIVER BOOST
FB
13
82.5k
10
2
VEE
4
5
6
110nA/%D
ISC
OSCILLATOR
RT
SYNC
CTRL1
–
TG
R
+
CTRL2
S
CTRL3
DISABLE
BG ENABLE
gm = 12µA/V
SW
SYNCHRONOUS
CONTROLLER
Q
PWM
COMPARATOR
CTRLT
BG
FB
–
1.5V
OVERCURRENT
COMPARATOR
–
9
60k
PWM LOGIC
S2
–
RO = 25MΩ
LED CURRENT
SENSE AMP
VC2
VEE
ISP
ISN
2.4k
LED_ISP
+
2.4k
LED_ISN
C/10
COMPARATOR
VC3
VEE
–
COMPENSATION
SWITCHES
VEE
14
VOLTAGE
REGULATION
AMP
SS
2.2nF
21
B
1µF
VEE
16
RSLED
6mΩ
15
220µF
220µF
1.2k
+ 6mV –
1.205V
FB
40.2k
17
8.25k
5µA
CHARGING
CURRENT
PWM_OUT1
RESET
VEE
27
VFNEG
VEE
–
VREF
1.1V
PWM_OUT2
PWM_OUT
DRIVER
PWM_OUT3
FB
FAULT
VFNEG
–
SGND
SGND
12
+
RESET
25
VFNEG
+
11
RS
10A
4mΩ
LED
220µF
VEE
133k
22
5µA
+
–
+
gm = 600µA/V
VC1
6.8nF
2.2µH
VEE
6.8nF
20
32
+
6.8nF
18
30
gm = 200µA/V
COMPENSATION
SWITCH
LOGIC
19
0.1µF
29
4.58k
–
INDUCTOR
CURRENT
SENSE AMP
S1
PWM3
31
+110mV–
gm = 100µA/V
PWM2
10µF
VEE
VEE
+
+
PWM1
VEE
+
CONTROL
CURRENT
BUFFER
8
100µF
24µA
1.65V
CURRENT
MIRROR
7
34
LOW SIDE
DRIVER
OVERVOLTAGE
COMPARATOR
–+++++
INTVCC
VIN
36
20µF
133k
23
24
0.25V
VEE
VEE
35
33
37
26
VEE
VEE
28
VEE
3744 F01
VEE
Figure 1. Block Diagram
3744fa
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13
LT3744
Operation
The LT3744 utilizes fixed frequency, peak inductor current mode control to accurately regulate the current in a
single externally switched LED, multiple parallel LEDs, or
a string of LEDs. The current control loop will regulate
the LED current at an accuracy of ±3% at 60mV when
the CTRL input is at 1.5V. If the output voltage reaches
the regulation voltage determined by the resistor divider
from the output to the FB pin and VEE, the peak inductor
current will be reduced by the voltage regulation loop. In
voltage regulation, the output voltage has an accuracy of
±3%. For additional operation information, refer to the
Block Diagram in Figure 1.
To provide maximum flexibility, the LT3744 may be used
to regulate negative output voltages in an inverting buckboost topology. This allows the use of a single lithium-ion
battery to drive a multi-LED string without the need to use
complex buck-boost or multiple converter topologies.
VEE is the internal ground of the LT3744 and SGND is the
system/board ground. All digital and analog input signals
are referenced to SGND. All digital, analog, and gate drive
output signals are referenced to VEE. SGND and VEE may
have a potential difference of up to 20V. The voltage at
the VEE pin should never be higher than the voltage at
the SGND pin.
The LED current control loop uses the reference current
determined by the voltage at the analog control pins:
CTRL1, CTRL2 and CTRL3. The analog dimming range
using the CTRL pins is 20:1. At 1.5V, the voltage between
the LED_ISP and LED_ISN pins will be regulated at 60mV.
The lowest CTRL input for guaranteed operation is 75mV. At
this VCTRL, the voltage between the LED_ISP and LED_ISN
pins will be regulated at 3mV ±500µV (±17%). Control
voltages above 1.65V have no effect on the regulated LED
current. The regulated LED current corresponds to the state
of the PWM1, PWM2 and PWM3 pins. When PWM1 is
high, and PWM2 and PWM3 are low, CTRL1 pin is used
as the current regulation reference, and PWM_OUT1 is
high. When PWM2 is high and PWM3 is low, CTRL2 pin is
used as the current regulation reference, and PWM_OUT2
is high. Whenever PWM3 is high, CTRL3 pin is used as
the current regulation reference, and PWM_OUT3 is high.
The LT3744 is designed to drive LEDs with fast rising
and falling edges. This includes transitioning between
multiple current states for color mixing, or between LEDs
with different forward voltages. By using three states,
the LT3744 may be used as a standalone driver for RGB
systems, or in high performance LED projectors where color
blending creates more pure colors. The rapid transition
between the three states is achieved with a switchedcapacitor topology, where each output capacitor stores
the forward voltage of each state so that returning to this
state is achieved quickly. Each of these capacitors must be
switched individually with drain-to-drain FETs. To prevent
the capacitor from discharging through the FET switches,
the bottom rail for the PWM_OUT drivers is provided on
the VFNEG pin. Schottky diodes connected from the negative terminal of the switched capacitors to the VFNEG pin,
allows the output capacitors to have up to 15V difference
between them. This allows the use of multiple LEDs in one
of the strings and single LEDs in the others.
A 2.0V external reference voltage is provided on the VREF pin
to allow the use of a resistor voltage divider to the CTRL1,
CTRL2, CTRL3 and CTRLT pins. Although the current limit
for VREF is set at 3mA, for accuracy, the load current on
the VREF pin should be limited to 0.5mA.
INTVCC provides a regulated 5V for internal circuitry and for
the gate driver. For stability, this pin should be bypassed
with at least a 10µF capacitor to VEE. The INTVCC pin is
current limited to 50mA. Please be aware that the current
limit on this pin is thermally derated for temperatures above
120°C. Do not use this pin to drive any external load. The
internal UVLO on the INTVCC pin prevents switching until
the voltage is higher than 2.9V.
The inductor overcurrent is set at 110mV between the ISP
and ISN pins and has –35mV hysteresis. The overcurrent
is limited on a cycle-by-cycle basis; shutting down the
high side gate once the overcurrent level is reached. If the
feedback voltage is less than 100mV during an overcurrent
event, the bottom gate is disabled, otherwise the bottom
FET will conduct current until the lower overcurrent limit
threshold is reached. The FAULT pin is asserted whenever
an overcurrent event occurs.
3744fa
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LT3744
Operation
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The voltage reference
at the FB pin is 1.205V. If the output voltage level is high
enough to engage the voltage loop, the peak inductor
current will be reduced to support the load at the output.
Whenever the voltage on the FB pin is less than 250mV,
the FAULT flag is asserted.
Whenever the FB pin is greater than 1.1V and the voltage
across the LED_ISP and LED_ISN pins less than 6mV,
the FAULT flag is asserted. If there is any internal fault
condition to the LT3744 (such as thermal shutdown or
UVLO), the FAULT flag is asserted.
For maximum efficiency, the BG driver is disabled whenever
the voltage across the LED_ISP and LED_ISN pins is less
than 6mV. For overvoltage protection, if VFB exceeds 1.5V,
the PWM_OUT drivers are turned off and switching stops.
The EN/UVLO pin functions as a precision shutdown
pin, with a 1.3V rising threshold and a 1.235V falling
threshold. Full shutdown is guaranteed below 0.3V with a
quiescent current of less than 1µA. In addition, when the
voltage at the EN/UVLO pin is less than 1.235V, a 4.8µA
pull-down current source is internally connected to this
pin. This current allows the amount of hysteresis to be
programmed with a series resistor to the EN/UVLO pin or
resistor divider from VIN.
During start-up (or after a reset event), the TG, BG and
PWM_OUT drivers are disabled until the first rising edge
of any of the PWM pins inputs. After this, all PWM_OUT
drivers are turned on to allow multiple capacitor topologies
to charge all of the capacitors at once. Soft-start is also
allowed to charge with a 5µA current source and switching
commences. During this start-up time, the average inductor
current is regulated to 48mV between the ISP and ISN
pins. Once the current in the LED/load (sensed by the
voltage across the LED_ISP and LED_ISN pins) reaches
15% of maximum (9mV), the PWM_OUT drivers connect
the correct LED to the output, corresponding to the state
of the PWM input pins. This avoids potentially long startup times and overshoot of the VC pin, causing potentially
damaging currents to flow into the LED. This start-up
scheme also avoids undesirably bright “start-up flash”
that is observed in many other high current LED drivers.
If the voltage between LED_ISP and LED_ISN does not
exceed 9mV before the SS (soft-start) pin voltage reaches
roughly 3.5V, then the startup sequence is terminated,
the correct LED is connected to the output, and normal
operation begins. This is required so that regulated LED_ISP
and LED_ISN voltages below 9mV are dimmed correctly
after soft-start has timed out. Soft-start ramps the internal
feedback voltage used in the voltage regulation loop. If
the output voltage is prebiased, the BG driver is disabled
until the voltage at the soft-start pin exceeds the voltage
at the feedback pin. This prevents high negative currents
from flowing in the bottom FET during a start-up recovery.
The thermal shutdown is guaranteed to be higher than
the operational temperature of the part. During thermal
shutdown, all switching is terminated, all PWM_OUT
signals are forced low, and the part is in reset (forcing
the SS pin low).
The switching frequency is determined by a resistor from
the RT pin to VEE. The RT pin is current limited to 66μA,
limiting the switching frequency to 2.4MHz when the RT pin
is shorted to VEE. The LT3744 may also be synchronized
to an external clock through the use of the SYNC pin. The
SYNC pin is referenced to SGND. When the voltage on the
FB pin decreases below 400mV, the switching frequency
is reduced linearly to a minimum of 10%.
3744fa
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15
LT3744
Applications Information
Programming LED Current
LED Current Regulation
The analog voltage at the CTRL pins are buffered and
produce a reference voltage, VCTRL, across an internal
resistor. The regulated LED current is determined by:
The regulation voltage across the LED_ISP and LED_ISN
pins is 60mV when there is 1.5V at the corresponding
control pin. When PWM1 is high with a low on PWM2
and PWM3, the voltage at the CTRL1 pin is used as the
reference for the regulated LED current. When PWM2 is
high with a low on PWM3, the voltage at the CTRL2 pin
is used as the reference for the regulated LED current.
Whenever PWM3 is high, the voltage at the CTRL3 pin is
used. During start-up, or a recovery from a fault condition,
the inductor current is regulated at 80% of maximum
current (48mV between ISP and ISN) until the voltage
between LED_ISP and LED_ISN is greater than 9mV or
the voltage at the soft-start pin has reached 3.5V. This will
prevent excessive current overshoot in the LED when it
begins conducting. Also, whenever the voltage between
LED_ISP and LED_ISN is lower than 6mV, the bottom
gate (BG) is disabled, improving low current efficiency.
ILED =
VCTRL
25 • RSLED
where RSLED is the external sense resistor in series with
the LED cathode and ILED is the LED current. Figure 2
shows the maximum LED current vs RSLED.
Table 1 lists several resistance values and the corresponding maximum LED current and sense resistor power dissipation. The accuracy of the LED sense resistor is very
important. Susumu, Panasonic and Vishay offer accurate
sense resistors. The accuracy of the inductor current sense
resistor is not as critical and lower accuracy resistors
may be used.
The analog voltage at the CTRL pins adjusts the regulated LED current, Figure 3 shows the regulated voltage
across the sense resistor for control voltages up to 2V.
The LT3744 utilizes a highly accurate regulation scheme
to achieve ±1.8mV regulation accuracy across the LED
sense resistor at 60mV and ±500μV at 3mV. This high accuracy allows up to 20:1 analog dimming ratios. A resistor
divider from VREF to the CTRL pins may be used. When
sizing the resistor divider, please be aware that the VREF
pin is current limited to 0.5mA, and that above 1.65V, the
control voltage has no effect on the regulated LED current.
MAXIMUM OUTPUT CURRENT (A)
35
30
25
20
15
10
5
0
0
2
4
6
8 10 12 14 16 18 20
RSLED (mΩ)
70
3744 F02
Figure 2. RSLED Value Selection for Regulated Output Current
MAXIMUM LED
CURRENT (A)
RESISTOR, RSLED
(mΩ)
POWER DISSIPATION
(W)
1
60
0.06
5
12
0.3
10
6
0.6
20
3
1.2
LED_ISP-LED_ISN (mV)
Table 1. Sense Resistor Values
ANALOG DIMMING LIMITED TO
VCTRLX = 75mV (20:1)
60
50
40
30
20
10
0
0
0.25 0.5 0.75 1.0 1.25 1.50 1.75 2.0
VCTRLx (V)
3744 F03
Figure 3. Sense Voltage vs CTRL Voltage
3744fa
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LT3744
Applications Information
Inductor Selection
Inductor sizing depends on circuit topology. The LT3744
may be used in a step-down configuration, producing positive voltages, or in an inverting buck-boost configuration,
producing negative voltages with respect to supply ground.
For step-down applications, size the inductor so that the
peak-to-peak ripple current is approximately 30% of the
output current. The following equation sizes the inductor
for best performance in a step-down application:
V •V –V 2
LSTEP−DOWN = IN LED LED
0.3 • fSW •ILED • VIN
where VLED is the LED forward voltage, VIN is the input
voltage, IO is the maximum regulated current in the inductor and fSW is the switching frequency. The peak current
in a step-down application is:
V •V –V 2
IL(PEAK _ STEP–DOWN)= IN LED LED + ILED
2 • fSW • L • VIN
The inductor saturation current should be equal or higher
than the peak current. For inverting buck-boost applications, use the following equation to size the inductor for
best performance:
VIN • VLED
LINVERTING =
0.3 • fSW •IO • ( VIN + VLED )
The peak current for inverting buck-boost applications
will be:
VIN • VLED
IL(PEAK _INVERTING) =
2 • fSW • L • ( VIN + VLED )
V +V
+ IN LED • 1.2 •ILED
VIN
The overcurrent comparator terminates switching when the
voltage between the ISP and ISN pins exceeds 110mV. If
this occurs, and the FB pin voltage is higher than 100mV,
BG will be high, allowing the inductor current to decrease.
Once the voltage across the ISP and ISN sense pins has
decreased below 75mV, normal switching will resume.
During overcurrent, if the FB pin voltage is lower than
100mV, BG is turned off, allowing the inductor current
to discharge through the body diode of the bottom FET.
Recommended inductor manufacturers are listed in Table 2.
Table 2. Recommended Inductor Manufacturers
VENDOR
WEBSITE
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Vishay
www.vishay.com
Würth Electronics
www.we-online.com
NEC-Tokin
www.nec-tokin.com
Switching MOSFET Selection
The following parameters are critical in determining the
best switching MOSFETs for a given application: total gate
charge (QG), on-resistance (RDS(ON)), gate-to-drain charge
(QGD), gate-to-source charge (QGS), gate resistance (RG),
breakdown voltages (maximum VGS and VDS) and drain
current (maximum ID). The following guidelines provide
information to make the selection process easier, and
Table 3 lists some recommended parts and manufacturers.
For both switching MOSFETs the rated drain current should
be greater than the maximum inductor current, either
IL(PEAK_STEP-DOWN) or IL(PEAK_INVERTING) (see Inductor
Selection section).
The rated drain current is temperature dependent and
most MOSFET data sheets include a table or graph of the
rated drain current vs temperature. Use this information to
properly derate the delivered current using the CTRLT pin
(see Load Current Derating Using the CTRLT Pin section).
The rated VDS should be higher than the maximum input
voltage (including transients) for both MOSFETs. The
signals driving the gates of the switching MOSFETs have
a maximum voltage of 5V with respect to the source.
However, during start-up and recovery conditions, the
gate-drive signals may be as low as 3V. Therefore, to
ensure that the LT3744 recovers properly, the maximum
threshold voltage should be less than 2V, and for a robust
design, ensure that the rated VGS is greater than 7V.
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17
LT3744
Applications Information
Power losses in the switching MOSFETs are related to the
on-resistance, RDS(ON); gate resistance, RG; gate-to-drain
charge, QGD and gate-to-source charge, QGS. Power lost to
the on-resistance is an ohmic loss, I2RDS(ON), and usually
dominates for input voltages less than 15V. Power lost
while charging the gate capacitance dominates for input
voltages greater than 15V. When operating at higher
input voltages, efficiency can be optimized by selecting
a high side MOSFET with higher RDS(ON) and lower QG.
The total power loss in the high side MOSFET can be approximated by:
6
MOSFET POWER LOSS (W)
5
4
3
TOTAL
2
0
PLOSS = (Ohmic Loss) + ( Transition Loss)
PLOSS
TRANSITIONAL
1
OHMIC
0
10
20
VIN (V)
30
40
3744 F04a
Figure 4a. Power Loss Example for M1
V
≈ O •IO2 • RDS(ON) • ρT +
VIN
4.0
3.5
MOSFET POWER LOSS (W)
VIN •IOUT
• ((QGD + QGS ) • (2 • RG +RPU +RPD )) • fSW
5V
where ρT is a dimensionless temperature-dependent factor
in the MOSFET’s on-resistance. Using 70°C as the maximum ambient operating temperature, ρT is roughly equal
to 1.3. RPD and RPU are the LT3744 high side gate-driver
output impedance: 1.5Ω and 3Ω, respectively.
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The trade-off
between RDS(ON), QG, and QGS for the high side MOSFET
is evident in the following example. VO is equal to 4V, IO
is equal to 10A, and the switching frequency is 500kHz.
The following N-channel MOSFETs are rated for a VDS of
40V and have the same package, but with 8× different
RDS(ON) and 4.5× different QG and QGD:
M1: RDS(ON) = 2.3mΩ, QG = 45.5nC, QGS = 13.8nC,
QGD = 14.4nC, RG = 1Ω
M2: RDS(ON) = 18mΩ, QG = 10nC, QGS = 4.5nC,
QGD = 3.1nC, RG = 3.5Ω
Power loss for M1 is shown in Figure 4a where nearly all
of the losses are transitional. Power loss for M2 is shown
in Figure 4b. For M2, the ohmic losses dominate at low
VIN, and transitional loss dominant at higher VIN.
3.0
2.5
TOTAL
2.0
TRANSITIONAL
1.5
1.0
OHMIC
0.5
0
0
10
20
30
40
VIN (V)
3788 F04b
Figure 4b. Power Loss Example for M2
Power loss within the low side MOSFET is entirely from
the RDS(ON) of the FET. Select the low side FET with the
lowest RDS(ON) while keeping the total gate charge, QG to
30nC or less.
Table 3. Recommended Switching FETs
VIN VLED ILED
(V) (V) (A)
8
4
TOP FET
12 2-4 10
FDMS8680
26
Si7884BDP
4
BOTTOM FET
MANUFACTURER
10 BSC010NE2LSI BSC018N04LS Infineon
www.infineon.com
20
FDMS8672AS Fairchild
www.fairchildsemi.com
SiR470DP
Vishay
www.vishay.com
3744fa
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LT3744
Applications Information
PWM Dimming
VOUT
The LT3744 has versatile dimming that accommodates many
different PWM dimmed LED applications. This includes
traditional PWM dimming with a single LED and a singlecurrent level (Figure 5), shunt dimming (Figure 6), PWM
dimming between three different currents with a single LED
(Figure 7), or PWM dimming with three individual LEDs all
at different regulated currents (Figures 8 and 9). When all
three PWM input signals are low, no switching occurs and
all three PWM_OUT signals are held low (to VFNEG). After
startup or a recovery from a fault condition (UVLO, Thermal
Shutdown, etc.), on the first rising edge of any PWM input
signal, switching begins, the Soft-Start capacitor is allowed
to charge, and all PWM_OUT signals are held high. During
this recovery time, the PWM input signals are ignored and
the inductor current is regulated at 80% of the maximum
output current (48mV between ISP and ISN). This allows
the output capacitors to rapidly charge. The startup cycle
is terminated when the voltage across the LED_ISP and
LED_ISN input reaches 9mV or when the Soft-Start voltage
reaches approximately 3.5V.
220µF
220µF
220µF
PWM_OUT1
LT3744
PWM_OUT2
PWM_OUT3
VFNEG
LED_ISP
3mΩ
LED_ISN
3744 F07
Figure 7. Driving a Single LED with Multiple Different
Current Levels
VOUT
220µF
220µF
VOUT
220µF
LT3744
PWM_OUT1
PWM_OUT2
PWM_OUT3
NC
NC
PWM_OUT1
220µF
LED_ISP
LT3744
3mΩ
PWM_OUT2
LED_ISN
VFNEG
3744 F05
Figure 5. Driving a Single LED
PWM_OUT3
VFNEG
VOUT
LT3744
PWM_OUT1
PWM_OUT2
PWM_OUT3
–15V
LED_ISP
3mΩ
LED_ISN
NC
NC
2.2µF
LED_ISP
3744 F08
Figure 8. Driving Multiple LEDs from the Same Output Using
a –15V Supply on VFNEG
3mΩ
LED_ISN
VFNEG
3744 F06
Figure 6. Shunt Dimming
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19
LT3744
Applications Information
Table 4 shows the PWM_OUT driver logic.
Switched Capacitor and PWM Dimming MOSFET
Selection
Table 4. PWM_OUT Driver Logic Truth Table
PWM3
0
0
0
0
1
1
1
1
PWM2
0
0
1
1
0
0
1
1
PWM1
0
1
0
1
0
1
0
1
PWM_OUT3
Low
Low
Low
Low
High
High
High
High
PWM_OUT2
Low
Low
High
High
Low
Low
Low
Low
PWM_OUT1
Low
High
Low
Low
Low
Low
Low
Low
The VFNEG pin is the negative rail for the PWM_OUT drivers. When dimming with multiple current levels, or with
multiple different LEDs, the use of Schottky diodes or an
additional negative supply is required to allow the negative
drive voltage to go below the power ground. This is needed
to eliminate a leakage path for the output capacitors and
allow the fastest LED current recovery time.
VOUT
220µF
220µF
220µF
PWM_OUT1
LT3744
PWM_OUT2
PWM_OUT3
The rated VDS for the switched capacitor and PWM dimming MOSFETs should be higher than the maximum
output voltage. Although this permits a MOSFET choice
with a smaller QG specification than that of the switching
MOSFETs, it will have little affect on efficiency because
the PWM switching frequency will be much lower than
the driver switching frequency. Power lost charging the
gate of these MOSFETs will be much lower than the power
lost charging the switching MOSFETs. RDS(ON) conduction
losses in these MOSFETs will also be much smaller if the
duty cycle of the PWM signal is very low. When the LT3744
is configured to produce negative voltages, additional onresistance will produce large amounts of ripple current in
the LED. For configurations producing negative voltages,
choose MOSFETs with the lowest available RDS(ON).
The switched capacitor and PWM dimming MOSFETs are
driven with a maximum positive gate voltage of 5V, limited
by the INTVCC pin. This requires that the threshold of the
MOSFETs is lower than 2V. The maximum negative gate
drive voltage is limited by the voltage at the VFNEG pin.
When the LT3744 is configured to drive LED loads with
large differences in output voltages, the gate of these
MOSFETs must be able to handle a maximum negative
voltage equal in magnitude to the maximum output voltage
without damage. As an example, if the maximum LED load
voltage is 10V, the MOSFETs must survive –10V from gate
to source/body. Please be aware that many MOSFETs have
maximum VDS ratings that are higher than the maximum
VGS rating. This means that the maximum VGS rating should
be used as the limiting voltage when selecting switched
capacitor and PWM dimming MOSFETs.
Table 5. Recommended PWM MOSFETs
VFNEG
LED_ISP
3mΩ
LED_ISN
MAXIMUM ILED
VLED (V) (A)
PWM MOSFET
(DUAL
PACKAGE)
COMMENTS
12
6
FDMB2307NZ
Common
Drain
Fairchild
www.fairchildsemi.com
12
8
Si7900AEDN
Common
Drain
Vishay
www.vishay.com
12
6
PHKD6N02LT
Dual
Package
SO8
NXP/Philips
www.nxp.com
3744 F09
Figure 9. Driving Multiple LEDs from the Same
Output Using Schottky Diodes For VFNEG
MANUFACTURER
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LT3744
Applications Information
Programming Switching Frequency
The LT3744 has a switching frequency range between
100kHz and 1MHz. This frequency is programmed with an
external resistor from the RT pin to VEE. Do not leave this
pin open under any condition. The RT pin is also current
limited to 66µA. See Table 6 and Figure 10 for resistor
values and the corresponding switching frequencies.
Table 6. Switching Frequency
SWITCHING FREQUENCY (MHz)
RT (kΩ) - 1%
1.00
40.2
0.75
53.6
0.50
82.5
0.30
143
0.10
453
1.2
of these specified parameters will cause erratic switching
behavior and subharmonic oscillations. Synchronization
is tested at 190kHz and 1.1MHz with a 422k RT resistor.
Operation under other conditions is guaranteed by design.
When synchronizing to an external clock, please be aware
that there will be a fixed delay from the input clock edge to
the edge of the signal at the SW pin. The SYNC pin must
be grounded if the synchronization to an external clock
is not required. When SYNC is grounded, the switching
frequency is determined by the resistor RT.
Frequency Foldback
To minimize erratic switching for low output voltages, the
switching frequency is linearly decreased from 100% to
a minimum of 10%, when the FB pin voltage is linearly
decreased from 400mV to 0V as shown in Figure 11.
This will provide a minimum of 50kHz when the desired
switching frequency is 500kHz.
120
0.8
0.6
0.4
0.2
0
0
50 100 150 200 250 300 350 400 450 500
RT (kΩ)
3744 F10
Figure 10. Frequency vs RT Resistance
OSCILLATOR FREQUENCY (%)
FREQUENCY (MHz)
1.0
100
80
60
40
20
0
0
200
400
600
800
1000
FEEDBACK VOLTAGE (mV)
1200
3744 F11
Switching Frequency Synchronization
Figure 11. Frequency Foldback
The internal oscillator may be synchronized to an external
clock through the SYNC pin. The external clock applied
to the SYNC pin must have a logic low below 0.8V and a
logic high above 2.0V. The input frequency must be 10%
higher than the frequency that would otherwise be determined by the resistor at the RT pin. Input signals outside
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21
LT3744
Applications Information
Input Capacitor Selection
INTVCC Capacitor Selection
The input capacitor should be sized at 10µF for every 1A
of output current and placed between VIN and SGND very
close to the high side MOSFET. It should have a ripplecurrent rating equal to half of the maximum output current. Additionally, a small 1µF ceramic capacitor should
be placed between VIN and VEE as close as possible to the
VIN pin and the exposed pad of the package for optimal
noise immunity.
The bypass capacitor for the INTVCC pin should be larger
than 10µF to ensure stability, and it should be connected
as close as possible to the exposed pad (VEE) underneath
the package. It is recommended that the ESR be lower
than 50mΩ to reduce noise within the LT3744. For driving MOSFETs with gate charges larger than 10nC, use
1µF/nC of total gate charge.
It is recommended that several low ESR (equivalent series
resistance) ceramic capacitors be used as the input capacitance. Use only X5R or X7R capacitors as they maintain
their capacitance over a wide range of operating voltages
and temperatures.
CBOOT Capacitor Selection
The CBOOT capacitor must be sized less than or equal to
220nF and more than 50nF to ensure proper operation of
the LT3744. Use 220nF for high current switching MOSFETs
with high gate charge.
Output Capacitor Selection
The output capacitors need to have very low ESR to reduce
output ripple. The minimum size of the output capacitor
should use the following equation:
1MHz
COUT_ MIN = (IOUT • 8µF/A ) •
fSW
In this equation, IOUT is the maximum load current, and fSW
is the switching frequency. The capacitors also need to be
surge-rated to the maximum output current. To achieve the
lowest possible ESR, several low ESR capacitors should
be used in parallel. Many applications benefit from the
use of high density POSCAP capacitors, which are easily
destroyed when exposed to overvoltage conditions. To
prevent this, select POSCAP capacitors that have a voltage
rating that is at least 50% higher than the regulated voltage. When using switched output capacitors, an additional
small capacitor connected from the LED Anode to VEE is
required. Size this capacitor at a maximum of 1/100th of
the switched capacitor size.
Soft-Start
The LT3744 utilizes the soft-start function to control the
regulated output voltage. The charging current is 5µA and
reduces the output voltage as long as the SS pin voltage
is lower than the reference voltage of 1.205V. In a fault
condition, (including thermal shutdown, or UVLO from
either VIN, INTVCC or VREF) the soft-start pin is discharged
to VEE. When the fault condition no longer exists, the softstart pin is allowed to charge. Whenever the voltage at the
feedback pin is higher than the soft-start pin (a prebiased
output) the BG driver is disabled, preventing large negative
inductor currents on a recovery from a fault condition.
Common-Anode LED Applications
The unique drive stage used on the LT3744 allows the
anodes of three LEDs to be connected together – where the
forward voltages may be up to 15V away from each other
(allowing multiple LEDs in a single string to be connected to
the same common point as a single LED). This connection
will work in both inverting buck-boost and noninverting
step down regulators. Some of the advantages using the
noninverting topology is that the efficiency will be higher
- typically by 5% to 10% depending on step-down ratio
and regulated current; the inductor current will be less (in
the inverting buck-boost configuration, inductor current
is only delivered to the load on the “off” cycle); the LED
current recovery time is faster (since the inductor current
is delivered to the load constantly in the noninverting
configuration); and the control loop bandwidth could be
5-times faster than the inverting buck-boost topology.
Some of the disadvantages of the noninverting topology
are that the output voltage is limited to less than the supply,
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LT3744
Applications Information
the common-anode voltage will change depending on the
LED load (LED color, forward voltage, regulated current,
number of LEDs, etc.) – where the heat sink for the LEDs
must be electrically isolated from chassis ground. The
differences between the configurations are summarized
in table 7.
Table 7. Comparison Between Noninverting and Inverting BuckBoost Common-Anode Configurations
Topology
Max. Efficiency
Inductor Current
Loop Bandwidth
ILED Recovery Time
Max VOUT
Heat sink
Noninverting
Step-Down
90-95%
ILED
fSW/5
2/fSW
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