LT6301IFE#TRPBF

SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVERS FEATURES • • • • • • • • • Sixteen Low-Voltage Differential Transceivers. Designed for Signaling Rates up to 200 Mbps per Receiver or 650 Mbps per Transmitter. Simplex (Point-to-Point) or Half-Duplex (Multipoint) Interface Typical Differential Output Voltage of 340 mV Into a 50-Ω Load Integrated 110-Ω Line Termination on 'LVDM1677 Product Propagation Delay Time: – Driver: 2.5 ns Typ – Receiver: 3 ns Typ Driver is High Impedance When Disabled or With VCC < 1.5 V for Power Up/Down Glitch-Free Performance and Hot-Plugging Events Bus-Terminal ESD Protection Exceeds 12 kV Low-Voltage TTL (LVTTL) Logic Input Levels Are 5-V Tolerant Packaged in Thin Shrink Small-Outline Package With 20 mil Terminal Pitch DESCRIPTION The SN65LVDM1676 and SN65LVDM1677 (integrated termination) are sixteen differential line transmitters or receivers (tranceivers) that use low-voltage differential signaling (LVDS) to achieve signaling rates up to 200 Mbps per transceiver configured as a receiver and up to 650 Mbps per transceiver configured as a transmitter. These products are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers are doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50-Ω load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver. SN65LVDM1676DGG ( Marked as LVDM1676) SN65LVDM1677DGG (Marked as LVDM1677) (TOP VIEW) GND VCC VCC GND ATX/RX A1A A2A A3A A4A BTX/RX B1A B2A B3A B4A GND VCC VCC GND C1A C2A C3A C4A CTX/RX D1A D2A D3A D4A DTX/RX GND VCC VCC GND 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 A1Y A1Z A2Y A2Z A3Y A3Z A4Y A4Z B1Y B1Z B2Y B2Z B3Y B3Z B4Y B4Z C1Y C1Z C2Y C2Z C3Y C3Z C4Y C4Z D1Y D1Z D2Y D2Z D3Y D3Z D4Y D4Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2007, Texas Instruments Incorporated SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of transceivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) The SN65LVDM1676 and SN65LVDM1677 are characterized for operation from –40°C to 85°C. FUNCTION TABLE (1) INPUTS (1) OUTPUTS (Y – Z) TX/RX A Y Z A VID≥ 100 mV L NA Z Z H –100 mV < VID < 100 mV L NA Z Z ? VID ≤ -100 mV L NA Z Z L Open circuit L NA Z Z H NA H L L H Z NA H H H L Z H = high level, L= low level, Z= high impedance, ? = indeterminate LVD Transceiver A Y Z TX/RX 2 Submit Documentation Feedback SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 LOGIC DIAGRAM (POSITIVE LOGIC) A1A A1Y B1A A1Z A2A A2Y B1Z B2A A2Z ATX/RX A3A BTX/RX A3Y B3A A4Y C1Y B4A C2Y D1A C3A D2A D2Y D2Z DTX/RX C3Y D3A C3Z C4A D1Y D1Z C2Z CTX/RX B4Y B4Z C1Z C2A B3Y B3Z A4Z C1A B2Y B2Z A3Z A4A B1Y C4Y D3Y D3Z D4A C4Z Submit Documentation Feedback D4Y D4Z 3 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 Ω A, TX/RX Input 10 kΩ 5Ω Y or Z Output 7V 300 kΩ 7V VCC VCC 300 kΩ 300 kΩ 5Ω A Output Z Input Y Input 7V 7V 110 Ω ’LVDM1677 Product Only 4 Submit Documentation Feedback 7V SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) RATING VCC Supply voltage range VI Input voltage range |VID| Differential input voltage magnitude, (SN65LVDM1677 only) IO Receiver output current PD Continuous power dissipation ESD (1) (2) (3) –0.5 V to 4 V Electrostatic discharge A, TX/RX –0.5 V to 6 V Y or Z –0.5 V to 4 V 1V ±20 mA (3) See the Dissipation Rating Table Y, Z, and GND Class 3, A: 8 kV, B: 600 V All Pins Class 3, A: 7 kV, B: 500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING DGG 2094 mW 16.7 mW/°C 1089 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage 0.8 0.1 ŤV Ť ID 2 0.6 Receiver low-level output current IOH Receiver high-level output current TA Operating free-air temperature ID 2 (1) 8 –8 (1) –40 V ŤV Ť 2.4 – VCC–0.8 IOL UNIT 85 V mA °C The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. Submit Documentation Feedback 5 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ( 1) MAX 140 175 45 60 340 454 UNIT DRIVER ICC Driver enabled, receiver disabled RL = 50 Ω ('LVDM1676) or RL = 100 Ω ('LVDM1677) Supply current Driver disabled, receiver enabled, no load RL = 50 Ω ('LVDM1676) or RL = 100 Ω ('LVDM1677), See Figure 2 and Figure 1 |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(S Change in steady-state common-mode output voltage between logic states S) RL = 50 Ω ('LVDM1676) or RL = 100 Ω ('LVDM1677), See Figure 3 247 mA mV –50 50 1.125 1.37 5 –50 50 mV 50 150 mV V VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current VIH = 2 V 3 20 µA IIL Low-level input current VIL = 0.8 V 2 10 µA IOS Short-circuit output current VOY or VOZ = 0 V 10 mA VOD = 0 V 10 mA IO(OFF) Power-off output current VCC = 1.5 V, 10 µA CIN Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V VO = 2.4 V –10 5 pF RECEIVER Positive-going differential input voltage threshold VIT+ VIT– Negative-going differential input voltage threshold VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA II Input current (Y or Z inputs) IID (1) Power-off input current (Y or Z inputs) mV –100 2.4 V 0.4 VIY = VIZ = 0 V –40 VIY = VIZ = 2.4 V 'LVDM1676 VIY = 0 V and VIZ = 100 mV, VIY = 2.4 V and VIZ = 2.3 V 'LVDM1677 VIY = 0.2 V and VIZ = 0 V, VIY = 2.4 V and VIZ = 2.2 V Differential input current |IIY– IIZ| (inputs) II(OFF) 6 100 See Figure 6 and Table 1 VCC = 0 V, VI = 2.4 V All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback –24 V µA –8 –1.2 5 10 µA 1.5 2.2 mA –25 25 µA SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DRIVER tPLH Propagation delay time, low-to-high-level output 1.3 2.5 3.6 tPHL Propagation delay time, high-to-low-level output 1.3 2.5 3.6 tr Differential output signal rise time 0.5 1.2 tf Differential output signal fall time 0.5 1.2 tsk(p) Pulse skew (|tPHL - tPLH|) 0.1 0.6 tsk(o) Channel-to-channel output skew (2) 0.1 0.4 tsk(pp) Part-to-part skew (3) tPZH Propagation delay time, high-impedance-to-high-level output 11 20 tPZL Propagation delay time, high-impedance-to-low-level output 10 20 tPHZ Propagation delay time, high-level-to-high-impedance output 3 10 tPLZ Propagation delay time, low-level-to-high-impedance output 3 10 RL = 50 Ω ('LVDM1676) or RL = 100 Ω ('LVDM1677), CL = 10 pF, See Figure 4 ns 1 See Figure 5 RECEIVER tPLH Propagation delay time, low-to-high-level output 1.5 3 4.5 tPHL Propagation delay time, high-to-low-level output 1.5 3 4.5 tr Output signal rise time 0.6 1.6 tf Output signal fall time 0.6 1.6 tsk(p) Pulse skew (|tPHL– tPLH|) 0.2 0.8 0.7 1.2 CL = 10 pF, See Figure 7 skew (4) tsk(o) Channel-to-channel output tsk(pp) Part-to-part skew (5) tPZH Propagation delay time, high-impedance-to-high-level output 9 15 tPZL Propagation delay time, high-impedance-to-low-level output 8 15 tPHZ Propagation delay time, high-level-to-high-impedance output 12 20 tPLZ Propagation delay time, low-level-to-high-impedance output 11 20 (1) (2) (3) (4) (5) ns 1 See Figure 8 All typical values are at 25°C and with a 3.3-V supply. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback 7 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION IOY Y II IOZ Z VOD VOY VOC VI (VOY + VOZ)/2 VOZ Figure 1. Driver Voltage and Current Definitions 3.75 kΩ Y VOD Input Z RL 3.75 kΩ ± 0 V ≤ VTEST ≤ 2.4 V Figure 2. Driver VOD Test Circuit Y RL/2 (2 Places) 3V A 0V Input Z VOC(PP) VOC(SS) VOC CL = 10 pF (2 Places) VOC NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 8 Submit Documentation Feedback SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) 3V VCC/2 Input tpLH Y Input Z VOD 0V tpHL 100% 80% RL VOD(H) Output CL = 10 pF (2 Places) 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal RL/2 (2 Places) Y 0.8 V or 2 V Z CL = 10 pF (2 Places) TX/RX VOY VOZ + – 1.2 V 3V VCC/2 0V TX/RX tpZH tpHZ @ 1.4 V 1.25 V 1.2 V VOY or VOZ tpZL tpHZ 1.2 V 1.15 V @1V VOZ or VOY NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 5. Enable and Disable Time Circuit and Definitions Submit Documentation Feedback 9 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) IIY IIZ (VIY + VIZ)/2 Y VID IO A Z VIY VIC VO VIZ Figure 6. Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES RESULTING COMMONMODE INPUT VOLTAGE VIY VIZ VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V VID VIY 1.4 V VIZ 1V VID 0.4 V 0V VIY VIZ CL = 10 pF VO –0.4 V tpHL VO tpLH ~VCC 80% VCC/2 ~0V 20% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 7. Timing Test Circuit and Waveforms 10 Submit Documentation Feedback SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 1.2 V Z 500 Ω A Y 10 pF VO ± VTEST TX/RX NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST Y 1V 3V VCC/2 0V TX/RX tpLZ tpZL 2.5 V VCC/2 A VOL + 0.5 V VOL 0V VTEST Y 1.4 V 3V VCC/2 0V TX/RX tpHZ tpZH A VOH VCC/2 VOH – 0.5 V 0V Figure 8. Enable/Disable Time Test Circuit and Waveforms Submit Documentation Feedback 11 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 VIC − Common-Mode Input Voltage − V VCC > 3.15 V VCC = 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|− Differential Input Voltage − V Figure 9. DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C V OH− High-Level Output Voltage − V V OL − Low-Level Output Voltage − V VCC = 3.3 V TA = 25°C 3 2 1 0 3 2.5 2 1.5 1 .5 0 0 2 4 6 8 10 12 0 IOL − Low-Level Output Current − mA Figure 10. 12 −2 −4 Figure 11. Submit Documentation Feedback −6 IOH − High-Level Output Current − mA −8 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 5 VCC = 3.3 V TA = 25°C VOL − Low-Level Output Votlage − V VOH − High-Level Output Voltage − V VCC = 3.3 V TA = 25°C 3 2 1 0 4 3 2 1 0 0 −20 −40 −60 IOH − High-Level Output Current − mA −80 0 Figure 12. 20 40 60 IOL − Low-Level Output Current − mA 80 Figure 13. Submit Documentation Feedback 13 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) DRIVER EYE PATTERN TEST CONDITIONS • • • • VCC = 3.6 V TA = 25°C (ambient temperature) All 16 channels switching simultaneously with NRZ data. Scope is triggered at the same frequency with pulse. Input signal level = 0 V to 3 V single ended. Resistive loading with no added capacitance EQUIPMENT • • • Hewlett Packard HP6624A DC power supply Tektronix TDS6604 Digital Storage Scope Agilent ParBERT E4832A Hewlett Packard HP6624A DC Power Supply Agilent ParBERT (E4832A) Bench Test Board Figure 14. Equipment Setup 14 Submit Documentation Feedback Tektronix TDS6604 Digital Storage Scope SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) (a) representative Transceiver configured as Rx @ 200 Mbps (Ch1 = xyA) (b) representative Transceiver configured as Tx @ 650 Mbps (M1 = xyY-xyZ) NOTE: x represents transceiver group A, B, C, or D, and y represents transceiver 1, 2, 3, or 4. Figure 15. Typical Driver Eye Pattern for the SN65LVDM1676 With 12 Transceivers Configured as Rx and 4 Transceivers Configured as Tx all Switching Frequency Asynchronous Data (TA = 25°C; VCC = 3.6 V; PRBS = 223-1) Submit Documentation Feedback 15 SN65LVDM1676 SN65LVDM1677 www.ti.com SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different, however, in how it handles the open-input circuit situation. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 16. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level, regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 16. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. 16 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDM1676DGG ACTIVE TSSOP DGG 64 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1676 SN65LVDM1676DGGR ACTIVE TSSOP DGG 64 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1676 SN65LVDM1676DGGRG4 ACTIVE TSSOP DGG 64 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1676 SN65LVDM1677DGG ACTIVE TSSOP DGG 64 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1677 SN65LVDM1677DGGG4 ACTIVE TSSOP DGG 64 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1677 SN65LVDM1677DGGR ACTIVE TSSOP DGG 64 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDM1677 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of