LT6372-1
Precision Instrumentation Amplifier with
Level Shift and Output Clamping
FEATURES
DESCRIPTION
Single Gain Set Resistor: G = 1 to >1000
n Excellent DC Precision
n Input Offset Voltage: 60μV Max
n Input Offset Voltage Drift: 0.6μV/°C Max
n Low Gain Error: 0.01% Max (G = 1)
n Low Gain Drift: 35ppm/°C Max (G > 1)
n High DC CMRR: 86dB Min (G = 1)
n Integrated Output Clamps
n Integrated Output Level Shift
n Input Bias Current: 800pA Max
n 3.1MHz –3dB Bandwidth (G = 1)
n Low Noise:
n 0.1Hz to 10Hz Noise: 0.2μV
P-P
n 1kHz Voltage Noise: 7nV/√Hz
n Integrated Input RFI Filter
n Wide Supply Range 4.75V to 35V
n Temperature Ranges: –40°C to 85°C and –40°C to 125°C
n MS16E and 20-Lead 3mm × 4mm QFN Packages
The LT®6372-1 is a gain programmable, high precision
instrumentation amplifier that delivers industry leading
DC precision. This high precision enables smaller signals to be sensed and eases calibration requirements,
particularly over temperature. The LT6372-1 incorporates
features into the LT6370 which further improve accuracy
and simplify interfacing to an ADC.
n
The LT6372-1 uses a proprietary high performance bipolar process which enables industry leading accuracy coupled with exceptional long-term stability. The LT6372-1
is laser trimmed for very low input offset voltage (60µV)
and high CMRR (86dB, G = 1). Proprietary on-chip test
capability allows the gain drift (35ppm/°C) to be guaranteed with automated testing.
The LT6372-1’s difference amplifier uses a split reference
configuration which simplifies level shifting the amplifier’s
output to the center of the ADC’s input range. Output
clamp pins are also provided to limit the voltage which can
be applied to an ADC’s input. EMI filtering is integrated on
the LT6372-1’s inputs to maintain accuracy in the presence of harsh RF interference.
APPLICATIONS
Bridge Amplifier
Data Acquisition
n Thermocouple Amplifier
n Strain Gauge Amplifier
n Medical Instrumentation
n Transducer Interfaces
n Differential to Single-Ended Conversion
n
The LT6372-1 is available in a compact MS16E or a 20-pin
3mm x 4mm QFN. The LT6372-1 is fully specified over the
–40°C to 85°C and –40°C to 125°C temperature ranges.
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
+15V
+
350Ω VIN
–
4
2.5V
REF2
RG
243Ω
LT6372-1
REF1
–
CLHI
CLLO
91Ω
10nF
COG
REF
VDD
LTC2367-16
GND
6372-1 TA01a
Level Shifted
to VREF/2
Output
Clamped
Positive
52428
26214
2
1
65536
39322
3
0
–15V
GAIN OF 100 BRIDGE AMPLIFIER
G = 100
5
VOUT (V)
350Ω
6
VREF
Output
Clamped
Negative
–1
–100 –75 –50 –25 0
25
VIN (mV)
13107
ADC OUTPUT CODE
350Ω
LTC6655-5
VIN
VOUT
+
10V
350Ω
LT6372–1
Driving LTC2367–16 with
LT6372–1 Driving LTC2369–18
Levelwith
Shift
and Output
Clamping
Level–Shift
and Output
Clamping
0
50
75
100
63721 TA01b
Rev. 0
Document Feedback
For more information www.analog.com
1
LT6372-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–)..................................36V
Input Voltage (+IN, –IN, +RG,S, +RG,F, –RG,S, –RG,F,
REF1, REF2, CLHI, CLLO).... (V– – 0.3V) to (V+ + 0.3V)
Differential Input Voltage
(+IN to –IN)..........................................................±36V
(REF1 to REF2).................................................... ±15V
Input Current (+RG,S, +RG,F, –RG,S, –RG,F)..............±2mA
Input Current (+IN, –IN, CLLO) ............................. ±10mA
Input Current (REF1, REF2, CLHI) ........................–10mA
Output Short-Circuit Duration..............Thermally Limited
Output Current........................................................80mA
Operating and Specified Temperature Range
I-Grade.................................................–40°C to 85°C
H-Grade.............................................. –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
+RG,S
16 NIC
NIC 1
+RG,F
+RG,S
NIC
REF2
V+
OUTPUT
REF1
CLHI
15 REF2
–IN 2
NIC 3
NIC 4
13 OUTPUT
+IN 5
12 REF1
NIC 6
11 NIC
8
9 10
CLHI
7
DNC
MSE PACKAGE
16-LEAD PLASTIC MSOP
θJA = 35°C/W
EXPOSED PAD (PIN 17) MUST FLOAT OR
BE CONNECTED TO V+ IN ADDITION TO PIN 12
14 V+
21
V–
CLLO
17
16
15
14
13
12
11
10
9
V–
1
2
3
4
5
6
7
8
+RG,F
20 19 18 17
TOP VIEW
–RG,F
–RG,S
NIC
–IN
+IN
NIC
CLLO
V–
–RG,F
–RG,S
TOP VIEW
UDC PACKAGE
20-LEAD (3mm x 4mm) PLASTIC QFN
θJA = 52°C/W
EXPOSED PAD (PIN 21) IS CONNECTED
–
TO V (PIN 7) (PCB CONNECTION OPTIONAL)
ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT6372IMSE-1#PBF
LT6372IMSE-1#TRPBF
63721
16-Lead Plastic MSOP
–40°C to 85°C
LT6372HMSE-1#PBF
LT6372HMSE-1#TRPBF
63721
16-Lead Plastic MSOP
–40°C to 125°C
LT6372IUDC-1#PBF
LT6372IUDC-1#TRPBF
LHHV
20-Lead (3mm x 4mm) Plastic QFN
–40°C to 85°C
LT6372HUDC-1#PBF
LT6372HUDC-1#TRPBF
LHHV
20-Lead (3mm x 4mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LT6372-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CONDITIONS
G
Gain Range
G = (1 + 24.2k/RG) (Note 2)
Gain Error (Notes 3, 4)
G=1
G=1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
Gain vs Temperature (Notes 3, 4)
G = 1 (Note 5)
G > 1(Note 6)
Gain Nonlinearity (Notes 3, 7)
MIN
TYP
1
–0.004
l
–0.02
l
–0.02
l
–0.05
l
MAX
UNITS
1000
V/V
0.01
0.015
0.12
0.42
0.12
0.42
0.12
0.5
%
%
%
%
%
%
%
%
0.2
20
0.5
35
ppm/°C
ppm/°C
VOUT = ±10V, G = 1
VOUT = ±10V, G = 10
VOUT = ±10V, G = 100
VOUT = ±10V, G = 1000
1
3
20
50
3
40
50
ppm
ppm
ppm
ppm
VOUT = ±10V, G = 1, RL = 600Ω
VOUT = ±10V, G = 10, RL = 600Ω
VOUT = ±10V, G = 100, RL = 600Ω
VOUT = ±10V, G = 1000, RL = 600Ω
4
6
70
250
l
l
ppm
ppm
ppm
ppm
VOST, Total Input Referred Offset Voltage, VOST = VOSI + VOSO/G
VOSI
VOSO
Input Offset Voltage
(Note 8)
±10
±60
±175
μV
μV
±70
±275
±500
μV
μV
±0.6
μV/°C
l
Output Offset Voltage (Note 8)
l
VOSI/T
Input Offset Voltage Drift (Notes 5, 8)
Input Offset Voltage Hysteresis (Note 9)
VOSO/T
IB
IOS
l
TA = –40°C to 125°C
l
Output Offset Voltage Drift (Notes 5, 8)
l
Output Offset Voltage Hysteresis (Note 9) TA = –40°C to 125°C
l
Input Bias Current
TA = –40°C to 85°C
TA = –40°C to 125°C
±3
±4
±10
0.1Hz to 10Hz, G = 1
0.1Hz to 10Hz, G = 1000
μV
±0.8
±1.5
±3
nA
nA
nA
±0.2
±1.4
±4
nA
nA
l
Input Noise Voltage (Note 10)
μV/°C
±0.1
l
l
Input Offset Current
μV
2
0.2
μVP-P
μVP-P
Total RTI Noise = √eni2 + (eno/G)2 (Note 10)
eni
Input Noise Voltage Density
f = 1kHz
7
nV/√Hz
eno
Output Noise Voltage Density
f = 1kHz
65
nV/√Hz
Input Noise Current
0.1Hz to 10Hz
10
pAP-P
in
Input Noise Current Density
f = 1kHz
200
fA/√Hz
RIN
Input Resistance
VIN = –12.6V to 13V
225
GΩ
CIN
Differential
Common Mode
f = 100kHz
f = 100kHz
0.9
15.9
pF
pF
VCM
Input Voltage Range
Guaranteed by CMRR
V– + 1.8/V+ – 1.4
V– + 2.4
V+ – 2
V
V
l
Rev. 0
For more information www.analog.com
3
LT6372-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CONDITIONS
CMRR
DC to 60Hz, 1k Source Imbalance,
VCM = –12.6V to 13V
G=1
G=1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
Common Mode Rejection Ratio
AC Common Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
l
l
l
l
100
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
120
140
150
dB
dB
dB
dB
f = 20kHz, MS16E Package
G=1
G = 10
G = 100
G = 1000
69
92
110
110
dB
dB
dB
dB
130
dB
dB
dB
dB
dB
dB
dB
dB
VS = ±2.375V to ±17.5V
G=1
G=1
G = 10
G = 10
G = 100
G = 100
G = 1000
G = 1000
l
116
110
128
120
122
118
122
118
4.75
l
l
l
Guaranteed by PSRR
l
IS
Supply Current
VS = ±15V
TA = –40°C to 85°C
TA = –40°C to 125°C
l
l
VS = ±2.375V
TA = –40°C to 85°C
TA = –40°C to 125°C
l
l
VS = ±15V, RL = 10kΩ
140
140
140
35
V
2.75
2.85
3
3.1
mA
mA
mA
2.65
2.7
2.85
2.95
mA
mA
mA
–14.5
–14.3
–14.9/14
l
13.7
13.6
V
V
–2
–1.8
–2.3/1.6
l
1.5
1.3
V
V
35
30
55
l
mA
mA
3.1
1.15
184
19
MHz
MHz
kHz
kHz
VS = ±2.375V, RL = 10kΩ
IOUT
86
80
106
100
120
115
128
120
MAX
74
98
102
105
Supply Voltage
Output Voltage Swing
TYP
f = 20kHz, QFN20 Package
G=1
G = 10
G = 100
G = 1000
VS
VOUT
MIN
Output Short Circuit Current
BW
–3dB Bandwidth
G=1
G = 10
G = 100
G = 1000
SR
Slew Rate
G = 1, VOUT = ±10V
11
V/μs
tS
Settling Time
20V Output Step to 0.0015%
G=1
G = 10
G = 100
G = 1000
5.8
9.8
16
100
μs
μs
μs
μs
Rev. 0
4
For more information www.analog.com
LT6372-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2kΩ.
SYMBOL PARAMETER
CONDITIONS
RREFIN
REF Input Resistance
REF1 or REF2, Untested REF pin floating
MIN
IREFIN
REF Input Current
V+IN = V–IN = VREF1 = VREF2= 0V, REF1 or REF2
VREF
REF Voltage Range
REF1 or REF2
AVREF
REF Gain to Output
VREF1 = 0V to 5V, VREF2 = 0V
REF Gain Error
VREF1 = 0V to 5V, VREF2 = 0V
TYP
MAX
30
l
–20
–30
l
V–
–14
kΩ
–7
3
V+
0.5
l
–175
–200
±50
UNITS
μA
μA
V
V/V
175
200
ppm
ppm
CLLO Input Current
VCLLO = 0V
l
1
μA
CLHI Input Current
VCLHI = 5V
l
1
μA
V+ – 2
V
V+ – 2.5
CLLO Input Operating Voltage Range
Outside this range CLLO is disabled
l
V– + 3
CLHI Input Operating Voltage Range
Outside this range CLHI is disabled
l
V– + 2
l
–0.57
–0.74
CLLO Clamp Voltage (VOUT – VCLLO)
CLHI Clamp Voltage (VOUT – VCLHI)
–0.45
0.45
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Gains higher than 1000 are possible but the resulting low RG values
can make PCB and package lead resistance a significant error source.
Note 3: Gain tests are performed with –IN at mid-supply and +IN driven.
Note 4: When the gain is greater than 1 the gain error and gain drift
specifications do not include the effect of external gain set resistor RG.
Note 5: This specification is guaranteed by design.
Note 6: This specification is guaranteed with high-speed automated testing.
Note 7: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
PCB layout, heat sinking and air flow conditions.
V
V
V
0.55
0.755
V
V
Note 8: For more information on how offsets relate to the amplifiers, see
section “Input and Output Offset Voltage” in the Applications section.
Note 9: Hysteresis in output voltage is created by mechanical stress
that differs depending on whether the IC was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis is roughly proportional to the square of the
temperature change. For instruments that are stored at well controlled
temperatures (within 20 or 30 degrees of operational temperature),
hysteresis is usually not a significant error source. Typical hysteresis is the
worst case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned
by one thermal cycle.
Note 10: Referred to the input.
Rev. 0
For more information www.analog.com
5
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Distribution of Input Offset
MS16EPackage
Package
Voltage, MS16
50
50 Units
45
40
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
45
35
30
25
20
15
10
40
50
TA = –40°C to 85°C
50 Units
30
25
20
15
10
40
TA = –40°C to 125°C
50 Units
35
30
25
20
15
10
5
5
5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
INPUT OFFSET VOLTAGE (µV)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
6372-1 G02
Distribution of Input Offset
Voltage, QFN Package
45
6372-1 G03
Distribution of Input Offset
Voltage Drift, QFN Package
Distribution of Input Offset
Voltage Drift, QFN Package
50
50
50 Units
45
PERCENTAGE OF PARTS (%)
40
35
30
25
20
15
10
40
TA = –40°C to 85°C
50 Units
45
PERCENTAGE OF PARTS (%)
50
35
30
25
20
15
10
40
TA = –40°C to 125°C
50 Units
35
30
25
20
15
10
5
5
5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50
INPUT OFFSET VOLTAGE (µV)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
0
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
6372-1 G04
Distribution of Output Offset
MS16EPackage
Package
Voltage, MS16
50
45
6372-1 G06
6372-1 G05
Distribution of Output Offset
MS16EPackage
Package
Voltage Drift, MS16
50
50 Units
45
PERCENTAGE OF PARTS (%)
40
35
30
25
20
15
10
45
35
30
25
20
15
10
5
0
–240 –180 –120 –60 0
60 120 180 240
OUTPUT OFFSET VOLTAGE (µV)
0
6372-1 G07
50
TA = –40°C to 85°C
50 Units
40
5
Output
Offset
Voltage
Distribution of
Output
Offset
Drift, MS16E
Voltage
Drift, Package
MS16 Package
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
45
35
6372-1 G01
PERCENTAGE OF PARTS (%)
Distribution of Input Offset
MS16EPackage
Package
Voltage Drift, MS16
PERCENTAGE OF PARTS (%)
50
Distribution of Input Offset
MS16EPackage
Package
Voltage Drift, MS16
TA = –40°C to 125°C
50 Units
40
35
30
25
20
15
10
5
–5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
6372-1 G08
0
–5 –4 –3 –2 –1 0 1 2 3 4
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
5
6372-1 G09
Rev. 0
6
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Distribution of Output Offset
Voltage Drift, QFN Package
Distribution of Output Offset
Voltage, QFN Package
50
TA = –40°C to 85°C
50 Units
45
40
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
50
50 Units
45
35
30
25
20
15
10
40
35
30
25
20
15
10
5
5
0
–160 –120 –80 –40 0
40 80 120 160
OUTPUT OFFSET VOLTAGE (µV)
0
–5 –4 –3 –2 –1 0 1 2 3 4
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
30
25
20
15
10
40
10
45
25
20
15
10
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
GAIN ERROR (ppm)
0
–500
40
35
30
25
20
15
10
–250
0
250
GAIN ERROR (ppm)
0
–100 –80 –60 –40 –20 0 20 40 60 80 100
GAIN ERROR (ppm)
500
6372-1 G15
REF Gain Drift
50
REF1 = 0V
REF2 = ±10V
10 Units
–10
–20
40
30
30
20
20
GAIN ERROR (ppm)
GAIN ERROR (ppm)
0
Gain Drift (G = 1)
50
REF1 = REF2
8 Units
40
10
10
0
–10
–20
0
–10
–20
–30
–30
–40
–40
–40
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6372-1 G16
–50
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6372-1 G17
G=1
19 Units
10
–30
–50
–50
REF2 = 0V
REF1 = 0V to 5V
TA = 25°C
730 Units
6372-1 G14
REFDivider
DividerGain
GainDrift
Drift
REF
20
–5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT OFFSET VOLTAGE DRIFT (µV/°C)
5
6372-1 G13
GAIN ERROR (ppm)
15
50
30
5
30
20
Distribution of REF Divider Gain
Error Error
Gain
35
5
40
25
6372-1 G12
PERCENTAGE OF PARTS (%)
35
50
30
0
5
G = 1000
TA = 25°C
730 Units
45
PERCENTAGE OF PARTS (%)
PERCENTAGE OF PARTS (%)
40
35
Distribution of Gain Error
50
45
40
6372-1 G11
Distribution of Gain Error
G=1
TA = 25°C
730 Units
TA = –40°C to 125°C
50 Units
5
6372-1 G10
50
45
PERCENTAGE OF PARTS (%)
50
Distribution of Output Offset
Voltage Drift, QFN Package
–50
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6372-1 G18
Rev. 0
For more information www.analog.com
7
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Lead Free Reflow Profile Due to
IR Reflow
3000
300
G = 1000
16 Units
2500
TL = 217°C
TS(MAX) = 200°C
225
1500
TP = 260°C
TS = 190°C
1000
500
0
tL
130s
RAMP TO
150°C
75
–1000
tP
30s
T = 150°C
150
–500
RAMP
DOWN
40s
–1500
0
25
50
75
TEMPERATURE (°C)
100
0
125
0
2
4
6
MINUTES
10
8
VOUT = ±10V
Gain Nonlinearity (G = 1000)
VOUT = ±10V
NONLINEARITY (20ppm/DIV)
NONLINEARITY (2ppm/DIV)
VOUT = ±10V
RL = 600Ω
RL = 2k
RL = 10k
RL = 600Ω
RL = 2k
RL = 10k
OUTPUT VOLTAGE (2V/DIV)
160
BANDWIDTH
LIMITED
CMRR (dB)
120
100
80
Positive Power Supply Rejection
Ratio vs Frequency,
Frequency RTI
MS16E Package
VS = ±15V
TA = 25°C
140
BANDWIDTH
LIMITED
120
100
80
G=1
G = 10
G = 100
G = 1000
100
1k
10k
FREQUENCY (Hz)
6372-1 G24
CMRR vs Frequency, RTI
MS16E Package
QFN Package
VS = ±15V
TA = 25°C
140
OUTPUT VOLTAGE (2V/DIV)
6372-1 G23
CMRR vs Frequency, RTI
QFN Package
160
RL = 600Ω
RL = 2k
RL = 10k
OUTPUT VOLTAGE (2V/DIV)
6372-1 G22
10
6372-1 G21
Gain Nonlinearity (G = 100)
Gain Nonlinearity (G = 10)
60
OUTPUT VOLTAGE (2V/DIV)
6372-1 G20
NONLINEARITY (100ppm/DIV)
–25
6372-1 G19
CMRR (dB)
RL = 600Ω
RL = 2k
RL = 10k
120s
–2000
–50
40
VOUT = ±10V
G=1
G = 10
G = 100
G = 1000
60
100k
6372-1 G25
40
10
100
1k
10k
FREQUENCY (Hz)
100k
6372-1 G26
160
POSITIVE POWER SUPPLY REJECTION
RATIO (dB)
GAIN ERROR (ppm)
2000
380s
Gain Nonlinearity (G = 1)
NONLINEARITY (2ppm/DIV)
Gain Drift (G = 1000)
VS = ±15V
140
120
100
80
60
G=1
G = 10
G = 100
G = 1000
40
20
0.1
1
10
100 1k 10k 100k
FREQUENCY (Hz)
1M
6372-1 G27
Rev. 0
8
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Negative Power Supply Rejection
Ratio vs Frequency
120
100
80
G=1
G = 10
G = 100
G = 1000
20
10
100
1k
10k
FREQUENCY (Hz)
100k
100
1/fCORNER = 2Hz
1/fCORNER = 3Hz
10
1
0.1
1M
G=1
G = 10
G = 100, 1000
1
BW LIMIT
G = 1000
10
100
1k
FREQUENCY (Hz)
10k
10
0.1
0.1Hz to 10Hz Voltage Noise,
G = 1, RTI
VS = ±15V
TA = 25°C
G = 100
TIME (1s/DIV)
TIME (1s/DIV)
6372-1 G33
6372-1 G32
0.1Hz to 10Hz Voltage Noise,
G = 1000, RTI
0.1Hz to 10Hz Noise Current,
Balanced Source R
0.1Hz to 10Hz Noise Current,
Unbalanced Source R
NOISE CURRENT (1pA/DIV)
NOISE VOLTAGE (50nV/DIV)
VS = ±15V
TA = 25°C
G = 1000
100k
0.1Hz to 10Hz Voltage Noise,
G = 100, RTI
VS = ±15V
TA = 25°C
G = 10
6372-1 G31
UNBALANCED SOURCE R
VS = ±15V
TA = 25°C
TIME (1s/DIV)
6372-1 G34
10k
NOISE VOLTAGE (50nV/DIV)
NOISE VOLTAGE (100nV/DIV)
TIME (1s/DIV)
TIME (1s/DIV)
10
100
1k
FREQUENCY (Hz)
6372-1 G30
0.1Hz to 10Hz Voltage Noise,
G = 10, RTI
VS = ±15V
TA = 25°C
G=1
1
6372-1 G29
6372-1 G28
NOISE VOLTAGE (500nV/DIV)
100k
UNBALANCED SOURCE R
BALANCED SOURCE R
100
NOISE CURRENT (500fA/DIV)
40
1/fCORNER = 1Hz
CURRENT NOISE DENSITY (fA/√Hz)
140
60
1000
400
VS = ±15V
VOLTAGE NOISE DENSITY (nV/√Hz)
NEGATIVE POWER SUPPLY REJECTION
RATIO (dB)
160
Current Noise Density vs
Frequency
Input-Referred Voltage Noise
Density vs Frequency
BALANCED SOURCE R
VS = ±15V
TA = 25°C
TIME (1s/DIV)
6372-1 G35
6372-1 G36
Rev. 0
For more information www.analog.com
9
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
400
200
0
–200
–400
–600
–800
–15
–10
–5
0
5
10
COMMON-MODE INPUT VOLTAGE (V)
1.0
1.0
0.8
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–1.0
–15
15
6372-1 G37
–10
–5
0
5
10
INPUT COMMON–MODE VOLTAGE (V)
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–1.0
–50
15
2.5
14
–9
POSITIVE OUTPUT SWING (V)
–8
1.0
125°C
85°C
25°C
–40°C
0.5
0
0
5
10 15 20 25 30
SUPPLY VOLTAGE (V)
35
13
12
11
10
125°C
85°C
25°C
–40°C
9
8
0.1
40
1
10
RESISTIVE LOAD (kΩ)
100
6372-1 G40
50
25
40
20
0
–50
±15V, SINK
±15V, SOURCE
4.75V, SINK
4.75V, SOURCE
–25
0
25
50
75
TEMPERATURE (°C)
100
–12
–13
–14
–15
0.1
125
6372-1 G43
1
10
RESISTIVE LOAD (kΩ)
6372-1 G42
Slew Rate vs Temperature
G=1
VS = ±15V
TA = 25°C
THD < –40dB
14
13
15
G=1
VOUT = 20VPP
12
11
10
9
8
7
5
RISING
FALLING
6
0
100
100
15
10
10
–11
SLEW RATE (V/µs)
30
VOUT (VP–P)
SHORT CIRCUIT CURRENT (mA)
60
125
125°C
85°C
25°C
–40°C
–10
Undistorted Output Swing vs
Frequency
20
100
6372-1 G41
Output Short Circuit Current vs
Temperature
30
0
25
50
75
TEMPERATURE (°C)
Output Voltage Swing vs Load
Resistance
Output Voltage Swing vs Load
Resistance
15
1.5
–25
6372-1 G39
3.0
2.0
+IN BIAS CURRENT
–IN BIAS CURRENT
OFFSET CURRENT
–0.8
6372-1 G38
Supply Current vs Supply Voltage
SUPPLY CURRENT (mA)
+IN BIAS CURRENT
–IN BIAS CURRENT
OFFSET CURRENT
–0.8
NEGATIVE OUTPUT SWING (V)
REF PIN CURRENT (µA)
600
Input Bias and Offset Current vs
Temperature
INPUT BIAS, OFFSET CURRENTS (nA)
125°C
85°C
25°C
–40°C
INPUT BIAS, OFFSET CURRENTS (nA)
800
Input Bias Current vs Common
Mode Voltage
REF Pin Current vs Input
Common Mode Voltage
1k
10k
100k
FREQUENCY (Hz)
1M
10M
6372-1 G44
5
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6372-1 G45
Rev. 0
10
For more information www.analog.com
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
Large Signal Transient Response
Large Signal Transient Response
Large Signal Transient Response
VOUT
2V/DIV
VOUT
2V/DIV
G=1
VS = ±15V
TA = 25°C
CL = 100pF
2µs/DIV
VOUT
2V/DIV
6372-1 G46
G = 10
VS = ±15V
TA = 25°C
CL = 100pF
Large Signal Transient Response
VOUT
2V/DIV
4µs/DIV
6372-1 G47
G = 100
VS = ±15V
TA = 25°C
CL = 100pF
Small Signal Transient Response
100µs/DIV
6372-1 G48
Small Signal Transient Response
VOUT
5mV/DIV
VOUT
5mV/DIV
G = 1000
VS = ±15V
TA = 25°C
CL = 100pF
10µs/DIV
6372-1 G49
G=1
VS = ±15V
TA = 25°C
CL = 100pF
1µs/DIV
6372-1 G50
G = 10
VS = ±15V
TA = 25°C
CL = 100pF
1µs/DIV
6372-1 G51
Small Signal Transient Response
Small Signal Transient Response
VOUT
5mV/DIV
VOUT
5mV/DIV
G = 100
VS = ±15V
TA = 25°C
CL = 100pF
10µs/DIV
6372-1 G52
G = 1000
VS = ±15V
TA = 25°C
CL = 100pF
100µs/DIV
6372-1 G53
Rev. 0
For more information www.analog.com
11
LT6372-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15V, VCM = VREF1 = VREF2 = 0V, VCLLO = V–, VCLHI = V+, RL = 2k, unless otherwise noted.
60
Clamp Transient Response
(Clamped Output)
Gain vs Frequency
VS = ±15V
TA = 25°C
50
GAIN (dB)
40
VOUT
2V/DIV
30
20
0V
VIN
0V
200mV/DIV
10
0
–10
–20
100
G=1
G = 10
G = 100
G = 1000
1k
10k
100k
FREQUENCY (Hz)
1M
VS = ± 15V
G = 20
VCHI = 4.1V
VCLO = 0V
VREF1 = 0V
VREF2 = 4.1V
10M
5µs/DIV
6372-1 G55
6372-1 G54
Clamp Voltage
Clamp
Voltagevs
vsTemperature
Temperature
800
7
600
6
5
4
6
3
4
2
2
0
–2
VS = ±15V
VREF2 = VCLHI = 4.1V
VREF1 = VCLLO = 0V
RL = 10kΩ
G = 20
–1 –0.75 –0.50 –0.25 0 0.25 0.50 0.75
INPUT VOLTAGE (V)
1
CLAMPED OUTPUT VOLTAGE (mV)
VOUT
I+
I–
8
SUPPLY CURRENT (mA)
CLAMPED OUTPUT VOLTAGE (V)
LT6372–1
SupplyCurrent
Current While
LT6372-1 Supply
Clamping
While Clamping
VS = ±15V
VCLHI = VCLLO = 0V
400
200
CLAMPED HIGH
0
–200
CLAMPED LOW
–400
–600
–800
–50
6372-1 G56
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6372-1 G57
Rev. 0
12
For more information www.analog.com
LT6372-1
PIN FUNCTIONS
(MS16E/QFN20)
–RG,F (Pin 1/Pin 19): For use with an external gain setting
resistor. This connection should be routed to the gain setting resistor separately from –RG,S in order to minimize
gain errors.
REF1 (Pin 10/Pin 12): Reference for the output voltage.
REF1 can be tied to REF2 and used as a reference for the
output. REF1 can also be used with REF2 to form a voltage
divider and level shift the output.
–RG,S (Pin 2/Pin 20): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from –RG,F in order to minimize
gain errors.
OUTPUT (Pin 11/Pin 13): Output voltage referenced to
the REF pins.
–IN (Pin 4/Pin 2): Negative Input Terminal. This input is
high impedance.
+IN (Pin 5/Pin 5): Positive Input Terminal. This input is
high impedance.
REF2 (Pin 13/Pin 15): Reference for the output voltage.
REF2 can be tied to REF1 and used as a reference for the
output. REF2 can also be used with REF1 to form a voltage
divider and level shift the output.
CLLO (Pin 7/Pin 8): Low Side Clamp Input. The voltage
applied to the CLLO pin defines the lower voltage limit
of the output. Typically, the output clamps 500mV below
the voltage applied to the CLLO pin. Do not float CCLO.
+RG,S (Pin 15/Pin 17): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from +RG,F in order to minimize
gain errors.
V– (Pin 8/Pin 7): Negative Power Supply. A bypass capacitor should be used between supply pins and ground.
+RG,F (Pin 16/Pin 18): For use with an external gain setting resistor. This connection should be routed to the gain
setting resistor separately from +RG,S in order to minimize
gain errors.
CLHI (Pin 9/Pin 10): High Side Clamp Input. The voltage
applied to the CLHI pin defines the upper voltage limit of
the output. Typically, the output clamps 500mV above the
voltage applied to the CLHI pin. Do not float CLHI.
V+ (Pin 12/Pin 14): Positive Power Supply. A bypass
capacitor should be used between supply pins and ground.
NIC (Pins 3, 6, 14/Pins 1, 3, 4, 6, 11, 16): No Internal
Connection.
DNC (QFN Pin 9): Do Not Connect. This pin should float.
Rev. 0
For more information www.analog.com
13
LT6372-1
SIMPLIFIED BLOCK DIAGRAM
V+
R1
12.1k
I1
D2
C1
D1
–IN
EMI
FILTER
200Ω
V+
Q1
D3
D4
I3
–
I2
VB
V–
+
R6
10k
R5
10k
A1
OUTPUT
D13
–RG,F
V–
–RG,S
D9
D14
V–
V+
D13
+RG,S
D15
+
V+
R2
12.1k
I4
D6
EMI
FILTER
CLHI
–
+RG,F
+IN
D11
D18
A3
V–
D17
R9
20k
C2
V–
D5
200Ω
D8
I6
REF2
D19
Q2
D7
CLLO
–
I5
VB
+
A2
R8
20k
R7
10k
V–
REF1
D10
V–
V–
D16
V+
V–
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
6372-1 BD
Rev. 0
14
For more information www.analog.com
LT6372-1
THEORY OF OPERATION
The LT6372-1 is an improved version of the classic three op
amp instrumentation amplifier topology that incorporates
features to improve accuracy and simplify interfacing to
ADCs. Laser trimming and proprietary monolithic construction allow for tight matching and extremely low drift of
circuit parameters over the specified temperature range.
Refer to the Simplified Block Diagram to aid in understanding the following circuit description. The collector currents
in Q1 and Q2 as well as I1 and I4 are trimmed to minimize
input offset voltage drift, thus assuring a high level of performance. R1 and R2 are trimmed to an absolute value of
12.1k to assure that the gain can be set accurately (0.12%
at G = 100) with only one external resistor, RG. The value of
RG determines the transconductance of the preamp stage.
As RG is reduced to increase the programmed gain, the
transconductance of the input preamp stage also increases
to that of the input transistors Q1 and Q2. This causes the
open-loop gain to increase when the programmed gain is
increased, reducing the input related errors and noise. The
input voltage noise at high gains is determined only by Q1
and Q2. At lower gains the noise of the difference amplifier
and preamp gain setting resistors may increase the noise.
The gain bandwidth product is determined by C1, C2 and
the preamp transconductance, which increases with programmed gain. Therefore, the bandwidth is self-adjusting
and does not drop directly proportional to gain.
The input transistors Q1 and Q2 offer excellent matching,
drift and noise performance, which is due to using a proprietary high performance process, as well as low input
bias current due to the high beta of these input devices.
The input bias current is further reduced by trimming I3
and I6. The collector currents in Q1 and Q2 are held constant due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop. The action of the amplifier loops impresses
the differential input voltage across the external gain set
resistor RG. Since the current that flows through RG also
flows through R1 and R2, the ratios provide a gained-up
differential voltage,
G = 1+
R1+ R2
RG
to the difference amplifier A3. The difference amplifier
removes the common mode voltage and provides a single-ended output voltage referenced to the average of the
voltages on REF1 and REF2. This split reference resistor
configuration allows the output voltage to be easily level
shifted to the center of an ADCs input range without external components. The offset voltage of the difference amplifier is trimmed to minimize output offset voltage drift, thus
assuring a high level of performance, even in low gains.
Resistors R5 to R9 are trimmed to maximize CMRR and
minimize gain error. The resulting gain equation is:
G = 1+
24.2k
RG
Solving for the gain set resistor gives:
RG =
24.2k
G–1
Table 1 shows appropriate 1% resistor values for a variety of gains.
Table 1. LT6372-1 Gain and RG Lookup.
Resulting Gains for Various 1% Standard Resistor Values
Gain
Standard 1% Resistor Value (Ω)
1
–
1.996
24.3k
5.007
6.04k
10.06
2.67k
20.06
1.27k
50.69
487
100.6
243
201
121
497.9
48.7
996.9
24.3
Convenient Integer Gains Using Various Standard 1% Resistor Values
Integer Gain
Standard 1% Resistor Value (Ω)
1
–
3
12.1k
21
1.21k
23
1.1k
122
200
201
121
221
110
243
100
1211 (Note 2)
20
Additionally, The LT6372-1 has two integrated output
voltage clamps which can be used to limit the voltage
Rev. 0
For more information www.analog.com
15
LT6372-1
APPLICATIONS INFORMATION
applied to an ADCs input. Typically, CLHI is tied to the
ADC’s reference and CLLO is tied to the ADC’s ground
connection.
Valid Input and Output Range
Instrumentation amplifiers traditionally specify a valid
input common mode range and an output swing range.
This however often fails to identify limitations associated
with internal swing limits. Referring to the Simplified
Block Diagram, the output swing of pre-amplifiers A1
and A2 as well as the common-mode input range of the
difference amplifier A3 impose limitations on the valid
operating range. Figure 1 shows the operating region
where a valid output is produced for various configurations. Further valid input and output range plots can be
generated using the Diamond Plot Tool.
VD/2
+
+15V
V+
VCM
+
–
LT6370
LT6372-1
REF1,2
VD/2
–
OUT
V–
6372-1 F01a
–15V
INPUT COMMON–MODE VOLTAGE (V)
15
10
5
G=1
VS = ±15V
VREF2 = 0V
VREF1 = 0V
VCLHI = 15V
VCLLO = –15V
0
–5
–10
–15
–15
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
6372-1 F01b
VD/2
+
+15V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-1
REF1,2
–
OUT
V–
–15V
6371-2 F01c
INPUT COMMON–MODE VOLTAGE (V)
15
10
5
G = 100
VS = ±15V
VREF2 = 0V
VREF1 = 0V
VCLHI = 15V
VCLLO = –15V
0
–5
–10
–15
–15
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
6372-1 F01d
Figure 1. Input Common Mode Range vs Output Voltage
Rev. 0
16
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
+
+5V
V+
VCM
RG
243Ω
+
–
VD/2
15
+15V
INPUT COMMON–MODE VOLTAGE (V)
VD/2
CLHI
LT6370
LT6372-1
REF1, 2
CLLO
–
– V
OUT
6372-1 F01m
–15V
G = 100
VS = ±15V
VREF1 = 0V
VREF2 = 0V
VCLHI = 5V
VCLLO = 0V
10
5
0
–5
–10
–15
–15
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
63721 F01n
VD/2
+5V
+
V+
VCM
+
–
LT6370
LT6372-1
REF1,2
VD/2
OUT
V–
–
6372-1 F01e
–5V
INPUT COMMON-MODE VOLTAGE (V)
5
4
3
2
G=1
VS = ±5V
VREF2 = 0V
VREF1 = 0V
VCLHI = 5V
VCLLO = –5V
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2
OUTPUT VOLTAGE (V)
3
4
5
6372-1 F01f
VD/2
+
+5V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-1
REF1,2
–
OUT
V–
–5V
6372-1 F01g
INPUT COMMON-MODE VOLTAGE (V)
5
4
3
2
G = 100
VS = ±5V
VREF2 = 0V
VREF1 = 0V
VCLHI = 5V
VCLLO = –5V
1
0
–1
–2
–3
–4
–5
–5 –4 –3 –2 –1 0 1 2
OUTPUT VOLTAGE (V)
3
4
5
6372-1 F01h
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
Rev. 0
For more information www.analog.com
17
LT6372-1
APPLICATIONS INFORMATION
VD/2
+
+5V
V+
VCM
+
–
REF2
LT6370
LT6372-1
REF1
VD/2
–
OUT
V–
6372-1 F01i
INPUT COMMON–MODE VOLTAGE (V)
5.0
G=1
V+ = 5V
V– = 0V
VREF2 = 5V
VREF1 = 0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VCLHI = 5V
VCLLO = 0V
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
6372-1 F01j
VD/2
+
+5V
V+
VCM
+
–
RG
243Ω
VD/2
LT6370
LT6372-1
–
REF2
OUT
REF1
V–
6372-1 F01k
INPUT COMMON-MODE VOLTAGE (V)
5.0
G = 100
V+ = 5V
V– = 0V
VREF2 = 5V
VREF1 = 0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VCLHI = 5V
VCLLO = 0V
0.5
0
0
0.5
1
1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
4
4.5
5
6372-1 F01l
Figure 1 (Continued). Input Common Mode Range vs Output Voltage
Rev. 0
18
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
Split Reference Pins
Output Level Shifting with the LT6372-1’s difference amplifier features split reference pins, REF1 and REF2, which
allow the output to be easily and accurately level shifted
without the use of external circuitry. REF1 and REF2 are
typically tied to an ADC ground and reference respectively.
In this configuration the amplifier’s output is conveniently
level shifted to the center of the ADC input range.
If REF1 and REF2 are shorted to each other, they can
function as the reference for the output voltage like a traditional instrumentation amplifier.
Parasitic resistance in series with REF1 and REF2 should
be minimized to preserve CMRR and gain performance.
It is also important to note that the drift in any circuitry
used to drive REF1 or REF2 can results in an additional
output drift term. Therefore, it may be important to consider the temperature accuracy of the circuitry used to
drive the REF pin.
Gain Setting Resistor Connections
Each pre-amplifier gives a set of RG connection terminals which should be routed separately to the gain setting
resistor. Doing this minimizes the impact which parasitic
trace and lead resistance has on gain accuracy. When
routing to the gain setting resistors, large loops should
be avoided as they can couple noise into the amplifier.
In applications where clamping is not desired, CLLO
should be tied to V– and CLHI to V+ to disable clamping.
Input and Output Offset Voltage
The offset voltage of the LT6372-1 has two main components: the input offset voltage due to the input amplifiers
and the output offset due to the output amplifier. The total
offset voltage referred to the input (RTI) is found by dividing the output offset by the programmed gain and adding
it to the input offset voltage. At high gains the input offset
voltage dominates, whereas at low gains the output offset
voltage dominates. The total offset voltage is:
Total input offset voltage (RTI) = VOSI + VOSO/G
Total output offset voltage (RTO) = VOSI • G + VOSO
The preceding equations can also be used to calculate
offset drift in a similar manner.
Output Offset Trimming
The LT6372-1 is laser trimmed for low offset voltage
so that no external offset trimming is required for most
applications. In the event that the offset voltage needs
to be adjusted, the circuit in Figure 2 is an example of
an optional offset adjustment circuit. The op amp buffer
provides a low impedance signal to the REF pin in order
to achieve the best CMRR and lowest gain error.
V+ 5V
Output Clamps
CLHI and CLLO are high impedance inputs and do not
conduct significant current during clamping. Rather, internal amplifier nodes are controlled by CLHI and CLLO to
limit the output voltage.
–
REF2
LT6372-1
REF1
V–
±5mV
ADJUSTMENT
RANGE
V+
OUTPUT
R1
+10mV
100Ω
LTC2057
+
When the CLLO is tied to 0V, attempts to drive the output
below 0V will be clamped at –0.45 typically. When CLHI
is tied to 5V, attempts to drive the output above 5V will
be clamped at 5.45V typically.
+
–
The CLHI and CLLO clamp pins limit the output voltage
swing of the LT6372-1. CLHI and CLLO are typically tied
to the ADC supply/reference and ADC ground respectively.
In this case the ADC input is protected from being overdriven by the LT6372-1 which is likely running off a higher
supply voltage.
10k
100Ω
–10mV
R2
V–
LT6372-1 F02
Figure 2. Optional Trimming of Output Offset Voltage
Thermocouple Effects
In order to achieve accuracy on the microvolt level, thermocouple effects must be considered. Any connection
of dissimilar metals forms a thermoelectric junction and
Rev. 0
For more information www.analog.com
19
LT6372-1
APPLICATIONS INFORMATION
In order to minimize thermocouple-induced errors, attention must be given to circuit board layout and component
selection. It is good practice to minimize the number of
junctions in the amplifier’s input and RG signal paths and
avoid connectors, sockets, switches, and relays whenever
possible. If such components are required, they should be
selected for low thermal EMF characteristics. Furthermore,
the number, type, and layout of junctions should be matched
for both inputs with respect to thermal gradients on the circuit board. Doing so may involve deliberately introducing
dummy junctions to offset unavoidable junctions.
Air currents can also lead to thermal gradients and cause
significant noise in measurement systems. It is important
to prevent airflow across sensitive circuits. Doing so will
often reduce thermocouple noise substantially. Placing
PCB input traces close together, and on an internal PCB
layer, can help minimize temperature differentials resulting from air currents reacting with the input trace thermal
surface area.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MICROVOLTS REFERRED TO 25°C
Connectors, switches, relay contacts, sockets, resistors,
and solder are all candidates for significant thermal EMF
generation. Even junctions of copper wire from different
manufacturers can generate thermal EMFs of 200nV/°C,
which is comparable to the maximum input offset voltage
drift specification of the LT6372-1. Figure 3 and Figure 4
illustrate the potential magnitude of these voltages and their
sensitivity to temperature.
25
35
30
40
45
TEMPERATURE (°C)
6370 F03
Figure 3. Thermal EMF Generated by Two Copper Wires
From Different Manufacturers
THERMALLY PRODUCED VOLTAGE IN MICROVOLTS
generates a small temperature-dependent voltage. Also
known as the Seebeck Effect, these thermal EMFs can be
the dominant error source in low-drift circuits.
100
SLOPE ≈ 1.5µV/°C
BELOW 25°C
50
0
64% SN/36% Pb
60% Cd/40% SN
SLOPE ≈ 160nV/°C
BELOW 25°C
–50
–100
10
30
0
40
50
20
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURE
SOURCE: NEW ELECTRONICS 02-06-77
6370 F04
Figure 4. Solder-Copper Thermal EMFs
Rev. 0
20
For more information www.analog.com
LT6372-1
Reducing Board-Related Leakage Effects
For the lowest leakage, amplifiers can be used to drive the
guard ring. These buffers must have very low input bias
current since that will now be a leakage.
Leakage currents can have a significant impact on system
accuracy, particularly in high temperature and high voltage
applications. Quality insulation materials should be used,
and insulating surfaces should be cleaned to remove fluxes
and other residues. For humid environments, surface coating may be necessary to provide a moisture barrier.
+
LT6372-1
–
Leakage into the RG pin conducts through the on-chip feedback resistor, creating an error at the output of the preamplifiers. This error is independent of gain and degrades
accuracy the most at low gains. This leakage can be minimized by encircling the RG connections with a guard-ring
operated at a potential very close to that of the RG pins.
NIC pins adjacent to each RG pin can be used to simplify
the implementation of this guard-ring. These NIC pins do
not provide any bias and have no internal connections. In
some cases, the guard-ring can be connected to the input
voltage which biases one diode drop below RG.
+
Figure 6. Guard-Rings Can Be Used to Minimize
Leakage into the Input Pins
Input Bias Current Return Path
The low input bias current of the LT6372-1 (800pA max) and
high input impedance (225GΩ) allow the use of high impedance sources without introducing additional offset voltage
errors, even when the full common mode range is required.
However, a path must be provided for the input bias currents of both inputs when a purely differential signal is being
amplified. Without this path, the inputs will float to either rail
and exceed the input common mode range of the LT6372-1,
resulting in a saturated input amplifier. Figure 7 shows three
examples of an input bias current path. The first example
is of a purely differential signal source with a 10kΩ input
current path to ground. Since the impedance of the signal
source is low, only one resistor is needed. Two matching
resistors are needed for higher impedance signal sources as
shown in the second example. Balancing the input impedance improves both AC and DC common mode rejection
and DC offset. The need for input resistors is eliminated if a
center tap is present as shown in the third example.
V+
V–
6372-1 F05
Figure 5. Guard-Rings Can Be Used to Minimize
Leakage into the RG Pins
Leakage into the input pins reacts with the source resistance, creating an error directly at the input. This leakage
can be minimized by encircling the input connections with
a guard-rings operated at a potential very close to that
of the input pins. In some cases, the guard-ring can be
connected to RG which biases one diode above the input.
–
THERMOCOUPLE
RG
–
LT6372-1
REF1,2
MICROPHONE,
HYDROPHONE,
ETC
RG
–
LT6372-1
+
200k
RG
LT6372-1
REF1,2
+
10k
V–
6372-1 F06
LT6372-1
–
V+
REF1,2
+
200k
CENTER-TAP PROVIDES
BIAS CURRENT RETURN
6372-1 F07
Figure 7. Providing an Input Common Mode Current Path
Rev. 0
For more information www.analog.com
21
LT6372-1
APPLICATIONS INFORMATION
Input Protection
Additional input protection can be achieved by adding
external resistors in series with each input. If low value
resistors are needed, a clamp diode from the positive
supply to each input will help improve robustness. A
2N4394 drain/source to gate is a good low leakage diode
which can be used as shown in Figure 8. Robust input
resistors should be chosen, such as carbon composite
or bulk metal foil. Metal film and carbon film should not
be used because of their poor performance.
VCC
VCC
J1
2N4393
J2
2N4393
RIN
OPTIONAL FOR HIGHEST
ESD PROTECTION
+
VCC
LT6372-1
RG
OUT
REF1,2
–
RIN
VEE
6372-1 F08
Figure 8. Input Protection
Maintaining AC CMRR
To achieve optimum AC CMRR, it is important to balance
the capacitance on the RG gain setting pins. Furthermore,
if the source resistance on each input is not equal, adding an additional resistance to one input to improve input
source resistance matching will improve AC CMRR.
RFI Reduction/Internal RFI Filter
In many industrial and data acquisition applications, the
LT6372-1 will be used to amplify small signals accurately
in the presence of large common mode voltages or high
levels of noise. Typically, the sources of these very small
signals (on the order of microvolts or millivolts) are sensors that can be a significant distance from the signal
conditioning circuit. Although these sensors may be connected to signal conditioning circuitry using shielded or
unshielded twisted-pair cabling, the cabling may act as
an antenna, conveying very high frequency interference
directly into the input stage of the LT6372-1.
The amplitude and frequency of the interference can have
an adverse effect on an instrumentation amplifier’s input
stage by causing any unwanted DC shift in the amplifier’s
input offset voltage. This well known effect is called RFI
rectification and is produced when out-of-band interference is coupled (inductively, capacitively or via radiation)
and rectified by the instrumentation amplifier’s input transistors. These transistors act as high frequency signal
detectors, in the same way diodes were used as RF envelope detectors in early radio designs. Regardless of the
type of interference or the method by which it is coupled
into the circuit, an out-of-band error signal appears in
series with the instrumentation amplifier’s inputs.
To help minimize this effect, the LT6372-1 has 50MHz onchip RFI filters to help attenuate high frequencies before
they can interact with its input transistors. These on-chip
filters are well matched due to their monolithic construction, which helps minimize any degradation in AC CMRR.
To reduce the effect of these out-of-band signals on the
input offset voltage of the LT6372-1 further, an additional
external low-pass filter can be used at the inputs. The
filter should be located very close to the input pins of
the circuit. An effective filter configuration is illustrated
in Figure 9, where three capacitors have been added to
the inputs of the LT6372-1.
The filter limits the input signal according to the following
relationship:
FilterFreqDIFF =
FilterFreqCM =
1
2πR(2CD +CC )
1
2πRCC
where CD ≥10CC.
CD affects the difference signal. CC affects the commonmode signal. Any mismatch in R × CC degrades the
LT6372-1 CMRR. To avoid inadvertently reducing CMRRbandwidth performance, make sure that CC is at least one
magnitude smaller than CD.The effect of mismatched CCs
is reduced with a larger CD:CC ratio.
Rev. 0
22
For more information www.analog.com
LT6372-1
APPLICATIONS INFORMATION
IN +
R
1.54k
CC
10n
CD
100n
IN –
R
1.54k
1. Pick R and CD to have a low pass pole at least 10x
higher than the highest signal of interest (e.g. 500Hz for
a 50Hz signal) using:
V+
+
FilterFreqDIFF =
RG
LT6372-1
VOUT
–
CC
10n
V–
f– 3dB ≈ 500Hz
6372-1 F09
EXTERNAL RFI
FILTER
Figure 9. Adding a Simple External RC Filter at the Inputs to
an Instrumentation Amplifier Is Effective in Further Reducing
Rectification of High Frequency Out-Of-Band Signals
To avoid any possibility of common mode to differential
mode signal conversion, match the common mode lowpass filter on each input to 1% or better. Here are the steps
to help determine appropriate values for the filter:
1
2πR(2CD +CC )
=
1
2πR(2CD +0.1CD )
=
1
4.2πRCD
2. Select CC = CD/10.
If implemented this way, the common-mode pole frequency is placed about 20x higher than the differential
pole frequency. Here are the differential and commonmode low pass pole frequencies for the values shown in
Figure 9:
FilterFreqDIFF = 500Hz
FilterFreqCM = 10kHz
Rev. 0
For more information www.analog.com
23
LT6372-1
APPLICATIONS INFORMATION
Error Budget Analysis
The LT6372-1 features a split reference configuration providing a convenient and effective way to interface a bipolar
swing to an ADC input without additional precision components. Performing the same level shift with traditional
+
10V
350Ω
350Ω
350Ω
5V REF
+
10V
350Ω
REF2
RG
243Ω
intsrumentation amplifiers as shown in Figure 11 requires
external precison components which decrease accuracy, increase cost and occupy valuable PCB space. The
error budget in Table 2 shows the total system error of a
LT6372-1 used as a bridge amplifier.
350Ω
LT6372-1
REF1
350Ω
350Ω
–
RG
243Ω
LT6370A
350Ω
–
+
–
6372-1 F11
6372-1 F10
PRECISION BRIDGE TRANSDUCER
5V REF
REF
LT6370A MONOLITHIC
INSTRUMENTATION AMPLIFIER
G = 100, RG = ±0.1%, ±10ppm TC
Figure 10. Precision Bridge Amplifier Using LT6372-1
PRECISION BRIDGE TRANSDUCER
R1
R2
LT6370A MONOLITHIC
INSTRUMENTATION AMPLIFIER
G = 100, RG = ±0.1%, ±10ppm TC
Figure 11. Precision Bridge Amplifier with External Level Shift
Table 2. Error Budget
ERROR, ppm OF FULL SCALE
ERROR SOURCE
CALCULATION
= 25°C
Absolute Accuracy at TA
Gain Error, %
Input Offset Voltage, µV
Output Offset Voltage, µV
Input Offset Current, nA
CMRR, dB
LT6372-1
2200
3000
137.5
12.25
250
Gain Error in % • 10k + 1000
VOSI/20mV
[VOSO/100]/20mV
[(IOS)(350)/2]/20mV
[(CMRR in ppm)(5V)/20mV
Total Accuracy Error
Drift to 85°C
Gain Drift, ppm/°C
Input Offset Voltage Drift, µV/°C
Output Offset Voltage Drift, µV/°C
2700
1800
120
(Gain Drift + 10ppm/°C)(60°C)
[(VOSI Drift)(60°C)]/20mV
[(VOSO Drift)(60°C)]/100/20mV
Total Drift Error
Resolution
Gain Nonlinearity, ppm of Full Scale
Typ 0.1Hz to 10Hz Voltage Noise, µVP-P
5599.75
4620
50
10
(0.1Hz to 10Hz Noise)/20mV
Total Resolution Error
Grand Total Error
60
10279.75
G = 100
All errors are min/max and referred to input.
Rev. 0
24
For more information www.analog.com
LT6372-1
TYPICAL APPLICATIONS
Differential Output Instrumentation Amplifier
AC Coupled Instrumentation Amplifier
+VS
+VS
+
VBIAS
–
–
12pF
10k
–
–IN
–VS
LTC2057
OUTPUT
R1
500k
C1
0.3µF
LTC2057
6372-1 TA02
+
–OUT
f –3dB =
1
(2π)(R1)(C1)
= 1.06Hz
6372-1 TA03
Precision Voltage-to-Current Converter
VS
+
+IN
LT6372-1
RG
RX
REF1,2
VX
–
–IN
–V S
LTC2057
+
[(+IN) – (–IN)]G
V
IL = X =
RX
RX
G=
IL
–
–VS
LT6372-1
REF1,2
10k
REF1,2
–IN
RG
+OUT
LT6372-1
–
RG
+IN
+
+IN
+
LOAD
24.2kΩ
+1
RG
6372-1 TA04
High Side, Bidirectional Current Sense
IL = ±2A
VBUS
VBUS > –12V
VBUS < 11V
RSENSE
0.05Ω
+
RG
499Ω
+VS
LT6372-1
–
LOAD
! 24.2k $
VOUT =IL •RSENSE • #1+
&
RG %
"
= 2.5V / A
REF1,2
6372-1 TA05
–VS
Rev. 0
For more information www.analog.com
25
LT6372-1
PACKAGE DESCRIPTION
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.50 REF
2.65 ±0.05
1.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ±0.05
4.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
0.75 ±0.05
1.50 REF
19
R = 0.05 TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
20
0.40 ±0.10
1
PIN 1
TOP MARK
(NOTE 6)
4.00 ±0.10
2
2.65 ±0.10
2.50 REF
1.65 ±0.10
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. 0
26
For more information www.analog.com
LT6372-1
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
0.305 ±0.038
(.0120 ±.0015)
TYP
16
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0213 REV F
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
27
LT6372-1
TYPICAL APPLICATION
P3
P2
P4
P1
D4 D3 D2 D1
IN4 IN3 IN2 IN1
S4 S3 S2 S1
U1
ADG441
VSS GND VDD
R9 5.1V
C1
0.1µF
RF3 1.1k
RF2
R5
350
R7
350
R4
R3
R2
R1
200K 200k 200k 200k
+10V
RG
97.6
SW1
P1
Gain Select
Switch
P2
P3
RF4 73.2
R6
350
RF3
1.1k
11k
V+
+IN
+RGF
+RGS
U3
LT6372-1
5V nominal
-RGS
REF2
-RGF
(0V diff input)
REF1
-IN V+10V
Output
1K D1
1N751
+10V
RF4 73.2
R8
350
RF2
11k
P4
S4 S3 S2 S1
VSS GND VDD
U2
ADG441
IN4 IN3 IN2 IN1
D4 D3 D2 D1
+10V
+10V
Programmable Gain Amplifier
+10V
P4
P1
P3
P2
Gains: 2, 20,
200, and 500V/V
6372-1 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Instrumentation Amplifiers
AD8429
Low Noise Instrumentation Amplifier
VS = 36V, IS = 6.7mA, VOS = 50µV, BW = 15MHz, eni = 1nV/√Hz, eno = 45nV/√Hz
LT6372-0.2
Low Drift Instrumentation Amplifier
LT6372-1 with Min Gain = 0.2V/V
LT6370
Low Drift Instrumentation Amplifier
VS = 30V, IS = 2.65mA, VOS = 25µV, BW = 3.1MHz, eni = 7nV/√Hz, eno = 65nV/√Hz
LTC1100
Zero-Drift Instrumentation Amplifier
VS = 18V, IS = 2.4mA, VOS = 10μV, BW = 19kHz, 1.9µVP-P DC to 10Hz
AD8421
Low Noise Instrumentation Amplifier
VS = 36V, IS = 2mA, VOS = 25μV, BW = 10MHz, eni = 3nV/√Hz, eno = 60nV/√Hz
AD8221
Low Power Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 25μV, BW = 825kHz, eni = 8nV/√Hz, eno = 75nV/√Hz
LT1167
Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 40μV, BW = 1MHz, eni = 7.5nV/√Hz, eno = 67nV/√Hz
AD620
Low Power Instrumentation Amplifier
VS = 36V, IS = 900μA, VOS = 50μV, BW = 1MHz, eni = 9nV/√Hz, eno = 72nV/√Hz
LTC6800
RRIO Instrumentation Amplifier
VS = 5.5V, IS = 800μA, VOS = 100μV, BW = 200kHz, 2.5µVP-P DC to 10Hz
LTC2053
Zero-Drift Instrumentation Amplifier
VS = 11V, IS = 750μA, VOS = 10μV, BW = 200kHz, 2.5µVP-P DC to 10Hz
LT1168
Low Power Instrumentation Amplifier
VS = 36V, IS = 350μA, VOS = 40μV, BW = 400kHz, eni = 10nV/√Hz, eno = 165nV/√Hz
Operational Amplifiers
LTC2057
40V Zero Drift Op Amp
VOS = 4μV, Drift = 15nV/°C, IB = 200pA, IS = 900μA
Analog to Digital Converters
LTC2389-16
16-Bit SAR ADC
2.5Msps, 96dB SNR, 162.5mW
LTC2367-16
16-Bit SAR ADC
500Ksps, 94.7dB SNR, 6.8mW
Rev. 0
28
10/20
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 2020
工商网监
湘ICP备2023018690号
