LT8210EUJ#PBF

LT8210 100V VIN and VOUT Synchronous 4-Switch Buck‑Boost DC/DC Controller with Pass-Thru FEATURES DESCRIPTION Pin-Selectable Pass-Thru or Fixed Output CCM, DCM, Burst Mode® Operation n Programmable Non-Switching Pass-Thru Window n 18μA Pass-Thru Mode I with 99.9% Efficiency Q n V Range: 2.8V to 100V (4.5V for Start-Up) IN n V OUT Range: 1V to 100V n Reverse Input Protection to –40V n ±1.25% Output Voltage Accuracy (–40°C to 125°C) n ±3% Accurate Current Monitoring n ±5% Accurate Current Regulation n 10V Quad N-Channel MOSFET Gate Drivers n EXTV CC LDO Powers Drivers from VOUT/External Rail n ±20% Cycle-by-Cycle Inductor Current Limit n No Top MOSFET Refresh Noise in Buck or Boost n Fixed/Phase-Lockable Frequency: 80kHz to 400kHz n Spread Spectrum Frequency Modulation for Low EMI n Power Good Output Voltage/Overcurrent Monitor n Available in a 38-Lead TSSOP and 40-Lead (6mm x 6mm) QFN Packages The LT®8210 is a 4-switch synchronous buck-boost DC/DC controller that can operate in pass-thru, forced continuous, pulse-skipping and Burst Mode® operation. Pass-Thru is a feature that passes the input directly to the output when the input is within a user programmable window. Pass-Thru mode eliminates switching losses and EMI along with maximizing efficiency. For input voltages above or below the pass-thru window, the buck or boost regulation loops maintain the output at the set maximum or minimum values, respectively. n The GATEVCC driver supply is regulated to 10.6V allowing the use of standard-level MOSFETs and can be powered through the EXTVCC pin for improved efficiency. The GATEVCC regulator is back-drive-protected to ride through input brownouts while maintaining regulation. Optional reverse input protection down to –40V can be implemented with the addition of a single N-channel MOSFET. The LT8210 includes a precision current sense amplifier that can accurately monitor and limit output or input average current. APPLICATIONS All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 10135340. Automotive, Industrial, Telecom, Avionics Systems n Automotive Start-Stop, Emergency Call Applications n ISO 7637, ISO 16750, MIL-1275, DO-160 Applications n TYPICAL APPLICATION 4m A + 4.7µH B 220µF 10µF ×2 D 22µF ×2 0.1µF SNSP1 SNSN1 PGND VOUT 8V TO 16V 5A SNSP2 SNSN2 VIN EXTVCC 100k VDD 96 PASS– THRU REGION 24 92 88 12 FB1 7.15k MODE2 2.2µF 100 36 VOUT LT8210 MODE1 4.7µF Transfer Characteristic 220µF FB2 100k PWGD SYNC/ SPRD RT SS GND VC1 38.3k 46.4k 1nF 330pF 59k 4.7nF VDD 7.15k IMON VC2 100pF 8210 TA01a 71.5k 15nF 0 84 VIN VOUT EFFICIENCY 4 8 12 16 INPUT VOLTAGE (V) 20 EFFICIENCY (%) VINP DG GATEVCC Pass-Thru Transfer Characteristic (VOUT(BOOST) = 8V, VOUT(BUCK) = 16V) BG2 SW2 BST2 TG2 EN/UVLO BST2 + C 0.1µF TG1 BST1 SW1 BG1 BST1 4m VOLTAGE (V) VIN REGULATES: 4V TO 100V SURVIVES: –40V TO 100V 24 80 8210 TA01b 2.2nF Rev. B Document Feedback For more information www.analog.com 1 LT8210 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Table of Contents........................................... 2 Absolute Maximum Ratings............................... 3 Pin Configuration........................................... 3 Order Information........................................... 3 Electrical Characteristics.................................. 4 Typical Performance Characteristics.................... 7 Pin Functions............................................... 12 Block Diagram.............................................. 14 Operation................................................... 15 Overview.................................................................. 15 Continuous Conduction Mode (CCM)...................... 15 Discontinuous Conduction Mode (DCM)................. 15 Burst Mode Operation.............................................. 15 Pass-Thru Mode...................................................... 15 Power Switch Control (CCM, DCM, Burst Mode Operation).................................................. 16 Power Switch Control: Buck Region (VINP > 1.19 • VOUT)............................................. 17 Power Switch Control: Boost Region (VINP  175°C VINP DG–VIN GATEVCC VDD PGND UNDERVOLTAGE COMPARTORS VIN NO_SW VINP VOUT MODE1 CLK_BST SLP CLK_BK PGND BOOST LOGIC BST2 TG2 CLK_BST RT SNSN2 REVERSE RESET_BST SYNC RT VCP BG2 NO_SW SHORT_FB SYNC CHARGE PUMP GATEVCC OPERATING REGION CONTROL MODE2 SNSP2 GATEVCC SW2 SLP 1.01V + + + VOUT A3 – 600μA/V – 1.20V IMON + + SHORT_FB – 1.00V A2 FB2 – + SHORT_FB + PWGD + 0.90V FB1 + FB2 – 1.10V SHORT_FB A1 VDD – 1.00V – 5μA FB1 NO_SW NO_SW GND SS VC1 VC2 8210 BD F01 Figure 1. Block Diagram 14 Rev. B For more information www.analog.com LT8210 OPERATION Refer to the Block Diagram (Figure 1) when reading the following sections about the operation of the LT8210. Overview The LT8210 has four different operating modes that can be selected by setting the MODE1 and MODE2 pins either high (>1.17V) or low ( 1.19 • VOUT) A When VINP is greater than VOUT by 19% (typical) or more, the part will run in the buck region. In the buck region, switch D is always on while switch C is always off. Switches A and B will toggle on and off acting as a synchronous buck regulator. If the inductor current should drop below the reverse current sense threshold in DCM or negative current sense threshold in CCM, switch B will be turned off for the remainder of the switching cycle, preventing the inductor current from falling any further. B C 100% OFF D 100% ON –VOUT L VINP–VOUT L IL A+D B+D A+D B+D 8210 F04 Power Switch Control: Boost Region (VINP > VOUT(BUCK), the LT8210 will operate in the buck region. In this region switch D is always on while switch C is always off, switches A and B will toggle on and off, acting as a synchronous buck regulator, while maintaining the output at VOUT(BUCK). When VIN is between 93% to 119% of VOUT(BUCK), switch D will also begin switching to avoid the need for pulse skipping. Switch C will alternate with D in this region. When VINP 1.45V AND TJUNCTION < 175°C CHIP ON/SWITCHER OFF • SWITCHER DISABLED • GATEVCC AND VDD OUTPUTS ENABLED • SS HELD LOW VGATEVCC > 3.9V AND VDD > 2.9V VIN > –1.2V operation or to a resistive divider between VIN and ground to program an undervoltage lockout (UVLO) threshold. EXTVCC/GATEVCC/VDD Power Supplies Power for the TG1, BG1, TG2, BG2 MOSFET drivers and the internal VDD regulator are derived from GATEVCC. The GATEVCC supply is linearly regulated to 10.6V (typical) from PMOS low dropout regulators powered by either the VINP or EXTVCC pins. When the voltage on EXTVCC exceeds 8V (typical) and is simultaneously lower than VINP, GATEVCC will be regulated from EXTVCC. The internal comparison between EXTVCC and VINP causes the LT8210 to regulate GATEVCC from the lower of these two voltages, minimizing power dissipation. This comparison criteria is dropped when VINP is less than 8.5V (typical). This allows the EXTVCC pin to maintain GATEVCC above 10V during an input brownout condition. If EXTVCC is not used connect to ground through a 100k resistor. The GATEVCC regulator has built-in backdrive protection should the input momentarily drop below the GATEVCC voltage to avoid discharging the bypass capacitor and resetting the part. The LT8210 will maintain normal operation as long as both the VINP and GATEVCC voltages remain above their undervoltage lockout (UVLO) thresholds, typically 2.7V and 3.7V, respectively. The GATEVCC regulator is current limited in order to prevent excessive power dissipation and possible damage. This current limit decreases linearly at higher voltages, effectively clamping the internal power dissipation at 3W (typical). Figure 10 shows the typical GATEVCC current limit as a function of voltage on the VINP and EXTVCC pins. Lower current limit at higher voltages CC 120 DG CHARGING INP FROM VINP FROM EXTVCC VDG–VINP > 2.8V AND VINP > 2.8V IGATEVCC (mA) 100 • CHARGE PUMP ENABLED • DG PIN CHARGING • SS HELD LOW SWITCHER ENABLED • SS PIN CHARGES • SWITCHING BEGINS • FORCED DISCONTINOUS MODE UNTIL SS > 2.5V CC 80 60 40 20 0 8210 F09 Figure 9. Start-Up Sequence 10 20 30 40 50 60 70 VOLTAGE (V) 80 90 100 8210 F10 Figure 10. GATEVCC Current Limit vs VINP, EXTVCC Rev. B For more information www.analog.com 19 LT8210 OPERATION restricts the amount of gate drive current that the LT8210 can provide and should be considered when selecting the power MOSFETs and the switching frequency. The voltage at the VDD pin is linearly regulated to 3.3V from GATEVCC and powers the low voltage circuitry within the LT8210. It should be bypassed with a minimum 2.2μF X5R/X7R capacitor to ground placed close to the pin. VDD is a good choice for tying logic pins high (e.g., MODE1, MODE2, SYNC/SPRD) and as the pull-up supply for the PWGD pin. The VDD regulator has a 10mA current limit. For powering external loads other than those described from the VDD rail please contact the factory for support. Reverse Input Protection The LT8210 includes optional reverse input protection down to –40V. To implement this feature, a power N-channel MOSFET should be placed with its source connected to VIN, its drain connected to VINP and its gate connected to the DG pin. When the voltage at VIN drops below –1.2V (typical) the DG pin is clamped to the VIN pin through an internal 30Ω (typical) switch. With its gate and source shorted, the external MOSFET is forced into cutoff, disconnecting VINP and downstream circuitry from the input and preventing damage. The VIN, DG, and EN/UVLO pins are all able to withstand voltages down to –40V without damage or excessive current flow. If polarized capacitors are used for input filtering, they should be placed on the VINP side of the DG MOSFET. During normal operation, the DG – VIN voltage is charged to approximately 8.5V via the internal charge pump in order to fully enhance the MOSFET. Switching will be disabled if the DG – VIN voltage drops below 2.1V (typical) and re-enabled when it exceeds 2.8V (typical). The DG undervoltage lockout is POWER INPUT –40V TO 100V + VIN DG TO DRAIN OF SWITCH A VINP LT8210 8210 F11 Figure 11. Implementing Reverse Input Protection 20 intended to prevent excessive power dissipation in the DG MOSFET when it is not enhanced and current conducts through its body diode. The internal charge pump is able to source up to 180μA from the DG pin for fast charging and minimal delay at start-up. If reverse input protection is not needed, VINP should be connected to VIN directly or through a small RC filter (e.g., 1Ω, 1μF) and a 1nF, 25V ceramic capacitor should be placed between the DG and VIN pins. Current Monitoring and Regulation The LT8210 is equipped with a precision current sense amplifier that can be used for monitoring and regulating average current. The current measurement accuracy is comparable to stand-alone current sense amplifiers making it suitable for applications that require precision monitoring. The input common mode range of the amplifier spans 0V to 100V allowing monitoring and regulation of output, input, or ground current (Figure 12, Figure 13 and Figure 14, respectively). A current linearly proportional to the voltage between the SNSP2, SNSN2 pins is sourced from the IMON pin and into a resistor connected to ground, generating an amplified version of the sense resistor voltage. As the voltage on the IMON pin approaches 1.00V, amplifier A3 will begin to sink current from VC1 (and also VC2 in pass-thru mode) until the part transitions from voltage regulation to current regulation. The closed loop IMON voltage is regulated to within 3% of 1.01V for tight current limiting. A current regulation loop may be implemented in CCM, DCM, Burst Mode operation, or pass-thru mode. The IMON amplifier operates continuously while the part is enabled including the nonswitching states in DCM, Burst Mode operation, and passthru mode. If the IMON voltage approaches 1.01V while in the non-switching pass-thru state, switching will be re-initiated to limit average current. Do not place RSENSE2 on either the SW1 or SW2 nodes. If the current regulation/ monitoring is not needed, connect IMON to VDD and the SNSP2, SNSN2 pins to ground to disable internal circuitry and reduce quiescent current. Rev. B For more information www.analog.com LT8210 OPERATION RSENSE2 FROM DRAIN OF SWITCH D TO SYSTEM VOUT + VOUT SNSP2 SNSN2 LT8210 8210 F12 Figure 12. Output Current Sense FROM POWER INPUT OR DG FET RSENSE2 TO DRAIN OF SWITCH A + SNSP2 SNSN2 VINP LT8210 8210 F13 Figure 13. Input Current Sense FROM DRAIN OF SWITCH D VOUT + VOUT RSENSE2 LOAD A turn-on, the following three pulses will be skipped, and so on. The foldback circuit increases the number of skipped pulses with each successive switch A pulse where this threshold is exceeded, otherwise the skip count is reset. The maximum foldback of the switching frequency is 1/32×fSW. In addition to preventing inductor runaway, the LT8210 foldback scheme significantly reduces switch A power dissipation in a short circuit condition. When the output is shorted to ground, the power dissipation in switch A is dominated by transitional losses as it turns on and off. Reducing the number of switch A pulses over a given period reduces the dissipated power proportionally. The boost loop is naturally protected from inductor current runaway in the LT8210 as it can only occur when VINP ~ VOUT, which is within the buck-boost region. While the buck loop is simultaneously controlling the inductor current each cycle it is not possible for the boost channel to run away. Bootstrap Capacitor Voltage SNSP2 SNSN2 LT8210 8210 F14 Figure 14. Ground Current Sense Buck Foldback The LT8210 actively prevents inductor current runaway while the buck loop is switching. The inductor current can run away when its rising slope exceeds the falling slope to such a degree that the current continues to increase each period even while switching at the minimum SW1 duty cycle. A buck regulator is most susceptible to runaway when the output voltage is near ground causing the inductor current falling slope to be flat. This situation is exacerbated by high input voltage and high switching frequency. To prevent runaway, the LT8210 may skip switch A pulses while VOUT is less than 10% of VINP and the FB1 voltage is lower than 900mV. At the start of the switch A on-time, the sensed inductor current must be below an internally set pulse-skipping threshold otherwise the next pulse on switch A will be skipped. If the inductor current exceeds the pulse-skipping threshold on the next switch During normal operation the BST1 and BST2 capacitors are charged from the GATEVCC supply through diodes DBST1 and DBST2 while switches B and C are turned on, respectively. Depending on the switching region, switch B and/or C may be off continuously, preventing conventional charging. The LT8210 utilizes an internal charge pump to maintain the bootstrap capacitor voltage of the nonswitching channel(s) and avoid forced top gate refresh pulses. While the bootstrap capacitor voltage is above 0.75 • GATEVCC, a charging current of 50μA (typical) is sourced from the BST pin of the non-switching channel. If this voltage drops below 0.75 • GATEVCC, the average charging current is increased to roughly 200μA. Finally, if the bootstrap capacitor voltage should fall below roughly 2V, a minimum on-time bottom gate pulse will be forced to maintain a minimum bootstrap capacitor voltage. An internal clamp across each boost capacitor prevents overcharging. In the non-switching pass-thru state, the internal charge pump is enabled to recharge the BST1 and BST2 capacitors whenever the voltage across either drops below 0.75 • GATEVCC and then disabled when it exceeds 0.9 • GATEVCC. Rev. B For more information www.analog.com 21 LT8210 OPERATION PWGD Pin The PWGD pin is an open drain logic output which goes high when the output voltage and IMON pin voltage are within preset limits after switching is enabled. The internal PWGD pull-down is released when VOUT is within ±10% of its programmed value. In CCM, DCM, and Burst Mode operation, this occurs when the FB1 voltage is within ±10% of the 1.00V system reference. In pass-thru mode, PWGD will go high when VFB1 > 0.90V and VFB2 < 1.10V, indicating that the output voltage is within ±10% of the programmed output pass-thru window. PWGD will be pulled low if the voltage on the IMON pin exceeds 1.20V, indicating that the average current exceeds its programmed limit by 20% or more. The LT8210 includes a 0.90V + FB1 – FB2 + 1.10V – built-in self-test to confirm the system reference circuitry is functioning properly. This reference voltage is used for voltage regulation, current regulation, clock generation, and fault detection. If the system reference is outside of preset tolerances switching is disabled and the PWGD pin pulled low. Switching will also be disabled and the PWGD pin pulled low if the VINP, GATEVCC, VDD, or DG pin voltage fall below their respective under voltage lockout thresholds. The PWGD pin pull-up resistor can be connected to any external rail up to 40V. Using either VDD or GATEVCC as the pull-up supply has the added advantage that PWGD will be in the correct state when the LT8210 is disabled. Figure 15 shows the conditions which determine the state of the PWGD pin. SWITCHING DISABLED PWGD 40V NFET IMON + 1.20V – 8210 F15 Figure 15. PWGD Logic 22 Rev. B For more information www.analog.com LT8210 APPLICATIONS INFORMATION 7. CSS selected to set soft-start behavior. The Applications Information section serves as a guideline for selecting external components based on the details of the application. For this section please refer to the basic LT8210 application circuit shown in Figure 16. Component selection typically follows the approach described below: 8. (Optional) – Reverse input protection (DG) MOSFET selected to stand-off worst case VINP to VIN voltage and minimize conduction loss during regulation. 9. (Optional) – Current regulation and/or monitoring implemented with RSENSE2, RIMON, CIMON. 1. RSENSE is selected based on the required output current and the input voltage range The examples and equations in this section assume continuous conduction mode unless otherwise noted. For pass-thru mode use VOUT(BUCK), VOUT(BOOST) in place of VOUT for buck, boost calculations, respectively. All electric characteristics referred to in this section represent typical values unless otherwise specified. 2. Inductor value (L) and switching frequency (fSW) are chosen based on ripple, stability and efficiency requirements. 3. Power MOSFETs (A, B, C, D) are selected to maximize efficiency while satisfying the voltage and current ranges of the application. Maximum Output Current and RSENSE Selection RSENSE is chosen based on the required output current. With a properly selected inductor value, the maximum average inductor current is relatively independent of inductor current ripple, duty cycle, and switching region. This simplifies the selection of RSENSE, which can often be an iterative process. The RSENSE value in the buck region 4. CIN and COUT capacitors selected to filter input and output RMS currents and achieve the desired voltage ripple. 5. CBST1, CBST2, and CGATEVCC capacitors are selected to store adequate charge to power the gate drivers. 6. Type II compensation network designed for VC1 (and also VC2 if pass-thru mode is used). DG VIN + CIN L B CIN C BST1 COUT (CER) CBST2 SNSP1 SNSN1 PGND SNSN2 VIN EXTVCC VOUT R1A FB1 R2A MODE1 FB2 MODE2 CGATEVCC PWGD SYNC/ SPRD RT CVDD COUT LT8210 VDD DBST2 + SNSP2 DG GATEVCC BST2 VOUT BG2 SW2 BST2 TG2 EN/UVLO DBST1 RSENSE2 D CBST1 (CER) TG1 BST1 SW1 BG1 VINP REN1 REN2 RSENSE A SS RT GND CSS VC1 RC1 CP1 RC2 CC1 RPWGD R2B IMON VC2 CP2 R1B 8210 F16 RIMON CC2 CIMON Figure 16. Basic LT8210 Applications Circuit Rev. B For more information www.analog.com 23 LT8210 APPLICATIONS INFORMATION for a given maximum output current, IOUT(MAX), can be calculated as: R SENSE(BUCK) ≈ 50mV IOUT(MAX) While operating in the boost region, the output current is equal to the inductor current multiplied by D’BST ≅ VINP/VOUT. Using VINP(MIN) the RSENSE for a desired IOUT(MAX) can be calculated as: R SENSE(BOOST) ≈ 50mV IOUT(MAX) • VOUT 150 NORMALIZED CURRENT (%) The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. The inductor value is inversely related to the ripple current. Typically, the inductor ripple current, ∆IL, is set to 20%to 40% of the maximum inductor current. The minimum inductor value necessary to maintain a desired ripple can be calculated for both buck and boost regions as: VINP(MIN) Maximum Current vs Duty Cycle 125 100 75 BUCK REGION BUCK– BOOST REGION BOOST REGION 50 IL(PEAK) IL(AVG) IOUT(MAX) 25 0 0.25 0.50 0.75 1 1.25 1.50 1.75 VINP/VOUT (V) 2 8210 F17 Figure 17. Example of Maximum Average Inductor Current and Output Current vs VINP/VOUT A margin of 20% to 30% on the lower of the two calculated RSENSE values is usually recommended. The RSENSE resistor should be a low inductance type so as not to degrade stability. A small low pass filter between RSENSE and the SNSP1 and SNSN1 pins like that shown in Figure 18 is not required but may improve switching edge jitter in some applications. These filter components should be placed near the pins. RSENSE SW1 10Ω 1nF SNSP1 L SW2 10Ω SNSN1 LT8210 8210 F18 Figure 18. Optional SNSP1, SNSN1 Filter for Improved Jitter 24 Inductor Selection L ( BUCK) > VOUT • ( VIN(MAX) − VOUT ) fSW • IOUT(MAX) • ΔIL % • VIN(MAX) L ( BOOST) > VIN(MIN) 2 • ( VOUT − VIN(MIN) ) fSW • IOUT(MAX) • ΔIL % • VOUT 2 In addition to ripple considerations, the inductance should be large enough to prevent subharmonic oscillations. In a current mode controlled regulator, the current sense loop creates a double pole at half the switching frequency which can degrade system stability when its quality factor (QCS) is much greater than 1.0. The current sense loop damping is a function of the inductor current slope and the internal slope compensating ramp. The LT8210 slope compensation scheme is designed to provide optimal damping of the current sense loop for any input voltage when the inductor value is set to the following value. L OPTIMAL = (260 + (5.5 • VOUT ))• R SENSE • 1 fSW for example : L OPTIMAL (VOUT =12V ) = 325 • R SENSE • L OPTIMAL (VOUT =48 V ) = 525 • R SENSE • 1 fSW 1 fSW This simplifies loop compensation as the current sense loop damping becomes independent of duty cycle and switching region. Selecting LOPTIMAL also optimizes line regulation and line step response. A lower inductance value will increase QCS, and a sufficiently undersized inductor can result in subharmonic oscillation for buck duty cycles above 50% and boost duty cycles below 50%. Choose an inductor at least 70% of the calculated optimal value to avoid subharmonic Rev. B For more information www.analog.com LT8210 APPLICATIONS INFORMATION instability. Inductor parasitics can significantly impact converter efficiency. For high efficiency, choose an inductor with low core loss, such as ferrite. The inductor should also have low DC resistance (DCR) to reduce the I2R losses. Selecting an inductor with DCR comparable to the RDS(ON) of the power MOSFETs is a reasonable starting point. If radiated noise is a concern, a shielded inductor should be used. Ferrite cores saturate abruptly leading to significant increase in ripple when the saturation current rating, ISAT, is exceeded. ISAT should be greater than the worst-case peak inductor current with added margin. The maximum peak inductor current can be approximated: IL(MAX) ≈ 60mV R SENSE + ∆IL(MAX) A Assuming an inductor ripple current, ∆IL(MAX), of 40%, the peak inductor current could be 145% of the maximum output current. Adding an additional margin of 25% beyond worst-case yields a conservative minimum inductor ISAT rating of 90mV/RSENSE, for example. Switching Frequency Selection The RT frequency adjust pin allows the user to program the switching frequency from 80kHz to 400kHz. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, but requires larger inductor and capacitor values. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. For low power applications, consider operating at higher switching frequencies to minimize total solution size. The selection of RSENSE, the inductor value and switching frequency are interrelated. To maintain the ripple current amplitude and subharmonic stability, the inductor value will track the product of RSENSE and the switching period, T. The RSENSE value is set by load requirements. The inductor value is determined by ripple current and subharmonic stability criteria. A practical approach is to adjust the switching frequency to optimize system performance once the RSENSE and L values have already been chosen. The component selection flow would follow: 1. Select RSENSE based on required output current. 2. Select inductor value based on desired ripple for a range of fSW (e.g., 80kHz to 120kHz). 3. Adjust switching frequency to satisfy: fsw(OPTIMAL) = (260 + (5.5 • VOUT ))• R SENSE L Setting the switching frequency to fSW(OPTIMAL) has a host of benefits including: optimized loop stability, optimized line rejection, and flat average maximum inductor current across duty cycle and switching region. RT Set Switching Frequency The switching frequency of the LT8210 is set with a resistor from the RT pin to ground. Table 2 shows switching frequency versus RT for 1% resistor values. The minimum and maximum switching frequencies are internally limited should the RT resistor be shorted (typically fSW = 700kHz) or opened (typically fSW = 45kHz). It is strongly recommended to use a RT resistor even when LT8210 is synchronized to an external clock using the SYNC/SPRD pin. If the synchronization signal is lost, the LT8210 will revert to the RT set value within approximately 20μs. Table 2. Switching Frequency vs RT Value (1% Resistor) RT (kΩ) fSW (kHz) RT (kΩ) fSW (kHz) 16.2 411 41.2 190 16.9 397 43.2 184 17.8 379 45.2 177 18.7 364 47.5 171 20.0 343 49.9 165 21.0 329 52.3 160 22.1 315 54.9 155 23.2 300 59.0 147 24.3 289 64.9 138 25.5 277 71.5 130 26.7 267 78.7 122 28.0 257 86.6 115 29.4 247 95.3 109 30.9 237 100 105 32.4 229 110 100 34.0 220 121 95 35.7 212 133 90 37.4 205 150 85 39.2 200 174 80 Rev. B For more information www.analog.com 25 LT8210 APPLICATIONS INFORMATION Frequency Synchronization Spread-Spectrum Frequency Modulation The LT8210 switching frequency can be synchronized to an external clock using the SYNC/SPRD pin. The threshold of the SYNC/SPRD receiver makes it compatible with standard 1.8V to 5.0V logic levels. Driving the SYNC/SPRD with a 50% duty cycle waveform is a good choice, otherwise maintain the duty cycle between 10% and 90%. Because an internal phase-locked loop (PLL) is used, there is no restriction between the synchronization frequency and the RT set oscillator frequency. The LT8210 is designed to transition seamlessly between RT set switching frequency and the external synchronization clock. If the SYNC/SPRD signal drops below 50kHz or stops altogether, the LT8210 will revert to the RT set frequency within 20μs (typical). Setting the RT programmed frequency near the synchronization frequency is recommended to maintain normal switching should the external clock signal be lost. When a synchronization clock is first applied the internal PLL may take 50μs or more to settle within 5% of the external clock frequency. When the clock synchronization feature is not used, connect SYNC/SPRD to VDD to enable spread spectrum modulation, otherwise connect to GND. SYNC functionality is internally disabled while in Burst Mode SW operation. Switching regulators can be particularly troublesome for applications where electromagnetic interference (EMI) is a concern. To improve EMI performance, the LT8210 includes a user selectable triangular frequency modulation scheme. When the SYNC/SPRD pin is tied to VDD spread spectrum functionality is enabled. The LT8210 will slowly spreads fSW between the nominal RT set frequency to 112.5% of that value. Figure 21 and Figure 22 demonstrate the difference in the noise spectrum and switching waveforms with the spread spectrum feature enabled. Conducted Average EMI Comparison (AM Band) 70 SPREAD OFF SPREAD ON AMPLITUDE (dBµV/m) 60 RBW = 10kHz 5.5dB 50 40 5.4dB 30 8.9dB 9.3dB 20 10 0 0.15 0.65 1.15 1.65 2.15 FREQUENCY (MHz) 2.65 3.15 8210 F21 Figure 21. Conducted Average EMI Comparison (AM Band) Example SYNC 1V/DIV IL 2A/DIV SW2 50V/DIV SW1 20V/DIV IL 2A/DIV SW2 20V/DIV 10µs/DIV 8210 F19 Figure 19. Transition from RT Set Frequency to Synchronization VOUT (AC) 100mV/DIV 40µs/DIV FIGURE 37 CIRCUIT VIN = 20V SYNC 1V/DIV 8210 F22 Figure 22. Switching Waveforms with Spread-Spectrum Enabled IL 2A/DIV SW1 20V/DIV SW2 20V/DIV 10µs/DIV 8210 F20 Figure 20. Transition from Synchronization to RT Set Frequency 26 Rev. B For more information www.analog.com LT8210 APPLICATIONS INFORMATION 2.0 The LT8210 requires four external N-channel power MOSFETs (switches A, B, C, D in Figure 16). The gate drive voltage of the LT8210 is typically greater than 10V allowing the use of both logic-level and standard-level threshold devices. The MOSFET maximum VBR(DSS) and drain current (ID) ratings should exceed worst-case voltage and current conditions of the application with added margin for safety. The maximum continuous drain current of a power MOSFET is de-rated as a function of temperature with that information commonly available in the data sheet. It is important to consider power dissipation when selecting power MOSFETs. The most efficient circuit will use MOSFETs that dissipate the least amount of power. Dissipated power and the resulting temperature rise in external components will set the upper bound on the power that can be delivered by the LT8210. MOSFET power dissipation comes from two primary components: (1) I2R conduction losses when the switch is fully turned “on” and drain current is flowing, and (2) power dissipated while the switch is turning “on” or “off”. Conduction losses are independent of frequency. Switching losses, on the other hand, scale with frequency and voltage. Generally speaking, conduction losses are dominant at higher currents and lower voltages, whereas switching losses tend to dominate at lower currents and higher voltages. Accurately predicting MOSFET power dissipation is a complex problem that is best suited to efficiency calculators such as that included in LTpowerCAD® II. That being said, efficiency calculators are no substitute for real world measurements. The following section provides approximations of the main source(s) of power dissipation for switches A, B, C, and D as a function of the input and output voltages and switching region. The purpose is to guide MOSFET selection by determining where the majority of power is being dissipated. In the following equations ρτ is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically 0.4%/°C as shown in Figure 23. For a maximum junction temperature of 125°C, using a value of ρτ = 1.5 is reasonable. QSW is the switching charge and can be approximated as QSW = QGD + QGS/2 if not explicitly stated in the MOSFET data sheet. ρτ NORMALIZED ON-RESISTANCE (Ω) Power MOSFET Selection 1.5 1.0 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 8210 F23 Figure 23. Normalized RDS(ON) vs Temperature The constant k is empirically derived to equal 1.3 and is a function of driver resistance, MOSFET threshold and gate resistance. Switch A: The power dissipation in switch A is due to both conduction and switching losses and typically reaches a maximum at either VIN(MIN) in the boost region, or VIN(MAX) in the buck region. Table 3. Switch A Power Dissipation REGION Buck POWER DISSIPATION 2 IOUT • (VOUT /VIN )• ρ τ • R DS(ON) + k •IOUT • VIN • fSW • Q SW Buck-Boost 2 IOUT • (VOUT /VIN )• ρ τ • R DS(ON) + k •IOUT • VIN • fSW • Q SW Boost 2 IOUT • (VOUT /VIN ) 2 • ρ τ • R DS(ON) Pass-Thru (Non-Switching) 2 IOUT • ρ τ • R DS(ON) Switch B: Switch B power dissipation is due mainly to conduction losses and reaches a maximum in the buck region at VIN(MAX). Table 4. Switch B Power Dissipation REGION Buck Buck-Boost POWER DISSIPATION 2 IOUT • (1– VOUT /VIN ) • ρ τ • R DS(ON) 2 IOUT • (1 – VOUT /VIN ) • ρ τ • R DS(ON) Boost 0 Pass-Thru (Non-Switching) 0 Rev. B For more information www.analog.com 27 LT8210 APPLICATIONS INFORMATION Switch C: Switch C power dissipation is due to both conduction and switching losses and reaches a maximum at VIN(MIN). REGION Buck Buck-Boost POWER DISSIPATION 0 2 IOUT • VOUT • (VOUT – VIN )• ρ τ • R DS(ON) / 2 VIN + k • IOUT • VOUT 2 • fSW • Q SW /VIN Boost 2 2 IOUT • VOUT • (VOUT – VIN )• ρ τ • R DS(ON) / VIN Example of Switch Power Dissipation vs VINP VOUT = 24V MA MB MC MD TOTAL POWER LOSS 4 POWER LOSS (W) Table 5. Switch C Power Dissipation 5 3 2 1 0 0 + k • IOUT • VOUT 2 • fSW • Q SW /VIN Pass-Thru (Non-Switching) 48 60 Figure 24. Example of Switch Power Dissipation vs VINP 0 Table 6. Switch D Power Dissipation POWER DISSIPATION Buck 2 IOUT • ρ τ • R DS(ON) Buck-Boost 2 IOUT • (VOUT /VIN ) • ρ τ • R DS(ON) Boost 2 IOUT • (VOUT /VIN ) • ρ τ • R DS(ON) Pass-Thru (Non-Switching) 2 IOUT • ρ τ • R DS(ON) In most applications the losses reach a maximum when the LT8210 is delivering IOUT(MAX) at VIN(MIN). Switches A and C will typically dissipate the majority of the power in these situations. To achieve higher output current it may be beneficial to use two MOSFETs in parallel for switches A and C to minimize conduction losses. While the power dissipated in switches B and D is comparatively low during normal operation, it may become significant if the output is shorted to ground. A representative example of switch power dissipation as a function of input voltage is shown in Figure 24. Other power loss sources include: the gate drive current (fSW • ∑ switching MOSFET QG) multiplied by the supply voltage of the GATEVCC regulator (either VINP or VEXTVCC), 28 24 36 INPUT VOLTAGE (V) 8210 F24 Switch D: Switch D power dissipation is due mainly to conduction losses and reaches a maximum in the boost region at VIN(MIN). REGION 12 as well as and the energy required to charge MOSFET QOSS, QRR each switching cycle depending on switching region. Power MOSFETs of a particular technology trade on-resistance, RDS(ON), and gate charge QG (along with QSW, QOSS, QRR) and maximizing efficiency often comes down to finding a MOSFET that strikes the right balance between these factors. Higher switching frequency and higher voltage operation drive up switching losses making the value of QG (and QSW, QOSS, QRR) increasingly significant. In the non-switching pass-thru state, efficiency depends primarily on conduction losses in power switches A, D, and DG (if used) along with the inductor DCR. In these situations prioritize low RDS(ON) over QG to maximize efficiency. CIN and COUT Selection Input and output capacitors are necessary to suppress the voltage ripple caused by discontinuous current moving in and out of the regulator. In the buck region the input current is discontinuous while in the boost region the output current is discontinuous. Selecting the proper input and output capacitors boils down to three considerations: 1. Voltage ripple is inversely proportional to capacitance. 2. ESR must be low to minimize its contribution to voltage ripple. 3. RMS current rating of the capacitor(s) should exceed worst-case application conditions with margin. Rev. B For more information www.analog.com LT8210 APPLICATIONS INFORMATION For buck operation, the value of CIN to achieve a desired input ripple voltage (∆VIN) can be calculated as: C IN ≅ IOUT(MAX) ⎛ VOUT ⎞ ⎛ VOUT ⎞ •⎜ ⎟ • ⎜ 1− ⎟ ∆VIN • fsw ⎝ VIN ⎠ ⎝ VIN ⎠ ∆VIN is typically chosen at a level acceptable to the user. 100mV to 200mV is a good starting point. The ESR of the input capacitance should be less than: ∆VIN ESR (IN,MAX) < The input RMS current can be approximated by: VOUT VIN • VIN VOUT −1 This formula has a maximum at VIN = 2VOUT, where IRMS  =  IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The capacitance necessary to achieve a desired output ripple, ∆VOUT, can be calculated for the buck and boost switching regions: C OUT(BOOST) = IOUT(MAX) • ( VOUT − VIN(MIN) ) ∆VOUT • fsw • VOUT VOUT • ( VIN(MAX) − VOUT ) C OUT(BUCK) = ∆VOUT • fsw 2 • VIN(MAX) • 8 • L The ESR of the output capacitor should be low enough to not significantly increase the ripple voltage: ESR (BOOST) < ESR (BUCK ) < ∆VOUT • VIN(MIN) IOUT(MAX) • VOUT ∆VOUT • L • fSW ⎛ VOUT ⎞ VOUT • ⎜ 1– ⎟ V IN(MAX ) ⎠ ⎝ COUT should also tolerate the maximum RMS output current of when operating in the boost region: IOUT(RMS) ≈ IOUT(MAX) • %IRMS,ALUM ≈ IOUT(MAX) IIN(RMS) ≈ IOUT(MAX) • For both the CIN and COUT capacitors, a good approach for larger values is to use a parallel combination of aluminum electrolytics for bulk capacitance and ceramics for low ESR and to handle the RMS currents. When used together, the percentage of RMS current that will flow through the aluminum electrolytic capacitor can be approximated by the following equation: VOUT VIN(MIN) −1 100% 1+ ( 2π • fSW • C (CER) • R ESR(ALUM) ) 2 Where RESR(ALUM) is the ESR of the aluminum capacitor and C(CER) is the total value of the ceramic capacitor(s). Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. Specifically, the ceramic capacitors on the input should be placed in close proximity to switches A and B, and output ceramics should be placed close to switches C and D. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in higher ESR bulk capacitors. X5R and X7R are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. At higher input and output voltages multiple ceramic capacitors in parallel may be needed due to limited availability of high voltage, large value ceramic capacitors in standard footprints. In situations with high input and/or output voltage ripple a RC low-pass filter with time constant of 1μs or greater is recommended for VINP and VOUT inputs to maintain low jitter on switching edges. Bootstrap Capacitors (CBST1, CBST2) The top MOSFET gate drive signals, TG1 and TG2, are driven between their respective BST and SW pin voltages. The BST1 and BST2 voltages are biased from floating bootstrap capacitors CBST1 and CBST2, which are normally recharged from GATEVCC through diodes DBST1 and DBST2 when their respective top MOSFET is off. The bootstrap capacitors CBST1 and CBST2 need to store roughly 100 times the gate charge (QG) required by top switches A and D. In most situations, a 0.1μF to 0.47μF, X5R or X7R, 25V capacitor is adequate. The bypass capacitance from GATEVCC to ground should be at least ten times the value Rev. B For more information www.analog.com 29 LT8210 APPLICATIONS INFORMATION of the CBST1, CBST2 capacitors. The rise times of the SW1 and SW2 pins can be slowed down through the addition of series resistors between the respective bootstrap capacitors and the BST1 or BST2 pins. The slowing down of the switch edges can improve overshoot but may also degrade efficiency due to increased transitional losses. Bootstrap Diodes (DBST1, DBST2) Silicon diodes rated for 1A with very fast reverse recovery time (