LT8391A
60V 2MHz Synchronous 4-Switch
Buck-Boost LED Driver Controller
FEATURES
DESCRIPTION
4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
n Up to 95% Efficiency at 2MHz
n Proprietary Peak-Buck Peak-Boost Current Mode
n Wide V Range: 4V to 60V
IN
n Wide V
OUT Range: 0V to 60V (51V LED)
n ±3% LED Current Accuracy
n 2000:1 External and 128:1 Internal PWM Dimming
n High Side PMOS PWM Switch Driver
n No Top MOSFET Refresh Noise in Buck or Boost
n Adjustable and Synchronizable: 600kHz to 2MHz
n Flicker-Free Spread Spectrum for Low EMI
n Open and Short LED Protection with Fault Reporting
n Available in 28-Lead TSSOP with Exposed Pad and
28-Lead QFN (4mm × 5mm)
n AEC-Q100 Qualified for Automotive Applications
The LT®8391A is a synchronous 4-switch buck-boost LED
controller that regulates LED current from input voltage
above, below, or equal to the output voltage. The proprietary peak-buck peak-boost current mode control scheme
allows adjustable and synchronizable 600kHz to 2MHz
fixed frequency operation, or internal 25% triangle spread
spectrum operation for low EMI. With 4V to 60V input,
0V to 60V output, and seamless low noise transitions
between operation regions, the LT8391A is ideal for LED
driver and battery charger applications in automotive,
industrial, and battery-powered systems.
n
The LT8391A provides both internal (up to 128:1) and
external (up to 2000:1) LED current PWM dimming with
a high-side PMOS switch. Two CTRL pins provide flexible
20:1 analog dimming with ±3% LED current accuracy at
100mV full scale. Fault protection is provided to detect an
open or short LED condition, during which the LT8391A
retries, latches off, or keeps running.
APPLICATIONS
n
n
Automotive Head Lamps/Running Lamps
High Frequency LED Lighting
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
94% Efficient 24W (16V, 1.5A) 2MHz Buck-Boost LED Driver
VIN
6V TO 32V CONTINUOUS
4V TO 56V TRANSIENT
2.2µH
6mΩ
22µF
63V
4.7µF
100V
×2
0.1µF
SW1 LSP
BST1
INTVCC
LSN
BG1
BG2
10µF
25V
×2
0.1µF
SW2
BST2
Efficiency vs VIN
100
INTVCC
95
GND
165k
100k
FAULT
ANALOG DIM
90.9k
113k
48.7k
56mΩ
INTVCC
ISN
PWM
22nF
80
75
70
60
PWM DIM
VREF
CTRL2
SS
85
65
PWMTG
FAULT
CTRL1
0.47µF
1M
ISP
4.7µF
100k
1µF
FB
SYNC/SPRD
INTVCC
90
TG2
VOUT
EN/UVLO
SSFM OFF
SSFM ON
LT8391A
EFFICIENCY (%)
1µF
383k
TG1
VIN
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
45
8391a TA01b
RP
VC
RT
4.7k
3.3nF
PWM SETTING
EXT
59.0k
2MHz
INT
16V
1.5A
LEDs
300k
488Hz
8391a TA01a
Rev. A
Document Feedback
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1
LT8391A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN/UVLO, VOUT, ISP, ISN....................................60V
(ISP-ISN)..........................................................–1V to 1V
BST1, BST2................................................................66V
SW1, SW2, LSP, LSN..................................... –6V to 60V
INTVCC, (BST1-SW1), (BST2-SW2)..............................6V
(BST1-LSP), (BST1-LSN).............................................6V
FB, PWM, SYNC/SPRD, CTRL1, CTRL2, FAULT............6V
Operating Junction Temperature Range (Notes 2, 3)
LT8391AE........................................... –40°C to 125°C
LT8391AI............................................ –40°C to 125°C
LT8391AH........................................... –40°C to 150°C
LT8391AJ............................................ –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
SW1
26 SW2
TG1
4
25 TG2
LSP
5
LSN
6
VIN
7
INTVCC
8
EN/UVLO
29
GND
28 27 26 25 24 23
24 VOUT
TG1 1
22 TG2
LSP 2
23 PWMTG
21 VOUT
LSN 3
22 SYNC/SPRD
20 PWMTG
29
GND
VIN 4
19 SYNC/SPRD
21 RT
INTVCC 5
9
20 VC
EN/UVLO 6
RP 10
19 FB
RP 7
16 FB
PWM 11
18 SS
PWM 8
15 SS
VREF 12
17 FAULT
CTRL1 13
16 CTRL2
18 RT
17 VC
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJA = 30°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
FAULT
ISN
CTRL2
15 ISN
ISP
VREF
9 10 11 12 13 14
CTRL1
ISP 14
2
SW2
27 BST2
3
BST2
2
BG2
BST1
TOP VIEW
BG1
28 BG2
BST1
1
SW1
BG1
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Rev. A
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LT8391A
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8391AEFE#PBF
LT8391AEFE#TRPBF
LT8391AFE
28-Lead Plastic TSSOP
–40°C to 125°C
LT8391AIFE#PBF
LT8391AIFE#TRPBF
LT8391AFE
28-Lead Plastic TSSOP
–40°C to 125°C
LT8391AHFE#PBF
LT8391AHFE#TRPBF
LT8391AFE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8391AEUFD#PBF
LT8391AEUFD#TRPBF
8391A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT8391AIUFD#PBF
LT8391AIUFD#TRPBF
8391A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT8391AHUFD#PBF
LT8391AHUFD#TRPBF
8391A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 150°C
LT8391AJFE#WPBF
LT8391AJFE#WTRPBF
LT8391AFE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8391AHFE#WPBF
LT8391AHFE#WTRPBF
LT8391AFE
28-Lead Plastic TSSOP
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
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3
LT8391A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VIN Operating Voltage Range
VIN Quiescent Current
l
VEN/UVLO = 0.3V, VOUT = 12V
VEN/UVLO = 1.1V, VOUT = 12V
Not Switching, VOUT = 12V
TYP
4
VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
Not Switching
VOUT Voltage Range
VOUT Quiescent Current
MIN
l
MAX
UNITS
60
V
2
µA
µA
mA
1
270
2.1
2.8
60
V
20
0.1
0.1
40
0.5
0.5
60
µA
µA
µA
4.85
0
Linear Regulators
INTVCC Regulation Voltage
IINTVCC = 20mA
5.0
5.15
V
INTVCC Load Regulation
IINTVCC = 0mA to 80mA
1
4
%
INTVCC Line Regulation
IINTVCC = 20mA, VIN = 6V to 60V
1
4
%
145
190
INTVCC Current Limit
VINTVCC = 4.5V
INTVCC Dropout Voltage (VIN – INTVCC)
IINTVCC = 20mA, VIN = 4V
INTVCC Undervoltage Lockout Threshold
Falling
110
160
3.44
INTVCC Undervoltage Lockout Hysteresis
VREF Regulation Voltage
3.54
3.64
0.24
IVREF = 100µA
l
1.97
2.00
mA
mV
V
V
2.03
V
VREF Load Regulation
IVREF = 0mA to 1mA
0.4
1
%
VREF Line Regulation
IVREF = 100µA, VIN = 4V to 60V
0.1
0.2
%
VREF Current Limit
VREF = 1.8V
2
2.5
3.2
mA
VREF Undervoltage Lockout Threshold
Falling
1.78
1.84
1.90
VREF Undervoltage Lockout Hysteresis
50
V
mV
Control Inputs/Outputs
EN/UVLO Shutdown Threshold
EN/UVLO Enable Threshold
Falling
l
0.3
0.6
1.0
V
l
1.196
1.220
1.244
V
EN/UVLO Enable Hysteresis
13
EN/UVLO Hysteresis Current
VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V
CTRL1, CTRL2 Input Bias Current
VCTRL1/2 = 0.75V (Note 4), Current out of
Pin
CTRL1, CTRL2 Dim-Off Threshold
Falling
l
mV
–0.1
2.2
–0.1
0
2.5
0
0.1
2.8
0.1
µA
µA
µA
0
20
50
nA
190
200
210
mV
CTRL1, CTRL2 Dim-Off Hysteresis
28
mV
PWM Dimming
4
External PWM Dimming Threshold
Rising, RP = 30k
External PWM Dimming Hysteresis
RP = 30k
Internal PWM Dimming Duty Cycle
VPWM = 1V, RP ≥ 51k
VPWM = 1.5V, RP ≥ 51k
VPWM = 2V, RP ≥ 51k
Switching Frequency to Internal PWM Dimming
Frequency Ratio
RP = 51k
RP = 82k
RP = 130k
RP = 200k
RP = 300k
l
1.3
1.4
1.5
220
3
53
47
97
V
mV
%
%
%
256
512
1024
2048
4096
Rev. A
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LT8391A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RP Pin Current Limit
VRP = 0V, Current out of Pin
40
µA
Minimum VOUT for PWMTG to be On
PWM dimming on
2.4
PWMTG On Voltage V(VOUT-PWMTG)
VOUT = 12V
4.5
5
5.5
V
PWMTG Off Voltage V(VOUT-PWMTG)
VOUT = 12V
–0.1
0
0.1
V
3
V
PWM to PWMTG Turn On Propagation Delay
CPWMTG = 3.3nF to VOUT, 50% to 50%
90
ns
PWM to PWMTG Turn Off Propagation Delay
CPWMTG = 3.3nF to VOUT, 50% to 50%
40
ns
PWMTG Turn On Fall Time
PWMTG Turn Off Rise Time
CPWMTG = 3.3nF to VOUT, 10% to 90%
CPWMTG = 3.3nF to VOUT, 90% to 10%
300
10
ns
ns
Error Amplifier
Full Scale LED Current Regulation V(ISP-ISN)
VCTRL1/2 ≥ 1.35V (Note 4), VISP = 12V
VCTRL1/2 ≥ 1.35V (Note 4), VISP = 0V
l
l
97
97
100
100
103
103
mV
mV
9/10th LED Current Regulation V(ISP-ISN)
VCTRL1/2 = 1.15V (Note 4), VISP = 12V
VCTRL1/2 = 1.15V (Note 4), VISP = 0V
l
l
87
87
90
90
93
93
mV
mV
1/2 LED Current Regulation V(ISP-ISN)
VCTRL1/2 = 0.75V (Note 4), VISP = 12V
VCTRL1/2 = 0.75V (Note 4), VISP = 0V
l
l
47.5
47.5
50
50
52.5
52.5
mV
mV
1/20th LED Current Regulation V(ISP-ISN)
VCTRL1/2 = 0.30V (Note 4), VISP = 12V
VCTRL1/2 = 0.30V (Note 4), VISP = 0V
l
l
3
3
5
5
7
7
mV
mV
Zero Scale LED Current Regulation V(ISP-ISN)
VCTRL1/2 = 0.25V (Note 4), VISP = 12V
VCTRL1/2 = 0.25V (Note 4), VISP = 0V
l
l
–2
–2
0
0
2
2
mV
mV
l
0
60
V
ISP/ISN Input Common Mode Range
ISP/ISN Low Side to High Side Switchover
Voltage
VISP = VISN
1.8
V
ISP/ISN High Side to Low Side Switchover
Voltage
VISP = VISN
1.7
V
ISP Input Bias Current
VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
ISN Input Bias Current
VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
2000
µS
LED Current Regulation Amplifier gm
FB Regulation Voltage
VC = 1.2V
FB Line Regulation
VIN = 4V to 60V
l
0.98
FB Load Regulation
FB in Regulation, Current Out of Pin
V
0.2
0.5
%
0.2
0.8
%
10
VC Output Impedance
VC Standby Leakage Current
1.02
660
FB Voltage Regulation Amplifier gm
FB Input Bias Current
1.00
µS
40
10
VC = 1.2V, PWM Dimming Off
–10
0
nA
MΩ
10
nA
Rev. A
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5
LT8391A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
35
40
50
50
65
60
UNITS
Current Comparator
Maximum Current Sense Threshold V(LSP-LSN)
Buck, VFB = 0.8V
Boost, VFB = 0.8V
LSP Pin Bias Current
VLSP = VLSN = 12V
60
µA
LSN Pin Bias Current
VLSP = VLSN = 12V
60
µA
FB Overvoltage Threshold (VFB)
Rising
l
l
mV
mV
Fault
l
1.03
1.05
1.07
l
15
25
35
Rising, V(ISP-ISN) = 0V
l
0.93
0.95
0.97
FB Open LED Hysteresis
V(ISP-ISN) = 0V
l
35
50
65
FB Short LED Threshold (VFB)
Falling
l
0.24
0.25
0.26
FB Short LED Hysteresis
Hysteresis
l
35
50
65
FB Overvoltage Hysteresis
FB Open LED Threshold (VFB)
ISP/ISN Over Current Threshold V(ISP-ISN)
VISP = 12V
ISP/ISN Open LED Threshold V(ISP-ISN)
Falling, VFB = 1.0V
l
8
750
ISP/ISN Open LED Hysteresis
VFB = 1.0V
l
3
FAULT Pull-Down Resistance
10
V
mV
V
mV
V
mV
mV
12
mV
5
7
mV
100
200
Ω
100
200
Ω
SS Hard Pull-Down Resistance
VEN/UVLO = 1.1V
SS Pull-Up Current
VFB = 0.8V, VSS = 0V
10.5
12.5
14.5
µA
SS Pull-Down Current
VFB = 1.0V, VSS = 2V
1.05
1.25
1.45
µA
SS Fault Latch-Off Threshold
Falling
1.7
V
SS Fault Latch-Off Hysteresis
50
mV
SS Fault Reset Threshold
0.2
V
1.00
V
Oscillator
RT Pin Voltage
RT = 100kΩ
Switching Frequency
VSYNC/SPRD = 0V, RT = 226k
VSYNC/SPRD = 0V, RT = 100k
VSYNC/SPRD = 0V, RT = 59.0k
SYNC Frequency
SYNC/SPRD Input Bias Current
6
685
1360
2000
600
VSYNC/SPRD = 5V
SYNC/SPRD Threshold Voltage
Highest Spread Spectrum Above Oscillator
Frequency
l
645
1290
1900
–0.1
0
0.4
VSYNC/SPRD = 5V
21
23
725
1430
2100
kHz
kHz
kHz
2100
kHz
0.1
µA
1.5
V
25
%
Rev. A
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LT8391A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
0.73
0.75
0.77
UNITS
Region Transition
Buck-Boost to Boost (VIN/VOUT)
Boost to Buck-Boost (VIN/VOUT)
0.83
0.85
0.87
Buck to Buck-Boost (VIN/VOUT)
1.23
1.25
1.27
Buck-Boost to Buck (VIN/VOUT)
1.31
1.33
1.35
Peak-Buck to Peak-Boost (VIN/VOUT)
0.96
0.98
1.00
Peak-Boost to Peak-Buck (VIN/VOUT)
1.00
1.02
1.04
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
V(BST-SW) = 5V
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
VINTVCC = 5V
TG1, TG2 Rise Time
TG1, TG2 Fall Time
2.6
1.4
Ω
Ω
3.2
1.2
Ω
Ω
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
25
20
ns
ns
BG1, BG2 Rise Time
BG1, BG2 Fall Time
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
25
20
ns
ns
TG Off to BG On Delay
CL = 3.3nF
25
ns
BG Off to TG On Delay
CL = 3.3nF
25
ns
TG1 Minimum Duty Cycle in Buck Region
Peak-Buck Current Mode
10
%
TG1 Maximum Duty Cycle in Buck Region
Peak-Buck Current Mode
90
%
TG1 Fixed Duty Cycle in Buck-Boost Region
Peak-Boost Current Mode
80
%
BG2 Fixed Duty Cycle in Buck-Boost Region
Peak-Buck Current Mode
20
%
BG2 Minimum Duty Cycle in Boost Region
Peak-Boost Current Mode
10
%
BG2 Maximum Duty Cycle in Boost Region
Peak-Boost Current Mode
90
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8391AE is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8391AI is guaranteed over the –40°C to 125°C operating junction
temperature range. The LT8391AH is guaranteed over the –40°C to 150°C
operating junction temperature range. The LT8391AJ specifications over
the –40°C to 150°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
High junction temperatures degrade operating lifetimes. Operating lifetime
is derated at junction temperatures greater than 125°C.
Note 3: The LT8391A includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
Note 4: VCTRL1/2 represents the condition of CTRL1 when CTRL2 is equal
to 2V or the condition of CTRL2 when CTRL1 is equal to 2V.
Rev. A
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7
LT8391A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs LED Current
(Buck Region)
Efficiency vs LED Current
(Buck-Boost Region)
Efficiency vs LED Current
(Boost Region)
90
90
90
80
80
80
70
60
0
0.2
0.4
0.6 0.8 1 1.2
LED CURRENT (A)
1.4
70
60
50
FRONT PAGE APPLICATION
VIN = 32V, VLED = 16V, fSW = 2MHz
40
1.6
0
0.2
0.4
0.6 0.8 1 1.2
LED CURRENT (A)
Switching Waveforms
(Buck Region)
VSW2
20V/DIV
VSW1
20V/DIV
VSW2
20V/DIV
VSW2
20V/DIV
3.0
2.5
1.6
2.0
IQ (µA)
1.7
1.0
1.3
0.5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
8391a G05
0.4
0.6 0.8 1 1.2
LED CURRENT (A)
500ns/DIV
FRONT PAGE APPLICATION
VIN = 8V, ILED = 1.5A
VIN Shutdown Current
2.8
1.4
1.6
0.0
–50 –25
8391a G06
VIN Quiescent Current
2.6
VIN = 60V
1.5
1.4
5
0.2
IL
2A/DIV
500ns/DIV
FRONT PAGE APPLICATION
VIN = 18V, ILED = 1.5A
LED Current vs VIN
0
0
8391a G03
VSW1
20V/DIV
8391a G04
1.5
FRONT PAGE APPLICATION
VIN = 8V, VLED = 16V, fSW = 2MHz
Switching Waveforms
(Boost Region)
IL
2A/DIV
IL
2A/DIV
1.2
40
1.6
Switching Waveforms
(Buck-Boost Region)
VSW1
20V/DIV
500ns/DIV
FRONT PAGE APPLICATION
VIN = 32V, ILED = 1.5A
60
8391a G02
8391a G01
1.8
1.4
70
50
FRONT PAGE APPLICATION
VIN = 18V, VLED = 16V, fSW = 2MHz
IQ (mA)
40
EFFICIENCY (%)
100
EFFICIENCY (%)
100
EFFICIENCY (%)
100
50
LED CURRENT (A)
TA = 25°C, unless otherwise noted.
VIN = 12V
VIN = 60V
2.4
VIN = 12V
2.2
VIN = 4V
2.0
VIN = 4V
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G07
8391a G08
8
8391a G09
Rev. A
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LT8391A
TYPICAL PERFORMANCE CHARACTERISTICS
5.15
INTVCC Voltage vs Temperature
5.15
5.10
5.10
5.05
5.05
TA = 25°C, unless otherwise noted.
INTVCC Voltage vs VIN
4.0
INTVCC UVLO Threshold
3.9
IINTVCC = 0mA
5.00
IINTVCC = 80mA
IINTVCC = 20mA
VINTVCC (V)
VINTVCC (V)
VINTVCC (V )
3.8
5.00
4.95
4.95
4.90
4.90
RISING
3.7
3.6
FALLING
3.5
3.4
4.85
–50 –25
0
4.85
25 50 75 100 125 150
TEMPERATURE (°C)
3.3
0
10
20
30
VIN (V)
40
50
8391a G10
2.04
2.03
2.03
2.02
2.02
VREF (V)
VREF (V)
VREF Voltage vs VIN
VREF UVLO Threshold
2.00
1.95
2.01
2.00
IVREF = 100µA
2.00
1.99
1.99
IVREF = 1mA
1.98
RISING
1.85
FALLING
1.80
1.75
1.97
0
1.90
1.98
1.97
1.96
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G12
VREF (V)
VREF Voltage vs Temperature
IVREF = 0mA
0
8391a G11
2.04
2.01
3.2
–50 –25
60
1.96
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
30
VIN (V)
40
50
1.70
–50 –25
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G14
8391a G13
EN/UVLO Enable Threshold
8391a G15
EN/UVLO Hysteresis Current
CTRL1/CTRL2 Dim-Off Threshold
3.0
1.240
0.30
1.235
2.8
1.230
0.25
RISING
1.220
FALLING
1.215
1.210
2.6
VCTRL (V)
IHYS (µA)
VEN/UVLO (V)
1.225
2.4
RISING
0.20
FALLING
0.15
2.2
1.205
1.200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G16
2.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G17
0.10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G18
Rev. A
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9
LT8391A
TYPICAL PERFORMANCE CHARACTERISTICS
106
75
50
25
104
104
102
102
100
98
96
0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
VCTRL (V)
94
0
10
20
30
VISP (V)
40
0.99
20
0.98
0
0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04
VFB (V)
0.97
–50 –25
VIN = 4V
VIN = 12V
VIN = 60V
0
60
55
50
45
40
35
30
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
BUCK
BOOST
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G23
FB Overvoltage Threshold
8391a G24
FB Open LED Threshold
1.10
RISING
FB Short LED Threshold
1.10
0.40
1.05
0.35
1.00
0.30
RISING
FALLING
VFB (V)
VFB (V)
Maximum Current Sense
vs Temperature
65
8391a G22
0.95
0.90
0.85
0.85
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G25
RISING
0.95
0.90
10
25 50 75 100 125 150
TEMPERATURE (°C)
70
1.00
40
0
0
8391a G21
CURRENT LIMIT (mV)
1.01
VFB (V)
V(ISP-ISN) (mV)
80
60
ISP = 0V
ISP = 12V
ISP = 60V
94
–50 –25
60
1.03
1.02
0.80
–50 –25
50
FB Regulation vs Temperature
100
1.00
98
8391a G20
V(ISP-ISN) Regulation vs VFB
1.05
100
96
8391a G19
120
106
V(ISP-ISN) (mV)
V(ISP-ISN) (mV)
V(ISP-ISN) (mV)
100
V(ISP-ISN) Regulation
vs Temperature
V(ISP-ISN) Regulation vs VISP
0.80
–50 –25
VFB (V)
125
V(ISP-ISN) Regulation vs VCTRL
TA = 25°C, unless otherwise noted.
FALLING
FALLING
0.25
0.20
0.15
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G26
0.10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G27
Rev. A
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LT8391A
TYPICAL PERFORMANCE CHARACTERISTICS
15.0
25
12.5
20
10.0
RISING
FALLING
10
PULL-UP
7.5
5.0
2.5
5
0
–50 –25
2.5
0
SWITCHING FREQUENCY (MHz)
30
15
Oscillator Frequency
vs Temperature
SS Current vs Temperature
ISS (µA)
V(ISP-ISN) (mV)
ISP/ISN Open LED Threshold
TA = 25°C, unless otherwise noted.
25 50 75 100 125 150
TEMPERATURE (°C)
0.0
–50 –25
PULL-DOWN
0
25 50 75 100 125 150
TEMPERATURE (°C)
RT = 59.0k
2.0
RT = 100k
1.5
1.0
RT = 226k
0.5
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8391a G30
8391a G28
8391a G29
Rev. A
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11
LT8391A
PIN FUNCTIONS
BG1: Buck Side Bottom Gate Drive. Drives the gate of
buck side bottom N-channel MOSFET with a voltage swing
from ground to INTVCC.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor to the SW1 pin. The BST1 pin swings from a diode
voltage drop below INTVCC to (VIN + INTVCC).
SW1: Buck Side Switch Node. The SW1 pin swings from
a Schottky diode voltage drop below ground up to VIN.
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-channel MOSFET with a voltage swing from
SW1 to BST1.
LSP: Positive Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
LSN: Negative Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
VIN: Input Supply. The VIN pin must be tied to the power
input to determine the buck, buck-boost, or boost operation regions. Locally bypass this pin to ground with a
minimum 1µF ceramic capacitor.
INTVCC: Internal 5V Linear Regulator Output. The INTVCC
linear regulator is supplied from the VIN pin, and powers the internal control circuitry and gate drivers. Locally
bypass this pin to ground with a minimum 4.7µF ceramic
capacitor.
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the part and reduce VIN quiescent current below 2µA. Force the pin above 1.233V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from VIN to ground. An
accurate 2.5µA pull-down current allows the programming of VIN UVLO hysteresis. If neither function is used,
tie this pin directly to VIN.
RP: Internal PWM Dimming Frequency Setting. The RP pin
is used to set the internal PWM dimming frequency with a
resistor to ground. Do not use a resistor larger than 1MΩ
and do not leave this pin open. If an external PWM dimming
pulse is available at the PWM pin, tie this pin to ground.
PWM: PWM Dimming Input. The PWM pin can be used
in two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with
a digital pulse from 0V to a voltage higher than 1.5V to
control PWM dimming of the LED string. Make sure the
RP pin is tied to ground in this case. For internal PWM
dimming, apply an analog voltage between 1V and 2V to
generate an internal digital pulse by comparing with the
internal ramp. If PWM dimming is not used, tie this pin to
INTVCC. Forcing the pin low turns off TG1 and TG2, turns
on BG1 and BG2, disconnects the VC pin from all internal
loads, and turns off PWMTG.
VREF: Voltage Reference Output. The VREF pin provides an
accurate 2V reference capable of supplying 1mA current.
Locally bypass this pin to ground with a 0.47µF ceramic
capacitor.
CTRL1: Control Input for LED Current Sense Threshold. The
CTRL1 pin is used to program the LED regulation current:
ILED =
Min ( VCTRL1 – 0.25V,VCTRL2 – 0.25,1V )
10 •RLED
The VCTRL1 can be set by an external voltage reference
or a resistor divider from VREF to ground. For 0.25V ≤
VCTRL1 ≤ 1.15V, the current sense threshold linearly goes
up from 0mV to 90mV. For VCTRL1 ≥ 1.35V, the current
sense threshold is constant at 100mV full scale value.
For 1.15V ≤ VCTRL1 ≤ 1.35V, the current sense threshold
smoothly transitions from the linear function of VCTRL1
to the 100mV constant value. Tie CTRL1 to VREF for the
100mV full scale threshold. Force the pin below 0.2V to
stop switching.
ISP: Positive Terminal of the LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin
connection.
ISN: Negative Terminal of the LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin
connection.
12
Rev. A
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LT8391A
PIN FUNCTIONS
CTRL2: Thermal Control Input for LED Current Sense
Threshold. The CTRL2 pin is used to program LED current
derating versus temperature. The VCTRL2 with a negative
temperature coefficient can be set by an external temperature dependent resistor divider from VREF to ground.
For 0.25V ≤ VCTRL2 ≤ 1.15V, the current sense threshold
linearly goes up from 0mV to 90mV. For VCTRL2 ≥ 1.35V,
the current sense threshold is constant at 100mV full
scale value. For 1.15V ≤ VCTRL2 ≤ 1.35V, the current sense
threshold smoothly transitions from the linear function of
VCTRL2 to the 100mV constant value. Tie CTRL2 to VREF
for the 100mV full scale threshold. Force the pin below
0.2V to stop switching.
FAULT: LED Fault Open Drain Output. The FAULT pin is
pulled low when any of the following conditions happens:
1. Open LED (VFB > 0.95V & V(ISP-ISN) < 10mV)
2. Short LED (VFB < 0.25V)
To function, the pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high state
and latched during PWM low state.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
22nF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and
stops switching. Using a single resistor from SS to VREF,
the LT8391A can be set in three different fault protection
modes during open or short LED fault conditions: hiccup
(no resistor), latchoff (499k), and keep-running (100k).
See more details in the Applications Information section.
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and LED fault protection. The
internal error amplifier with its output VC regulates VFB
to 1.00V through the DC/DC converter. During open LED
(VFB > 0.95V & V(ISP-ISN) < 10mV) or short LED (VFB <
0.25V) fault conditions, the part pulls the FAULT pin low
and gets into one fault mode per customer setting. During
an overvoltage (VFB > 1.05V) condition, the part turns off
all TG1, BG1, TG2, BG2, and PWMTG.
VC: Error Amplifier Output to Set Inductor Current
Comparator Threshold. The VC pin is used to compensate the control loop with an external RC network. During
PWM low state, the VC pin is disconnected from all internal loads to store its voltage information for the highest
PWM dimming performance.
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 600kHz to 2MHz.
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at internal oscillator frequency. Apply a clock signal for external
frequency synchronization. Tie to INTVCC for 25% triangle
spread spectrum above internal oscillator frequency.
PWMTG: PWM Dimming Top Gate Drive. A buffered and
inverted version of the PWM input signal, the PWMTG
pin drives an external high side PMOS PWM switch with
a voltage swing from the higher voltage of (VOUT –5V)
and 1.2V to VOUT. Leave this pin unconnected if not used.
VOUT: Output Supply. The VOUT pin must be tied to the
power output to determine the buck, buck-boost, or boost
operation regions. The VOUT pin also serves as positive rail
for the PWMTG drive. Locally bypass this pin to ground
with a minimum 1µF ceramic capacitor.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
SW2: Boost Side Switch Node. The SW2 pin swings from
a Schottky diode voltage drop below ground to VOUT.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor to the SW2 pin. The BST2 pin swings from a diode
voltage drop below INTVCC to (VOUT + INTVCC).
BG2: Boost Side Bottom Gate Drive. Drives the gate of
boost side bottom N-Channel MOSFET with a voltage
swing from ground to INTVCC.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
Rev. A
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13
LT8391A
BLOCK DIAGRAM
LSN
VIN
INTVCC
LSP
INTVCC
+
5V LDO
–
VREF
+
A1
–
2V REF
BST1
A3
TG1
PEAK_BUCK
SW1
BUCK
LOGIC
INTVCC
PWMON
RT
OSC
SYNC/SPRD
0.2V
CTRL1
0.2V
CTRL2
EN/UVLO
1.220V
BG1
VOS
GND
+
–
+
–
+
–
FBOV
VOUT/BST2
VIN/BST1
CHARGE
CONTROL
FB
GND
1.05V
INHIBIT
SWITCH
–
+
BG2
+
–
ISOC
2.5µA
PWMON
VISP-ISN
0.75V
PEAK_BOOST
BOOST
LOGIC
INTVCC
SW2
TG2
+
PWM
RP
VOUT
PWMTG
–
INT/EXT
PWM
VIS
FB
FAULT
+
–
+
–
0.25V
FB
10µA
LED
FAULT
LOGIC
+
–
INTVCC
EA1
OPEN
VOUT –5V 0.95V
BST2
VREF
12.5µA
PWMON
0.1V
A4
1.25µA
+
+
–
EA2
SHORT
PWMON
1V
FB
+
+
+
CTRL1
CTRL2
1.25V
–
+
+
A2=10
VIS
SS
VC
GND
–
ISP
ISN
0.25V
8391a BD
14
Rev. A
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LT8391A
OPERATION
The LT8391A is a current mode LED controller that can
regulate LED current from input voltage above, below, or
equal to the LED string voltage. The ADI proprietary peakbuck peak-boost current mode control scheme uses a single inductor current sense resistor and provides smooth
transition between buck region, buck-boost region, and
boost region. Its operation is best understood by referring
to the Block Diagram.
PEAK-BUCK
PEAK-BOOST
Power Switch Control
Figure 1 shows a simplified diagram of how the four
power switches A, B, C, and D are connected to the inductor L, the current sense resistor RSENSE, power input VIN,
power output VOUT, and ground. The current sense resistor RSENSE connected to the LSP and LSN pins provides
inductor current information for both peak current mode
control and reverse current detection in buck region,
buck-boost region, and boost region. Figure 2 shows the
current mode control as a function of VIN/VOUT ratio and
Figure 3 shows the operation region as a function of VIN/
VOUT ratio. The power switches are properly controlled
to smoothly transition between modes and regions.
Hysteresis is added to prevent chattering between modes
and regions.
VIN
TG1
VOUT
A
SW1
BG1
B
RSENSE
L
D
8391a F02
Figure 2. Current Mode vs VIN/VOUT Ratio
(1)
BUCK
(3)
(2)
BUCK-BOOST
(2)
BOOST
(4)
0.75
0.85
1.00
1.25
1.33
VIN/VOUT
8391a F03
Figure 3. Operation Region vs VIN/VOUT Ratio
TG2
SW2
C
0.98 1.00 1.02
VIN/VOUT
BG2
8391a F01
Figure 1. Simplified Diagram of the Power Switches
There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode control in buck-boost region, (3) peak-boost current mode
control in buck-boost region, and (4) peak-boost current
mode control in boost region. The following sections
give detailed description for each state with waveforms,
in which the shoot-through protection dead time between
switches A and B, between switches C and D are ignored
for simplification.
Peak-Buck in Buck Region (VIN >> VOUT)
When VIN is much higher than VOUT, the LT8391A uses
peak-buck current mode control in buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current hits
the peak buck current threshold commanded by VC voltage at buck current comparator A3 during (A+D) phase,
switch A is turned off and switch B is turned on for the
rest of the cycle. Switches A and B will alternate, behaving
like a typical synchronous buck regulator.
Rev. A
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15
LT8391A
OPERATION
A
A
B
B
C
100% OFF
C
D
100% ON
D
20%
80%
IL
IL
A+D
B+D
B+D
A+D
20%
80%
A+D
A+C
A+D
B+D
A+C
B+D
8391a F05
8391a F04
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT)
Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
When VIN is slightly higher than VOUT, the LT8391A uses
peak-buck current mode control in buck-boost region
(Figure 5). Switch C is always turned on for the beginning 20% cycle and switch D is always turned on for the
remaining 80% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. After 20% cycle, switch C is turned off and
switch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
threshold commanded by VC voltage at buck current comparator A3 during (A+D) phase, switch A is turned off and
switch B is turned on for the rest of the cycle.
Peak-Boost in Buck-Boost Region (VIN
LBOOST >
0
–10
0.1
Figure 9. CISPR 25 Average Conducted EMI
PEAK CONDUCTED EMI (dBµV)
The rising edge of the synchronization clock represents
the beginning of a switching cycle, turning on switches A
and C, or switches A and D.
L>
10• VOUT •RSENSE
f
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
Rev. A
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LT8391A
APPLICATIONS INFORMATION
RSENSE Selection and Maximum Output Current
Power MOSFET Selection
RSENSE is chosen based on the required output current.
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
The LT8391A requires four external N-channel power
MOSFETs, two for the top switches (switches A and D
shown in Figure 1) and two for the bottom switches
(switches B and C shown in Figure 1). Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance
RDS(ON), reverse transfer capacitance CRSS and maximum
current IDS(MAX).
In boost region, the lowest maximum average load current happens at VIN(MIN) and can be calculated as:
⎛ 50mV ΔIL(BOOST) ⎞ VIN(MIN)
IOUT(MAX_BOOST) = ⎜
−
⎟⎠ • V
2
⎝ RSENSE
OUT
where ∆IL(BOOST) is peak-to-peak inductor ripple current
in boost region and can be calculated as:
ΔIL(BOOST) =
VIN(MIN)•(VOUT − VIN(MIN) )
f•L• VOUT
In buck region, the lowest maximum average load current
happens at VIN(MAX) and can be calculated as:
To achieve 2MHz operation, the power MOSFET selection is critical. With typical 25ns shoot-through protection
dead time, high performance power MOSFETs with low
Qg and low RDS(ON) must be used.
Since the gate drive voltage is set by the 5V INTVCC
supply, logic-level threshold MOSFETs must be used in
LT8391A applications. Switching four MOSFETs at higher
frequency like 2MHz, the substantial gate charge current
from INTVCC can be estimated as:
(
IINTVCC = f • QgA + QgB + QgC + QgD
⎛ 50mV ΔIL(BUCK) ⎞
IOUT(MAX_BUCK) = ⎜
−
⎟⎠
2
⎝ RSENSE
where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
f is the switching frequency
ΔIL(BUCK) =
where:
VOUT •(VIN(MAX) − VOUT )
f•L• VIN(MAX)
The maximum current sense RSENSE in boost region is:
RSENSE(BOOST) =
2•50mV• VIN(MIN)
2•ILED(MAX)• VOUT + ΔIL(BOOST)• VIN(MIN)
The maximum current sense RSENSE in buck region is
RSENSE(BUCK) =
)
2•50mV
2•ILED(MAX) + ΔIL(BUCK)
The final RSENSE value should be lower than the calculated
RSENSE in both buck and boost regions. A 20% to 30%
margin is usually recommended.
QgA, QgB, QgC, QgD are the total gate charges of
MOSFETs A, B, C, D at 5V VGS.
Make sure the total required INTVCC current not exceeding the INTVCC current limit in the data sheet. Typically,
MOSFETs with less than 15nC Qg are recommended.
The LT8391A uses the VIN/VOUT ratio to transition between
modes and regions. Bigger IR drop in the power path caused
by improper MOSFET and inductor selection may prevent the
LT8391A from smooth transition. Make sure that low RDS(ON)
MOSFETs and low DCR inductor are used to satisfy:
ILED(MAX) ≤
0.025 • VOUT
R A,B +RC,D +RSENSE +RL
where:
RA,B is the maximum RDS(ON) of MOSFETs A or B at 25°C
RC,D is the maximum RDS(ON) of MOSFETs C or D at 25°C
RL is the maximum DCR resistor of inductor at 25°C
Rev. A
For more information www.analog.com
21
LT8391A
APPLICATIONS INFORMATION
The RDS(ON) and DCR increase at higher junction temperatures and the process variation have been included
in the calculation above.
In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the
maximum power dissipation happens in boost region,
when it remains on all the time. Its maximum power dissipation at maximum output current is given by:
⎛ ILED(MAX)•VOUT ⎞2
PA(BOOST) = ⎜
⎟ •ρ T •RDS(ON)
VIN
⎝
⎠
where ρT is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically 0.4%/°C as shown in Figure 11. For a
maximum junction temperature of 125°C, using a value
of ρT = 1.5 is reasonable.
ρT NORMALIZED ON-RESISTANCE (Ω)
2.0
0.5
50
100
0
JUNCTION TEMPERATURE (°C)
150
Figure 11. Normalized RDS(ON) vs Temperature
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output current
is given by:
VIN − VOUT
•ILED(MAX)2•ρ T •RDS(ON)
VIN
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
PC(BOOST) =
(VOUT − VIN )•VOUT
VIN
•RDS(ON)+k•VOUT 3•
22
PD(BOOST) =
VOUT
•ILED(MAX)2•ρ T •RDS(ON)
VIN
For the same output voltage and current, typically switch
A has the highest power dissipation in buck region at
VIN(MAX) and switch C has the highest power dissipation
in boost region at VIN(MIN).
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
The junction-to-ambient thermal resistance RTH(JA)
includes the junction-to-case thermal resistance RTH(JC)
and the case-to-ambient thermal resistance RTH(CA). This
value of TJ can then be compared to the original, assumed
value used in the iterative calculation process.
1.0
8391a F11
PB(BUCK) =
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
TJ = TA + P • RTH(JA)
1.5
0
–50
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
2
ILED(MAX)
VIN
•ILED(MAX)2•ρ T
•CRSS•f
Optional Schottky Diode (DB, DD) Selection
The optional Schottky diodes DB (in parallel with switch B)
and DD (in parallel with switch D) conduct during the
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode
of synchronous switches B and D from turning on and
storing charge during the dead time. In particular, DB
significantly reduces reverse recovery current between
switch B turn-off and switch A turn-on, and DD significantly reduces reverse recovery current between switch
D turn-off and switch C turn-on. They improve converter
efficiency and reduce switch voltage stress. In order for
the diode to be effective, the inductance between it and
the synchronous switch must be as small as possible,
mandating that these components be placed adjacently.
Rev. A
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LT8391A
APPLICATIONS INFORMATION
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, of at least 1µF, should also
be placed from VIN to GND and VOUT to GND as close to
the LT8391A pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss
in the higher ESR bulk capacitors. X5R or X7R dielectrics
are preferred, as these materials retain their capacitance
over wide voltage and temperature ranges. Many ceramic
capacitors, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired operating
voltage.
Discontinuous input current is highest in buck region due
to the switch A toggling on and off. Make sure that the
CIN capacitor network has low enough ESR and is sized
to handle the maximum RMS current. In buck region, the
input RMS current is given by:
Δ VCAP(BOOST) =
ΔVCAP(BUCK) =
ILED •(VOUT − VIN(MIN) )
C OUT • VOUT • f
⎛
⎞
V
VOUT • ⎜ 1– OUT ⎟
⎝ VIN(MAX) ⎠
8 • L • f2 • C OUT
The maximum steady ripple due to the voltage drop
across the ESR is given by:
Δ VESR(BOOST) =
VOUT •ILED(MAX)
VIN(MIN)
•ESR
⎛
⎞
V
VOUT • ⎜ 1– OUT ⎟
⎝ VIN(MAX) ⎠
ΔVESR(BUCK) =
• ESR
L•f
INTVCC Regulator
Input Capacitance CIN
IRMS ≈ILED(MAX)•
The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
VOUT
VIN
•
−1
VIN
VOUT
The formula has a maximum at VIN = 2VOUT, where IRMS
= ILED(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief.
Output Capacitance COUT
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the COUT capacitor
network is capable of reducing the output voltage ripple.
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. The INTVCC powers internal circuitry and gate drivers in the LT8391A. The
INTVCC regulator can supply a peak current of 145mA and
must be bypassed to ground with a minimum of 4.7µF
ceramic capacitor. Good local bypass is necessary to supply
the high transient current required by MOSFET gate drivers.
Higher input voltage applications with large MOSFETs
being driven at higher switching frequencies may cause
the maximum junction temperature rating for the LT8391A
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
loading of the INTVCC also needs to be taken into account
for the power dissipation calculation. The total LT8391A
power dissipation in this case is VIN • IINTVCC, and overall
efficiency is lowered. The junction temperature can be
estimated by using the equation:
TJ = TA + PD • θJA
Rev. A
For more information www.analog.com
23
LT8391A
APPLICATIONS INFORMATION
where θJA (in °C/W) is the package thermal resistance.
VIN
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked operating in continuous mode at maximum VIN.
R1
EN/UVLO
Top Gate MOSFET Driver Supply (CBST1, CBST2)
The top MOSFET drivers, TG1 and TG2, are driven between
their respective SW and BST pin voltages. The boost voltages are biased from floating bootstrap capacitors CBST1
and CBST2, which are normally recharged through both the
external and internal bootstrap diodes when the respective
top MOSFET is turned off. External bootstrap diodes are recommended because the internal bootstrap diodes are not
always strong enough to refresh top MOSFETs at 2MHz. Both
capacitors are charged to the same voltage as the INTVCC
voltage. The bootstrap capacitors CBST1 and CBST2, need to
store about 100 times the gate charge required by the top
switches A and D. In most applications, a 0.1µF to 0.47µF,
X5R or X7R dielectric capacitor is adequate.
Programming VIN UVLO
A resistor divider from VIN to the EN/UVLO pin implements VIN undervoltage lockout (UVLO). The EN/UVLO
enable falling threshold is set at 1.214V with 10mV hysteresis. In addition, the EN/UVLO pin sinks 2.5µA when the
voltage on the pin is below 1.214V. This current provides
user programmable hysteresis based on the value of R1.
The programmable UVLO thresholds are:
R1+R2
VIN(UVLO+) =1.233V•
+2.5µA•R1
R2
RUN/STOP
CONTROL
(OPTIONAL)
R2
LT8391A
GND
8391a F12
Figure 12. VIN Undervoltage Lockout (UVLO)
string. The voltage drop across RLED is (Kelvin) sensed by
the ISP and ISN pins. The CTRL1 and CTRL2 pins should
be tied to a voltage higher than 1.35V to get the full-scale
100mV (typical) threshold across the sense resistor. Either
the CTRL1 or CTRL2 pin can be used to dim the LED current to zero, although relative accuracy decreases with the
decreasing sense threshold. When either the CTRL1 or
CTRL2 pin voltage is less than 1.15V, the LED current is:
ILED =
Min(VCTRL1,VCTRL2 )− 250mV
10•RLED
where Min(VCTRL1, VCTRL2) is the minimum value of CTRL1
and CTRL2 pin voltages. When Min(VCTRL1, VCTRL2) is
between 1.15V and 1.35V, the LED current varies with the
Min(VCTRL1, VCTRL2), but departs from the equation above
by an increasing amount as Min(VCTRL1, VCTRL2) increases.
Ultimately, when Min(VCTRL1, VCTRL2) > 1.35V, the LED
current no longer varies. The typical V(ISP-ISN) threshold
vs Min(VCTRL1, VCTRL2) is listed in Table 2.
Table 2. V(ISP-ISN) Threshold vs Min(VCTRL1, VCTRL2)
Min(VCTRL1, VCTRL2) (V)
V(ISP-ISN) (mV)
1.15
90
R1+R2
R2
1.20
94.5
Figure 12 shows the implementation of external shutdown control while still using the UVLO function. The
NMOS grounds the EN/UVLO pin when turned on, and
puts the LT8391A in shutdown with quiescent current
less than 2µA.
When Min(VCTRL1, VCTRL2) is higher than 1.35V, the LED
current is regulated to:
Programming LED Current
The LED current is programmed by placing an appropriate
value current sense resistor, RLED, in series with the LED
The CTRL1/CTRL2 pin should not be left open (tie to VREF
if not used). The CTRL1/CTRL2 pin can also be used in
VIN(UVLO−) =1.220V•
24
ILED =
1.25
98
1.30
99.5
1.35
100
100mV
RLED
Rev. A
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LT8391A
APPLICATIONS INFORMATION
conjunction with a thermistor to provide overtemperature
protection for the LED load, or with a resistor divider to
VIN to reduce output power and switching current when
VIN is low. The presence of a time varying differential
voltage ripple signal across ISP and ISN at the switching frequency is expected. The amplitude of this signal
is increased by higher LED load current, lower switching
frequency, or smaller value output filter capacitor. Some
level of ripple signal is acceptable, and the compensation capacitor on the VC pin filters the signal so the average difference between ISP and ISN is regulated to the
user-programmed value. The ripple voltage amplitude
(peak-to-peak) in excess of 20mV should not cause misoperation, but may lead to noticeable offset between the
average value and the user-programmed value.
Dimming Control
There are two methods to control the LED current for dimming using the LT8391A. One method uses the CTRL1 or
CTRL2 pin to adjust the current regulated in the LEDs. A
second method uses the PWM pin to modulate the LED
current between zero and full current to achieve a precisely programmed average current.
Compared to the analog dimming method, the PWM dimming method offers much higher dimming ratio without
any color shift. To make PWM dimming more accurate, the
switch demand current is stored on the VC node when the
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve the
recovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capacitor
from discharging during the PWM signal low phase.
The choice of switching frequency, inductor value, and
loop compensation affects the minimum PWM on time,
below which the LT8391A loses the LED current regulation. For the same application, the LT8391A achieves
the highest PWM dimming ratio (up to 2000:1) in buck
region, the medium PWM dimming ratio (up to 2000:1)
in buck-boost region, and the lowest PWM dimming ratio
(up to 1000:1) in boost region.
In either fixed frequency operation set by RT resistor or
spread spectrum frequency operation, the internal oscillator is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
and PWM signals must have synchronized rising edges to
achieve flicker-free PWM dimming performance.
The LT8391A provides both external PWM dimming and
internal PWM dimming. For external PWM dimming,
choose RP resistor less than 30k and apply external PWM
clock signal on the PWM pin. For internal PWM dimming,
choose RP resistor to one of the five resistor values in
Table 3 and apply analog DC voltage or a resistor divider
from VREF to the PWM pin. The RP resistor sets the internal PWM dimming frequency, and the analog DC voltage
on the PWM pin from 1V to 2V sets the internal PWM
dimming duty ratio from 0% to 100% with a discrete
1/128 step size in Figure 13. A 1µF ceramic capacitor on
the PWM pin is recommended to minimize the internal
PWM dimming duty ratio jitter caused by switching noise.
Table 3. Internal PWM Dimming Frequency vs RP Value
(5% Resistor)
RP (k)
fSW
fSW = 1MHz
fSW = 1.5MHz
fSW = 2MHz
≤ 30
External
External
External
External
51
fSW/256
3.9kHz
5.9kHz
7.8kHz
82
fSW/512
2.0kHz
2.9kHz
3.9kHz
130
fSW/1024
1.0kHz
1.5kHz
2.0kHz
200
fSW/2048
0.49kHz
0.73kHz
0.98kHz
300
fSW/4096
0.24kHz
0.37kHz
0.49kHz
PWMTG DUTY RATIO (%)
100
PWMTG DUTY
RATIO (%)
ALWAYS
ON
50
ALWAYS
OFF
0
0.0
0.5
1.0
1.5
2.0
PWM (V)
2.5
3.0
8391 F13
Figure 13. Internal PWM Dimming Duty Ratio vs PWM Voltage
High Side PMOS PWM Switch Selection
A high side PMOS PWM switch is recommended in most
LT8391A applications to maximize the PWM dimming
ratio and protect the LED string during fault conditions.
Compared to a low side NMOS PWM switch, the high side
PMOS PWM switch allows a single wire to the LED string
Rev. A
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25
LT8391A
APPLICATIONS INFORMATION
and ground return path through chassis. The high side
PMOS PWM switch is typically selected for drain-source
voltage VDS, gate-source threshold voltage VGS(TH), and
continuous drain current ID. For proper operations, VDS
rating should exceed the open LED regulation voltage set
by the FB pin, the absolute value of VGS(TH) should be less
than 3V, and ID rating should be above ILED(MAX).
Programming Output Voltage and Thresholds
The LT8391A has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R3 and R4
(Figure 14) according to the following equation:
VOUT = 1.00 V•
R3+R4
R4
VOUT
R3
LT8391A
FB
R4
8391a F14
Figure 14. Feedback Resistor Connection
In addition, the FB pin also sets output overvoltage threshold, open LED threshold, and short LED threshold. For an
LED driver application with small output capacitors, the
output voltage usually overshoots a lot during an open
LED event. Although the 1.00V FB regulation loop tries to
regulate the output, the loop is usually too slow to prevent
the output from overshooting. Once the FB pin hits its
overvoltage threshold 1.05V, the LT8391A stops switching by turning off TG1, BG1, TG2, and BG2, and also turns
off PWMTG to disconnect the LED string for protection.
The output overvoltage threshold can be set as:
VOUT(OVP) = 1.05V•
R3+R4
R4
Make sure the expected VFB during normal operation
stays between the short LED rising threshold 0.3V and
the open LED falling threshold 0.9V:
0.3V ≤ VLED •
26
R4
≤ 0.9 V
R3+R4
These equations set the maximum LED string voltage with
full open LED protection for the LT8391A to be 51V.
FAULT Pin
The LT8391A provides an open-drain status pin, FAULT,
which is pulled low during either open LED or short LED
conditions. The open LED condition happens when the FB
pin is above 0.95V and the voltage across V(ISP-ISN) is less
than 10mV. The short LED condition happens when the
FB pin is below 0.25V. The FAULT status is updated when
the SS pin is above 1.75V and the PWM signal is high.
Soft-Start and Fault Protection
As shown in Figure 8 and explained in the Operation section, the SS pin can be used to program soft-start by connecting an external capacitor from the SS pin to ground.
The internal 12.5µA pull-up current charges up the capacitor, creating a voltage ramp on the SS pin. As the SS pin
voltage rises linearly from 0.25V to 1V (and beyond), the
output voltage rises smoothly and transitions into LED
current regulation. The soft-start range is defined to be
the voltage range from 0V to the FB voltage in LED current regulation. The soft-start time can be calculated as:
t SS = VLED •
C
R4
• SS
R3+R4 12.5µA
Make sure the CSS is at least five to ten times larger than
the compensation capacitor on the VC pin. A 22nF ceramic
capacitor is a good starting point.
The SS pin is also used as a fault timer. Once an open
LED or a short LED fault is detected, a 1.25µA pull-down
current source is activated. Using a single resistor from
the SS pin to the VREF pin, the LT8391A can be set to
three different fault protection modes: hiccup (no resistor), latch-off (499k), and keep-running (100k).
With a 100k resistor in keep-running mode, the LT8391A
continues switching normally, either regulating the programmed VOUT during open LED fault or regulating the
current during short LED fault. With a 499k resistor in
latch-off mode, the LT8391A stops switching until the
EN/UVLO pin is pulled low and high to restart. With no
resistor in hiccup mode, the LT8391A enters low duty
Rev. A
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LT8391A
APPLICATIONS INFORMATION
cycle auto-retry operation. The 1.25µA pull-down current
discharges the SS pin to 0.2V and then 12.5µA pull-up
current charges the SS pin up. If the fault condition has
not been removed when the SS pin reaches 1.75V, the
1.25µA pull-down current turns on again, initiating a new
hiccup cycle. This will continue until the fault is removed.
Loop Compensation
The LT8391A uses an internal transconductance error
amplifier, the output of which, VC, compensates the control loop. The external inductor, output capacitor, and the
compensation resistor and capacitor determine the loop
stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the VC pin are set to optimize control
loop response and stability. For a typical LED application,
a 2.2nF compensation capacitor on the VC pin is adequate,
and a series resistor should always be used to increase
the slew rate on the VC pin to maintain tighter regulation
of LED current during fast transients on the input supply
of the converter.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
boost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
5. Other losses. Schottky diode DB and DD are responsible for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs
predominately at light loads. Switch A causes reverse
recovery current loss in buck region, and switch C
causes reverse recovery current loss in boost region.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in the input
current, then there is no change in efficiency.
PC Board Layout Checklist
Efficiency Considerations
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT8391A circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
2. Transition loss. This loss arises from the brief amount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends upon
the input voltage, load current, driver strength and
MOSFET capacitance, among other factors.
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board provides heat sinking for power components.
The ground plane layer should not have any traces
and it should be as close as possible to the layer with
power MOSFETs.
n Place C , switch A, switch B and D in one comIN
B
pact area. Place COUT, switch C, switch D and DD in
one compact area.
n Use immediate vias to connect the components to
the ground plane. Use several large vias for each
power component.
n Use planes for V and V
IN
OUT to maintain good voltage
filtering and to keep power losses low.
n
Rev. A
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27
LT8391A
APPLICATIONS INFORMATION
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to
any DC net (VIN or GND).
n Separate the signal and power grounds. All smallsignal components should return to the exposed
GND pad from the bottom, which is then tied to the
power GND close to the sources of switch B and
switch C.
n Place switch A and switch C as close to the controller as possible, keeping the power GND, BG and SW
traces short.
n Keep the high dV/dT SW1, SW2, BST1, BST2, TG1
and TG2 nodes away from sensitive small-signal
nodes.
n The path formed by switch A, switch B, D and the
B
CIN capacitor should have short leads and PCB trace
lengths. The path formed by switch C, switch D, DD
and the COUT capacitor also should have short leads
and PCB trace lengths.
n The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the
input capacitor.
n
28
Connect the top driver bootstrap capacitor CBST1
closely to the BST1 and SW1 pins. Connect the top
driver bootstrap capacitor CBST2 closely to the BST2
and SW2 pins.
n Connect the input capacitors C and output capaciIN
tors COUT closely to the power MOSFETs. These
capacitors carry the MOSFET AC current.
n Route LSP and LSN traces together with minimum
PCB trace spacing. Avoid sense lines pass through
noisy areas, such as switch nodes. The filter capacitor between LSP and LSN should be as close as possible to the IC. Ensure accurate current sensing with
Kelvin connections at the RSENSE resistor. A low ESL
sense resistor is recommended.
n Connect the V pin compensation network close to
C
the IC, between VC and the signal ground. The capacitor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
n Connect the INTV
CC bypass capacitor, CINTVCC,
close to the IC, between the INTVCC and the power
ground. This capacitor carries the MOSFET drivers’
current peaks.
n
Rev. A
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LT8391A
TYPICAL APPLICATIONS
94% Efficient 24W (16V 1.5A) 2MHz Buck-Boost LED Driver with Fault Protection
VIN
6V TO 32V CONTINUOUS
4V TO 56V TRANSIENT
22µF
63V
L1
2.2µH
R1
6mΩ
M1
4.7µF
100V
×2
0.1µF
SW1 LSP
BST1
LSN
M4
D2
D1
INTVCC
M2
10µF
25V
×2
0.1µF
SW2
BST2
BG1
BG2
INTVCC
M3
GND
1µF
383k
165k
100k
FAULT
ANALOG DIM
L1: COILCRAFT XAL5030-222MEB 2.2µH
M1, M2: NXP BUK9M42-60E
M3, M4: INFINEON IPZ40N04S5L-7R4
M5: VISHAY Si2343CDS
D1, D2: NXP BAT46WJ
D3: NXP PMEG3010EB
R1: SUSUMU KRL3216D-C-R006-F
113k
TG2
VOUT
4.7µF
1µF
1M
FB
48.7k
ISP
SYNC/SPRD
INTVCC
56mΩ
INTVCC
ISN
M5
PWMTG
FAULT
CTRL1
100k
90.9k
LT8391A
EN/UVLO
SSFM OFF
SSFM ON
TG1
VIN
PWM
PWM DIM
D3
VREF
0.47µF
CTRL2
SS
22nF
RP
VC
RT
4.7k
3.3nF
59.0k
2MHz
PWM SETTING
EXT
INT
16V
1.5A
LEDs
300k
488Hz
8391a TA02a
Rev. A
For more information www.analog.com
29
LT8391A
TYPICAL APPLICATIONS
100Hz 2000:1 External PWM
Dimming (VIN = 32V)
100Hz 2000:1 External PWM
Dimming (VIN = 18V)
100Hz 800:1 External PWM
Dimming (VIN = 8V)
VPWM
5V/DIV
VPWM
5V/DIV
VPWM
5V/DIV
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
ILED
1A/DIV
ILED
1A/DIV
ILED
1A/DIV
8391 TA02b
2µs/DIV
2µs/DIV
OPEN LED Protection: Hiccup
Mode (RSS = Open)
OPEN
8391 TA02c
2µs/DIV
OPEN LED Protection: Latch-Off
Mode (RSS = 499k)
RECONNECT
OPEN
RECONNECT
OPEN LED Protection:
Keep-Running Mode (RSS = 100k)
VOUT
20V/DIV
VSS
2V/DIV
VSS
2V/DIV
VOUT
20V/DIV
VSS
2V/DIV
VFAULT
5V/DIV
VFAULT
5V/DIV
VFAULT
5V/DIV
ILED
2A/DIV
ILED
2A/DIV
ILED
4A/DIV
VOUT
20V/DIV
20ms/DIV
30
8391a TA02e
20ms/DIV
8391a TA02f
8391 TA02d
OPEN
RECONNECT
20ms/DIV
8391a TA02g
Rev. A
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LT8391A
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV L 0117
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev. A
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31
LT8391A
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
32
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
LT8391A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
06/21
Added AEC-Q100 Qualified for Automotive Applications to Features section.
PAGE NUMBER
1
Added LT8391J to Operating Junction Temperature Range section.
2
Changed theta JA to 43°C/W of UFD Package.
2
Added “AUTOMOTIVE PRODUCTS**” and supplemental text to Ordering Information table.
3
Updated Note 2.
7
Rev. A
For more information www.analog.com
33
LT8391A
TYPICAL APPLICATION
Low EMI 2MHz Buck-Boost Driving 2-Beam LEDs (2× 12V, 1A)
VIN
9V TO 18V CONTINUOUS
5V TO 40V TRANSIENT
INPUT EMI FILTER
FB1
0.1µF
22µF 4.7µF
50V
53V
×2
+
0.1µF
×2
0.1µF
4.7µF
50V
L1
3.3µH
R1
10mΩ
M1
SW1 LSP
BST1
LSN
M4
INTVCC
BG1
BG2
VIN
TG2
LT8391A
VOUT
1µF
1µF
499k
100k
INTVCC
100mΩ
INTVCC
ISN
4.7µF
FAULT
FAULT
ANALOG DIM
CTRL1
100k
37.4k
ISP
SYNC/SPRD
SSFM ON
1M
FB
EN/UVLO
SSFM OFF
M3
D5
TG1
D4
L1: WURTH 744311330 3.3µH
FB1, FB2: WURTH 74279221281
M1 TO M4: INFINEON IPZ40N04S5L-7R4
M5: VISHAY Si2419CDS
M6: INFINEON BSZ025N04LS
D1, D2: NXP BAT46WJ
D3: NXP PMEG4010CEJ
D4, D5: DIODES SDM1M40LP8
R1: SUSUMU KRL3216D-C-R010-F
10Ω
GND
10Ω
10µF
50V
×2
+
0.1µF
×2
D2
INTVCC
D1
M2
162k
0.1µF
SW2
BST2
PWMTG
PWM
D3
PWM DIM
VREF
OUTPUT EMI FILTER
M5
FB2
0.47µF
CTRL2
SS
RP
VC
22nF
RT
1.5k
PWM SETTING
EXT
INT
59.0k
2MHz
300k
488Hz
3.3nF
22nF
DIM2
5V: BEAM2 OFF
0V: BEAM2 ON
5.1k
100k
0.1µF
BEAM1
12V
1A
LEDs
BEAM2
M6 12V
1A
LEDs
8391a TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT8391
60V, Synchronous 4-Switch Buck-Boost LED
Controller with Spread Spectrum
VIN: 4V to 60V, VOUT: 0V to 60V, ±3% Current Accuracy, Internal and External
PWM Dimming, TSSOP-28 and 4mm × 5mm QFN-28
LT8390/LT8390A
High Efficiency, 2MHz, Synchronous, 4-Switch
Buck-Boost Controller
VIN: 4V to 60V, VOUT: 1V to 60V, ISD =
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