LT8393
60VIN, 100VOUT Synchronous
4-Switch Buck-Boost LED Driver
Controller with Low EMI
DESCRIPTION
FEATURES
4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
n Up to 95% Efficiency
n Proprietary Peak-Buck Peak-Boost Current Mode
n Wide V Range: 4V to 60V
IN
n Wide V
OUT Range: 0V to 100V
n ±4% LED Current Accuracy
n 2000:1 External and 128:1 Internal PWM Dimming
n 10V High Side PMOS PWM Switch Driver
n No Top MOSFET Refresh Noise in Buck or Boost
n Adjustable and Synchronizable: 350kHz to 2MHz
n Flicker-Free Spread Spectrum for Low EMI
n Open and Short LED Protection with Fault Reporting
n AEC-Q100 Qualified for Automotive Applications
The LT®8393 is a synchronous 4-switch buck-boost LED
controller that regulates LED current from input voltage above, below, or equal to the output voltage. The
proprietary peak-buck peak-boost current mode control
scheme allows adjustable and synchronizable 350kHz to
2MHz fixed frequency operation, or internal 25% triangle
spread spectrum operation for low EMI. With 4V to 60V
input, 0V to 100V output, and seamless low noise transitions between operation regions, the LT8393 is ideal for
LED driver and battery charger applications in automotive,
industrial, and battery-powered systems.
n
The LT8393 provides both internal (up to 128:1) and
external (up to 2000:1) LED current PWM dimming with
10V of high side PMOS gate drive. The CTRL pin provides
flexible 20:1 analog dimming with ±4% LED current accuracy at 100mV full scale. Fault protection is provided to
detect an open or short LED condition, during which the
LT8393 retries, latches off, or keeps running.
APPLICATIONS
n
n
Automotive Head Lamps/Running Lamps
High Voltage LED Lighting
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
93% Efficient 24W (80V, 300mA) 350kHz Buck-Boost LED Driver
22µH
10mΩ
VIN
6V TO 40V
4.7µF
50V
×2
22µF
50V
0.1µF
INTVCC
SW1 LSP
BST1
LSN
0.1µF
SW2
BST2
BG1
GND
BG2
2x4.7µF
100V
Efficiency vs VIN
100
INTVCC
95
TG1
VOUT
1µF
EN/UVLO
SSFM OFF
SSFM ON
SYNC/SPRD
INTVCC
100k
4.7µF
FAULT
ANALOG DIM
TG2
LT8393
100k
100k
1M
FB
INTVCC
10.7k
ISP
330mΩ
FAULT
ISN
CTRL
PWMTG
VREF
0.47µF
EFFICIENCY (%)
143k
VIN
1µF
499k
PWM
90
85
80
75
70
PWM DIM
VLED
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
45
8393 TA01b
RP
SS
VC
0.1μF
RT
1.5k
15nF
EXT
422k
350kHz
INT
82k
170Hz
2V TO 80V
300mA
LEDs
8393 TA01a
Rev. B
Document Feedback
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1
LT8393
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN/UVLO.............................................................60V
VOUT, ISP, ISN..........................................................100V
(ISP-ISN)..........................................................–1V to 1V
BST1..........................................................................66V
BST2........................................................................106V
SW1, LSP, LSN............................................... –6V to 60V
SW2............................................................ –6V to 100V
INTVCC, (BST1-SW1), (BST2-SW2)..............................6V
(BST1-LSP), (BST1-LSN).............................................6V
FB, PWM, SYNC/SPRD, CTRL, FAULT..........................6V
Operating Junction Temperature Range (Notes 2, 3)
LT8393E............................................. –40°C to 125°C
LT8393J.............................................. –40°C to 150°C
LT8393H............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
26 SW2
TG1
4
25 TG2
TG1 1
22 TG2
LSP
5
24 VOUT
LSP 2
21 VOUT
LSN
6
23 PWMTG
LSN 3
VIN
7
22 SYNC/SPRD
21 RT
INTVCC 5
20 VC
EN/UVLO 6
RP 10
19 FB
RP 7
PWM 11
18 SS
PWM 8
VREF 12
17 FAULT
CTRL 13
16 GND
15 SS
15 ISN
θJA = 30°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
GND
VREF
9 10 11 12 13 14
FE PACKAGE
28-LEAD PLASTIC TSSOP
2
18 RT
FAULT
ISP 14
19 SYNC/SPRD
17 VC
16 FB
ISN
9
20 PWMTG
29
GND
VIN 4
ISP
EN/UVLO
8
28 27 26 25 24 23
CTRL
INTVCC
29
GND
SW2
3
BST2
SW1
BG2
27 BST2
BG1
28 BG2
2
BST1
1
SW1
BG1
BST1
UFDM PACKAGE
28-LEAD (4mm × 5mm) PLASTIC SIDE WETTABLE QFN
θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
Rev. B
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LT8393
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8393EFE#PBF
LT8393EFE#TRPBF
LT8393FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT8393JFE#PBF
LT8393JFE#TRPBF
LT8393FE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8393HFE#PBF
LT8393HFE#TRPBF
LT8393FE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8393EUFDM#PBF
LT8393EUFDM#TRPBF
8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 125°C
LT8393JUFDM#PBF
LT8393JUFDM#TRPBF
8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
LT8393HUFDM#PBF
LT8393HUFDM#TRPBF
8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
LT8393JFE#WPBF
LT8393JFE#WTRPBF
LT8393FE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8393HFE#WPBF
LT8393HFE#WTRPBF
LT8393FE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8393JUFDM#WPBF
LT8393JUFDM#WTRPBF
8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
LT8393HUFDM#WPBF
LT8393HUFDM#WTRPBF 8393
28-Lead (4mm x 5mm) Plastic Side
Wettable QFN
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a Label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. B
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3
LT8393
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VIN Operating Voltage Range
VIN Quiescent Current
TYP
4
VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
Not Switching
VOUT Voltage Range
VOUT Quiescent Current
MIN
l
1
270
2.4
l
VEN/UVLO = 0.3V, VOUT = 12V
Not Switching, VOUT = 12V
0
MAX
UNITS
60
V
2
µA
µA
mA
4
100
V
30
0.1
50
0.5
70
µA
µA
4.85
5.0
5.15
V
Linear Regulators
INTVCC Regulation Voltage
IINTVCC = 20mA
INTVCC Current Limit
VINTVCC = 4.5V
110
150
190
mA
INTVCC Undervoltage Lockout Threshold
Falling
3.44
3.54
3.64
V
INTVCC Undervoltage Lockout Hysteresis
0.24
VREF Regulation Voltage
IVREF = 100µA
VREF Current Limit
VREF = 1.8V
VREF Undervoltage Lockout Threshold
Falling
l
V
1.96
2.00
2.04
V
2
2.5
3.2
mA
1.78
1.84
1.90
V
VREF Undervoltage Lockout Hysteresis
50
mV
Control Inputs/Outputs
EN/UVLO Shutdown Threshold
EN/UVLO Enable Threshold
Falling
l
0.3
0.6
1.0
V
l
1.196
1.220
1.244
V
EN/UVLO Enable Hysteresis
13
EN/UVLO Hysteresis Current
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V
CTRL Input Bias Current
VCTRL = 0.75V, Current Out of Pin
CTRL Dim-Off Threshold
Falling
2.1
–0.1
l
2.5
0
mV
2.9
0.1
µA
µA
0
20
50
nA
180
200
220
mV
CTRL Dim-Off Hysteresis
28
mV
PWM Dimming
4
External PWM Dimming Threshold
Rising, RP = 30k
External PWM Dimming Hysteresis
RP = 30k
Internal PWM Dimming Duty Cycle
VPWM = 1V, RP ≥ 51k
VPWM = 1.5V, RP ≥ 51k
VPWM = 2V, RP ≥ 51k
Switching Frequency to Internal PWM Dimming
Frequency Ratio
RP = 51k
RP = 82k
RP = 130k
RP = 200k
RP = 300k
l
1.3
1.4
1.5
220
47
97
V
mV
3
53
%
%
%
1024
2048
4096
8192
16384
Minimum VOUT for PWMTG to be On
PWM Dimming On
2.4
4
V
PWMTG On Voltage V(VOUT-PWMTG)
VOUT = 12V
8.5
10
11.5
V
PWMTG Off Voltage V(VOUT-PWMTG)
VOUT = 12V
–0.1
0
0.1
V
PWM to PWMTG Turn On Propagation Delay
CPWMTG = 3.3nF to VOUT, 50% to 50%
180
ns
PWM to PWMTG Turn Off Propagation Delay
CPWMTG = 3.3nF to VOUT, 50% to 50%
50
ns
PWMTG Turn On Fall Time
PWMTG Turn Off Rise Time
CPWMTG = 3.3nF to VOUT, 10% to 90%
CPWMTG = 3.3nF to VOUT, 90% to 10%
180
70
ns
ns
Rev. B
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LT8393
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Error Amplifier
Full Scale LED Current Regulation V(ISP-ISN)
VCTRL = 2V, VISP = 12V
VCTRL = 2V, VISP = 0V
l
l
96
96
100
100
104
104
mV
mV
1/2 LED Current Regulation V(ISP-ISN)
VCTRL = 0.75V, VISP = 12V
VCTRL = 0.75V, VISP = 0V
l
l
47
47
50
50
53
53
mV
mV
1/20th LED Current Regulation V(ISP-ISN)
VCTRL = 0.30V, VISP = 12V
VCTRL = 0.30V, VISP = 0V
l
l
3
3
5
5
7
7
mV
mV
l
0
ISP/ISN Input Common Mode Range
100
V
ISP Input Bias Current
VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
ISN Input Bias Current
VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
23
–10
0
µA
µA
µA
1700
µS
LED Current Regulation Amplifier gm
FB Regulation Voltage
VC = 1.2V
l
0.98
FB Voltage Regulation Amplifier gm
FB Input Bias Current
1.02
615
FB in Regulation, Current Out of Pin
20
VC Output Impedance
VC Standby Leakage Current
1.00
40
15
VC = 1.2V, PWM Dimming Off
V
µS
nA
MΩ
–10
0
10
nA
34
38
48
48
62
58
mV
mV
1.05
1.07
Current Comparator
Maximum Current Sense Threshold V(LSP-LSN)
Buck, VFB = 0.8V
Boost, VFB = 0.8V
FB Overvoltage Threshold (VFB)
Rising
1.03
15
25
35
FB Open LED Threshold (VFB)
Rising, V(ISP-ISN) = 0V
0.93
0.95
0.97
FB Open LED Hysteresis
V(ISP-ISN) = 0V
35
50
65
FB Short LED Threshold (VFB)
Falling
0.24
0.25
0.26
FB Short LED Hysteresis
Hysteresis
35
50
65
ISP/ISN Over Current Threshold V(ISP-ISN)
VISP = 12V
ISP/ISN Open LED Threshold V(ISP-ISN)
Falling, VFB = 1.0V
7
10
13
mV
ISP/ISN Open LED Hysteresis
VFB = 1.0V
3
5
7
mV
l
l
Fault
FB Overvoltage Hysteresis
750
FAULT Pull-Down Resistance
SS Hard Pull-Down Resistance
VEN/UVLO = 1.1V
SS Pull-Up Current
VFB = 0.8V, VSS = 0V
SS Pull-Down Current
VFB = 1.0V, VSS = 2V
SS Fault Latch-Off Threshold
Falling
SS Fault Reset Threshold
V
mV
V
mV
V
mV
mV
100
200
Ω
100
200
Ω
10
12.5
15
µA
1
1.25
1.5
µA
1.7
V
0.2
V
Rev. B
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5
LT8393
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
330
1900
350
2000
370
2100
kHz
kHz
kHz
Oscillator
Switching Frequency
VSYNC/SPRD = 0V, RT = 422k
VSYNC/SPRD = 0V, RT = 51.1k
l
SYNC Frequency
350
2000
SYNC/SPRD Threshold Voltage
0.4
1.5
V
Region Transition
Buck-Boost to Boost (VIN/VOUT)
0.72
0.75
0.78
Boost to Buck-Boost (VIN/VOUT)
0.82
0.85
0.88
Buck to Buck-Boost (VIN/VOUT)
1.22
1.25
1.28
Buck-Boost to Buck (VIN/VOUT)
1.30
1.33
1.36
Peak-Buck to Peak-Boost (VIN/VOUT)
0.96
0.98
1.00
Peak-Boost to Peak-Buck (VIN/VOUT)
1.00
1.02
1.04
NMOS Drivers
6
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
V(BST-SW) = 5V
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
VINTVCC = 5V
TG Off to BG On Delay
BG Off to TG On Delay
2.6
1.4
Ω
Ω
3.2
1.2
Ω
Ω
CL = 3.3nF
60
ns
CL = 3.3nF
60
ns
Rev. B
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LT8393
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8393E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8393J and LT8393H are guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT8393 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs LED Current
(Buck-Boost Region)
Efficiency vs LED Current
(Boost Region)
100
100
90
90
90
80
80
80
70
60
50
40
70
60
50
30
VIN = 32V, VLED = 16V, fSW = 350KHz
0
0.5
1.5
1
LED CURRENT (A)
2
20
70
60
50
40
40
30
20
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs LED Current
(Buck Region)
30
VIN = 16V, VLED = 16V, fSW = 350KHz
0
0.5
1.5
1
LED CURRENT (A)
8393 G01
2
8393 G02
20
VIN = 8V, VLED = 16V, fSW = 350KHz
0
0.5
1.5
1
LED CURRENT (A)
2
8393 G03
Rev. B
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7
LT8393
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Waveforms
(Buck Region)
TA = 25°C, unless otherwise noted.
Switching Waveforms
(Buck-Boost Region)
VSW1
20V/DIV
VSW2
20V/DIV
Switching Waveforms
(Boost Region)
VSW1
20V/DIV
VSW1
20V/DIV
VSW2
20V/DIV
VSW2
20V/DIV
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
8393 G04
2µs/DIV
VIN = 32V, VLED = 16V, ILED = 2A
8393 G05
2µs/DIV
VIN = 16V, VLED = 16V, ILED = 2A
LED Current vs VIN
2µs/DIV
VIN = 8V, VLED = 16V, ILED = 2A
VIN Shutdown Current
2.20
2.15
8393 G06
VIN Quiescent Current
3.0
3.0
2.5
2.5
2.0
2.00
1.95
VIN = 60V
IQ (µA)
2.05
IQ (µA)
LED CURRENT (A)
2.10
1.5
VIN = 12V
1.0
2.0
VIN = 60V
1.5
VIN = 12V
1.0
VIN = 4V
1.90
1.80
VIN = 4V
0.5
1.85
0
30
40
20
INPUT VOLTAGE (V)
10
50
0.0
–50 –25
60
0
0.5
8393 G07
5.15
0.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
5.15
8393 G09
INTVCC Voltage vs VIN
4.0
IINTVCC = 20mA
VINTVCC (V)
IINTVCC = 80mA
5.00
4.95
4.95
4.90
4.90
RISING
3.8
5.05
VINTVCC (V)
VINTVCC (V)
5.00
INTVCC UVLO Threshold
3.9
5.10
5.10
IINTVCC = 0mA
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G08
INTVCC Voltage vs Temperature
5.05
0
3.7
FALLING
3.6
3.5
3.4
4.85
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
4.85
3.3
0
10
20
30
VIN (V)
40
50
8393 G11
8393 G10
8
60
3.2
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G12
Rev. B
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LT8393
TYPICAL PERFORMANCE CHARACTERISTICS
VREF Voltage vs Temperature
2.04
2.04
2.03
2.03
2.02
2.00
1.95
IVREF = 100µA
IVREF = 1mA
2.00
1.99
1.99
1.98
1.98
1.97
1.97
1.96
–50 –25
0
1.96
25 50 75 100 125 150
TEMPERATURE (°C)
VREF (V)
2.00
RISING
1.90
2.01
VREF (V)
VREF (V)
2.01
VREF UVLO Threshold
VREF Voltage vs VIN
2.02
IVREF = 0mA
TA = 25°C, unless otherwise noted.
FALLING
1.85
1.80
1.75
0
10
20
30
VIN (V)
40
50
8393 G13
1.70
–50 –25
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G14
EN/UVLO Enable Threshold
8393 G15
EN/UVLO Hysteresis Current
CTRL Dim-Off Threshold
0.30
3.0
1.240
1.235
2.8
0.25
RISING
1.220
FALLING
1.215
1.210
2.6
VCTRL (V)
1.225
IHYS (µA)
VEN/UVLO (V)
1.230
2.4
RISING
0.20
FALLING
0.15
2.2
1.205
1.200
–50 –25
0
2.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
8393 G16
V(ISP-ISN) Regulation vs VCTRL
106
V(ISP-ISN) (mV)
V(ISP-ISN) (mV)
100
75
50
25
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G18
V(ISP-ISN) Regulation
vs Temperature
V(ISP-ISN) Regulation vs VISP
106
104
104
102
102
100
98
96
0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
VCTRL (V)
0
8393 G17
V(ISP-ISN) (mV)
125
0.10
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
94
100
98
ISP=0V
ISP=12V
ISP=100V
96
0
20
40
60
VISP (V)
80
8393 G19
100
8393 G20
94
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G21
Rev. B
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9
LT8393
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
vs Temperature
FB Regulation vs Temperature
1.03
1.02
80
1.01
60
65
1.00
40
0.99
20
0.98
0
0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04
VFB (V)
70
CURRENT LIMIT (mV)
100
VFB (V)
V(ISP-ISN) (mV)
120
V(ISP-ISN) Regulation vs VFB
TA = 25°C, unless otherwise noted.
0.97
–50 –25
VIN = 4V
VIN = 12V
VIN = 60V
0
55
50
45
40
BUCK
BOOST
35
30
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G22
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G23
8393 G24
FB Open LED Threshold
FB Overvoltage Threshold
1.10
FB Short LED Threshold
1.10
0.40
1.05
0.35
RISING
1.05
FALLING
RISING
0.95
0.90
0.90
0.85
0.85
FALLING
0
30
15.0
25
12.5
Oscillator Frequency
vs Temperature
2.5
20
10.0
ISS (µA)
V(ISP-ISN) (mV)
PULL-UP
7.5
5.0
FALLING
5
2.5
0
–50 –25
0.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
PULL-DOWN
0
2
RT=51.1k
1.5
1
0.5
RT=422k
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G28
10
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G27
SS Current vs Temperature
15
0
8393 G26
ISP/ISN Open LED Threshold
10
0.10
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G25
RISING
FALLING
0.15
0.80
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
RISING
0.25
0.20
SWITCHING FREQUENCY (MHz)
0
VFB (V)
0.95
0.80
–50 –25
0.30
1.00
VFB (V)
VFB (V)
1.00
8393 G29
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8393 G30
Rev. B
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LT8393
PIN FUNCTIONS
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the part and reduce VIN quiescent current below 2µA. Force the pin above 1.233V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from VIN to ground. An
accurate 2.5µA pull-down current allows the programming
of VIN UVLO hysteresis. If neither function is used, tie this
pin directly to VIN.
modes during open or short LED fault conditions: hiccup
(no resistor), latchoff (499k), and keep-running (100k).
See more details in the Typical Application section.
ISP: Positive Terminal of the LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin connection.
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and LED fault protection. The
internal error amplifier with its output VC regulates VFB
to 1.00V through the DC/DC converter. During open LED
(VFB > 0.95V & V(ISP-ISN) < 10mV) or short LED (VFB <
0.25V) fault conditions, the part pulls the FAULT pin low
and gets into one fault mode per customer setting. During
an overvoltage (VFB > 1.05V) condition, the part turns off
all TG1, BG1, TG2, BG2, and PWMTG.
ISN: Negative Terminal of the LED Current Sense Resistor (RLED). Ensure accurate current sense with Kelvin
connection.
CTRL: Control Input for LED Current Sense Threshold. The
CTRL pin is used to program the LED regulation current:
ILED =
Min ( VCTRL – 0.25V,1V )
10 •RLED
The VCTRL can be set by an external voltage reference or
a resistor divider from VREF to ground. For 0.25V ≤ VCTRL
≤ 1.15V, the current sense threshold linearly goes up
from 0mV to 90mV. For VCTRL ≥ 1.35V, the current sense
threshold is constant at 100mV full scale value. For 1.15V
≤ VCTRL ≤ 1.35V, the current sense threshold smoothly
transitions from the linear function of VCTRL to the 100mV
constant value. Tie CTRL to VREF for the 100mV full scale
threshold. Force the pin below 0.2V to stop switching.
VREF: Voltage Reference Output. The VREF pin provides an
accurate 2V reference capable of supplying 1mA current.
Locally bypass this pin to ground with a 0.47µF ceramic
capacitor.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timing by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
0.1µF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and
stops switching. Using a single resistor from SS to VREF,
the LT8393 can be set in three different fault protection
VC: Error Amplifier Output to Set Inductor Current Comparator Threshold. The VC pin is used to compensate the
control loop with an external RC network. During PWM
low state, the VC pin is disconnected from all internal
loads to store its voltage information for the highest PWM
dimming performance.
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 350kHz to 2MHz.
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at internal oscillator frequency. Apply a clock signal for external
frequency synchronization. Tie to INTVCC for 25% triangle
spread spectrum above internal oscillator frequency.
FAULT: LED Fault Open Drain Output. The FAULT pin is
pulled low when any of the following conditions happens:
1. Open LED (VFB > 0.95V & V(ISP-ISN) < 10mV)
2. Short LED (VFB < 0.25V)
To function, the pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high state
and latched during PWM low state.
RP: Internal PWM Dimming Frequency Setting. The RP
pin is used to set the internal PWM dimming frequency
with a resistor to ground. Do not use a resistor larger
than 1MΩ and do not leave this pin open. If an external
PWM dimming pulse is available at the PWM pin, tie this
pin to ground.
Rev. B
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11
LT8393
PIN FUNCTIONS
PWM: PWM Dimming Input. The PWM pin can be used
in two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with
a digital pulse from 0V to a voltage higher than 1.5V to
control PWM dimming of the LED string. Make sure the
RP pin is tied to ground in this case. For internal PWM
dimming, apply an analog voltage between 1V and 2V to
generate an internal digital pulse by comparing with the
internal ramp. If PWM dimming is not used, tie this pin to
INTVCC. Forcing the pin low turns off TG1 and TG2, turns
on BG1 and BG2, disconnects the VC pin from all internal
loads, and turns off PWMTG.
PWMTG: PWM Dimming Top Gate Drive. A buffered and
inverted version of the PWM input signal, the PWMTG
pin drives an external high side PMOS PWM switch with
a voltage swing from the higher voltage of (VOUT –10V)
and 1V to VOUT. Leave this pin unconnected if not used.
VOUT: Output Supply. The VOUT pin must be tied to the
power output to determine the buck, buck-boost, or boost
operation regions. The VOUT pin also serves as positive rail
for the PWMTG drive. Locally bypass this pin to ground
with a minimum 1µF ceramic capacitor.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin requires an external bootstrap Schottky diode
from the INTVCC pin and requires an external bootstrap
capacitor to the SW2 pin.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
SW2: Boost Side Switch Node.
INTVCC: Internal 5V Linear Regulator Output. The INTVCC
linear regulator is supplied from the VIN pin, and powers
the internal control circuitry and gate drivers. Locally
bypass this pin to ground with a minimum 4.7µF ceramic
capacitor.
BG1: Buck Side Bottom Gate Drive. Drives the gate of buck
side bottom N-channel MOSFET with a voltage swing from
ground to INTVCC.
SW1: Buck Side Switch Node.
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-channel MOSFET with a voltage swing from
SW1 to BST1.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode
from the INTVCC pin and requires an external bootstrap
capacitor to the SW1 pin.
LSN: Negative Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
LSP: Positive Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
VIN: Input Supply. The VIN pin must be tied to the power
input to determine the buck, buck-boost, or boost operation
regions. Locally bypass this pin to ground with a minimum
1µF ceramic capacitor.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
BG2: Boost Side Bottom Gate Drive. Drives the gate of
boost side bottom N-Channel MOSFET with a voltage
swing from ground to INTVCC.
12
Rev. B
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LT8393
BLOCK DIAGRAM
LSN
VIN
INTVCC
LSP
INTVCC
+
5V LDO
–
VREF
+
A1
–
2V REF
BST1
A3
TG1
PEAK_BUCK
SW1
BUCK
LOGIC
INTVCC
PWMON
RT
OSC
SYNC/SPRD
BG1
VOS
GND
0.2V
CTRL
+
–
+
–
FBOV
VOUT/BST2
VIN/BST1
CHARGE
CONTROL
FB
GND
1.05V
INHIBIT
SWITCH
EN/UVLO
1.220V
–
+
BG2
+
–
ISOC
2.5µA
PWMON
VISP-ISN
0.75V
PEAK_BOOST
BOOST
LOGIC
INTVCC
SW2
TG2
+
PWM
RP
VOUT
PWMTG
–
INT/EXT
PWM
VIS
FB
FAULT
+
–
EA1
OPEN
VOUT –10V 0.95V
+
–
0.25V
FB
BST2
VREF
12.5µA
PWMON
0.1V
A4
10µA
LED
FAULT
LOGIC
+
–
1.25µA
+
+
–
EA2
SHORT
PWMON
1V
FB
+
CTRL
+
1.25V
–
+
+
A2=10
VIS
SS
VC
GND
–
ISP
ISN
0.25V
8393 BD
Rev. B
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13
LT8393
OPERATION
The LT8393 is a current mode LED controller that can
regulate LED current from input voltages above, below,
or equal to the LED string voltage. The ADI proprietary
peak-buck peak-boost current mode control scheme uses
a single inductor current sense resistor and provides
smooth transition between the buck region, buck-boost
region, and boost region. Its operation is best understood
by referring to the Block Diagram.
PEAK-BUCK
PEAK-BOOST
Power Switch Control
Figure 1 shows a simplified diagram of how the four power
switches A, B, C, and D are connected to the inductor L,
the current sense resistor RSENSE, power input VIN, power
output VOUT, and ground. The current sense resistor RSENSE
connected to the LSP and LSN pins provides inductor current information for both peak current mode control and
reverse current detection in the buck region, buck-boost
region, and boost region. Figure 2 shows the current mode
control as a function of VIN/VOUT ratio and Figure 3 shows
the operation region as a function of VIN/VOUT ratio. The
power switches are properly controlled to smoothly transition between modes and regions. Hysteresis is added to
prevent chattering between modes and regions.
VIN
TG1
A
B
RSENSE
L
(1)
BUCK
(3)
(2)
BUCK-BOOST
(2)
BOOST
(4)
0.75
0.85
1.00
1.25
1.33
VIN/VOUT
D
TG2
SW2
8393 F03
Figure 3. Operation Region vs VIN/VOUT Ratio
Peak-Buck in Buck Region (VIN >> VOUT)
C
BG2
8393 F01
Figure 1. Simplified Diagram of the Power Switches
There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode control
in buck-boost region, (3) peak-boost current mode control
in buck-boost region, and (4) peak-boost current mode
control in boost region. The following sections give detailed
description for each state with waveforms, with the shootthrough protection dead time between switches A and B,
and between switches C and D ignored for simplification.
14
8393 F02
Figure 2. Current Mode vs VIN/VOUT Ratio
VOUT
SW1
BG1
0.98 1.00 1.02
VIN/VOUT
When VIN is much higher than VOUT, the LT8393 uses peakbuck current mode control in the buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current
hits the peak buck current threshold commanded by the
VC voltage at buck current comparator A3 during “A+D”
phase, switch A is turned off and switch B is turned on
for the rest of the cycle. Switches A and B will alternate,
behaving like a typical synchronous buck regulator.
Rev. B
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LT8393
OPERATION
A
A
B
B
C
100% OFF
C
D
100% ON
D
20%
80%
IL
IL
A+D
B+D
B+D
A+D
20%
80%
A+D
A+C
A+D
B+D
A+C
B+D
8393 F05
8393 F04
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT)
Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
When VIN is slightly higher than VOUT, the LT8393 uses
peak-buck current mode control in the buck-boost region
(Figure 5). Switch C is always turned on for the beginning
20% of the cycle and switch D is always turned on for the
remaining 80% of the cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. After 20% of the cycle, switch C is turned off
and switch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
threshold commanded by the VC voltage at buck current
comparator A3 during the “A+D” phase, switch A is turned
off and switch B is turned on for the rest of the cycle.
Peak-Boost in Buck-Boost Region (VIN
VOUT •(VIN(MAX) − VOUT )
f•ILED(MAX) • ΔIL %• VIN(MAX)
10
0
LBOOST >
–10
–20
0.1
10
1
FREQUENCY (MHz)
100
8393 F09
Figure 9. CISPR 25 Average Conducted EMI
80
PEAK CONDUCTED EMI (dBµV)
edge of the synchronization clock represents the beginning of a switching cycle, turning on switches A and C,
or switches A and D.
60
where:
f is switching frequency
VIN(MIN) is minimum input voltage
50
VIN(MAX) is maximum input voltage
40
30
VOUT is output voltage
20
10
ILED(MAX) is maximum LED current
0
–10
–20
0.1
f•ILED(MAX)• ΔIL %• VOUT 2
∆IL% is allowable inductor current ripple
SSFM ON WITH FILTER
NOISE FLOOR
CLASS 5 LIMITS
70
VIN(MIN)2 •(VOUT − VIN(MIN) )
1
10
FREQUENCY (MHz)
100
8393 F10
Figure 10. CISPR 25 Peak Conducted EMI
Slope compensation provides stability in constant frequency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum inductance
required for stability can be calculated as:
Frequency Synchronization
The LT8393 switching frequency can be synchronized to
an external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always a
good choice, otherwise maintain the duty cycle between
10% and 90%. Due to the use of a phase-locked loop (PLL)
inside, there is no restriction between the synchronization
frequency and the internal oscillator frequency. The rising
L>
10• VOUT •RSENSE
f
For high efficiency, choose an inductor with low core
loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I2R losses, and must be able
to handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
Rev. B
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19
LT8393
APPLICATIONS INFORMATION
RSENSE Selection and Maximum Output Current
Power MOSFET Selection
RSENSE is chosen based on the required output current.
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
The LT8393 requires four external N-channel power MOSFETs, two for the top switches (switches A and D shown
in Figure 1) and two for the bottom switches (switches B
and C shown in Figure 1). Important parameters for the
power MOSFETs are the breakdown voltage VBR(DSS),
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
In boost region, the lowest maximum average load current
happens at VIN(MIN) and can be calculated as:
⎛ 50mV ΔIL(BOOST) ⎞ VIN(MIN)
IOUT(MAX_BOOST) = ⎜
−
⎟⎠ • V
2
⎝R
SENSE
OUT
where ∆IL(BOOST) is peak-to-peak inductor ripple current
in boost region and can be calculated as:
ΔIL(BOOST) =
VIN(MIN)•(VOUT − VIN(MIN) )
f•L• VOUT
In buck region, the lowest maximum average load current
happens at VIN(MAX) and can be calculated as:
⎛ 50mV ΔIL(BUCK) ⎞
IOUT(MAX_BUCK) = ⎜
−
⎟⎠
2
⎝R
where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
VOUT •(VIN(MAX) − VOUT )
(
IINTVCC = f • QgA + QgB + QgC + QgD
)
f is the switching frequency
QgA, QgB, QgC, QgD are the total gate charges of MOSFETs
A, B, C, D at 5V VGS
Make sure the total required INTVCC current not exceeding
the INTVCC current limit in the data sheet.
f•L• VIN(MAX)
The maximum current sense RSENSE in boost region is:
RSENSE(BOOST) =
2•50mV• VIN(MIN)
Since the gate drive voltage is set by the 5V INTVCC supply,
logic-level threshold MOSFETs must be used in LT8393
applications. Switching four MOSFETs at higher frequency,
the substantial gate charge current from INTVCC can be
estimated as:
where:
SENSE
ΔIL(BUCK) =
To achieve high frequency operation, the power MOSFET
selection is critical. With typical 60ns shoot-through
protection dead time, high performance power MOSFETs
with low Qg and low RDS(ON) must be used.
2•ILED(MAX)• VOUT + ΔIL(BOOST)• VIN(MIN)
The maximum current sense RSENSE in buck region is
The LT8393 uses the VIN/VOUT ratio to transition between
modes and regions. Bigger IR drop in the power path
caused by improper MOSFET and inductor selection may
prevent the LT8393 from smooth transition. Make sure
that low RDS(ON) MOSFETs and low DCR inductor are
used to satisfy:
ILED(MAX) ≤
0.025 • VOUT
RA,B +RC,D +RSENSE +RL
2•50mV
RSENSE(BUCK) =
2•ILED(MAX) + ΔIL(BUCK)
The final RSENSE value should be lower than the calculated
RSENSE in both buck and boost regions. A 20% to 30%
margin is usually recommended.
RA,B is the maximum RDS(ON) of MOSFETs A or B at 25°C
where:
RC,D is the maximum RDS(ON) of MOSFETs C or D at 25°C
RL is the maximum DCR resistor of inductor at 25°C
20
Rev. B
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LT8393
APPLICATIONS INFORMATION
The RDS(ON) and DCR increase at higher junction temperatures and the process variation have been included
in the calculation above.
In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the
maximum power dissipation happens in boost region, when
it remains on all the time. Its maximum power dissipation
at maximum output current is given by:
⎛ ILED(MAX)•VOUT ⎞2
PA(BOOST) = ⎜
⎟ •ρ T •RDS(ON)
VIN
⎝
⎠
where ρT is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with
temperature, typically 0.4%/°C as shown in Figure 11. For
a maximum junction temperature of 125°C, using a value
of ρT = 1.5 is reasonable.
ρT NORMALIZED ON-RESISTANCE (Ω)
2.0
0.5
50
100
0
JUNCTION TEMPERATURE (°C)
150
Figure 11. Normalized RDS(ON) vs Temperature
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output current is given by:
VIN − VOUT
•ILED(MAX)2•ρ T •RDS(ON)
VIN
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
PC(BOOST) =
PD(BOOST) =
VOUT
•ILED(MAX)2•ρ T •RDS(ON)
VIN
For the same output voltage and current, typically switch
A has the highest power dissipation in buck region at
VIN(MAX) and switch C has the highest power dissipation
in boost region at VIN(MIN).
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
The junction-to-ambient thermal resistance RTH(JA) includes the junction-to-case thermal resistance RTH(JC)
and the case-to-ambient thermal resistance RTH(CA). This
value of TJ can then be compared to the original, assumed
value used in the iterative calculation process.
1.0
8393 F11
PB(BUCK) =
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
TJ = TA + P • RTH(JA)
1.5
0
–50
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
(VOUT − VIN )•VOUT
VIN
•RDS(ON)+k•VOUT 3•
2
ILED(MAX)
VIN
•ILED(MAX)2•ρ T
•CRSS•f
Optional Schottky Diode (DB, DD) Selection
The optional Schottky diodes DB (in parallel with switch B)
and DD (in parallel with switch D) conduct during the
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode of
synchronous switches B and D from turning on and storing
charge during the dead time. In particular, DB significantly
reduces reverse recovery current between switch B turnoff and switch A turn-on, and DD significantly reduces
reverse recovery current between switch D turn-off and
switch C turn-on. They improve converter efficiency and
reduce switch voltage stress. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
Rev. B
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21
LT8393
APPLICATIONS INFORMATION
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, of at least 1µF, should also
be placed from VIN to GND and VOUT to GND as close to
the LT8393 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss in
the higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
Input Capacitance CIN
Discontinuous input current is highest in buck region due
to the switch A toggling on and off. Make sure that the
CIN capacitor network has low enough ESR and is sized
to handle the maximum RMS current. In buck region, the
input RMS current is given by:
IRMS ≈ILED(MAX)•
VOUT
VIN
•
−1
VIN
VOUT
The formula has a maximum at VIN = 2VOUT, where IRMS
= ILED(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief.
Output Capacitance COUT
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the COUT capacitor
network is capable of reducing the output voltage ripple.
The effects of ESR and the bulk capacitance must be
considered when choosing the right capacitor for a given
22
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
Δ VCAP(BOOST) =
ΔVCAP(BUCK) =
ILED •(VOUT − VIN(MIN) )
C OUT • VOUT • f
⎛
⎞
V
VOUT • ⎜ 1– OUT ⎟
⎝ VIN(MAX) ⎠
8 • L • f2 • C OUT
The maximum steady ripple due to the voltage drop across
the ESR is given by:
Δ VESR(BOOST) =
VOUT •ILED(MAX)
VIN(MIN)
•ESR
⎛
⎞
V
VOUT • ⎜ 1– OUT ⎟
⎝ VIN(MAX) ⎠
ΔVESR(BUCK) =
• ESR
L•f
INTVCC Regulator
An internal P-channel low dropout regulator produces
5V at the INTVCC pin from the VIN supply pin. The INTVCC
powers internal circuitry and gate drivers in the LT8393.
The INTVCC regulator can supply a peak current of 145mA
and must be bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary
to supply the high transient current required by MOSFET
gate drivers.
Higher input voltage applications with large MOSFETs
being driven at higher switching frequencies may cause
the maximum junction temperature rating for the LT8393
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
loading of the INTVCC also needs to be taken into account
for the power dissipation calculation. The total LT8393
power dissipation in this case is VIN • IINTVCC, and overall
efficiency is lowered. The junction temperature can be
estimated by using the equation:
TJ = TA + PD • θJA
where θJA (in °C/W) is the package thermal resistance.
Rev. B
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LT8393
APPLICATIONS INFORMATION
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked operating in continuous mode at maximum VIN.
VIN
R1
EN/UVLO
Top Gate MOSFET Driver Supply (CBST1, CBST2)
The top MOSFET drivers, TG1 and TG2, are driven between
their respective SW and BST pin voltages. The boost voltages are biased from floating bootstrap capacitors CBST1
and CBST2, which are normally recharged through both the
external and internal bootstrap diodes when the respective top MOSFET is turned off. External bootstrap diode is
required (no internal bootstrap diode) for boost side and
optional for buck side. External bootstrap diodes are recommended because the internal bootstrap diodes are not
always strong enough to refresh top MOSFETs at 2MHz.
Both capacitors are charged to the same voltage as the
INTVCC voltage. The bootstrap capacitors CBST1 and CBST2,
need to store about 100 times the gate charge required by
the top switches A and D. In most applications, a 0.1µF to
0.47µF, X5R or X7R dielectric capacitor is adequate.
Programming VIN UVLO
A resistor divider from VIN to the EN/UVLO pin implements
VIN undervoltage lockout (UVLO). The EN/UVLO enable
falling threshold is set at 1.220V with 10mV hysteresis. In
addition, the EN/UVLO pin sinks 2.5µA when the voltage
on the pin is below 1.220V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
VIN(UVLO+) =1.233V•
GND
Figure 12 shows the implementation of external shut-down
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LT8393 in shutdown with quiescent current less than 2µA.
Programming LED Current
The LED current is programmed by placing an appropriate
value current sense resistor, RLED, in series with the LED
string. The voltage drop across RLED is (Kelvin) sensed
8393 F12
Figure 12. VIN Undervoltage Lockout (UVLO)
by the ISP and ISN pins. The CTRL pin should be tied to
a voltage higher than 1.35V to get the full-scale 100mV
(typical) threshold across the sense resistor. The CTRL
pin can be used to dim the LED current to zero, although
relative accuracy decreases with the decreasing sense
threshold. When the CTRL pin voltage is less than 1.15V,
the LED current is:
ILED =
VCTRL −250mV
10•RLED
where VCTRL is the CTRL pin voltage. When VCTRL is between 1.15V and 1.35V, the LED current varies with the
VCTRL, but departs from the equation above by an increasing amount as VCTRL increases. Ultimately, when VCTRL >
1.35V, the LED current no longer varies. The typical VCTRL
threshold vs VCTRL is listed in Table 2.
Table 2. V(ISP-ISN) Threshold vs VCTRL
VCTRL (V)
V(ISP-ISN) (mV)
1.15
90
1.20
94.5
1.25
98
1.30
99.5
1.35
100
R1+R2
+2.5µA•R1
R2
R1+R2
VIN(UVLO−) =1.220V•
R2
RUN/STOP
CONTROL
(OPTIONAL)
R2
LT8393
When VCTRL is higher than 1.35V, the LED current is
regulated to:
ILED =
100mV
RLED
The CTRL pin should not be left open (tie to VREF if not
used). The CTRL pin can also be used in conjunction with
a thermistor to provide overtemperature protection for the
LED load, or with a resistor divider to VIN to reduce output
For more information www.analog.com
Rev. B
23
LT8393
APPLICATIONS INFORMATION
power and switching current when VIN is low. The presence
of a time varying differential voltage ripple signal across
ISP and ISN at the switching frequency is expected. The
amplitude of this signal is increased by higher LED load
current, lower switching frequency, or smaller value output
filter capacitor. Some level of ripple signal is acceptable,
and the compensation capacitor on the VC pin filters the
signal so the average difference between ISP and ISN is
regulated to the user-programmed value. The ripple voltage amplitude (peak-to-peak) in excess of 20mV should
not cause mis-operation, but may lead to noticeable offset
between the average value and the user-programmed value.
Dimming Control
There are two methods to control the LED current for dimming using the LT8393. One method uses the CTRL pin to
adjust the current regulated in the LEDs. A second method
uses the PWM pin to modulate the LED current between
zero and full current to achieve a precisely programmed
average current.
Compared to the analog dimming method, the PWM dimming method offers much higher dimming ratio without
any color shift. To make PWM dimming more accurate, the
switch demand current is stored on the VC node when the
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve the
recovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capacitor from discharging during the PWM signal low phase.
The choice of switching frequency, inductor value, and
loop compensation affects the minimum PWM on time,
below which the LT8393 loses the LED current regulation.
For the same application, the LT8393 achieves the highest
PWM dimming ratio (up to 2000:1) in buck region, the
medium PWM dimming ratio (up to 2000:1) in buck-boost
region, and the lowest PWM dimming ratio (up to 1000:1)
in boost region.
In either fixed frequency operation set by RT resistor or
spread spectrum frequency operation, the internal oscillator
is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
24
and PWM signals must have synchronized rising edges to
achieve flicker-free PWM dimming performance.
The LT8393 provides both external PWM dimming and
internal PWM dimming. For external PWM dimming, choose
RP resistor less than 30k and apply external PWM clock
signal on the PWM pin. For internal PWM dimming, choose
RP resistor to one of the five resistor values in Table 3 and
apply analog DC voltage or a resistor divider from VREF
to the PWM pin. The RP resistor sets the internal PWM
dimming frequency, and the analog DC voltage on the
PWM pin from 1V to 2V sets the internal PWM dimming
duty ratio from 0% to 100% with a discrete 1/128 step
size in Figure 13. A 1µF ceramic capacitor on the PWM pin
is recommended to minimize the internal PWM dimming
duty ratio jitter caused by switching noise.
Table 3. Internal PWM Dimming Frequency vs RP Value
(5% Resistor)
5% RP (kΩ)
fSW
