LT8495
SEPIC/Boost Converter with
2A, 70V Switch, 9µA Quiescent
Current, POR and Watchdog Timer
DESCRIPTION
FEATURES
Wide Input Voltage Range of ~1V to 60V
(2.5V to 32V for Start-Up)
n Low Ripple Burst Mode® Operation
n 9µA IQ at 12VIN to 5.0VOUT
n Output Ripple (12V)
90
EFFICIENCY (%)
15µH
SUPPLY CURRENT (µA)
•
VIN
3V TO 60V
Efficiency
25
0
WATCHDOG DISABLED
0
12
24
36
INPUT VOLTAGE (V)
48
60
8495 TA01b
VIN = 24V
80
VIN = 12V
VIN = 5V
75
70
65
60
0.0
0.2
0.4
0.6
LOAD CURRENT (A)
0.8
1.0
8495 TA01c
8495fb
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1
LT8495
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, BIAS Voltage.......................................................60V
SWEN, WDE, RSTIN Voltage......................................60V
FB Voltage..................................................................60V
SW Voltage................................................................70V
WDI, RST, WDO Voltage...............................................6V
RT Voltage...................................................................6V
CPOR, CWDT, SS Voltage............................................3V
Operating Junction Temperature Range
LT8495E, LT8495I (Notes 2, 3)........... –40°C to 125°C
LT8495H (Notes 2, 3)......................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package........................................................ 300°C
PIN CONFIGURATION
BIAS
CPOR
1
20 SW
FB
2
19 NC
20 19 18 17 16
FB
3
18 VIN
NC
4
17 NC
CPOR
5
CWDT
6
RST
7
14 GND
SS
8
13 WDE
NC
9
12 SWEN
RT 10
11 RSTIN
RT 2
16 WDI
14 GND
21
GND
GND 3
15 WDO
GND 4
13 GND
12 SW
11 GND
θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
8
WDO
9 10
VIN
7
WDI
6
WDE
RSTIN 5
FE PACKAGE
20-LEAD PLASTIC TSSOP
ORDER INFORMATION
15 GND
SS 1
SWEN
21
GND
FB
BIAS
RST
CWDT
TOP VIEW
TOP VIEW
UF PACKAGE
20-LEAD (4mm × 4mm) PLASTIC QFN
θJA = 47°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LT8495#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8495EUF#PBF
LT8495EUF#TRPBF
8495
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT8495IUF#PBF
LT8495IUF#TRPBF
8495
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT8495EFE#PBF
LT8495EFE#TRPBF
LT8495FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8495IFE#PBF
LT8495IFE#TRPBF
LT8495FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8495HFE#PBF
LT8495HFE#TRPBF
LT8495FE
20-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
8495fb
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LT8495
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VSWEN = 12V, VBIAS = VWDE = 5V, unless otherwise noted
(Note 2).
PARAMETER
CONDITIONS
Minimum VIN Operating Voltages
VBIAS < 2.5V
VBIAS ≥ 2.5V
Minimum BIAS Operating Voltages
VIN < 2.5V
VIN ≥ 2.5V
Power Switch Driver (PSD) Overvoltage Threshold VIN or BIAS Rising
VIN or BIAS Falling
(Note 4)
MIN
TYP
MAX
l
l
2.4
2.5
0
V
V
l
l
2.4
2.5
0
V
V
34
33.9
36.5
36.4
V
V
l
l
32.1
32
Power Switch Driver (PSD) Overvoltage Threshold
Hysteresis (Note 4)
Quiescent Current from VIN
Quiescent Current from BIAS
BIAS to VIN Comparator Threshold
100
VSWEN = 0V, VWDE = 0V, VRSTIN = 0V
VSWEN = 5V, VWDE = 0V, VFB = VRSTIN = 1.25V
VSWEN = 5V, VWDE = 5V, VFB = VRSTIN = 1.25V
VSWEN = 5V, VWDE = 0V, VFB = VRSTIN = 1.25V
(LT8495E, LT8495I)
(LT8495H)
VSWEN = 5V, VWDE = 5V, VFB = VRSTIN = 1.25V
(LT8495E, LT8495I)
(LT8495H)
VSWEN = 0V, VWDE = 0V, VRSTIN = 0V
VSWEN = 5V, VWDE = 0V, VFB = VRSTIN = 1.25V
VSWEN = 5V, VWDE = 5V, VFB = VRSTIN = 1.25V
VSWEN = 5V, VWDE = 0V, VFB = VRSTIN = 1.25V
(LT8495E, LT8495I)
(LT8495H)
VSWEN = 5V, VWDE = 5V, VFB = VRSTIN = 1.25V
(LT8495E, LT8495I)
(LT8495H)
VBIAS-VIN, VBIAS Rising, VIN = 12V
VBIAS-VIN, VBIAS Falling, VIN = 12V
Hysteresis (Rising-Falling Threshold)
Feedback Voltage
UNITS
mV
0.3
3.0
3.1
0.9
4.8
4.9
µA
µA
µA
l
l
3.0
3.0
6.2
8.0
µA
µA
l
l
3.1
3.1
6.3
8.0
µA
µA
0.07
1.7
6.0
0.5
2.8
8.5
µA
µA
µA
l
l
1.7
1.7
4.0
11
µA
µA
l
l
6.0
6.0
10.0
15.5
µA
µA
l
l
l
0.55
0.17
0.20
0.90
0.37
0.53
1.2
0.57
0.80
V
V
V
l
1.178
1.202
1.230
V
FB Pin Bias Current (Note 7)
VFB = 1.202V
0.1
20
nA
FB Voltage Line Regulation
5V ≤ VIN ≤ 32V, VBIAS = 5V
5V ≤ VIN ≤ 32V, VBIAS = 0V
0.2
0.2
10
10
m%/V
m%/V
Minimum Switch Off-Time
70
ns
Minimum Switch On-Time
95
ns
l
l
0.92
219
1.0
250
1.06
280
MHz
kHz
Switch Current Limit at Min. Duty Cycle (Note 5)
l
2.1
2.55
2.95
A
Switch Current Limit at Max. Duty Cycle (Note 6)
l
1.3
1.85
2.4
A
Switching Frequency
Switch VCESAT
RT = 68.1k
RT = 324k
ISW = 1.2A
Switch Leakage Current (Note 7)
VSW = 12V, VSWEN = 0V
Soft-Start Charging Current (Note 7)
VSS = 100mV
SWEN Pin Current (Note 7)
VSWEN = 1.2V
VSWEN = 5V
VSWEN = 12V
SWEN Rising Voltage Threshold
340
l
l
SWEN Voltage Hysteresis
5.2
0.9
mV
0.01
1
μA
8.2
12.2
μA
0
35
240
25
200
550
nA
nA
nA
1
1.1
30
V
mV
8495fb
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3
LT8495
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VSWEN = 12V, VBIAS = VWDE = 5V, unless otherwise noted
(Note 2).
PARAMETER
CONDITIONS
RSTIN Pin Current (Note 7)
VRSTIN = 1.2V
VRSTIN = 5V
VRSTIN = 12V
MIN
RSTIN Threshold as % of VFB Regulation Voltage
TYP
MAX
UNITS
0
35
240
25
200
550
nA
nA
nA
l
86
92
97
%
RSTIN Low to RST Asserted (tUV)
Step VRSTIN from 1.3V to 0.9V
l
8
23
60
µs
Watchdog Timeout and Reset Delay Period (tRST)
(Note 8)
CPOR = 4700pF, Watchdog Timeout Not Occurring
at Same Time as the Reset Delay
l
8.5
9.5
11.85
ms
Watchdog Upper Boundary (tWDU) (Note 8)
CWDT = 1000pF
l
14.9
16.7
20.9
ms
Watchdog Lower Boundary (tWDL) (Note 8)
CWDT = 1000pF
l
580
650
812
µs
RST Output Voltage Low
ISINK = 1.25mA
ISINK = 100μA, VBIAS = 1.3V, VIN = 0V
ISINK = 100μA, VIN = 1.3V, VBIAS = 0V
l
l
l
33
15
15
150
150
150
mV
mV
mV
RST Leakage Current
VRSTIN = 1.2V, VRST = 5V (LT8495E, LT8495I)
VRSTIN = 1.2V, VRST = 5V (LT8495H)
l
l
0
0
0.3
1.0
µA
μA
WDO Output Voltage Low
ISINK = 1.25mA
l
120
420
mV
WDO Leakage Current
VWDO = 5V
l
0
0.25
μA
WDI Pin Current
VWDI = 5V
0
0.1
µA
0.8
1.25
V
WDI Input Rising Threshold
l
0.4
WDI Voltage Hysteresis
58
WDI Input Pulse Width
WDE Pin Current (Note 7)
l
l
WDE Voltage Hysteresis
0.9
ns
0
35
240
25
200
550
nA
nA
nA
1
1.1
V
30
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Voltages are with respect to GND pin unless
otherwise noted.
Note 2: The LT8495E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8495I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT8495H is guaranteed over the full
–40°C to 150°C operating junction temperature range. Operating lifetime is
derated at junction temperatures greater than 125°C.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
4
300
VWDE = 1.2V
VWDE = 5V
VWDE = 12V
WDE Rising Voltage Threshold
mV
mV
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 4: See Power Supplies and Operating Limits in the Applications
Information section for more details.
Note 5: Current limit guaranteed by design and/or correlation to static test.
Slope Compensation reduces current limit at higher duty cycles.
Note 6: Max duty cycle current limit measured at 1MHz switching
frequency.
Note 7: Polarity specification for all currents into pins is positive. All
voltages are referenced to GND unless otherwise specified.
Note 8: This specification is guaranteed for only the exact capacitance as
listed in the conditions. Variation of the capacitance from the exact listed
value will cause proportional variation to tRST, tWDU and tWDL.
8495fb
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LT8495
TYPICAL PERFORMANCE CHARACTERISTICS
No Load Supply Current
FRONT PAGE APPLICATION
VIN=12V
Load Regulation
0.15
FRONT PAGE APPLICATION
0.10
2.0
60
40
20
TYPICAL
LOAD REGULATION (%)
SUPPLY CURRENT (µA)
80
Maximum Load Current
2.5
LOAD CURRENT (A)
100
TA = 25°C, unless otherwise noted.
1.5
1.0
MINIMUM
0.5
0
–50
–10
30
70
110
TEMPERATURE (°C)
0
12
24
36
VIN (V)
48
8495 G01
60
–0.15
VSW
10V/DIV
IL
0.5A/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
VOUT
5mV/DIV
8495 G04
8495 G07
200
400
600
800
LOAD CURRENT (mA)
1000
Transient Load Response; Load
Current Is Stepped from 300mA
to 500mA
IL
0.5A/DIV
8495 G05
500µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
3.0
2.5
2.5
SWITCH CURRENT LIMIT (A)
3.0
2.0
1.5
1.0
0.5
0.0
10
20
30
40 50 60 70
DUTY CYCLE (%)
80
8495 G06
Switch Current Limit at Minimum
Duty Cycle
Switch Current Limit at 500kHz
SWITCH CURRENT LIMIT (A)
IL
0.5A/DIV
0
VOUT
50mV/DIV
1µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 0.5A
Transient Load Response; Load
Current Is Stepped from 20mA
(Burst Mode Operation) to 220mA
VOUT
100mV/DIV
VIN=12V
FRONT PAGE APPLICATION
REFERENCED TO VOUT AT 100mA LOAD
LT8495 G03
Switching Waveforms, Full
Frequency Continuous Operation
VSW
10V/DIV
500µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
–0.05
8495 G02
Switching Waveforms,
Burst Mode Operation
10ms/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 20mA
–0.00
–0.10
0.0
150
0.05
90
8495 G08
2.0
1.5
1.0
0.5
0.0
–50
0
50
100
TEMPERATURE (°C)
150
8495 G09
8495fb
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5
LT8495
TYPICAL PERFORMANCE CHARACTERISTICS
Switch VCESAT
Feedback Voltage
1.25
400
300
200
FREQUENCY (MHz)
1.22
FB VOLTAGE (V)
SWITCH VCESAT (mV)
500
1.21
1.20
1.19
100
0
0.0
0.5
1.5
1.0
SWITCH CURRENT (A)
1.18
–50
2.0
Frequency Foldback
0
100
50
TEMPERATURE (°C)
RT = 324k
200
0.5
0.7
FB VOLTAGE (V)
1.0
100
80
60
40
0
50
100
TEMPERATURE (°C)
20
VIN OR BIAS RISING
34.5
VIN OR BIAS FALLING
33.5
100
50
TEMPERATURE (°C)
150
8495 G16
UPPER BOUNDARY PERIOD, t WDU (ms)
VIN OR BIAS VOLTAGE (V)
35.0
0
100
80
60
40
0
–50
150
0
50
100
TEMPERATURE (°C)
19
Watchdog Lower Boundary Period
760
CWDT = 1nF
TDK
C2012C0G1H102J
18
17
16
15
–50
–10
150
8495 G15
Watchdog Upper Boundary Period
Overvoltage Lockout
35.5
33.0
–50
120
8495 G14
8495 G13
34.0
140
20
0
–50
1.2
150
160
20
0.2
50
100
TEMPERATURE (°C)
Minimum Switch Off-Time
SWITCH OFF-TIME (ns)
600
0
180
120
SWITCH ON-TIME (ns)
SWITCHING FREQUENCY (kHz)
800
RT = 324k
8495 G12
Minimum Switch On-Time
RT = 68.1k
0
0.0
0.50
0.00
–50
150
140
400
0.75
8495 G11
1200
1000
RT = 68.1k
1.00
0.25
8495 G10
6
Oscillator Frequency
1.50
1.23
LOWER BOUNDRY PERIOD t WDL (µs)
600
TA = 25°C, unless otherwise noted.
30
70
110
TEMPERATURE (°C)
150
8495 G17
CWDT = 1nF
TDK
740 C2012COG1H102J
720
700
680
660
640
620
–50
0
50
100
TEMPERATURE (°C)
150
8495 G18
8495fb
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LT8495
TYPICAL PERFORMANCE CHARACTERISTICS
Watchdog Upper Boundary Period
vs Capacitance
Reset Timeout Period
10
9
0
50
100
TEMPERATURE (°C)
10k
RESET TIMEOUT PERIOD, t RST (ms)
11
8
–50
10k
1k
100
10
1
0.1
0.01
150
0.1
1
10
100
CWDT PIN CAPACITANCE, CWDT (nF)
8495 G19
0.1
1
10
100
CWDT PIN CAPACITANCE, CWDT (nF)
1
0.1
1
10
100
CPOR PIN CAPACITANCE, CPOR (nF)
FB Pin Current
1000
350
100
300
250
200
150
100
10
1
0.1
0.01
50
0
1000
1000
8495 G21
FB PIN CURRENT (µA)
SWEN/RSTIN/WDE PIN CURRENT (nA)
0.1
0
10
30
40
50
20
SWEN/RSTIN/WDE PIN VOLTAGE (V)
0.001
60
0
10
30
40
20
FB VOLTAGE (V)
RST Output Voltage
vs Supply Voltage
50
60
8495 G24
8495 G23
8495 G22
Internal UVLO
2.50
10k PULL-UP FROM VIN TO RST
VIN/BIAS VOLTAGE (V)
3
RST OUTPUT VOLTAGE (V)
LOWER BOUNDARY PERIOD, t WDU (ms)
1
10
0.1
0.01
1000
400
10
100
SWEN/RSTIN/WDE Pin Current
1k
100
1k
8495 G20
Watchdog Lower Boundary Period
vs Capacitance
0.01
0.01
Reset Timeout Period
vs Capacitance
100k
CPOR = 4.7nF
TDK
C2012COG1H472J
UPPER BOUNDARY PERIOD, t WDU (ms)
RESET TIMEOUT PERIOD t RST (ms)
12
TA = 25°C, unless otherwise noted.
2
1
0
0
1
2
VIN/BIAS VOLTAGE (V)
2.45
VIN/BIAS RISING
2.40
VIN/BIAS FALLING
2.35
2.30
–50
3
8495 G25
0
50
100
TEMPERATURE (°C)
150
8495 G26
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7
LT8495
TYPICAL PERFORMANCE CHARACTERISTICS
RST Pin Current
vs Supply Voltage
VIN = BIAS = RSTIN,
SWEN = WDE = 0
16
14
12
10
8
VIN = BIAS,
SWEN = WDE = RSTIN = 0
6
4
CURRENT INTO PIN (nA)
RST = 0.4V
18
RST PIN CURRENT (mA)
Pin Current
60
Quiescent Current
12
VFB = 1.25V
VSWEN = VWDE = VRSTIN = 1.2V
10
QUIESCENT CURRENT (µA)
20
TA = 25°C, unless otherwise noted.
40
IFB
20
ISWEN = IWDE = IRSTIN
VIN = 12V, VBIAS = 5V
VSWEN = VWDE = 5V
VFB = VRSTIN = 1.25V
8
6
CURRENT INTO BIAS
4
CURRENT INTO VIN
2
2
0
0
1
3
2
VIN VOLTAGE (V)
4
5
8495 G27
8
0
–50
0
100
50
TEMPERATURE (°C)
150
8495 G28
0
–50
0
100
50
TEMPERATURE (°C)
150
8495 G29
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LT8495
PIN FUNCTIONS
(QFN/TSSOP)
SS (Pin 1/Pin 8): Soft-Start Pin. Place a soft-start capacitor
on this pin. Upon start-up, the SS pin will be charged by
a (nominally) 256k resistor to about 2.1V.
RT (Pin 2/Pin 10): Oscillator Frequency Set Pin. Place a
resistor from this pin to ground to set the internal oscillator frequency. Minimize capacitance on this pin. See the
Applications Information section for more details.
GND (Pins 3, 4, 11, 13, 14, 15, Exposed Pad 21/Pin 14,
Exposed Pad 21): Ground. Solder all pins and the exposed
pad directly to the local ground plane. The exposed pad
metal of the package provides both electrical contact to
ground and good thermal contact to the printed circuit
board.
NC (Pins 4, 9, 17, 19, TSSOP only): No Connects: These
pins are not connected to internal circuitry and must be
left floating to ensure fault tolerance.
RSTIN (Pin 5/Pin 11): Reset Input Reference. Connect
a resistor divider to RSTIN to set the threshold voltage
for asserting RST. The RSTIN voltage is compared to an
internal 1.1V reference. RSTIN voltages lower than the
reference cause RST to assert low.
SWEN (Pin 6/Pin 12): Switch Enable Detect Pin. This pin
enables/disables the switching regulator and soft-start. A
resistor divider can be connected to SWEN to perform an
undervoltage lockout function.
WDE (Pin 7/Pin 13): Watchdog Timer Enable Pin. Drive
above 1.1V to enable the watchdog timer function. When
WDE is low, the WDO output driver is disabled causing
the pin to be high impedance.
WDO (Pin 8/Pin 15): Watchdog Out. Active low, opendrain output. WDO asserts low if WDE is enabled and the
microcontroller fails to drive the WDI pin of the LT8495
with the appropriate signal.
WDI (Pin 9/Pin 16): Watchdog Timer Input Pin. This pin
receives the watchdog signal from a microcontroller. If
the appropriate signal is not received, WDO will pulse low
for a period equal to the reset delay timer period (tRST).
VIN (Pin 10/Pin 18): Supply Input Pin. This pin is typically
connected to the input of the DC/DC converter. Must be
locally bypassed.
SW (Pin 12/Pin 20): Switch Pin. This is the collector of
the internal NPN power switch. Minimize trace area connected to this pin to minimize EMI.
BIAS (Pin 16/Pin 1): Supply Input Pin. This pin is typically connected to the output of the DC/DC converter in
cases where VIN can be higher than VOUT. Must be locally
bypassed.
FB (Pin 17/Pins 2, 3): Output Voltage Feedback Pin. The
LT8495 regulates the FB pin to 1.202V. Connect a resistor divider between the output, FB and GND to set the
regulated output voltage.
CPOR (Pin 18/Pin 5): WDO and RST Active Delay Period
Programming Pin. Attach an external capacitor (CPOR) to
GND to set the period (tRST). See the Applications Information section for more information.
CWDT (Pin 19/Pin 6): Watchdog Timer Programming Pin.
Place a capacitor (CWDT) between this pin and ground to
adjust the watchdog timer upper (tWDU) and lower (tWDL)
boundary periods. See the Applications Information section
for more information.
RST (Pin 20/Pin 7): Active Low, Open-Drain Reset. Asserts
low when RSTIN is less than ~1.1V (see Electrical Characteristics). After RSTIN rises, RST will remain asserted low
for the period (tRST) set by the capacitor on the CPOR pin.
8495fb
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9
LT8495
BLOCK DIAGRAM
2.1V
SS
Q S
SR2
R
256k
100mV
CHIP
SHUTDOWN
SOFTSTART
FB
1.00V
+
–
DIE
TEMP
165°C
34V
–
+
+
–
+
–
VOLTAGE
REFS
ILIMIT
VC_LIMITER
–
+A1
FREQUENCY
FOLDBACK
2.1V
1.10V
1.00V
OTHERS
Burst
Mode
DETECT
VC
34V
–
+
+
–
R Q
SR1
S
QUADRATIC
RAMP
GENERATOR
RSTIN
1.10V
POWER
SWITCH
DRIVER
WDI
+
–
GND
RST
–
+
PGOOD
RESET
WDO
ADJUSTABLE
RESET PULSE
GENERATOR
WATCHDOG
TIMEOUT
ENABLE
TRANSITION
DETECT
2.4V
Q1
+
–
CHIP
SHUTDOWN
1.00V
BIAS
SW
–
+A3
ADJUSTABLE
OSCILLATOR
WDE
2.4V
LOW POWER MODE
A2
RT
VIN
SUPPLY
SELECT
LOGIC
DISABLE PSD
1.202V
SWEN
+
–
OVP
2.3µA
2.3µA
CPOR
WATCHDOG
TIMER
23µA
23µA
CWDT
8495 BD
10
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LT8495
TIMING DIAGRAMS
Start-Up Timing
RSTIN Timing
2.4V
VIN
RSTIN
1.1V
1.3V
RST
SS
tRST
tUV
8495 TD02
RST
WDO
1.202V
0.2V
CPOR
CWDT
8495 TD01
tSTARTUP
tDW
tRST
Watchdog Timing, Lower Boundary
WDI
CWDT
WDO
tWDL
t < tWDL
tRST
8495 TD02a
Watchdog Timing, Upper Boundary
WDI
CWDT
WDO
tWDU
tRST
8495 TD03
tSTARTUP = TIME REQUIRED TO START UP THE CHIP, APPROXIMATELY 1ms
tDW = TIME REQUIRED TO START UP THE WATCHDOG OR POR TIMER, APPROXIMATELY 200µs
tUV = TIME REQUIRED TO ASSERT RST LOW AFTER RSTIN GOES BELOW ITS THRESHOLD, APPROXIMATELY 23µs
tRST = PROGRAMMED RESET PERIOD
tWDU = WATCHDOG UPPER BOUNDARY PERIOD, APPROXIMATELY 31 RAMPING CYCLES ON CWDT PIN
tWDL = WATCHDOG LOWER BOUNDARY PERIOD, APPROXIMATELY 1 RAMPING CYCLE ON CWDT PIN
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11
LT8495
OPERATION
The LT8495 is a constant-frequency, current mode
SEPIC/boost/flyback regulator with power-on reset and
a watchdog timer. Operation can be best understood by
referring to the Block Diagram. The switching regulation,
watchdog timer and reset detection functions are controlled by the SWEN, WDE and RSTIN pins respectively. If
all three pins are grounded, the part enters shutdown with
minimal current drawn from the VIN and BIAS sources. If
any of these three pins are driven above their respective
thresholds, this part is turned on.
Switching Regulator Operation
In the Block Diagram, the adjustable oscillator, with
frequency set by the external RT resistor, enables an RS
latch, turning on the internal power switch. An amplifier
and comparator monitor the switch current flowing through
an internal sense resistor, turning the switch off when this
current reaches a level determined by the voltage at VC.
An error amplifier adjusts the VC voltage by measuring
the output voltage through an external resistor divider
tied to the FB pin. If the error amplifier’s output voltage
(VC) increases, more current is delivered to the output;
if the VC voltage decreases, less current is delivered. An
active clamp on the VC voltage provides current limit. An
internal regulator provides power to the control circuitry.
In order to improve efficiency, the NPN power switch
driver (see Block Diagram) supplies NPN base current
from whichever of VIN and BIAS has the lower supply
voltage. However, if either of them is below 2.4V or above
34V (typical values), the power switch draws current from
the other pin. If both supply pins are below 2.4V or above
34V then switching activity is stopped.
To further optimize efficiency, the LT8495 automatically
enters Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the
output switch is shut down, reducing the VIN/BIAS pin
supply currents to be less than 3µA to 6µA typically (see
Electrical Characteristics table).
Start-Up Operation
Several functions are provided to enable a very clean
start-up for the LT8495.
12
• First, the SWEN pin voltage is monitored by an internal
voltage reference to give a precise turn-on threshold.
An external resistor divider can be connected from the
input power supply to the SWEN pin to provide a userprogrammable undervoltage lock-out function.
• Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current. When the part is brought
out of shutdown, the external SS capacitor is first discharged, and then an integrated 256k resistor pulls the
SS pin up to ~2.1V. By connecting an external capacitor
to the SS pin, the voltage ramp rate on the pin can be
set. Typical values for the soft-start capacitor range
from 100nF to 1µF.
• Finally, the frequency foldback circuit reduces the
maximum switching frequency when the FB pin is below
1V. This feature reduces the minimum duty cycle that
the part can achieve thus allowing better control of the
switch current during start-up.
Power-On Reset and Watchdog Timer Operation
The LT8495 has a power-on reset (POR) circuit and a reset
timer to assert the RST pin for a minimum amount of time.
After initial power up the open-drain RST pin is asserted
low for a programmable reset delay time (see the Timing
Diagrams). During normal operation, the RST pin can also
be asserted when either the RSTIN pin is below its threshold
or the chip enters shutdown due to an abnormal condition. After the chip exits shutdown and the RSTIN pin rises
above its threshold, the RST pin is released after the reset
delay time which is programmable through the CPOR pin.
The watchdog timer typically monitors a microcontroller’s
activity. The watchdog timer can be enabled or disabled
by applying a logic signal to the WDE pin. When enabled,
the watchdog timer requires successive negative edges
on the WDI pin to happen within a programmed time window to keep WDO from pulsing low. Therefore, if the time
between the two negative WDI edges is too short or too
long, the WDO pin will be pulsed low. When the WDO pin
pulls low, a reset timer keeps the WDO pin low for a delay
programmed by the CPOR pin. The WDO pin will go high
again after the reset timer expires or the chip shuts down
(see the Timing Diagrams). The window periods can be
set through the CWDT pin.
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APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation
To enhance efficiency at light loads, the LT8495 regulator
enters low ripple Burst Mode operation keeping the output
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode operation,
the LT8495 regulator delivers single-cycle bursts of current to the output capacitor with each followed by a sleep
period where the output power is delivered to the load by
the output capacitor. The quiescent currents of VIN/BIAS
are reduced to less than 3µA to 6µA typically during the
sleep time (see Electrical Characteristics table).
As the load current decreases towards a no-load condition, the frequency of single current pulses decreases
(see Figure 1), therefore the percentage of time that the
LT8495 operates in sleep mode increases, resulting in
reduced average input current and thus high efficiency
even at very low loads.
By maximizing the time between pulses, the LT8495 quiescent current is minimized. Therefore, to optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider and the reverse current
in the external diode must be minimized, as these appear
to the output as load currents. More specifically, during
SWITCHING FREQUENCY (kHz)
500
FRONT PAGE APPLICATION
400
300
200
100
0
0.1
1
10
100
LOAD CURRENT (mA)
the sleep time, the boost converter has the reverse diode
leakage current conducting from output to input, while
the SEPIC converter has leakage current conducting from
output to ground. Use the largest possible feedback resistors and a low leakage Schottky diode in applications with
ultralow Q current.
In Burst Mode operation, the burst frequency and the
charge delivered with each pulse will not change with
output capacitance. Therefore, the output voltage ripple
will be inversely proportional to the output capacitance.
In a typical application with a 47μF output capacitor, the
output ripple is about 10mV and with two 47μF output
capacitors the output ripple is about 5mV (see Switching
Waveforms, Burst Mode Operation in Typical Performance
Characteristics section). The output voltage ripple can continue to be decreased by increasing the output capacitance.
At higher output loads the LT8495 regulator runs at the
frequency programmed by the RT resistor and operates as
a standard current mode regulator. The transition between
high current mode and low ripple Burst Mode operation is
seamless, and will not disturb the output voltage.
Chip Enable Pins
The SWEN, WDE and RSTIN pins are used to enable various
portions of the LT8495. The lowest current state is when
all three pins are at 0V which disables all functions of the
LT8495. Raising any of these pins above their respective
input threshold voltages (see Electrical Characteristics
section) activates the core circuits of the LT8495. Start-up
of the LT8495 core circuits typically requires about 1ms
(see the Timing Diagram). See the sections Enabling the
Switching Regulator, Watchdog Timer, and Reset Conditions for further details about SWEN, WDE and RSTIN
respectively.
1000
Enabling the Switching Regulator
8495 F01
Figure 1. Switching Frequency in Burst Mode Operation
The SWEN pin is used to enable or disable the switching
regulator. This pin operates independently of the watchdog enable (WDE) and the RST control input (RSTIN). The
rising threshold of SWEN is typically 1V, with 30mV of
hysteresis. The switching regulator is disabled by driving
the SWEN pin below this threshold which deactivates the
NPN power switch. The switching regulator is enabled by
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13
LT8495
APPLICATIONS INFORMATION
driving SWEN above its threshold. Before active switching
begins, the soft-start capacitor is quickly discharged then
slowly charged causing a gradual start-up of the regulator.
SWEN can be connected to VIN if “always on” operation is
desired, although some current will flow into the SWEN
pin (see Typical Performance Characteristics) increasing
overall bias current of the system. Also, a resistor divider
can be connected to SWEN to create an undervoltage
lockout function (see Undervoltage Lockouts) for more
information.
Setting the Output Voltage
The output voltage is programmed with a resistor divider
from output to the FB pin (R2) and from the FB pin to
ground (R1). Choose the 1% resistors according to:
⎛V
⎞
R2 = R1⎜ OUT – 1⎟
⎝ 1.202 ⎠
Note that choosing larger resistors decreases the quiescent
current of the application circuits. In low load applications,
choosing larger resistors is more critical since the part
enters Burst Mode operation with lower quiescent current.
Power Switch Duty Cycle
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block
Diagram) cannot remain “on” for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
T –Minimum Switch Off-Time
DCMAX = P
•100%
TP
where TP is the clock period and the Minimum Switch
Off-Time (found in the Electrical Characteristics) is typically 70ns.
Conversely, the power NPNs (Q1 in the Block Diagram)
cannot remain "off” for 100% of each clock cycle, and
will turn on for a minimum time (Minimum Switch OnTime) when in regulation. This Minimum Switch On-Time
governs the minimum allowable duty cycle given by:
DCMIN =
14
where TP is the clock period and Minimum Switch On-Time
(found in the Electrical Characteristics) is typically 95ns.
The application should be designed such that the operating
duty cycle (DC) is between DCMIN and DCMAX. Normally,
DC rises with higher VOUT and lower VIN.
Duty cycle equations for both boost and SEPIC topologies
are given below, where VD is the diode forward voltage
drop and VCESAT is typically 340mV at 1.2A.
For the boost topology:
DC ≅ VOUT – VIN + VD
VOUT + VD – VCESAT
For the SEPIC topology:
VOUT + VD
DC ≅
VIN + VOUT + VD – VCESAT
The LT8495 can be used in configurations where the duty
cycle is higher than DCMAX, but it must be operated in the
discontinuous conduction mode or Burst Mode operation
so that the effective duty cycle is reduced.
Setting the Switching Frequency
The LT8495 uses a constant frequency PWM architecture
that can be programmed to switch from 250kHz to 1.5MHz
by using a resistor tied from the RT pin to ground. Table 1
shows the necessary RT values for various switching
frequencies.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
RT VALUE (kΩ)
0.25
324
0.4
196
0.6
124
0.8
88.7
1.0
68.1
1.2
54.9
1.4
45.3
1.5
41.2
Minimum Switch On-Time
•100%
TP
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LT8495
APPLICATIONS INFORMATION
where:
Inductor Selection
General Guidelines: The high frequency operation of the
LT8495 allows for the use of small surface mount inductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. To
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low DCR
(copper wire resistance) to reduce I2R losses, and must be
able to handle the peak inductor current without saturating. Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology when using uncoupled inductors, where
each inductor only carries a fraction of the total switch
current. Molded chokes or chip inductors usually do not
have enough core area to support peak inductor currents
in the 2A to 3A range. To minimize radiated noise, use a
toroidal or shielded inductor. Note that the inductance of
shielded types will drop more as current increases, and
will saturate more easily.
Minimum Inductance: Although there can be a trade-off
with efficiency, it is often desirable to minimize board
space by choosing smaller inductors. When choosing
an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current,
and (2) avoidance of subharmonic oscillation. Choose
an inductance that is high enough to meet both of these
requirements.
Adequate Load Current: Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
provided to a load (IOUT). In order to provide adequate
load current, L should be at least:
L>
DC • VIN
⎛
⎞
V
•I
2 ( f ) ⎜ ILIM – OUT OUT ⎟
VIN • η ⎠
⎝
For boost topologies, or:
L>
DC • VIN
⎛
⎞
V
•I
2 ( f ) ⎜ ILIM – OUT OUT –IOUT ⎟
VIN • η
⎝
⎠
L = L1||L2 for uncoupled SEPIC topology
DC = switch duty cycle (see previous section)
ILIM = switch current limit, typically about 2.35A at 50%
duty cycle (see the Typical Performance Characteristics
section)
η = power conversion efficiency (typically 85% to 90%
for boost and 80% to 85% for SEPIC at high currents)
f = switching frequency
Negative values of L indicate that the output load current
IOUT exceeds the switch current limit capability of the
LT8495.
Avoiding Subharmonic Oscillations: The internal slope
compensation circuit of LT8495 helps prevent the subharmonic oscillations that can occur when the duty cycle is
greater than 50%, provided that the inductance exceeds
a minimum value. In applications that operate with duty
cycles greater than 50%, the inductance must be at least:
L>
( VIN − VCESAT ) • (2DC– 1)
0.76 • (1.5 •DC+1) • f • (1–DC)
for boost and coupled inductor SEPIC, or:
L1||L2 >
( VIN − VCESAT ) • (2DC– 1)
0.76 • (1.5 •DC+1) • f • (1–DC)
for the uncoupled inductor SEPIC topologies.
Maximum Inductance: Excessive inductance can reduce
current ripple to levels that are difficult for the current comparator (A2 in the Block Diagram) to cleanly discriminate,
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
LMAX =
VIN – VCESAT DC
•
IMIN(RIPPLE) f
where LMAX is L1||L2 for uncoupled SEPIC topologies and
IMIN(RIPPLE) is typically 150mA.
for the SEPIC topologies.
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15
LT8495
APPLICATIONS INFORMATION
Current Rating: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss.
In steady state, the peak and average input inductor currents (continuous conduction mode only) is given by:
IL1(PEAK) =
IL1(AVG) =
VOUT •IOUT VIN •DC
+
VIN • η
2 •L1• f
VOUT •IOUT
VIN • η
for the boost and uncoupled inductor SEPIC topology.
For uncoupled SEPIC topologies, the peak and average
currents of the output inductor L2 is given by:
IL2(PEAK) =IOUT +
VOUT • (1–DC)
2 •L2 • f
IL2(AVG) =IOUT
For the coupled inductor SEPIC:
⎡ V
⎤ V •DC
IL(PEAK) =IOUT • ⎢1+ OUT ⎥ + IN
⎣ VIN • η ⎦ 2 •L • f
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as closely as
possible to the VIN and BIAS pins of the LT8495. A 2.2µF
to 4.7µF input capacitor is sufficient for most applications.
Audible Noise
Ceramic capacitors are small, robust and have very low
ESR. However, due to their piezoelectric nature, ceramic
capacitors can sometimes create audible noise when used
with the LT8495. During Burst Mode operation, the LT8495
regulator’s switching frequency depends on the load current,
and at very light loads the regulator can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since LT8495 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet. If this is
unacceptable, use a high performance tantalum or electrolytic
capacitor at the output.
Diode Selection
⎡ V
⎤
IL(AVG) =IOUT • ⎢1+ OUT ⎥
⎣ VIN • η ⎦
Note: Inductor current can be higher during load transients.
It can also be higher during short circuit and start-up if
inadequate soft-start capacitance is used. Thus, IL(PEAK)
may be higher than the switch current limit of 2.95A, and
the RMS inductor current is approximately equal to IL(AVG).
Choose an inductor having sufficient saturation current
and RMS current ratings.
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wider voltage
and temperature ranges. Always use a capacitor with a
sufficient voltage rating. Many capacitors rated at 2.2µF
16
to 20µF, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired output voltage. Solid
tantalum or OS-CON capacitors can be used, but they will
occupy more board area than a ceramic and will have a
higher ESR with greater output ripple.
The diode used in boost or SEPIC topologies conducts current only during switch off-time. During switch on-time, the
diode has reverse voltage across it. The peak reverse voltage
is equal to VOUT in the boost topology and equal to (VOUT +
VIN) in the SEPIC topology. Use a diode with a reverse voltage rating greater than the peak reverse voltage.
An additional consideration is the reverse leakage current.
The leakage current appears to the output as load current
and affects the efficiency, most noticeably, under light load
conditions. In Burst Mode operation, after the inductor current vanishes, the reverse voltage across the boost diode is
approximately equal to VOUT – VIN in the boost topology and
VOUT in the SEPIC topology. The percentage of time that the
diode is reverse biased increases as load current decreases.
Schottky diodes that have larger forward voltages often
have less leakage, so a trade-off exists between light load
and high load efficiency. Also the Schottky diodes with larger
reverse bias ratings may have less leakage at a given output
voltage, therefore, superior leakage performance can be
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LT8495
APPLICATIONS INFORMATION
achieved at the expense of diode size. Finally, keep in mind
that the leakage current of a power Schottky diode goes
up exponentially with junction temperature. Therefore, the
Schottky diode must be selected with care to avoid excessive
increase in light load supply current at high temperatures.
Soft-Start
The LT8495 contains a soft-start circuit to limit peak
switch currents during start-up. High start-up current is
inherent in switching regulators since the feedback loop
is saturated due to VOUT being far from its final value. The
regulator tries to charge the output capacitor as quickly as
possible, which results in large peak currents. The start-up
current can be limited by connecting an external capacitor
(typically 100nF to 1µF) to the SS pin. This capacitor is
slowly charged to ~2.1V by an internal 256k resistor once
the part is activated. SS pin voltages below ~0.8V reduce
the internal current limit. Thus, the gradual ramping of
the SS voltage also gradually increases the current limit
as the capacitor charges. This, in turn, allows the output
capacitor to charge gradually toward its final value while
limiting the start-up current. When the switching regulator shuts down the soft-start capacitor is automatically
discharged to ~100mV or less before charging resumes,
thus assuring that the soft-start occurs after every reactivation of the switching regulation.
Power Supplies and Operating Limits
The LT8495 draws supply current from the VIN and BIAS
pins. The largest supply current draw occurs when the
switching regulator is enabled (SWEN is high) and the
power switch is toggling on and off. Under light load conditions the switching regulator enters Burst Mode operation
where the power switch toggles infrequently and the input
current is significantly reduced (see the Low Ripple Burst
Mode Operation section).
Power Switch Driver (PSD) Operating Range: The NPN
power switch is driven by a power switch driver (PSD) as
shown in the Block Diagram. The driver must be powered
by a supply (VIN or BIAS) that is above the minimum operating voltage and below the PSD overvoltage threshold.
These voltages are typically 2.4V and 34V respectively (see
Electrical Characteristics).
If neither VIN nor BIAS is within this operating range, the
PSD and the switching regulator are automatically disabled. Voltages up to 60V are not harmful to the PSD, however, as discussed, switching regulation is automatically
disabled when neither VIN nor BIAS is in the valid operating
range. See Table 2 for some example operating conditions.
Reset and Watchdog Operating Voltage Limits: The
reset circuits operate properly as long as either VIN or
BIAS is above 1.3V (see Reset Conditions section). The
watchdog timer operates properly when either VIN or BIAS
is between 2.5V and 60V. The table below gives some
example operating conditions.
Table 2: Operating Condition Examples
VIN (V)
BIAS (V)
RESET
CIRCUITS
SWITCHING
WATCHDOG REGULATOR
0
1.3
X
1.3
0
X
1
40
X
X
40
40
X
X
1
30
X
X
X
12
40
X
X
X
Automatic Power Supply Selection: In order to minimize
power loss, the LT8495 draws as much of its required current as possible from the lowest suitable voltage supply (VIN
or BIAS) in accordance with the requirements described
in the previous two sections. This selection is automatic
and can change as VIN and/or BIAS voltages change.
The LT8495 compares the VIN and BIAS voltages to determine which is lower. The comparator has an offset
and hysteresis as shown in the Electrical Characteristics
section. The voltage comparison happens continuously
when the power switch is toggling. The result of the latest
comparison is latched inside the LT8495 when switching
stops. If the power switch is not toggling, the LT8495 uses
the last VIN vs BIAS comparison to determine which supply is lower. After initial power up or any thermal lockout
the LT8495 always concludes that VIN is the lower supply
voltage until subsequent voltage comparisons can be made
while the power switch is toggling.
BIAS Connection for SEPIC Converters: For SEPIC converters, where VIN can be above or below VOUT, BIAS is
typically connected to VOUT which improves efficiency when
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LT8495
APPLICATIONS INFORMATION
VIN voltage is higher than VOUT. Connecting BIAS to VOUT
in a SEPIC topology also allows the switching regulator to
operate with VIN above 34V (typical switch driver overvoltage threshold) in cases where VOUT is regulated below the
PSD overvoltage threshold. Finally, connecting BIAS to VOUT
also allows the converter to operate from VIN voltages less
than 2.5V after VOUT rises within the PSD operating range.
This can be very useful in battery powered applications
since the battery voltage drops as it discharges.
BIAS Connection for Boost Converters: For boost converters, BIAS is typically connected to VOUT or to ground.
Connecting BIAS to VOUT allows the converter to operate
with VIN < 2.5V after VOUT has risen within the PSD operating range. However, during no load conditions on VOUT,
despite VIN being selected as the primary input supply,
the overall power loss will be slightly elevated due to the
small amount of current still being drawn from the higher
voltage BIAS pin. To minimize boost converter power loss
during no load conditions, connect BIAS instead to ground.
For boost applications with VOUT higher than the PSD operating range, the BIAS pin should not typically be connected
to VOUT. The LT8495 will never draw the majority of its
current from BIAS due to the excessive voltage, therefore
this connection does not help to improve efficiency. Alternative choices for the BIAS pin connection are ground
or another supply that is within the PSD operating range.
Maximum VIN for Boost Converters: VIN cannot generally
be higher than VOUT in boost topologies because of the DC
path from VIN to VOUT though the inductor and the output
diode. If VIN must be higher than VOUT, then the inductor
must be powered by a separate supply that is always below
VOUT. Otherwise a SEPIC topology can be used.
Also, the LT8495 will not operate in a boost topology
with VIN voltages above the PSD operating range unless
BIAS is connected to an alternative supply within the valid
operating range.
VIN/BIAS Ramp Rate: While initially powering a switching
converter application, the VIN/BIAS ramp rate should be
limited. High VIN/BIAS ramp rates can cause excessive inrush currents in the passive components of the converter.
This can lead to current and/or voltage overstress and may
damage the passive components or the chip. Ramping rates
18
less than 500mV/µs, depending on component parameters,
will generally prevent these issues. Also, be careful to avoid
hot plugging. Hot plugging occurs when an active voltage
supply is “instantly” connected or switched to the input of
the converter. Hot plugging results in very fast input ramp
rates and is not recommended. Finally, for more information,
refer to Linear Application Note 88, which discusses voltage
overstress that can occur when inductive source impedance is
hot plugged to an input pin bypassed by ceramic capacitors.
Watchdog Timer
The LT8495 includes an adjustable watchdog timer that
can monitor a microcontroller activity. If a code execution
error occurs, the watchdog timer can detect this and pull
the open drain WDO pin low. WDO can be connected to
RST or to another input of the microcontroller to reset or
interrupt the microcontroller. Note that the pull-up resistor must be connected to WDO for proper operation. This
resistor is often already integrated in the microcontroller.
The watchdog circuitry monitors negative edges on the
WDI pin. The WDI pin’s negative going pulses are restricted
to appear inside a programmed time window to prevent
WDO from going low. During a code execution error, the
microcontroller will generate WDI pulses that are either
too fast or too slow which will cause WDO to assert low
and force the microcontroller to reset the program (see
the Timing Diagram section).
While monitoring WDI, if the time between any two falling
edges is shorter than the watchdog lower boundary, tWDL
(see Figure 2), or longer than the watchdog upper boundary, tWDU (see Figure 3), WDO is pulled down for a programmable period of tRST (see Reset Conditions section).
WDI
5V/DIV
WDO
5V/DIV
CWDT
1V/DIV
tWDL = 5.2ms, CWDT = 10nF
CPOR
1V/DIV
2ms/DIV
8495 F02
Figure 2. Window Watchdog Waveforms
8495fb
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LT8495
APPLICATIONS INFORMATION
Thus, the WDI period should be higher than tWDL, and
lower than tWDU to keep WDO high under normal conditions. WDO also pulls low if no negative WDI edge occurs
during the watchdog upper boundary period.
0.064
0.058
K1 (nF/ms)
WDI
2V/DIV
WDO
5V/DIV
0.070
0.052
0.046
0.040
tWDU = 155ms, CWDT = 10nF
CWDT
1V/DIV
0.034
0.1
tRST = 93ms, CPOR = 47nF
CPOR
1V/DIV
1
10
100
1k
10k
UPPER BOUNDARY PERIOD, t WDU (ms)
8495 F04
50ms/DIV
8495 F03
Figure 4. Watchdog Upper Boundary Parameter
Figure 3. Timeout Watchdog Waveforms
1.6
To program the tWDU and tWDL periods, see the Watchdog
Upper and Lower Boundary Periods vs Capacitance graphs
in the Typical Characteristics section to select CWDT. The
required capacitor value can also be calculated from a given
watchdog timeout period by using the following equation:
1.3
K2 (ms/nF)
Selecting the Watchdog Timing Capacitor: The watchdog timeout period is adjustable and can be optimized
for software execution. The watchdog upper and lower
boundary timeout periods (tWDU and tWDL) are adjusted
by connecting a capacitor, CWDT, between the CWDT pin
and ground. tWDU is typically 30 • tWDL for large CWDT
values (greater than about 50nF). For lower values this
ratio reduces as shown in Figure 6.
1.0
0.7
0.4
0.01
0.1
1
10
100
CWDT PIN CAPACITANCE, CWDT (nF)
1k
8495 F05
Figure 5. Watchdog Lower Boundary Parameter
32
CWDT = K1 • tWDU
28
K3
Where CWDT is the external capacitor value in nF, tWDU is
the upper boundary period in ms, and K1 is their ratio with
typical values shown in Figure 4. K1 can be approximated
as 0.065nF/ms for upper boundaries greater than 50ms.
24
In addition, the following equation can be used to calculate
the watchdog lower boundary period for a given CWDT
capacitor value.
20
tWDL = K2 • CWDT
16
0.01
Where tWDL is the lower boundary in ms, CWDT is the
external capacitance in nF, and K2 is their ratio with typical values shown in Figure 5. K2 can be approximated as
0.52ms/nF for CWDT values greater than 10nF.
0.1
1
10
100
CWDT PIN CAPACITANCE, CWDT (nF)
1k
8495 F06
Figure 6. Upper and Lower Boundary Ratio
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8495fb
19
LT8495
APPLICATIONS INFORMATION
The watchdog lower boundary period (tWDL) has a fixed
relationship to tWDU for a given CWDT capacitance. The
tWDL period is related to tWDU by the following relationship:
tWDU = K3 • tWDL
where K3 is the ratio between upper and lower boundary
with typical values shown in Figure 6.
Leaving the CWDT pin unconnected will generate a minimum watchdog timeout of approximately 270μs. Maximum
timeout is limited by the largest available low leakage
capacitor. The Electrical Characteristics section indicates
the guaranteed tolerance of the timeout period for a given
capacitance. The accuracy of the timeout period will also
be affected by capacitor leakage (the nominal charging
current is 2.3μA) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
Watchdog Timer Start-Up: There are several conditions
when the WDI pin is not monitored by the watchdog timer.
For each condition, the start-up or resumption of WDI pin
monitoring occurs as described below:
• The watchdog timer is disabled during the POR or
thermal lockout. After POR and thermal lockout are
cleared, CWDT will begin ramping from 0V. The WDI
edges are ignored while the CWDT charges from 0V to
~200mV.
• The watchdog is disabled when WDE is low. After WDE
rises, CWDT may require 1µs to 100μs (typical) before
starting to ramp up. The WDI edges are ignored until
the CWDT charges from 0V to ~200mV.
• WDI edges are not monitored while WDO is asserted low.
Four CPOR cycles are required before WDO is released
and CWDT begins ramping up. The WDI edges are
ignored until the CWDT charges from 0V to ~200mV.
If desired, the RST pin can be connected to WDE to enable
the watchdog timer at about the same time RST is released.
For the example shown in Figure 7, RST is connected to
WDE. After the chip starts up, the output voltage ramps
up towards 5V for the microcontroller supply. When VOUT
rises above 4.5V, and thus RSTIN rises above 1.1V, the RST
and WDE pins will be held low for the additional period of
20
tRST. After tRST, RST is released and WDE will pull high,
thus enabling the microcontroller and the watchdog timer
at about the same time.
LT8495
RSTIN
1.10V
+ –
VOUT
374k
RST
CPOR
121k
POR
TIMER
+
–
CWDT
WATCHDOG
TIMER
1.00V
WDE
WDI
WDO
VDD
µC
RST
WDI
WDO
8495 F07
Figure 7. Watchdog Monitoring
Reset Conditions
The LT8495 has three reset conditions as described below.
All of these conditions can cause the open-drain RST pin
to pull low, as long as either VIN or BIAS is above 1.3V. A
pull-up resistor can be connected to the RST pin so that
it can be used as a reset for an external microcontroller
or other devices. An adjustable timer delays the release
of RST by tRST to ensure adequate reset duration for the
external devices.
The three reset conditions are as follows:
• POR: The RST pin is asserted if VIN and BIAS are both
below 2.4V (typical). This is the power-on reset condition which causes RST to assert upon initial power
up of the LT8495 (see Timing Diagrams). Under this
condition the switching regulator and watchdog timer
are disabled and the CWDT, CPOR, and SS capacitors
are discharged to ground.
• Thermal Lockout: An overtemperature condition on
the LT8495 die will cause the RST pin to assert low.
See High Temperature Considerations section for additional information. This condition disables the switching regulator, the watchdog timer and discharges the
CWDT, CPOR, and SS capacitors to ground. See Thermal
Lockout section for additional information.
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LT8495
APPLICATIONS INFORMATION
A programmable timer delays the release of RST by tRST
after all of the above reset conditions are no longer met.
Before releasing RST, the external CPOR capacitor ramps
up and down for four cycles creating the tRST delay
(see Figure 8). To program the tRST period, see the Reset
Timeout Period vs Capacitance graphs in the Typical Characteristics section to select CPOR. The required capacitor
value can also be calculated from a given reset timeout
period by using the following equation:
CPOR = K4 • tRST
RSTIN
5V/DIV
RST
5V/DIV
tRST = 93ms, CPOR = 47nF
CPOR
500mV/DIV
20ms/DIV
8495 F08
Figure 8. Reset Timer Waveforms
0.6
0.5
K4 (nF/ms)
• RSTIN Undervoltage Lockout: The open-drain RST pin
is asserted low if the RSTIN input is below the 1.1V
typical threshold (see Electrical Characteristics). This
function enables the use of an external resistor divider
to configure an under voltage detection circuit. This
reset condition has no effect on the switching regulator
or the watchdog timer. See the Undervoltage Lockouts
section for more information.
0.4
0.3
where CPOR is the external capacitor value in nF. tRST is
the reset timeout period in ms, and K4 is their ratio with
typical values shown in Figure 9, K4 can be approximated as
0.51nF/ms for reset timeout periods greater than 15ms. As
described previously, this same timer is used to determine
how long WDO is asserted low during a watchdog timeout.
As an example, to create a 9.5ms tRST timeout period,
choose a CPOR capacitor value of 4.7nF. Leaving the
CPOR pin unconnected will generate a tRST period of
approximately 40μs. The maximum period is limited by
the largest available low leakage capacitor. The Electrical
Characteristics section indicates the guaranteed tolerance of the timeout period for a given capacitance. The
accuracy of the timeout period will also be affected by
capacitor leakage (the nominal charging current is 2.3μA)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
As discussed previously, WDO is asserted low for a period of tRST after a watchdog error occurs. This period is
measured by counting four cycles on the CPOR pin in the
same way that the reset delay is measured. If a watchdog
timeout occurs at the same time as the reset delay period,
0.2
0.1
1
10
100
RESET TIMEOUT PERIOD, tRST(ms)
1k
8495 F09
Figure 9. Reset Timer Parameter
the watchdog takes priority in the counter. Therefore,
WDO is always asserted low for four cycles of the CPOR
pin, while the RST delay may be extended beyond four
cycles to a maximum of six cycles, thus increasing tRST
by up to 50%.
Finally note that the tRST delay on the RST pin does not affect
the switching regulator or watchdog timer. The switching
regulator and/or watchdog timer will start right after the
part is no longer in the POR or thermal lockout condition.
Undervoltage Lockouts
Undervoltage lockout (UVLO) functions can be implemented using the SWEN and/or RSTIN pins. An undervoltage lockout can shut down appropriate circuitry to
prevent undesired operation when input and/or output
voltages are too low.
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21
LT8495
APPLICATIONS INFORMATION
R4
1M
R3
487k
SWEN
1.00V
VC
–
+
2.1V
256k
SS
8495 F10
Figure 10. VIN Undervoltage Lockout
Input UVLO: Connecting a resistor divider from VIN to SWEN
(see Figure 10) implements an input undervoltage lockout
circuit. SWEN has an accurate rising threshold of 1.0V
with 30mV of hysteresis (typical–see Electrical Specifications). By connecting a resistor divider from VIN to SWEN,
the LT8495 will be programmed to disable the switching
regulator when VIN drops below a desired threshold. Typically, this threshold is used in situations where the input
supply is current limited, or has a relatively high source
resistance. A switching regulator draws constant power
from the source, so source current increases as source
voltage drops. This looks like a negative resistance load
to the source and can cause the source to current limit or
latch low under low source voltage conditions. The input
UVLO prevents the regulator from operating at source
voltages where the problems might occur.
As shown in Figure 10, by connecting a resistor divider
from VIN to SWEN, the falling undervoltage lockout threshold is set to:
VIN(UVLO) =
R3+R4
• 0.97V
R3
From the previous equation, the resistor divider shown in
Figure 10 gives the VIN pin a falling undervoltage lockout
threshold of 2.96V. When VIN is below this threshold, the
switching regulation is disabled and the SS pin starts to
discharge. After choosing the value of R3, for example,
R4 can be calculated using:
⎛ VIN(UVLO) ⎞
R4 = R3 • ⎜
– 1⎟ Ω
⎝ 0.97
⎠
22
Output UVLO: Connecting the RST and RSTIN pins as
shown in Figures 11 and 12 implements an output undervoltage lock out (UVLO) circuit. This circuit resets VOUT
powered devices when VOUT is below a desired voltage by
asserting the open drain RST pin low. Note that a pull-up
resistor is required on the RST pin, but might already be
integrated in the μC. There is typically a 23µs delay from
the RSTIN pin falling edge until RST is asserted low (see
Electrical Characteristics section) for glitch immunity of
the RSTIN pin. After RSTIN rises above its threshold, RST
continues to be asserted low for a delayed time programmable by the CPOR pin capacitor.
LT8495
POR
TIMER
VOUT
R2B
1M
R2A
8.87k
R1
316k
VOUT
RST
EN
2.3µA
– +
LT8495
VIN
CPOR
1.10V
RSTIN
FB
1.202V
VDD
µC
CPOR
–
+
23µA
VC
8495 F11
Figure 11. RSTIN Reset Lockout
As shown in Figure 12, the R2 resistor (calculated in the
Setting the Output Voltage section) is divided into two resistors, R2A & R2B to implement the UVLO function. Next,
the following equations are used to calculate their values.
⎛
⎞
92%
R2A = R1• ⎜
– 1⎟
⎝ UVLO%NOM ⎠
R2B = R2 –R2A
where UVLO%NOM is the desired nominal UVLO threshold
voltage as a percentage of the nominal VOUT. UVLO%NOM
is recommended to be 89.5% or less for most applications.
Continue reading for more information about selecting
UVLO%NOM.
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LT8495
APPLICATIONS INFORMATION
VOUT
High Temperature Considerations
VOUT
R2B
RSTIN
R2
R2A
FB
R1
FB
R1
8495 F12
Figure 12. RSTIN Pin Connection Options
When choosing UVLO%NOM, consider that the transient
response to VOUT load current steps may cause undershoot
of VOUT. Excessive VOUT undershoot can cause RSTIN to
drop below the comparator threshold and activate RST. The
following equation includes the maximum RSTIN comparator
threshold (97% of the FB reference - see Electrical Characteristics) to show what the maximum UVLO threshold can be.
97
92
For example, when choosing UVLO%NOM = 89.5%,
UVLO%MAX = 94.36% of VOUT. Therefore the RST pin may
assert if VOUT undershoots more than 5.64% below its
steady-state regulated voltage. Choose a lower UVLO%NOM
if more margin is required.
UVLO%MAX = UVLO%NOM •
In addition, the choice of UVLO%NOM affects the minimum
possible VOUT voltage before RST is asserted.
86
92
For example, when using UVLO%NOM = 89.5%, UVLO%MIN
= 83.66% of VOUT. Therefore the RST pin may not assert
unless VOUT is 16.34% below its nominal value. Note that
in terms of absolute VOUT UVLO voltage one must also
consider the tolerance of the FB regulation voltage and
the R1, R2A and R2B resistor tolerances.
UVLO%MIN = UVLO%NOM •
In the example shown in Figure 11, VOUT is regulated to
5V. For a desired UVLO% of 89.5%, the calculated R1,
R2A, and R2B values are 316k, 8.87k, and 1M respectively.
POR UVLO: When both VIN and BIAS are too low for proper
LT8495 operation (typically 12V)
D1
µC
RST
169k
WDI
8495 TA07
C1, C3: 2.2µF, 100V, X5R, 1206
C2: TAIYO YUDEN, EMK325BJ476MM-T
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-150-R
1.5MHz, 12V Output SEPIC Converter
VIN
9V TO 16V
•
C3
2.2µF
C1
2.2µF
D1
•
SW
CPOR
SS
RT
4.7nF
1µF
41.2k
C2
10µF ×2
3.09k
Efficiency, VIN = 12V
110k
85
GND
WDO
RST
EFFICIENCY
80
LT8495
WDE
1200
90
µC
WDI
900
75
70
600
POWER LOSS
65
POWER LOSS (mW)
CWDT
47pF
BIAS
RSTIN
FB
SWEN
1nF
1M
L2
4.7µH
VIN
VOUT
12V
0.5A
EFFICIENCY (%)
L1
4.7µH
300
60
8495 TA08a
C1, C3: 2.2µF, 50V, X5R, 1206
C2: TAIYO YUDEN, TMK325BJ106MM
D1: CENTRAL SEMI CMMSH2-40
L1, L2: COILTRONICS DRQ74-4R7
55
50
0
100
200
300
400
LOAD CURRENT (mA)
0
500
8495 TA08b
30
8495fb
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LT8495
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8495#packaging for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation CA
6.07
(.239)
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
DETAIL A
1.98
(.078)
REF
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
4.50 ±0.10
DETAIL A
2.74
(.108)
6.40
2.74
(.252)
(.108)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
6.07
(.239)
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.56
(.022)
REF
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP REV L 0117
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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31
LT8495
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8495#packaging for the most recent package drawings.
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.00 REF
2.45 ±0.05
2.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
0.75 ±0.05
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
4.00 ±0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
1
2.00 REF
2.45 ±0.10
2
2.45 ±0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
32
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LT8495
REVISION HISTORY
REV
DATE
DESCRIPTION
A
07/15
Added QFN package option.
PAGE NUMBER
Added QFN package option and H-Grade option in TSSOP.
B
06/17
1
2, 3, 4, 9
Clarified Quiescent Current specifications.
3
Clarified RST Leakage Current specifications.
4
Added Pin Current and Quiescent Current graphs.
8
Clarified Pin Functions for QFN package.
9
Clarified leakage current characteristics in High Temperature Considerations.
23
Added new Typical Applications.
30
Clarified Input Conditions on Top Typical Application
30, 34
8495fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8495
33
LT8495
TYPICAL APPLICATIONS
450kHz, Wide Input Range 12V Output SEPIC Converter
L1
10µH
VIN
3V TO 55V
(3V TO 32V FOR START-UP)
(VOUT RIPPLE
MAY INCREASE
BELOW 6V VIN)
•
C3
2.2µF
VOUT
12V
0.2A (VIN = 3V)
0.35A (VIN = 4.5V)
0.65A (VIN = 12V OR HIGHER)
D1
•
1M
L2
10µH
C1
2.2µF
SW
C2
10µF ×3
BIAS
RSTIN
FB
VIN
SWEN
3.09k
110k
GND
CPOR
LT8495
CWDT
4.7nF
SS
1nF
RT
1µF
169k
WDO
WDE
RST
µC
WDI
8495 TA06
C1, C3: 2.2µF, 100V, X5R, 1210
C2: 10µF, 25V, X5R, 1210
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-100-R
No Load Supply Current
Efficiency
100
90
EFFICIENCY (%)
SUPPLY CURRENT (µA)
60
40
WATCHDOG ENABLED
20
0
10
20
30
40
INPUT VOLTAGE (V)
50
VIN = 24V
80
75
70
65
WATCHDOG DISABLED
0
VIN = 12V
VIN = 5V
85
80
60
0.0
60
8495 TA06C
0.1
0.2
0.3
0.4
LOAD CURRENT (A)
0.5
0.6
8495 TA06b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT8494
70V, 2A Boost/SEPIC 1.5MHz High Efficiency DC/DC
Converter
VIN(MIN) = 2.5V, VIN(MAX) = 32V, VOUT(MIN) = 70V, IQ = 9µA, ISD =
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