LT8551
Multiphase Boost Converter
Expander with Internal Gate Drivers
DESCRIPTION
FEATURES
Expands Up to 4 Phases per Chip
nn Up to 80V Input or Output Voltage
nn Cascade with Multiple Chips for High Current
Applications
nn Supports Up to 18 Distinct Phases from 20° to 180°
nn Phases Can Share Phase Angle
nn Excellent DC and Transient Current Sharing
nn Phase-Lockable Fixed Frequency 125kHz to 1MHz
nn Supports Bidirectional Current Flow
nn R
SENSE or DCR Current Sensing
nn Eliminates the Need to Route Sensitive Feedback and
Control Signals.
nn 52-Lead (7mm × 8mm) QFN Package
The LT®8551 is a multiphase expander for synchronous
boost DC/DC converters. It operates in tandem with any
synchronous boost DC/DC converter to increase the load
current capability by adding additional phases, which are
clocked out-of-phase to reduce ripple current and filtering
capacitance. It easily adds phases without the need to
route sensitive feedback and control signals.
nn
The LT8551 integrates 5V gate drivers and can support up
to four boost phases per device. Multiple LT8551 devices
can be used for up to 18 phases. It accurately monitors
and adjusts the current of each channel to achieve excellent DC and transient current sharing.
The LT8551 operates over a fixed frequency from 100kHz
to 1MHz or can be synchronized to an external clock.
APPLICATIONS
High Current Distributed Power Systems
Telecom, Datacom, and Storage Systems
nn Industrial and Automotive
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 9077244.
nn
nn
TYPICAL APPLICATION
24V/25A Step-Up Expander System
SENSE–
SENSE+
BOOST
INTVCC VIN
LTC3769
TG
SW
INTVCC
RUN PLLIN/MODE BG
REG
REGSNS ENOUT
VIN
5V TO 24V
VIN
VOUT
24V/25A
VOUT FOLLOWS VIN
WHEN VIN > 24V
CLK1
POWER STAGE 1
TG1
BST1
REGIS
REGDRV
LT8551 PINS NOT SHOWN
IN THIS CIRCUIT:
BST2, BST3, BST4, TG2, TG3, TG4,
SW2, SW3, SW4, BG2, BG3, BG4,
ISP2, ISP3, ISP4, ISN2, ISN3, ISN4
SYNC, PHS1, PHS2, PHS3, MODE,
TGBUF, BGBUF, CLK2, IAMPP, IAMPN,
SHDN, RT/MS, ILIM
SW1
ISN1
ISP1
REG
VIN
LT8551
VCC
REG
TGSR TGSH TGSL BGSH ISP
ISN
BG1
GND
PINS FOR POWER
STAGES 2,3,4
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
8551 TA01a
Rev 0
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1
LT8551
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
PHS3
NC
ISP1
ISN1
ISN3
ISP3
REGIS
REGDRV
VIN
SW4
TG4
BST4
TOP VIEW
52 51 50 49 48 47 46 45 44 43 42 41
BG4 1
40 REGSNS
BG3 2
39 ISP4
REG 3
38 ISN4
SW3 4
37 ISP2
TG3 5
36 ISN2
BST3 6
35 ISP
BST2 7
34 ISN
53
GND
TG2 8
33 IAMPP
SW2 9
32 IAMPN
BG2 10
31 SHDN
BG1 11
30 MODE
BGBUF 12
29 VCC
TGBUF 13
28 ENOUT
27 ILIM
BST1 14
RT/MS
PHS1
PHS2
SYNC
BGSH
CLK1
CLK2
TGSL
TGSH
TGSR
TG1
15 16 17 18 19 20 21 22 23 24 25 26
SW1
SW1/2/3/4 (Note 5)…………………………………..80V
ISP1/2/3/4, ISN1/2/3/4, ISP, ISN, VIN,
REGIS, REGDRV Voltage (Note 2).......... .–0.3V to 80V
SHDN Voltage………………………………–0.3V to 70V
TGSL Voltage…………………………………–3V to 80V
TGSH Voltage…………………………………–3V to 86V
TG1/2/3/4, BST1/2/3/4, TGSR Voltage...... . –0.3V to 86V
BG1/2/3/4, RT/MS, SYNC, PHS1/2/3, CLK1/2,
REGSNS, IAMPP, ILIM, BGSH, BGBUF, TGBUF,
ENOUT, MODE, VCC, REG, (BST–SW)1/2/3/4,
(TG–SW)1/2/3/4, (VIN –REGDRV),
(TGSR–TGSL), (TGSH–TGSL) Voltage... –0.3V to 6.0V
IAMPN Voltage…………………………….–0.6V to 0.6V
(ISP–ISN)1/2/3/4, (ISP–ISN) Voltage ….... –0.3V to 0.3V
Operating Junction Temperature Range (Note 3)
LT8551E.............................................. –40°C to 125°C
LT8551I............................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 125°C, θJA = 31°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8551EUKG#PBF
LT8551EUKG#TRPBF
8551
52-Pin (7mm × 8mm) Plastic QFN
–40°C to 125°C
LT8551IUKG#PBF
LT8551IUKG#TRPBF
8551
52-Pin (7mm × 8mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev 0
2
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LT8551
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
VIN Operating Voltage Range
For Min Spec, VCC, REG = 0V
VIN Quiescent Current
REG = VCC = 5V, REGDRV, REGIS Floating
l
TYP
3.6
MAX
80
800
VIN Quiescent Current in Shutdown
Not Switching
VCC Undervoltage Lockout
VCC Falling, REG = VCC
5
l
3.3
3.55
1.05
1.15
V
µA
2
VCC Quiescent Current
UNITS
µA
mA
3.8
0.1
V
VCC Undervoltage Lockout Hysteresis
REG = VCC
SHDN Input Voltage High
SHDN Falling
l
SHDN Input Voltage Low
Device Disabled, Low Quiescent Current, VCC = REG = 3V
l
SHDN Pin Bias Current
VSHDN = 3V
VSHDN = 12V
MODE Low Falling Threshold
Slave LT8551
l
MODE High Rising Threshold
Slave LT8551
l
MODE Output Voltage Low
Master LT8551, 200µA into MODE pin
50
mV
MODE Output Voltage High
Master LT8551, 20µA out of MODE pin
4.8
V
SHDN Input Voltage High Hysteresis
V
1.25
60
0
8.5
V
mV
0.3
V
1
20
µA
µA
0.5
V
4.5
V
MODE Pin Impedance in Middle State
Master LT8551
9
kΩ
ENOUT Output Voltage Low
Master LT8551, 1mA into ENOUT Pin, VCC, REG in UVLO
60
mV
ENOUT Leakage Current
ENOUT = 5V, REG = VCC = 3V
0.2
1
µA
ENOUT Rising Threshold
2.1
V
ENOUT Threshold Hysteresis
0.4
V
Current Sensing
Maximum Positive Current Sense Voltage, ILIM = 0V, ISNn = 12V, ISPn Rising
(ISPn –ISNn)
ILIM = REG, ISNn = 12V, ISPn Rising
ILIM = Float, ISNn = 12V, ISPn Rising
l
l
l
27.0
56
84.5
30
60
90
32.5
64
95.5
mV
mV
mV
Maximum Negative Current Sense
Voltage, (ISNn –ISPn)
l
l
l
26.5
55.5
84
30
60
90
33
64.5
96
mV
mV
mV
ISP, ISN Common Mode Operating
Voltage Range
l
0
80
V
ISPn, ISNn Common Mode Operating
Voltage Range
l
0
80
V
ILIM High Rising Threshold
l
4.65
V
ILIM = 0V, ISNn = 12V, ISPn Falling
ILIM = REG, ISNn = 12V, ISPn Falling
ILIM = Float, ISNn = 12V, ISPn Falling
ILIM High Threshold Hysteresis
ILIM Low Falling Threshold
l
mV
80
mV
0.3
ILIM Low Threshold Hysteresis
ILIM Impedance at Floating
IAMPP Output Voltage
90
V
11
(ISP–ISN) = 30mV, ILIM = 0V, Master LT8551, ISP = 12V
(ISP–ISN) = 0mV, ILIM = 0V, Master LT8551, ISP = 12V
(ISP–ISN) = –30mV, ILIM = 0V, Master LT8551, ISP = 12V
(ISP–ISN) = 60mV, ILIM = REG, Master LT8551, ISP = 12V
(ISP–ISN) = 0mV, ILIM = REG, Master LT8551, ISP = 12V
(ISP–ISN) = –60mV, ILIM = REG, Master LT8551, ISP = 12V
(ISP–ISN) = 90mV, ILIM = Float, Master LT8551, ISP = 12V
(ISP–ISN) = 0mV, ILIM = Float, Master LT8551, ISP = 12V
(ISP–ISN) = –90mV, ILIM = Float, Master LT8551, ISP = 12V
l
l
l
l
l
l
l
l
l
2.33
1.33
0.33
2.33
1.35
0.34
2.33
1.35
0.34
2.4
1.4
0.4
2.4
1.4
0.4
2.4
1.4
0.4
kΩ
2.47
1.47
0.47
2.47
1.45
0.46
2.47
1.45
0.46
V
V
V
V
V
V
V
V
V
Rev 0
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3
LT8551
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
(ISPn –ISNn) Voltage In Regulation
IAMPP = 2.20V, IAMPN = 0V, ILIM = 0V, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = 0V, ISNn = 12V
IAMPP = 2.20V, IAMPN = 0V, ILIM = REG, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = REG, ISNn = 12V
IAMPP = 2.20V, IAMPN = 0V, ILIM = Float, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = Float, ISNn = 12V
(ISP–ISN) to IAMPP Voltage Gain
ILIM = 0V, Master LT8551, ISP = 0V
ILIM = REG, Master LT8551, ISP = 0V
ILIM = FLOAT, Master LT8551, ISP = 0V
IAMPP Sourcing Current Limit
(ISP–ISN) = 0mV, Master LT8551
l
250
µA
IAMPP Sinking Current Limit
(ISP–ISN) = 0mV, Master LT8551
l
60
µA
IAMPP Load Regulation
ILOAD = –200µA to 50 µA, Master LT8551
IAMPP Pin Bias Current
IAMPP = 1.2V, Slave LT8551
IAMPP = 2.4V, Slave LT8551
l
l
l
l
l
l
TYP
MAX
26.75
–21.25
51
–45
76.75
–67.25
21.25
–26.75
45
–51
67.25
–76.75
UNITS
mV
mV
mV
mV
mV
mV
33.3
16.7
11.1
1
3
6
mV
µA
µA
ILIM = REG
Mismatch Between (ISPn –ISNn) and
Master LT8551’s (ISP–ISN) in Regulation
l
–6
–4.75
6
4.75
%
%
ILIM = FLOAT
Mismatch Between (ISPn –ISNn) and
Master LT8551’s (ISP–ISN) in Regulation
l
–6
–5.5
6
5.5
%
%
ILIM = 0V
Mismatch Between (ISPn –ISNn) and
Master LT8551’s (ISP–ISN) in Regulation
l
–10
–8
10
8
%
%
1100
264
110
kHz
kHz
kHz
1000
1000
kHz
kHz
Oscillator
CLK1 Frequency
RT/MS = 24.3kΩ, Master LT8551
RT/MS = 100 kΩ, Master LT8551
RT/MS = 249kΩ, Master LT8551
l
l
l
900
236
90
Switching Frequency Range
Free-Running
Synchronizing
l
l
100
125
SYNC High Level for Synchronization
l
1.2
SYNC Low Level for Synchronization
l
1000
250
100
V
0.8
V
CLK1, CLK2 Rise Time
CLOAD = 220pF, Master LT8551 (Note 4)
7
ns
CLK1, CLK2 Fall Time
CLOAD = 220pF, Master LT8551 (Note 4)
5
ns
CLK2 Rising Threshold
Slave LT8551
l
CLK2 Falling Threshold
Slave LT8551
l
PHS1, PHS2 High Rising Threshold
4
1
V
4.65
l
PHS1, PHS2 High Threshold Hysteresis
PHS1, PHS2 Low Falling Threshold
l
PHS1, PHS2 Impedance at Floating
mV
80
mV
V
11
PHS3 Rising Threshold
kΩ
4.65
l
PHS3 Threshold Hysteresis
V
80
0.3
PHS1, PHS2 Low Threshold Hysteresis
V
80
V
mV
REG LDO
REG Voltage
REGSNS = 5V, IAMPN = 0V, ILOAD = 45mA
REG LDO Current Limit
VIN = 12V, REGSNS = 5V, REG, VCC = 4V
VIN = 24V, REGSNS = 5V, REG, VCC = 4V
250
145
mA
mA
REG LDO Gate Drive Clamp Voltage
(VIN – REGDRV) Voltage, REG, VCC = 4.5V
5.3
V
REG Load Regulation
ILOAD = 0A to 100mA, REGSNS = 5V, IAMPN = 0V
90
mV
l
4.9
5.1
5.3
V
Rev 0
4
For more information www.analog.com
LT8551
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
REGSNS Pin Bias Current
REGSNS = 5V
12
µA
TG1, TG2, TG3, TG4 Rise Time
CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4)
30
ns
TG1, TG2, TG3, TG4 Fall Time
CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4)
20
ns
BG1, BG2, BG3, BG4 Rise Time
CLOAD = 3.3nF (Note 4)
50
ns
BG1, BG2, BG3, BG4 Fall Time
CLOAD = 3.3nF (Note 4)
27
ns
Bottom & Top Gate Non-Overlap Time
TG Falling to BG Rising, CLOAD = 3.3nF (Note 4)
BG Falling to TG Rising, CLOAD = 3.3nF (Note 4)
85
80
ns
ns
Bottom & Top Gate Minimum Off-Time
CLOAD = 3.3nF (Note 4)
140
ns
Gate Drivers
Primary Gate Sensing
BGSH Rising Threshold
l
BGSH Falling Threshold
l
4
1
BGSH Threshold Hysteresis
V
V
1.4
V
BGSH to BGBUF Delay
CLOAD = 220pF, Master LT8551 (Note 4)
45
ns
BGBUF Rise Time
CLOAD = 220pF, Master LT8551 (Note 4)
8
ns
BGBUF Fall Time
CLOAD = 220pF, Master LT8551 (Note 4)
TGSH Rising Threshold
TGSR = 5V, TGSL = 0V
l
TGSH Falling Threshold
TGSR = 5V, TGSL = 0V
l
TGSH Threshold Hysteresis
6
ns
4
1
V
V
1.4
V
TGSH to TGBUF Delay
CLOAD = 220pF, Master LT8551 (Note 4)
45
ns
TGBUF Rise Time
CLOAD = 220pF, Master LT8551 (Note 4)
8
ns
TGBUF Fall Time
CLOAD = 220pF, Master LT8551 (Note 4)
6
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating Condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage or current source
to REGDRV, BG1, BG2, BG3, BG4, TG1, TG2, TG3 and TG4, otherwise
permanent damage may occur.
Note 3: The LT8551E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8551I is guaranteed to meet performance specifications from –40°C to
125°C junction temperature.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: Negative voltages on SW1/2/3/4 pins are limited, in an application,
by the body diodes of the external NMOS devices, or the parallel Schottky
diodes when present. The SW1/2/3/4 pins are tolerant of these negative
voltages in excess of one diode drop below ground, guaranteed by design.
Rev 0
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5
LT8551
TYPICAL PERFORMANCE CHARACTERISTICS
REG LDO Load Regulation
REGSNS = 5V
IAMPN = 0V
VIN = 12V
5.1
5.0
4.9
4.8
4.9
4.6
4.3
0
45
90
135
180
REG LDO LOAD CURRENT (mA)
4.0
225
IAMPN = 0.1V
IAMPN = 0V
IAMPN = –0.1V
3
3.5
4
4.5
5
REGSNS VOLTAGE (V)
5.5
8551 G01
10.0
7.5
15
25
35 45 55 65
VIN VOLTAGE (V)
75
15.0
12.5
10.0
0
10
20
30 40 50 60
VIN VOLTAGE (V)
70
80
80
8551 G03
4.9
4.8
4.7
4.6
LOAD = 0mA
REGSNS – IAMPN = 5V
4.4
5.0
–50 –25
0
4.3
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
8551 G05
VCC QUIESCENT CURRENT (mA)
VCC QUIESCENT CURRENT (mA)
4.9
70
4.5
7.5
5.3
5.0
30 40 50 60
VIN VOLTAGE (V)
5.0
VCC Quiescent Current vs
Temperature, Not Switching
5.1
20
5.1
17.5
8551 G04
5.2
10
5.2
20.0
85
T = 150°C
T = 25°C
T = –50°C
0
REG LDO Line Regulation
VIN = 6V
VIN = 12V
VIN = 80V
22.5
VCC Quiescent Current vs VIN
Voltage, Not Switching
5.3
60
5.3
3.8
VIN = 6V
VIN = 12V
VIN = 80V
VCC UVLO THRESHOLD (V)
5
120
0
6
REG VOLTAGE (V)
12.5
25.0
REG QUIESENCT CURRENT (µA)
REG QUIESCENT CURRENT (µA)
15.0
5.0
180
REG Quiescent Current vs
Temperature, Not Switching
T = 130°C
T = 25°C
T = –50°C
17.5
240
8551 G02
REG Quiescent Current vs VIN
Voltage, Not Switching
20.0
REG LDO Current Limit
300
5.2
REG VOLTAGE (V)
5.2
REG VOLTAGE (V)
REG Voltage vs REGSNS Voltage
5.5
REG LDO CURRENT LIMIT (mA)
5.3
5.2
5.1
5.0
4.9
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G07
8551 G08
30 40 50 60
VIN VOLTAGE (V)
70
80
8551 G06
VCC UVLO Threshold
3.7
RISING
3.6
FALLING
3.5
3.4
3.3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G09
Rev 0
6
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LT8551
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Threshold
1.30
3.4
VIN Quiescent Current vs VIN
Voltage, Not Switching
VIN UVLO Threshold
5.6
T = 130°C
RISING
1.20
FALLING
1.15
VIN QUIESCENT CURRENT (mA)
1.25
3.3
VIN UVLO THRESHOLD (V)
SHDN PIN THRESHOLD (V)
5.5
RISING
3.2
FALLING
3.1
5.4
5.3
5.2
T = 25°C
5.1
5.0
T = –50°C
4.9
3.0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
8551 G10
5.1
4.9
0
20
15
10
0
25 50 75 100 125 150
TEMPERATURE (°C)
T = 150°C
T = 25°C
T = –50°C
0
10
20
30
40
50
SHDN PIN VOLTAGE (V)
60
8551 G13
80
70
ILIM = REG
60
50
40
ILIM = GND
30
20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
85
8551 G12
2.0
1.7
1.4
1.1
0.8
ILIM = FLOAT
ILIM = REG
ILIM = GND
0.5
0.2
–90
70
–60
–30
0
30
ISP-ISN VOLTAGE (mV)
60
PHS1 Pin Current
–20
180
ILIM = GND
–30
120
–40
–50
ILIM = REG
–60
–70
–80
ILIM = FLOAT
–90
–100
–50 –25
90
8551 G15
Maximum Negative Current Limit
vs Temperature
MAXIMUM NEGATIVE CURRENT LIMIT (mV)
MAXIMUM POSITIVE CURRENT LIMIT (mV)
ILIM = FLOAT
90
75
8551 G14
Maximum Positive Current Limit
vs Temperature
100
35 45 55 65
VIN VOLTAGE (V)
2.3
5
4.7
–50 –25
25
2.6
25
SHDN PIN CURRENT (µA)
VIN QUIESENCT CURRENT (mA)
30
5.3
15
IAMPP–IAMPN Voltage vs (ISP–
ISN) Voltage
SHDN Pin Current vs Voltage
VIN = 6V
VIN = 12V
VIN = 80V
5.5
5
8551 G11
VIN Quiescent Current vs
Temperature, Not Switching
5.7
4.8
25 50 75 100 125 150
TEMPERATURE (°C)
IAMPP-IAMPN VOLTAGE (V)
0
PHS1 PIN CURRENT (µA)
1.10
–50 –25
0
0
–60
–120
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G16
60
8551 G17
–180
0
1
2
3
4
PHS1 PIN VOLTAGE (V)
5
8551 G18
Rev 0
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7
LT8551
TYPICAL PERFORMANCE CHARACTERISTICS
PHS1 High Threshold Voltage vs
Temperature
PHS1 Low Threshold Voltage vs
Temperature
4.50
FALLING
RISING
0.6
FALLING
0.5
4.30
T = 25°C
60
0
–60
–120
4.25
–50 –25
0
0.4
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
–180
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G19
2
3
4
PHS2 PIN VOLTAGE (V)
5
ILIM Pin Current vs Voltage
0.8
180
PHS2 VOLTAGE (V)
0.7
4.40
FALLING
ILIM PIN CURRENT (µA)
120
RISING
4.35
1
8551 G21
PHS2 Low Threshold Voltage vs
Temperature
4.50
4.45
0
8551 G20
PHS2 High Threshold Voltage vs
Temperature
RISING
0.6
FALLING
0.5
4.30
60
0
–60
–120
4.25
–50 –25
0
0.4
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G22
ILIM VOLTAGE (V)
RISING
FALLING
2.3
0.8
2.2
RISING
0.7
0.6
FALLING
0.5
0.4
0
25 50 75 100 125 150
TEMPERATURE (°C)
2
3
ILIM VOLTAGE (A)
0.3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G25
8551 G26
4
5
ENOUT Threshold Voltage
0.9
4.25
4.20
–50 –25
1
8551 G24
ILIM Low Threshold Voltage vs
Temperature
4.40
4.30
0
8551 G23
ILIM High Threshold Voltage vs
Temperature
4.35
–180
ENOUT THRESHOLD VOLTAGE (V)
PHS2 VOLTAGE (V)
PHS2 PIN CURRENT (µA)
0.7
4.40
4.35
180
120
RISING
PHS1 VOLTAGE (V)
PHS1 VOLTAGE (V)
4.45
ILIM VOLTAGE (V)
PHS2 Pin Current
0.8
RISING
2.1
2.0
1.9
1.8
FALLING
1.7
1.6
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G27
Rev 0
8
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LT8551
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Temperature
BST–SW UVLO Threshold
400
300
RT = 100k
200
RT = 249k
100
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G28
TGSR–TGSL UVLO THRESHOLD (V)
2.40
RT = 49.9k
500
0
–50 –25
TGSR–TGSL UVLO Threshold
3.7
BST-SW UVLO THRESHOLD (V)
OSICLLATOR FREQUENCY (kHz)
600
RISING
3.6
3.5
FALLING
3.4
3.3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G29
2.35
2.30
FALLING
2.25
2.20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8551 G30
Rev 0
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9
LT8551
PIN FUNCTIONS
REG (Pin 3): Output of REG LDO. Power supply for gate
drivers. Decouple this pin to ground with a minimum
4.7µF low ESR ceramic capacitor. Connect this pin to the
external PMOS drain side.
BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1): Bottom Gate
Driver Output. These pins drive the gates of the bottom
N-channel MOSFETs. Voltage swing at these pins is from
ground to REG.
BGBUF (Pin 12): Logic Output Pin. This pin is pulled up
to REG when BGSH is at logic high, and it is pulled down
to ground when BGSH is at logic low. For a slave LT8551,
leave this pin floating. See the Applications Information
section for more information.
TGBUF (Pin 13): Logic Output Pin. For a master LT8551,
this pin is pulled up to REG voltage when (TGSH–TGSL)
is at logic high, and it is pulled down to ground when
(TGSH–TGSL) is at logic low. For a slave LT8551, leave
this pin floating. See the Applications Information section
for more information.
BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52):Boosted
Floating Driver Supply. The (+) terminal of the boost-strap
capacitor is connected to this pin. This pin swings from a
diode voltage drop below REG up to VOUT + REG.
TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51): Top Gate Driver
Output. This is the output of a floating driver with a voltage swing equal to REG superimposed on the switch node
voltage.
SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50): Switch Node.
Voltage swing at these pins is from a diode voltage drop
below ground to VOUT.
TGSR (Pin 17): The Rail of Primary Channel Top Gate
Sense Circuit. For a master LT8551, connect this pin to
the primary channel top gate driver’s boost node. This pin,
combined with TGSH, TGSL pins, is to sense the primary
channel top MOSFET’s state. For a slave LT8551, connect
this pin to REG.
TGSH (Pin 18): Input of Primary Channel Top Gate Sense
Circuit. For a master LT8551, connect this pin to the primary channel top MOSFET’s gate. This pin, combined
with TGSR, TGSL pins, is to sense the primary channel
top MOSFET’s state. For a slave LT8551, connect this pin
to the master LT8551’s TGBUF pin.
TGSL (Pin 19): Lower Rail of Primary Channel Top Gate
Sense Circuit. For a master LT8551, connect this pin to
the primary channel top MOSFET’s source. This pin, combined with TGSR, TGSH pins, is to sense the primary
channel top MOSFET’s state. For a slave LT8551, connect
this pin to ground.
CLK1, CLK2 (Pins 21, 20): Clock Pin. These two pins
are used to synchronize the primary channel to all other
channels. See the Applications Information section for
more information.
BGSH (Pin 22): Logic Input of Primary Channel Bottom
Gate Sense Circuit. For a master LT8551, connect this
pin to the primary channel bottom MOSFET’s gate. This
pin is to sense the primary channel bottom MOSFET’s
state. For a slave LT8551, connect this pin to the master
LT8551’s BGBUF pin.
SYNC (Pin 23): To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock. The
high voltage level of the clock must exceed 1.2V, and the
low level must be less than 0.8V. Drive this pin to less
than 0.8V to revert to the internal free-running clock. See
the Typical Applications section.
PHS1, PHS2 (Pins 25, 24): Phase Selection Pin. These
pins, combined with PHS3 and RT/MS, set the switching
frequency and the phase of each channel. PHS1 and PHS2
are three-level input pins, they can be floated, set to REG
or ground. When the PHS1/PHS2 is floating, add a 1nF
cap from PHS1/PHS2to ground. See the Operation section
for more information.
Rev 0
10
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LT8551
PIN FUNCTIONS
RT/MS (Pin 26): Timing Resistor Pin and Master Slave
Selection Pin. This pin, combined with PHS1, PHS2 and
PHS3, sets the switching frequency and the phase of
each channel. Connecting a resistor to ground sets the
chip as master LT8551. Connecting this pin to the REG
pin sets the chip as slave LT8551. See the Applications
Information section for more information.
ILIM (Pin 27): Maximum Current Sense Voltage
Programming Pin. This pin is used to set the maximum
sense voltage in the primary channel current sense amplifier and expanded channel current sense amplifier. It is a
three level input pin. Connecting this pin to ground, REG
or leaving it floating sets the maximum current sense
voltage to 30mV, 60mV or 90mV, respectively. When the
ILIM is floating, add a 1nF cap from the ILIM to ground.
ENOUT (Pin 28): For a master LT8551, this pin is an opendrain logic output pin. For a slave LT8551, it is an input
pin. See more details in ENOUT Connection Section.
VCC (Pin 29): Power Supply for Control Circuits. Decouple
this pin to ground with a minimum 1µF low ESR ceramic
capacitor. VCC and REG need to be connected through a
1Ω resistor.
MODE (Pin 30):Stage Shedding Selection Pin. Connecting
this pin to GND disables stage shedding feature. See the
Operation section for more information.
SHDN (Pin 31): Shutdown Pin. This pin is used to enable/
disable the chip. Drive below 0.3V to disable the chip.
Drive above 1.2V (typical) to activate the chip. Do not
float this pin.
IAMPN (Pin 32): For a master LT8551, connect this pin
to local ground. For a slave LT8551, connect this pin
to the master LT8551’s IAMPN. See the Applications
Information section for more information.
IAMPP (Pin 33): For a master LT8551, this is an output pin. It is the buffered signal of the Primary Channel
Current Sense Amplifier output. For a slave LT8551, this
is an input pin. When multiple LT8551 devices are used,
connect all IAMPP pins together. See the Applications
Information section for more information.
ISP (Pin 35): Primary Channel Current Sense Amplifier
Input. The (+) input to the current sense amplifier is normally connected to DCR sensing network or current sensing resistor. This pin is only used for a master LT8551.
Ground this pin for a slave LT8551.
ISN (Pin 34): Primary Channel Current Sense Amplifier
Input. The (–) input to the current sense amplifier is
normally connected to DCR sensing networks or current sensing resistors. This pin is only used for a master
LT8551. Ground this pin for a slave LT8551.
REGSNS (Pin 40): REG LDO Voltage Sense Pin. Connect
this pin to the primary channel gate driver power supply
pin.
PHS3 (Pin 41): Phase Select Pin. This pin, combined with
PHS1, PHS2 and RT/MS, set the switching frequency and
the phase of each channel. PHS3 connects to REG or
ground. See the Operation section for more information.
NC (Pin 42): No Connection. Leave this pin floating or
connect to any adjacent pin.
ISN1, ISN2, ISN3, ISN4 (Pins 44, 36, 45, 38): Expanded
Channel Current Sense Amplifier (–) Input. The (–) input
to the current sense amplifier is normally connected to
DCR sensing network or current sensing resistor.
ISP1, ISP2, ISP3, ISP4 (Pins 43, 37, 46, 39): Expanded
Channel Current Sense Amplifier (+) Input. The (+) input
to the current sense amplifier is normally connected to
DCR sensing network or current sensing resistor.
REGIS (Pin 47): REG LDO Current Sense Pin. Connect
this pin to the external PMOS source side.
REGDRV (Pin 48): Gate Driver Output for REG LDO.
Connect this pin to the external PMOS gate.
VIN (Pin 49): Input Supply Pin. Must be locally bypassed
to ground.
GND (Exposed Pad Pin 53/Pin 27): Ground. Tie directly
to local ground plane.
Rev 0
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11
LT8551
BLOCK DIAGRAM
VOUT REG
ENOUT
REGIS
REGSNS
+
IAMPN
REGS_INT
–
+
REG
STAGE
SHEDDING
CONTROL
MODE
23
25
24
+
ISN
–
41
21
20
17
18
19
22
13
12
BST4
+
TG4
–
TIMING
CONTROL
4
SW4
REG
BG4
OSCILLATOR
AND CLOCK
PROCESSING
VC4
TGSR
TGSH
TGBUF
BGBUF
VIN
VOUT REG
CLK2
BGSH
43
1×
CLK1
TGSL
ISP1
ILIM
PHS1
PHS3
44
IAMP_INT
SYNC
PHS2
11
CHANNEL 2 AND 3
NOT SHOWN
–
ISP
RT/MS
16
CURRENT LIMIT
AND
FAULT CONTROL 1
A7 (1×)
IAMPN
1.8V
26
15
+
A0
34
A6
ISN1
14
A1
EA1
PRIMARY
GATE
SENSING
IAMP_INT4
ISN4
52
51
50
1
38
A4
EA4
+
35
VC1
REG
29 VCC
ILIM
27
IAMPP
33
32
–
IAMP_INT1
+
30
BG1
REGDRV
A5 (1×)
3
SW1
REG
CURRENT
LIMIT
CONTROL
–
40
OT
–
48
UVLO_VIN
+
47
VIN
TIMING
CONTROL
1
–
49
TG1
START-UP CONTROL
ENOUT
CONTROL
VBIAS
BST1
UVLO_VCC
+
28
SHDN
–
31
ISP4
39
VIN
ILIM
CURRENT LIMIT
AND
FAULT CONTROL 4
8551 BD
Rev 0
12
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LT8551
OPERATION
Introduction
Stage Shedding Mode
The LT8551 is a multiphase expander for synchronous
boost controllers. Each LT8551, which has 8 gate drivers,
can expand up to four phases. Multiple LT8551 devices
can also be used together in a system, and up to 18 different phases can be supported. In addition, the part supports more than one phase per phase angle.
The MODE pin is dedicated for the Stage Shedding feature. The MODE pin is an output pin for a master LT8551,
and it is an input pin for a slave LT8551.
The ADI proprietary control architecture allows the LT8551
to cycle-by-cycle duplicate the operation of a boost controller (named as Primary Controller). The LT8551 measures the primary controller’s inductor current as well as
primary controller’s gate driver operation timing, and at
the same time, accurately monitors and adjusts the current of each expanded channel to achieve excellent DC and
transient current sharing. The current sharing accuracy
is ±6%, ±6% and ±10% over temperature when ILIM set
at REG, Float and GND, respectively.
In normal operation, the primary boost regulator’s switch
current is compared with the expanded channel’s switch
current by the EA (EA1/2/3/4 in the Block Diagram).
When the primary channel’s current increases, the VC
(VC1/2/3/4 in the Block Diagram) voltage also increases,
which in turn controls the expanded channel’s switches to
increase the current until the expanded channel’s current
matches the primary channel’s current.
System with Multiple LT8551 devices
One LT8551 can expand up to four channels. This configuration can provide enough power for most high current
applications. However, for even higher power applications,
the LT8551 can be configured for multi-chip operation.
When two or more LT8551 devices are used together in
a system, one LT8551 is the master and other LT8551
devices are slaves. Connecting a resistor from the RT/MS
pin to ground sets the chip as the master and connecting
the RT/MS pin to REG sets the chip as a slave. When only
one LT8551 is used in a system, this LT8551 needs to be
set as a master.
For a master LT8551, when the MODE pin is floating, the
LT8551 operates in Stage Shedding mode at light loads.
In this case, when the (ISP–ISN) peak voltage is lower
than a certain value for some period of time, the part
turns off channels 1 and 3 to increase overall efficiency.
After channel 1 and 3 are off, if the (ISP–ISN) peak voltage is still lower than a certain value for some period of
time, the part also turns off channel 4 and only leaves
channel 2 running. For bidirectional applications, stage
shedding should be disabled when the current is regulated
in the reverse direction. Driving the MODE pin below 0.5V
disables the Stage Shedding feature.
In a multiple LT8551 devices system, all chips’ MODE
pins need to be connected together and leave them floating if the Stage Shedding feature is desired. The master LT8551 senses the (ISP–ISN) voltage to decide the
proper operation. The slave LT8551 devices follows the
master LT8551’s Stage Shedding operation with some
delay. Driving all chips’ MODE pins below 0.5V disables
the Stage Shedding feature.
Clock Scheme
This section discusses the LT8551’s clock scheme for a
multiple LT8551 system. This clock scheme can easily
apply to a single LT8551 system by ignoring the slave
LT8551 devices.
A master LT8551 generates two clock signals: CLK1 and
CLK2. In a multiple LT8551 system, as shown in Figure 1,
all LT8551 devices’ CLK2 pins need to be connected
together. The CLK1 signal is at the fundamental switching
frequency (Refer to Internal Oscillator and SYNC Pin and
Clock Synchronization sections for more information),
and it is used to synchronize the primary boost controller
Rev 0
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13
LT8551
OPERATION
and the slaves (in Figure 1). Under normal operation, the
CLK2 frequency is at the CLK1 frequency times the total
distinct phase number (TDPN), as shown in Figure 2. The
number shown above the CLK2 pulses in Figure 2 is called
the phase angle number (PAN).
When the primary controller skips one or more pulses,
the expanded channels also skip the same number of
pulse(s). This function is realized by CLK2. As shown in
Figure 4, when the primary controller skips one BG pulse,
the CLK2 also skips a group of pulses with phase number
from 1 to TDPN.
PRIMARY
CONTROLLER
SYNC
MASTER
LT8551
SYNC
CLK1
CLK2
RT/MS
SLAVE
LT8551
REG
SYNC
CLK1
CLK2
RT/MS
SLAVE
LT8551
REG
SYNC
CLK1
CLK2
RT/MS
Table 2 shows the PHS1, PHS2 and PHS3 connections
for a two LT8551 system with a total of 9 phases, including the primary controller’s phase, as an example. The
primary controller uses the CLK1 signal. The clocks used
by the eight expanded channels are shown in Figure 3.
Table 1. Table for Programming Total Distinct Phase Number
(TDPN) and Phase Angle Number (PAN)
PHS3
PHS2
PHS1
TDPN For
Master
PAN of Slave
Channel 1 Pulse
GND
GND
GND
NA
1
• • •
8551 F01
Figure 1. Clock Configuration in a Multiple LT8551 System
The total distinct phase number is programmed through
the master LT8551’s PHS1, PHS2 and PHS3 pins, according to Table 1. There is a delay locked loop in the chip
which can force the primary controller’s BG (Bottom Gate)
rising edge to align with the pulse whose phase angle
number equals the TDPN (in Figure 2).
Each expanded channel chooses one pulse from CLK2 in
one CLK1 clock cycle. The rising edge of this chosen pulse
aligns with the corresponding channel’s bottom gate turn
on edge with a very short delay. The master LT8551’s
channel 1 to channel 4 always choose the pulses whose
phase angle number equals 1 to 4, respectively. Four channels of a slave LT8551 choose pulses with four consecutive phase angles. The phase angle number of the slave
LT8551’s channel 1 pulse is also programmed through
PHS1, PHS2 and PHS3 pins, according to Table 1, and
the pulses of the slave LT8551’s channel 2, channel 3
and channel 4 have the next three phase angle number in
succession. LT8551.
GND
GND
REG
2
2
GND
GND
Floating
3
3
GND
REG
GND
4
4
GND
REG
REG
5
5
GND
REG
Floating
6
6
GND
Floating
GND
7
7
GND
Floating
REG
8
8
GND
Floating
Floating
9
9
REG
GND
GND
10
10
REG
GND
REG
11
11
REG
GND
Floating
12
12
REG
REG
GND
13
13
REG
REG
REG
14
14
REG
REG
Floating
15
15
REG
Floating
GND
16
16
REG
Floating
REG
17
17
REG
Floating
Floating
18
18
Table 2. Design Example for a 9-Phase Application
PHS3
PHS2
PHS1
PAN for Channel 1,
2, 3 and 4
Master LT8551
GND
Floating
Floating
1, 2, 3, 4
Slave LT8551
GND
REG
REG
5, 6, 7, 8
Rev 0
14
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LT8551
OPERATION
TDPN-1 TDPN
1
2
TDPN-1 TDPN
1
2
• • •
CLK2
CLK1
PRIMARY’S
BG
8551 F06
Figure 2. CLK1, CLK2 and Primary’s BG
CLOCK FOR SLAVE
CHANNEL 4
CLOCK FOR SLAVE
CHANNEL 3
CLOCK FOR SLAVE
CHANNEL2
CLOCK FOR SLAVE
CHANNEL 1
CLOCK FOR MASTER
CHANNEL 4
CLOCK FOR MASTER
CHANNEL 3
CLOCK FOR MASTER
CHANNEL 2
CLOCK FOR MASTER
CHANNEL 1
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
CLK2
CLK1
PRIMARY’S
BG
8551 F03
Figure 3. Clock Waveforms for a Two LT8551 System
TDPN-1 TDPN
1
TDPN-1 TDPN
1
• • •
TDPN-1 TDPN
1
• • •
CLK2
CLK1
PRIMARY’S
BG
8551 F04
Figure 4. CLK1, CLK2 and Primary’s BG Waveforms for Pulse Skipping
Rev 0
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15
LT8551
OPERATION
Primary Controller’s Switch State Detection
Primary Controller’s Inductor Current Sensing
This section discusses a system with multiple LT8551
devices. For a single LT8551 system, simply ignore the
slave LT8551 devices in this discussion.
This section discusses a system with multiple LT8551
devices. For a single LT8551 system, simply ignore the
slave LT8551 devices in this discussion.
The primary controller’s switch states are detected by
the master LT8551, and this information is used by both
master and slave LT8551 devices.
The primary controller’s inductor current is detected by
the master LT8551, and this information is used by both
the master and slave LT8551 devices.
The primary controller’s top switch state is sensed by
the master LT8551’s TGSR, TGSH, and TGSL pins, as
shown in Figure 5. This floating top gate logic signal is
converted to a ground based logic signal, and outputted
to the TGBUF pin. The master LT8551’s TGBUF is then
connected to the downstream slaves’ TGSH, as shown in
Figure 5. The slave’s TGSR and TGSL are connected to the
REG and GND respectively. If the (TGSR–TGSL) voltage is
less than 2.3V (typical), the TGBUF pin will be forced to
ground for both of the master and slave LT8551. See the
Applications Information section for more information.
As shown in Figure 6, the primary controller’s inductor
current is detected by the master LT8551’s ISP and ISN
pins. This signal is amplified, and then outputted to the
master LT8551’s IAMPP pin. For stability purposes, a cap
is required from the IAMPP to GND, and total capacitance must be between 100pF and 470pF. For a slave
LT8551, the ISP and ISN pins are not used and should
be grounded, and the IAMPP is an input pin. To pass the
primary’s inductor current information from the master
LT8551 to the slave LT8551 devices, all LT8551 devices’
IAMPP and IAMPN pins are connected together, respectively. Connect the IAMPN pins to the master LT8551’s
local ground. The IAMPP and IAMPN are connected to the
inputs of a unity gain differential sense amplify (A7 in the
Block Diagram). See the Applications Information section
for more information.
MASTER
LT8551
TGBUF
BGBUF
PRIMARY
CONTROLLER
BST
TG
SW
BG
TGSR
TGSH
TGSL
BGSH
RT/MS
SLAVE
LT8551
REG
TGBUF
BGBUF
SLAVE
LT8551
REG
TGBUF
BGBUF
TGSR
TGSH
TGSL
TGSR
TGSH
TGSL
BGSH
RT/MS
BGSH
RT/MS
• • •
RSENSE
MASTER
LT8551
IAMPP
IAMPN
8551 F05
ISN
ISP
RT/MS
Figure 5. Gate Sensing in a Multiple LT8551 System
A similar method is used for the primary controller’s bottom switch state detection, also shown in Figure 5. Since
the primary BG is a ground based signal, only one pin
(BGSH) is needed for the primary’s BG detection. Since
the master LT8551 passes the primary’s switch states to
the slaves, this avoids routing the primary’s noisy BST,
TG, SW and BG signals around the board.
SLAVE
LT8551
REG
IAMPP
IAMPN
ISN
ISP
RT/MS
SLAVE
LT8551
REG
IAMPP
IAMPN
• • •
ISN
ISP
RT/MS
8551 F06
Figure 6. Primary Regulator’s Switch Current
Sensing in Multiple LT8551 System
The signal across the primary inductor current sense
resistor is only tens of mV. By passing the amplified current signal from the master to the slaves, routing sensitive
small signals around the board is avoided.
Rev 0
16
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LT8551
OPERATION
Current Sensing Gain, Limit and Fault
The gain of five current amplifiers (A0 to A4 in the Block
Diagram) has three gain levels which are set by the ILIM
pin. Connecting the ILIM pin to GND/REG/Floating sets
the gain to 33.3/16.7/11.1, respectively. The outputs of
these amplifiers are called IAMP_INT/IMAP_INTx (in the
Block Diagram). The relation between the IAMP_INT/
IAMP_INTx and the (ISP–ISN)/(ISPx–ISNx) are shown
in Figure 7. There is a 1.4V offset. For expanded channels,
the IAMP_INTx’s value determines the current limit and
current fault as shown in Figure 8.
ILIM = REG ILIM = FLOAT
GAIN = 16.7 GAIN = 11.1
IAMP_INT (V)
IAMP_INTx (V)
1.4
ILIM = GND, GAIN = 33.3
ILIM = REG, GAIN = 16.7
ILIM = FLOAT, GAIN = 11.1
0.4
–60
–30
30
60
90
(ISP – ISN) (mV)
(ISPx – ISNx) (mV)
8551 F07
Figure 7. Current Sensing Amplifier Output Vs. Input
at Three Different Gains
2.8
IAMP_INTx (V)
Figure 9 illustrates the start-up sequence for the LT8551.
The shutdown pin for the chip is SHDN. When it is driven
below 0.3V, the chip is disabled (chip off state) and quiescent current is minimal. Increasing the SHDN voltage
can increase quiescent current but will not enable the chip
until SHDN is driven above 1.15V (typical) after which the
REG LDO is enabled (switcher off state).
Starting up the switching regulator happens after VCC
has risen above 3.55V (typical) and the ENOUT has been
driven above 2.1V (typical). For a master LT8551, the
ENOUT is an open drain pin. When VCC is lower than
3.55V, the ENOUT is pulled to GND to disable switching.
For a slave LT8551, the ENOUT is always a high impedance input pin.
CURRENT FAULT
Fault Sequence
CURRENT LIMIT
The LT8551 activates a fault sequence (see Figure 9)
when IAMP_INTx is higher than 2.8V, which is the fault
condition for a LT8551. The fault event is independent of
channels, which means that the fault condition occurring
in one channel won’t directly affect other channels. If one
of these conditions occurs for a certain channel, the corresponding channel’s gate driver outputs are pulled low. If
one of the LT8551’s channels enters latch off mode (see
Figure 9), only restarting the whole chip will reactivate
the channel.
2.4
NORMAL OPERATION
0.4
When the IAMP_INTx reaches 2.8V, the corresponding
channel enters current fault. When the current fault condition is detected, the corresponding channel enters into
a fault sequence which is described in more detail in the
Fault Sequence section.
Shutdown and Start-Up
2.4
–90
When the IAMP_INTx reaches 2.4V but lower than 2.8V,
or if it drops below 0.4V, the corresponding channel
enters current limit. When the current limit condition is
detected, both corresponding channel’s BGx and TGx are
pulled low immediately. The channel resumes switching at
the next clock rising edge after the current limit condition
is removed. The corresponding (ISPx–ISNx) voltages at
current limit are indicated in Figure 7.
CURRENT LIMIT
0
8551 F08
Figure 8. IAMP_INTx Voltage for Current Limit and
Current Fault
Rev 0
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17
LT8551
OPERATION
SHDN > 1.15V (TYPICAL) AND VIN > 3.3V (TYPICAL) AND
TJUNCTION 2.1V (TYPICAL) AND VCC > 3.55V (TYPICAL)
NORMAL MODE
• NORMAL OPERATION
• RESET FAULT COUNTER
FAULT
FAULT DETECTED
• SWITCHER DISABLED
• FAULT COUNTER +1
LATCH OFF MODE
NO
• SWITHER DISABLED
IS
FAULT COUNTER
LESS THAN 15?
YES
• WAITING FOR FAULT CONDITION
CLEARED
YES
POST FAULT DELAY
FAULT
• SWITCHER DISABLED
• WAITING FOR ABOUT 800 CLOCK CYCLES
PRE-NORMAL MODE
• NORMAL OPERATION FOR ABOUT 800
CLOCK CYCLES
FAULT
8551 F09
Figure 9. Start-Up and Fault Sequence
ENOUT Connection
REG
For a master LT8551, this pin is an open-drain logic
output pin. The master LT8551’s ENOUT pin is pulled
to ground when it is not ready for switching. For a slave
LT8551, this pin is an input pin. For both master and slave
LT8551 devices, when the ENOUT pin is lower than 2.1V
(typical), the gate driver’s switching activity is disabled.
When a master LT8551 is not ready for switching, it is
desired to disable the primary controller and the slave
LT8551 devices’ switching activity. Figure 10 is one recommended configuration.
18
47k
PRIMARY
CONTROLLER
EN OR
SHND
MASTER
LT8551
47pF
CONNECT TO
SYSTEM ENABLE SIGNAL
SLAVE
LT8551
ENOUT
ENOUT
SHDN
SHDN
8551 F10
Figure 10. Recommended ENOUT Connection
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Rev 0
LT8551
APPLICATIONS INFORMATION
The REG LDO supplies the power for the gate drivers and
output stages of CLK1, CLK2, TGBUF and BGBUF. Once the
SHDN pin is higher than 1.15V, REG will be regulated to
4V (typical), (REGSNS – IAMPN) voltage, or 5.25V (typical) from VIN, depending on whether (REGSNS – IAMPN)
is lower than 4V, or higher than 4V but lower than 5.25V,
or higher than 5.25V respectively, as shown in Figure 11.
The REG pin must be bypassed to power ground with an
X5R or X7R ceramic capacitor of at least 4.7μF placed
close to the REG pin.
local ground. Since the master’s local ground and the
primary controller’s local ground may have small voltage
difference, this can introduce a small error. To minimize
this error, the master LT8551 should be placed close to
the primary controller.
PRIMARY
CONTROLLER
INTVCC
CLP
LT8551
*VBIAS
REGDRV
MP
REG
10µF
1Ω
RF
5.25
5
2.2µF
CF
4
REGSNS
IAMPN
VIN
REGIS
REG VOLTAGE (V)
10nF
10Ω
CURRENT
LIMIT
+A5 –
1x
A6
+
–
REG LDO and VCC Power
REGS_INT
VCC
8551 F12
*LOWER VOLTAGE (VBIAS) CAN BE USED FOR VIN PIN TO REDUCE THERMAL
STRESS INSTEAD OF USING THE SUPPLY FOR THE POWER STAGE
0
0
4 5
(REGSNS – IAMPN) VOLTAGE (V)
Figure 12. REG LDO Configuration
8551 F11
Figure 11. REG Voltage vs REGSNS Voltage
VCC is the power supply for most of the internal circuitry
and it’s connected to REG through an external filter (RF,
CF) to filter the switching noise in REG, as shown in
Figure 12, the filter should be placed close to the VCC pin,
typical value of RF = 1Ω, CF = 1μF is recommended. The
internal UVLO comparator disables the LT8551’s switching activity when VCC is lower than 3.55V (typical).
Primary INTVCC Sensing
The primary controller gate driver’s power supply is
INTVCC, as shown in Figure 12. The primary INTVCC voltage is filtered and then sensed by the differential unity
gain amplifier A5 in Figure 12, and buffered to REGS_INT
as the reference voltage of the REG LDO. Notice that the
(–) of A5 is connected to IAMPN. As has been discussed
in the Primary Controller’s Inductor Current Sensing
section, both the master LT8551’s IAMPN and the slave
LT8551’s IAMPN are connected to the master LT8551’s
REG LDO Current Limit and External Power PMOS
Selection
Overcurrent protection circuitry limits the maximum current drawn from the REG LDO. When the VCC voltage is
below 3.3V during start-up or an overload condition, the
typical current limit is about 110mA. When the REG voltage is higher than 3.55V, the current limit depends on the
VIN voltage as shown in Figure 13. If the VIN voltage is
lower than 13.6V or higher than 30V, the current limit is
about 220mA or 100mA respectively. If the VIN voltage is
between 13.6V and 30V, the current limit is inversely proportional to the VIN voltage to limit the maximum power
dissipation in the external power PMOS. The power dissipation in the external PMOS can be calculated by:
P = (VBIAS – REG) • ILDO
Where VBIAS (VIN pin voltage) is the chip power supply
for the LT8551, ILDO is the current drawn from the REG
LDO for a specific application. Use the following formula
to calculate the junction temperature of the PMOS and
Rev 0
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19
LT8551
APPLICATIONS INFORMATION
compare the calculated value of TJ to the manufacturer’s
data sheets to help choose the appropriate PMOS that
will not overheat.
TJ = TA + P • RTH(JA) (1)
Where:
TJ is the junction temperature of the PMOS
TA is the ambient air temperature
P is the power dissipation of the PMOS.
RTH(JA) is the MOSFET’s thermal resistance from the
junction to the ambient air. Refer to the manufacturer’s
data sheets.
To reduce the power dissipation in the external PMOS,
it’s helpful to power up the chip with a lower voltage aux
power supply (VBIAS) instead of sharing the same power
supply with the power stage, especially in a high input
voltage application. Large enough copper area on the PC
board is needed for the PMOS to alleviate thermal stress.
To ensure the loop stability, it’s also recommended to
choose a PMOS with Qg < 40nC.
Operating Frequency Selection
The expander system (primary controller and LT8551
devices) adopts a constant frequency ranging from
100kHz to 1MHz determined by the master LT8551. The
primary controller and slave LT8551 devices are synchronized to the master LT8551 by connecting the master LT8551’s CLK1 pin to their SYNC pins as shown in
Figure 1. To minimize noise, it is recommended to add
an RC filter between master CLK1 and each primary’s or
slave’s SYNC pin. This RC filter should be close to SYNC
pins with typical value of R = 10Ω, C = 220pF.
The frequency can be set either by the internal oscillator,
or can be synchronized to an external clock source. A
trade-off between efficiency and component size exists in
selecting the switching frequency. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires more inductance and/or capacitance
to maintain low output ripple voltage. The switching frequency can be set by placing an appropriate resistor from
the RT/MS pin to ground and tying the SYNC pin low or
high. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following
sections provide more details.
MAXIMUM CURRENT (mA)
Internal Oscillator
220
CONSTANT
POWER
SET TO 100 mA
100
0
0
30
13.6
VIN (V)
The free-running switching frequency of the master
LT8551 can be set using the internal oscillator by tying
a resistor from RT/MS pin to ground while the SYNC pin
is driven low (1.2V). The oscillator frequency is calculated using the following formula:
8551 F13
Figure 13. REG LDO Current Limit vs VBIAS Voltage
fOSC =
25,000
kHz
R T + 0.15
(2)
Where fOSC is in kHz and RT is in kΩ. Conversely, RT (in
kΩ) be calculated from the desired frequency (in kHz)
using:
RT =
25,000
kΩ – 0.15kΩ (3)
fOSC
Rev 0
20
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LT8551
APPLICATIONS INFORMATION
SYNC Pin and Clock Synchronization
The LT8551 has a phase-locked loop (PLL) to synchronize
the internal oscillator to the external clock signal. The
PLL is an edge sensitive digital type that provides zero
degree phase shift between the external clock and internal
oscillators.
To synchronize to an external clock source properly, the
frequency of the external clock source must meet two
criteria listed below:
1. The PLL is guaranteed to work properly only when the
frequency of the external clock source ranges from
125kHz to 1MHz.
2. The external clock can be synchronized to only when
it’s faster than the free-running frequency set by the
RT resistor. If the external clock is lower than fOSC, as
set by RT, the internal oscillator will oscillate at fOSC.
Primary Controller Gate Sensing Filters and Dividers
As has been discussed in the Operation section, the
primary controller’s top and bottom switch states are
detected by the master LT8551 gate sensing pins (i.e.
TGSR, TGSH, TGSL and BGSH). This sensed top gate
signal and bottom gate signal are buffered to the master
LT8551’s TGBUF and BGBUF respectively.
Since the primary controller’s SW node moves fast, an
RC filter RF, CF and bypass capacitor CH must be used,
as shown in Figure 14, to avoid falsely sensing the primary controller’s top MOSFET’s state. Optional Schottky
clamps close to the TGSL pin of the LT8551 are recommended to prevent the TGSL pin from ringing below
ground or exceeding the pin’s absolute maximum rating if
long traces are used to sense the top gate. Optional filters
are also recommended for both of the primary controller’s
bottom gate sensing and the slave LT8551 devices’ gate
sensing pins, as shown in Figure 14. The time constant
of these filters should be less than 30ns, typical values of
RF = 20Ω, C = 1nF are recommended.
The LT8551 is recommended to work with a primary
controller which has gate driver rail lower than 5.5V. If
the primary has higher than 5.5V gate driver rail, resistor
PRIMARY
CONTROLLER
BST
MASTER
LT8551
TGSR
CF
RF
TG
CH
SLAVE
LT8551
REG
TGSR
TGSH
TGBUF
VIN
TGSH
TGSL
SW
TGSL
BG
BGSH
BGBUF
BGSH
8551 F14
OPTIONAL
Figure 14. Gate Sensing Configuration with Filters
and Schottky Clamps on TGSL
PRIMARY
CONTROLLER
SW
MASTER
LT8551
TGSL
R3
CH
R4
BST
TGSR
C2
R2
TGSH
TG
RF
BG
R1
C1
R5
BGSH
R6
CF
8551 F15
OPTIONAL
Figure 15. Gate Sensing Configuration when Primary
Gate Driver Rail is Higher than 5.5V
dividers are required as shown in Figure 15. Use the following equations to design the adequate divider and filter
for the gate sensing or refer to Table 3 for the recommended values:
RF C1C2
≤ 30ns
C1+C2
CF R5R6
≤ 30ns
R5+R6
R4
R6
5.5V
R2
=
=
=
R1+R2 R3+R4 R5+R6 Primary's VINTVCC
R1C1= R2C2
Rev 0
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21
LT8551
APPLICATIONS INFORMATION
Table 3. Recommended Values for Gate Sensing Filters
Primary’s
INTVCC
Voltage (V)
6.0
R1 = R3 = R5 R2 = R4 = R6
(kΩ)
(kΩ)
4.7
47
C1
(nF)
C2
(nF)
RF
(Ω)
10
1.0
22
6.5
10
33
3.3
1.0
27
7.0
10
22
2.2
1.0
30
7.5
10
15
1.0
0.68
47
8.0
10
15
1.0
0.68
47
9.0
10
13
1.0
0.68
47
9.5
9.1
13
1.0
0.68
47
10
10
10
1.0
1.0
43
In addition, R1–R6 should be in the range of kΩ or higher
to reduce the quiescent current. And in order to sense the
primary top gate state correctly during the SW node transition, the C1 and C2 capacitance within 1nF to 100nF and
CH>4.7nF are recommended. These dividers and filters
should be close to the master LT8551 in the PCB layout.
Power MOSFET, Schottky Diode (Optional) Selection
and Efficiency Considerations.
Critical parameters for power MOSFET selection include
the on-resistance (RDS(ON)), Miller capacitance (CMILLER),
BVDSS (i.e. drain-source breakdown voltage) and maximum output current, all those parameters can be found
on the manufacture’s data sheet. The gate drive voltage
is set by the REG LDO (5V, typical value), consequently
logic level (5V) MOSFET must be used for the LT8551.
It’s very important to consider power dissipation when
selecting the power MOSFETs. The most efficient circuit will use MOSFETs that dissipate the least amount of
power. Power dissipation must be limited to avoid overheating that might damage the device. When the LT8551
operates in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
Power Stage Components Selection Guideline
The power stage components include the input and output
capacitor, inductor, power N-channel MOSFETs and the
optional Schottky diode. Each LT8551’s expanded channel always adopts the exact same power stage components as the primary controller. The following sections
offer a brief guideline for the power device selection. Refer
to the primary controller’s data sheet for more detailed
information.
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also the inductor should have low DC
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
The inductor selection is interrelated with maximum average load current and inductor current ripple, which means
the inductor must have a rating greater than its peak operating current to prevent saturation and the inductance
must be large enough to decrease the current ripple so
that the maximum average current can be fed to the load
due to the limited peak inductor current.
Synchronous Switch Duty Cycle =
VIN
VOUT
If the maximum output current is IOUT(MAX) the MOSFET
power dissipation at maximum output current is given by:
PMAIN =
Inductor Selection
VOUT – VIN
VOUT
( VOUT – VIN ) VOUT •I
VIN
2
OUT(MAX )
•RDS(ON) +k • VOUT 3 •
PSYNC =
2
• (1+ δ )
IOUT(MAX )
•CMILLER • f
VIN
VIN
•IOUT(MAX )2 • (1+ δ ) •RDS(ON)
VOUT
Both MOSFETs have I2R losses while the bottom N-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high VIN the
high current efficiency generally improves with larger
MOSFETs, while for low VIN the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low.
Rev 0
22
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LT8551
APPLICATIONS INFORMATION
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Based on the power dissipation, the MOSFET junction
temperature can be obtained using the formula (1) in
the REG LDO Current Limit and External Power PMOS
Selection section to pick an adequate MOSFET that will
not overheat.
An optional Schottky diode in parallel with the top switch
conducts during the dead time between the conduction
of the main switch and the synchronous switch. This prevents the body diode of the synchronous switch from turning on, storing charge and requiring a reverse recovery
period that could reduce the overall efficiency. Although
improving the efficiency, the Schottky diode also exhibits much higher reverse leakage current than the silicon
diode particularly at high temperature, the combination of
high reverse voltage and current can lead to self-heating
of the diode. Choose a package with lower thermal resistance (θJA) to minimize self-heating of the diode.
CIN and COUT Selection
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The input capacitor CIN voltage rating should comfortably exceed the maximum input
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input voltage for any possible overvoltage transients that could
apply excess stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher
the required input capacitance. The required amount of
input capacitance is also greatly affected by the duty cycle.
High output current applications that also experience high
duty cycles can place great demands on the input supply,
both in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current, so COUT must be capable of reducing the output
voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when
choosing the right capacitor for a given output ripple
voltage. The steady ripple voltage due to charging and
discharging the bulk capacitance in a single phase boost
converter is given by:
VRIPPLE =
IOUT(MAX ) • ( VOUT – VIN(MIN) )
COUT • VOUT • f
V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VESR = IL(MAX) • ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (e.g., OS-CON and POSCAP).
Topside MOSFET Driver Supply (CBX, DBX)
An external bootstrap capacitor, CBX, supplies the gate
driver voltage for the top switch. This capacitor is connected between BSTx and SWx and is charged through
Schottky diode DBX from REG when the SWx pin is low.
When the top switch turns on, the SWx rises to VOUT
and the BSTx rises to VOUT + REG. The boost capacitor
needs to store about 100 times the gate charge required
by the top switch. In most applications, a 0.1μF to 0.47μF,
X5R or X7R dielectric capacitor is adequate. The bypass
capacitance from REG to GND should be at least ten times
the bootstrap capacitor value. In addition, the reverse
breakdown of the Schottky diode must greater than the
maximum power VOUT voltage.
Inductor Current Sensing
The LT8551 can be configured to sense the inductor
current through either low value series current sensing
Rev 0
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23
LT8551
APPLICATIONS INFORMATION
resistor (RSENSE) or inductor DC resistance (DCR). The
choice between the two current sensing schemes is
largely a design trade-off between cost, accuracy and
power consumption. DCR is becoming popular since it
saves expensive current sensing resistors and is more
power efficient, especially in high current applications.
However, current sensing resistors provide the most accurate current limits for the controller. The ISPx/ISNx (i.e.
ISP, ISP1/2/3/4, ISN, ISN1/2/3/4) pins are the inputs to
the current sense amplifiers. The common mode input
voltage range of the current sense amplifier is from 0V
to 80V. The current sense resistor is normally placed at
the input of the LT8551 in series with the inductor. Each
ISPx pin also provides power to the current sense amplifier when ISPx is higher than 1.1V (typical). It draws 0µA
to 100μA during normal operation. The ISNx pin current
is less than 1µA. The high impedance ISNx input to the
current amplifier allows accurate DCR current sensing.
Low Value Resistor Current Sensing: A typical RSENSE
inductor current sensing is shown in Figure 16a. The filter
components (RF, CF) need to be placed near the LT8551.
RF values greater than 100Ω should be avoided as this
may increase offset voltage. The filter time constant
(RF • CF) should be no more than 30nS. The positive and
negative sense traces need to be routed as a differential
pair close together and Kelvin (4-wire) connected underneath the sense resistor as shown in Figure 17. RSENSE
is chosen based on the maximum output current. Given
the maximum input current, I(MAX), maximum sense voltage, VSENSE(MAX), and maximum inductor ripple current,
∆IL(MAX), the value of the RSENSE can be chosen from the
following formula:
RSENSE =
VSENSE(MAX )
∆I
IMAX + L
2
IMAX depends on the required output current IOUT(MAX)
and can be calculated using:
⎛V ⎞
IMAX =I OUT(MAX ) • ⎜ OUT ⎟
⎝ VIN ⎠
KELVIN SENSE
TG
RSENSE
L
SW
VIN
BG
MASTER
LT8551
RF
ISNx
CF
ISPx
8551 F16a
FILTER COMPONENTS
CLOSE TO THE ISPx/ISNx PINS
a)
KELVIN SENSE
TG
L
SW
DCR
VIN
R1
BG
MASTER
LT8551
ISNx
C
R2 OPTIONAL
ISPx
8551 F16b
R2 AND C CLOSE TO THE ISPx/ISNx PINS
R1 CLOSE TO THE SW NODE
b)
Figure 16. Inductor Current Sense Filter
DCR Inductor Current Sensing: For applications requiring the highest possible efficiency, the LT8551 is capable
of sensing the voltage drop across the inductor DCR, as
shown in Figure 16b. The DCR of the inductor represents
the small amount of DC winding resistance, which can
be less than 1mΩ for today’s low value, high current
inductors. In high current applications requiring such an
inductor, conduction loss through a sense resistor would
cost several points of efficiency compared to DCR sensing. The inductor DCR is sensed by connecting an RC
filter across the inductor. This filter typically consists of
one or two resistors (R1 and R2) and one capacitor (C).
If the external (R1||R2)•C time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across C will be:
VSENSE =IL •DCR •
R2
R1+R2
Rev 0
24
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LT8551
APPLICATIONS INFORMATION
Therefore, R2 may be used to scale the voltage across the
sense terminals when the DCR is greater than the target
sense resistance. With the ability to program the current
limit through ILIM pin, R2 may be optional. C is usually
selected in the range of 0.01μF to 0.47μF. This forces
R1||R2 to be around kΩ range.
For DCR current sensing, the sense lines should also
run close together to a Kelvin connection underneath the
inductor as shown in Figure 17. To prevent noise from
coupling into the sensitive small-signal nodes, resistor
R1 should be placed close to the inductor, while R2 and
C are placed close to the LT8551 as shown in Figure 16b.
TO SENSE FILTER
NEXT TO ISPx/ISNx
VIN
VOUT
8551 F17
INDUCTOR OR RSENSE
Figure 17. Sense Lines Placement for DCR Sensing
or Resistor Sensing
Thermal Shutdown
If the die junction temperature reaches approximately
165°C, the LT8551 will go into thermal shutdown. All the
power switches will be turned off. For a master LT8551,
the ENOUT pin will be pulled down to ground so that it
will shut down all the switching activity of the system. The
LT8551 will be re-enabled when the die temperature has
dropped by about 5°C (nominal).
Efficiency Considerations
The percent efficiency of LT8551 is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would lead to
the most improvement. Percentage efficiency can be
expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + …)
Where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in
the circuit produce power losses, several sources usually
account for most of the losses in LT8551 circuits:
1. I2R losses. I2R losses arise from the DC resistance of
the MOSFETs, inductor and current sense resistor. It
is the majority of power losses at high input/output
current. In continuous mode, the average input current flows through the inductor and RSENSE, but is
chopped between the top and bottom MOSFETs. If the
two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the inductor’s DCR, RSENSE and the
board traces to obtain I2R losses.
2. Transition loss. This loss mostly arises from the brief
amount of the time the bottom MOSFET spends in the
saturation (Miller) region during the switching node
transitions. It depends on the output voltage, load
current, driver strength and MOSFET capacitance. The
transition can be significant at high output voltages
and low input voltage or high switching frequency.
3. REG current. This is the sum of MOSFETs driver
and REG control currents. The MOSFET driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate
is switched from low to high then to low again, a
packet of charge dQ moves from REG to ground. The
resulting dQ/dt is a current out of REG that is typically
much larger than control circuit current. In continuous mode, IGATECHG = f • [QT + QB], where QT and QB
are the gate charges of the top and bottom MOSFETs.
As mentioned in the REG LDO and VCC Power Section,
powering up the REG LDO with lower power supply
will not only improve efficiency, especially for high
input voltage application, but also alleviate the thermal stress for the LDO’s P-channel MOSFET.
4. Body diode conduction loss. During the dead time,
the loss in the top/bottom MOSFET is IL • VF, where
VF is around 0.7V. At higher switching frequency, the
dead time becomes a good percentage of switching
cycle and causes the efficiency to drop.
Other hidden losses, such as copper trace and internal battery resistances, can account for an additional efficiency
degradation in portable systems. It is very important to
include these system-level losses during the design phase.
Rev 0
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25
LT8551
APPLICATIONS INFORMATION
Circuit Board Layout Checklist
One recommended PC board design for a 9 phase system,
primary controller and two LT8551 devices, is shown in
Figure 18, the design can be expanded to more phases/
channels if needed. Use the following general checklist
to ensure the proper operation of the multiphase system:
• A multilayer PC board with dedicated ground planes
is generally preferred to reduce noise coupling and
improve heat sinking. The ground plane should be
immediately next to the routing layer for the components (i.e. MOSFETs, inductors, sense resistors, input
and output capacitors etc.)
• Keep small signal ground (SGND) and power ground
(PGND)separate. Only one connection point between
the SGND and PGND is required. It’s desirable to
return the SGND to a clean point on the PGND plane.
Do not return the small signal components grounds
to SGND through PGND. All power train components
should be referenced to PGND. Use immediate vias
to connect the power components to PGND. Several
vias are needed for each power component.
area should be minimized. However, on the other
hand, to conduct high inductor current and provide
a heat sink to the power MOSFET, the SWx nodes
PCB area cannot be too small. It’s usually preferred
to have a ground copper area placed underneath the
SWx nodes to provide additional shielding.
In addition to BSTx/SWx, the TGx and BGx are also
high dV/dt signals, which must be routed away from
the noise-sensitive traces. It is also highly recommended to use short and wide traces to route gate
driver signals in order to minimize the impedance in
gate driver paths. The TGx and SWx should be routed
together with minimum loop area to minimize the
inductance and high dV/dt noise. Likewise, the BGx
should be routed close to a PGND trace, as shown in
Figure 18. Try to route TGx, SWx, BGx traces on one
layer only.
LT8551
+
–
• The BSTx/SWx nodes’ voltage swings with a high
dV/dt rate. These nodes are rich in high frequency
noise components, and they are strong sources of
EMI noise. To minimize the coupling between these
nodes and other noise-sensitive traces, the copper
MTOP
TGx
SWx
REG
• Place power components, such as CIN, COUT, inductor and MOSFET, in one compact area. Use wide
but shortest possible traces for high current paths
(e.g. VIN, VOUT, PGND etc.) in this area to minimize
copper loss.
VOUT
BSTX
+
–
REG
MBOT
BGx
PGND
PGND PLANE
8551 F18
Figure 18. Gate Driver Routing Example
• Keep the high di/dt loop, which consists of the top
MOSFET, bottom MOSFET, and the ceramic capacitor
CH as shown in Figure 19, as short as possible to
minimize the pulsating loop inductance and absorb
switching noise.
VOUT
SW
+
COUT
CH
MTOP
L
SW
MBOT
L
MBOT
VIN
PGND
MTOP
MINIMIZE THIS
LOOP AREA
CH
VOUT
0.1µF TO 10µF X5R/X7R
CERAMIC CAPACITOR
8551 F19
PGND
a) High di/dt Loop
b) Recommended Layout Example
Figure 19. Minimize the High di/dt Loop Area in PCB Layout
Rev 0
26
For more information www.analog.com
LT8551
APPLICATIONS INFORMATION
• The decoupling capacitors for REG, VCC, VIN and the
current sense, etc. should be placed close to their
pins, use PGND for the REG decoupling capacitor
and SGND for VIN and VCC decoupling capacitors.
To minimize the connection impedance, it’s desired
to connect the decoupling capacitors directly to the
pins without using any via.
placed as close to the ISPx/ISNx pins as possible. If
the DCR sensing is used with an R/C network, the
DCR sensing resistor R1 should be close to the inductor, while R2 and C should be close to the IC. Place
the vias that connect the ISPx/ISNx lines directly at
the terminals of the current sensing resistors or the
inductors as shown in Figure 20.
• Of all the small signal traces, current sensing traces
are most sensitive to noise. The current sensing
traces should be routed differentially with minimum
spacing to minimize the chance of picking-up noise,
as shown in Figure 20. In addition, the filter resistors
and capacitors for current sensing traces should be
• When routing the interface signals between a master LT8551, primary controller, and/or slave LT8551,
keep the small-signal lines far from the noisy lines
and shield these lines with a ground plane. A recommended line arrangement is shown in Figure 21.
L
VIN
DIFFERENTIAL TRACE
LT8551
R
ISNx
L
THIS VIA SHOULD NOT
TOUCH ANY OTHER
INTERNAL VOUT
COPPER PLANE
DIFFERENTIAL TRACE R1
LT8551
ISNx
C
C
ISPx
VIN
SW
DIRECT TRACE CONNECTION
DO NOT USE VIA
THIS VIA SHOULD NOT
TOUCH ANY OTHER
INTERNAL VOUT
COPPER PLANE
R2
ISPx
DIRECT TRACE CONNECTION
DO NOT USE VIA
8551 F20
a) Resistor Sensing
b) Inductor DCR Sensing
Figure 20. Current Sensing PCB Design
PRIMARY
CONTROLLER
BST
MASTER
LT8551
TGSR
MASTER
LT8551
TGBUF
SLAVE
LT8551
TGSH
BGBUF
BGSH
SW
TGSL
CLK2
CLK2
BG
BGSH
CLK1
SYNC
SYNC
INTERFACE
TGSH
INTERFACE
TG
CLK1
MODE
MODE
SENSE+
ISP
IAMPP
IAMPP
SENSE–
ISN
IAMPN
IAMPN
INTVCC
REGSNS
RUN/ENABLE
ENOUT
REGSNS
REGSNS
ENOUT
GROUND PLANE
ENOUT
GROUND PLANE
ROUTE IN DIFFERENTIAL PAIR
8551 F21
ROUTE IN DIFFERENTIAL PAIR
ALL LINES ARE SHIELDED
BY THE GROUND PLANE
ALL LINES ARE SHIELDED
BY THE GROUND PLANE
Figure 21. Recommended Signal Lines Arrangement for PCB
Rev 0
For more information www.analog.com
27
LT8551
TYPICAL APPLICATIONS
48V/12.5A Step-Up Expander System
VBIAS
ITH
100pF
15k
FREQ
GND
LTC3769
15nF
ILIM
SS
0.1µF
OVMODE
INTVCC
10µF
1nF
1nF
47pF
10Ω
10Ω
ENOUT
CLK1
TGSR TGSH TGSL BGSH
ISP
ISN
100pF
1nF
TG1
BST1
REG
PHS1
PHS2
VCC
PHS3
SYNC
SW1
ISN1
LT8551
ISP1
BG1
RT/MS
IAMPP
PINS FOR
POWER
STAGES 2,3,4
GND
MODE
POWER STAGE 1
M5,
M6
D2
REG
0.22µF
COUT2
4.7µF
x5
+
COUT8,
COUT9
68µF
63V
10Ω
1nF
VIN
IAMPN
CLK2
TGBUF
BGBUF
VOUT
48V/12.5A*
VOUT FOLLOWS VIN
WHEN VIN > 48V
1nF
ILIM
160k
COUT6,
COUT7
68µF
63V
10nF
REG
REGSNS
SHDN
+
M3, M4
REGDRV
2.2µF
COUT1
4.7µF
×5
CIN1
4.7µF
×3
20Ω
VIN
REGIS
1Ω
CIN6
150µF
100V
BG
VIN
1µF
100V
MP
+
12.1k
M1, M2
PLLIN/MODE
47k
VIN
VIN
INTVCC
L1
10µH
7.87k
SW
RUN
13k
D1
RS1
3mΩ
0.22µF
10Ω
39k
1nF
TG
4.7µF
10nF
10Ω
SENSE+
EXTVCC
BOOST
PGOOD
INTVCC
464k
VFB
SENSE–
47k
VIN
5V TO 55V
1µF
100V
30.1k
+
RS2
3mΩ
CIN7
150µF
100V
CIN2
4.7µF
x3
POWER STAGE 2
L2
10µH
M7,
M8
8551 TA02a
POWER STAGE 3
POWER STAGE 4
D1, D2, ... : BAT46WJ
MP: ZXMP10A18G
RS1–RS5: PANASONIC ERJMB1SF3M0U
L1–L5: COILCRAFT SER2918H-103KL
CIN1–CIN5: TDK C3225X7S2A475M
COUT1–COUT5: TDK C3225X7S2A475M
COUT6–COUT15: PANASONIC EEHZC1J680P
M1, M2, M3, M4, M5, M6, M7, M8, ... : BSC100N06LS3
* WHEN VIN < 13V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
WHEN VIN > VOUT, THE CURRENT SHARING RELIES ON THE
MATCHING OF THE RDS(ON) OF THE N-CHANNEL MOSFETS.
Load Step from 0A to 12.5A, VIN = 16V, TDPN = 5
IL0
10A/DIV
IL1
10A/DIV
IL2
10A/DIV
VOUT
AC COUPLED
500mV/DIV
400µs/DIV
8551 TA02b
Rev 0
28
For more information www.analog.com
LT8551
TYPICAL APPLICATIONS
24V/25A Step-Up Expander System
ITH
VBIAS
100pF
5.1k
FREQ
GND
15nF
ILIM
SS
10nF
LTC3769
PGOOD
INTVCC
OVMODE
INTVCC
D1
MP
2.2µF
1nF
100pF
COUT1
4.7µF
×4
CIN1
4.7µF
×3
1nF
47pF
ENOUT
CLK1
10Ω
TGSR TGSH TGSL BGSH
ISP
ISN
1nF
TG1
BST1
SW1
ISN1
LT8551
ISP1
BG1
PINS FOR
POWER
STAGES 2,3,4
GND
MODE
POWER STAGE 1
M2
D2
REG
0.22µF
COUT2
4.7µF
x4
+
COUT7
100µF
35V
10Ω
1nF
VIN
RT/MS
IAMPP
IAMPN
CLK2
TGBUF
BGBUF
VOUT
24V/25A*
VOUT FOLLOWS VIN
WHEN VIN > 24V
1nF
10Ω
REG
PHS1
PHS2
VCC
PHS3
SYNC
COUT6
100µF
35V
10nF
REG
REGSNS
SHDN
+
20Ω
ILIM
75k
330kHz
CIN6
270µF
35V
12.1k
M6
PLLIN/MODE
REGDRV
1Ω
+
L1
3.3µH
M1
VIN
REGIS
1µF
VIN
INTVCC
RS1
3mΩ
BG
RUN
VIN
10µF
1nF
SW
47k
VIN
10Ω
0.22µF
10Ω
13k
VIN
5V TO 24V
TG
4.7µF
39k
1µF
232k
VFB
SENSE–
SENSE+
EXTVCC
BOOST
47k
10nF
30.1k
+
RS2
3mΩ
CIN7
270µF
35V
CIN2
4.7µF
x3
POWER STAGE 2
L2
3.3µH
M7
8551 TA03a
POWER STAGE 3
POWER STAGE 4
D1, D2, ... : BAS140W
MP: ZXMP10A18G
RS1–RS5: PANASONIC ERJMB1SF3M0U
L1–L5: PULSE PA1494.362NL
CIN1–CIN5: TDK C2012X7R1V475K125AC
CIN6–CIN10: PANASONIC EEHC1V271P
COUT1–COUT5: TDK C2012X7R1V475K125AC
COUT6–COUT10: PANASONIC EEHZK1V101P
M1–M5: RENESAS RJK0453
M6–M10: RENESAS RJK0452
* WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
WHEN VIN > VOUT, THE CURRENT SHARING RELIES ON THE
MATCHING OF THE RDS(ON) OF THE N-CHANNEL MOSFETS.
Load Step from 10A to 25A, VIN = 18V, TDPN = 5
IL0
5A/DIV
IL1
5A/DIV
IL2
5A/DIV
VOUT
AC COUPLED
500mV/DIV
400µs/DIV
8551 TA03b
Rev 0
For more information www.analog.com
29
LT8551
TYPICAL APPLICATIONS
48V Step-Up Expander System
ITH
22pF
2k
ILIM
SS
0.1µF
LTC3769
INTVCC
0.22µF
RUN
M3, M4
10nF
10Ω
10Ω
1nF
+
5.8V
REGSNS
SHDN
ENOUT
CLK1
TGSR TGSH TGSL BGSH
ISP
ISN
VIN
REGIS
1µF
1Ω
2.2µF
1nF
REG
PHS1
PHS2
VCC
PHS3
SYNC
1nF
BST1
SW1
ISN1
LT8551
ISP1
100pF
IAMPN
CLK2
TGBUF
BGBUF
D1–D5: BAS170W
MP1: ZXMP10A18G
RS1–RS5: PANASONIC ERJ-MP4QF4M0U
L1–L5: COILCRAFT SER2918H-103KL
CIN1–CIN5: MURATA GRM32ER71H106KA12A
CIN6–CIN10: KRM55WR71H226MH01K
COUT1–COUT5: TDK C3225X7S2A475M200AB
COUT6–COUT15: KRM55WR72A156MH01K
M1–M20: BSC100N06LS3
M5,
M6
D2
REG
0.22µF
1nF
RS2
4mΩ
VIN
CIN7
22µF
GND
MODE
100µF
100V
COUT2
4.7µF
COUT8,
COUT9
15µF
100V
L2
10µH
CIN2
10µF
M7,
M8
BG1
PINS FOR
POWER
STAGES 2,3,4
+
10Ω
ILIM
RT/MS
IAMPP
100µF
100V
POWER STAGE 1
TG1
REGDRV
MP
REG
71.5k
350kHz
VOUT
48V
7.5A AT 6VIN
15A AT 12VIN
30A AT 24VIN
45A AT 36VIN
20Ω
1nF
47k
46.4k
COUT6,
COUT7
15µF
100V
COUT1
4.7µF
L1
10µH
M1, M2
47k
REG
10µF
CIN1
10µF
BG
PLLIN/MODE
10nF
1N4448HWT
VIN
CIN6
22µF
SW
10Ω
13k
INTVCC
TG
4.7µF
10nF
RS1
4mΩ
VIN
D1
7.87k
12.1k
1nF
BOOST
OVMODE
INTVCC
VIN
6V TO 46V
1000µF
50V
10Ω
EXTVCC
47k
1000µF
50V
+
464k
VFB
SENSE–
SENSE+
PGOOD
+
1µF
50V
FREQ
GND
0.12µF
VIN
10Ω
VBIAS
POWER STAGE 2
8551 TA04
POWER STAGE 3
POWER STAGE 4
LT8551 PINS NOT SHOWN
IN THIS CIRCUIT:
BST2, BST3, BST4
TG2, TG3, TG4,
SW2, SW3, SW4,
BG2, BG3, BG4,
ISP2, ISP3, ISP4,
ISN2, ISN3, ISN4
Rev 0
30
For more information www.analog.com
LT8551
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF 7.10 ±0.05 8.50 ±0.05
(2 SIDES)
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.00 – 0.05
R = 0.115
TYP
5.50 REF
(2 SIDES)
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
6.45 ±0.10
5.41 ±0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 ±0.05
(UKG52) QFN REV Ø 0306
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Rev 0
For more information www.analog.com
31
LT8551
TYPICAL APPLICATION
48V/12.5A Step-Up Expander System
ITH
100pF
15k
15nF
VIN
1µF
100V
ILIM
SS
10nF
VBIAS
47k
INTVCC
D1
VIN
INTVCC
+
0.22µF
CIN1
4.7µF
×3
CIN6
150µF
100V
1µF
100V
RUN
10nF
47k
VIN REGSNS ENOUT
10µF
47pF
1nF
10nF
2.2µF
1nF
REG
PHS1
PHS2
VCC
PHS3
SYNC
10Ω
CLK1
TGSR TGSH TGSL BGSH
ISP
100pF
TG1
LT8551 PINS NOT SHOWN
IN THIS CIRCUIT:
BST2, BST3, BST4
TG2, TG3, TG4,
SW2, SW3, SW4,
BG2, BG3, BG4,
ISP2, ISP3, ISP4,
ISN2, ISN3, ISN4
1nF
ISP1
VIN
GND
MODE
PINS FOR
POWER
STAGES 2,3,4
POWER STAGE 1
+ CCOUT8,
OUT9
68µF
63V
COUT2
4.7µF
x5
10Ω
ISN1
BG1
REG
0.22µF
SW1
LT8551
M2
D2
BST1
RT/MS
IAMPP
IAMPN
CLK2
TGBUF
BGBUF
1nF
ISN
ILIM
160k
VOUT
48V/12.5A
VOUT FOLLOWS VIN
WHEN VIN > 48V
1nF
REGDRV
1Ω
COUT6,
COUT7
68µF
63V
M6
20Ω
SHDN
REGIS
MP
+
M1
PLLIN/MODE BG
REG
39k
13k
COUT1
4.7µF
×5
L1
10µH
10Ω
VIN
5V TO
55V
12.1k
RS1
3mΩ
SW
10Ω
4.7µF
1nF
TG
FREQ
GND
PGOOD
OVMODE INTVCC
7.87k
10Ω
SENSE+
EXTVCC
BOOST
LTC3769
30.1k
464k
VFB
SENSE–
+
RS2
3mΩ
CIN7
150µF
100V
CIN2
4.7µF
x3
L2
10µH
M7
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
8551 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
LTC3786
38V Low IQ Synchronous Boost Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to 900kHz Fixed
Operating Frequency, 3mm×3mm QFN-32, MSOP-16E
COMMENTS
LTC3769
60V Low IQ Synchronous Boost Controller 4.5V (Down to 2.3V After Start-up) ≤ VIN≤ 60V, VOUT up to 60V, 50kHz to 900kHz Fixed
Operating Frequency, 4mm×4mm QFN-24, TSSOP-20
LT8550
4-Phase Buck DC/DC Expander
VIN up to 80V, 18 Distinct Phases, 125KHz to 1MHz, Supports Bidirectional Current Flow,
7mm×8mm QFN-52
Rev 0
32
06/19
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