LT8652S
Dual Channel 8.5A, 18V,
Synchronous Step-Down Silent Switcher
with 16µA Quiescent Current
DESCRIPTION
FEATURES
Silent Switcher®2 Architecture:
n Ultralow EMI on Any PCB
n Eliminates PCB Layout Sensitivity
n Internal Bypass Capacitors Reduce Radiated EMI
n Spread Spectrum Frequency Modulation
n 8.5A DC from Each Channel Simultaneously
n Up to 12A on Either Channel
n Ultralow Quiescent Current Burst Mode® Operation:
n 16µA I Regulating 12V to 3.3V
Q
IN
OUT (Both Channels)
n Output Ripple 0.6V, VVC1 = VVC2 = VCC, VSYNC = 0V
VIN1 Quiescent Current in Sleep with
External Compensation
VEN = 2V, VFB1 = VFB2 > 0.6V, VVC1 = VVC2 = FLOAT, VSYNC = 0V
VIN Current in Regulation
VIN = 6, VOUT = 0.6, Output Load = 50mA, VSYNC = 0V
MAX
2.6
3.0
V
6
15
µA
16
30
100
µA
µA
210
260
300
µA
µA
7
10
mA
600
600
604
607.2
mV
mV
0.004
0.02
%/V
l
l
Feedback Reference Voltage
l
Feedback Voltage Line Regulation
TYP
VIN = 3.0V to 18V
596
592.8
l
Feedback Pin Input Current
VFB = 0.6V
Minimum On-Time
ILOAD = 4A, SYNC = FLOAT
l
–20
Oscillator Frequency
RT = 143k
RT = 60.4k
RT = 20k
l
l
l
Top Power NMOS Current Limit
l
Bottom Power NMOS Current Limit
20
nA
20
45
ns
255
660
1.85
300
700
2.00
345
740
2.15
22
26.5
32
A
12.5
16.5
20.5
A
24
Top Power NMOS RDS(ON)
VIN = 18V, VSW = 0V,18V
EN/UV Pin Threshold
EN/UV Falling
–15
l
0.76
EN/UV Pin Hysteresis
mΩ
15
0.8
0.84
20
EN/UV Pin Current
VEN/UV = 2V
PG Upper Threshold Offset from VFB
PG Lower Threshold Offset from VFB
–20
VFB Rising
l
3
VFB Falling
l
–3
PG Hysteresis
VPG = 3.3V
PG Pull-Down Resistance
VPG = 0.1V
SYNC Threshold
SYNC DC and Clock Low Level Voltage
SYNC DC High Level Voltage
SYNC Clock High Level Voltage
SYNC Pin Current
VSYNC = 6V
nA
6.5
11
%
–7
–11
%
40
nA
1300
Ω
2.8
1.5
V
V
V
630
0.4
%
60
TR/SS Source Current
l
1.0
V
20
–40
l
µA
mV
0.5
PG Leakage
kHz
kHz
MHz
mΩ
8
Bottom Power NMOS RDS(ON)
SW Leakage Current
UNITS
2.0
µA
3.0
µA
TR/SS Pull-Down Resistance
Fault Condition, TR/SS = 0.1V
200
Ω
Error Amplifier Transconductance
VC = 1.2V
1.4
mS
VC Source Current
VFB = 0.4V, VVC = 1.2V
200
µA
VC Sink Current
VFB = 0.8V, VVC = 1.2V
225
µA
15
A/V
250
1250
mV
mV
VC Pin to Switch Current Gain
TEMP Output Voltage
ITEMP = 0µA, Temperature = 25°C
ITEMP = 0µA, Temperature = 125°C
IMON Current
ISW = 2A, 12% Duty Cycle
ISW = 6A, 12% Duty Cycle
MON Pin Limit Regulation Voltage
l
27
77
30
82
33
87
µA
µA
l
0.95
1.00
1.05
V
Rev. B
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3
LT8652S
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8652SE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8652SI is guaranteed over the full –40°C to 125°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C. The junction temperature (TJ, in °C) is calculated from the
ambient temperature (TA, in °C) and power dissipation (PD, in watts)
according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
TYPICAL PERFORMANCE CHARACTERISTICS
12VIN to 1.0VOUT Efficiency
L = XEL4030
95 BIAS = 5V
90 FCM
EFFICIENCY (%)
4.5
85
4.0
80
75
3.5
70
3.0
65
2.5
60
2.0
55
1.5
55
1.0
50
45
0.5
45
40
0
40
POWER LOSS
50
0
2
4
6
8
LOAD CURRENT (A)
10
12
6.0
1MHz, L = 0.47µH
1.5MHz, L = 0.3µH 5.5
2MHz, L = 0.2µH
5.0
L = XEL4030
95 FCM
90
POWER LOSS (W)
EFFICIENCY
5.0VIN to 1.0VOUT Efficiency
4.5
4.0
EFFICIENCY
75
3.5
70
3.0
65
2.5
60
2.0
1.5
POWER LOSS
1.0
0.5
0
2
4
6
8
LOAD CURRENT (A)
10
8652S G01
100
L = XEL4030
95 BIAS = 5V
90 FCM
L = XEL4030–301ME, 0.3µH
90 BIAS = 5V
6.0
1MHz, L = 0.47µH
1.5MHz, L = 0.3µH 5.5
2MHz, L = 0.2µH
5.0
4.5
85
EFFICIENCY (%)
70
60
50
40
30
80
75
3.5
70
3.0
65
2.5
60
2.0
55
20
5VIN
12VIN
1
10
100
1k
LOAD CURRENT (mA)
10k
4.0
EFFICIENCY
1.5
POWER LOSS
50
1.0
0.5
45
40
POWER LOSS (W)
EFFICIENCY (%)
80
0
8652S G03
4
0
12.0VIN to 1.2VOUT Efficiency
100
0
12
8652S G02
1.0VOUT Efficiency—Burst Mode
Operation
10
POWER LOSS (W)
100
1MHz, L = 0.47µH
1.5MHz, L = 0.3µH 5.5
2MHz, L = 0.2µH
5.0
85
80
6.0
EFFICIENCY (%)
100
TA = 25°C, unless otherwise noted.
2
4
6
8
LOAD CURRENT (A)
10
12
0
8652S G04
Rev. B
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LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
5.0VIN to 1.2VOUT Efficiency
EFFICIENCY (%)
75
3.5
70
3.0
65
2.5
60
2.0
1.5
POWER LOSS
50
40
0
2
4
6
8
LOAD CURRENT (A)
10
12
0
3.5
3.0
80
2.5
75
60
2.0
POWER LOSS
0
2
1.5
1MHz, L = 1.2µH 1.0
1.5MHz, L = 1µH 0.5
2MHz, L = 0.6µH
0
4
6
8
10
12
LOAD CURRENT (A)
8652S G05
Efficiency at Different fSW
100
12VIN TO 1VOUT
BIAS = 5V
L = XEL4030
95
85
80
75
2.5MHz, 0.3µH
2MHz, 0.3µH
1.5MHz, 0.3µH
1MHz, 0.3µH
0.5MHz, 0.64µH
70
65
0
2
4
6
8
LOAD CURRENT (A)
10
80
75
70
60
0.5
1
1.5
2
SWITCHING FREQUENCY (MHZ)
0.00
–0.05
–0.10
CH1
CH2
–0.20
–0.25
0
2
4
6
8
OUTPUT CURRENT (A)
10
0.20
IOUT = 3A
24
BIAS = 5V
20
0.10
0.00
–0.10
–0.20
8652S G10
5
35
65
95
TEMPERATURE (°C)
125
–0.50
2
4
6
8
10 12 14
INPUT VOLTAGE (V)
16
18
LT8652 G11
155
No Load Supply Current with
Internal Compensation
VIN1 = VIN2
VOUT1 = 3.3V, VOUT2 = 1.0V
IN REGULATION
SYNC = 0V
16
12
8
4
CH1
CH2
–0.40
12
–25
8652S G09
28
–0.30
–0.15
0.594
–55
INPUT CURRENT (µA)
0.05
2.5
VIN1 = VIN2
0.30
0.10
0.598
Line Regulation
0.40
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
0.50
VIN1 = VIN2 = 12V
VOUT1 = VOUT2 = 1V
FCM, fSW = 1.5MHz
0.15
0.600
8652S G08
Load Regulation
0.20
0.602
0.596
65
12
Reference Voltage
0.604
85
8652S G07
0.25
0.606
12VIN TO 1VOUT
4A LOAD
BIAS = 5V
L = XEL4030-301ME
90
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs fSW
95
90
60
8652S G06
REFERENCE VOLTAGE (V)
100
5.0
4.0
65
0.5
5.5
4.5
85
70
1.0
45
EFFICIENCY
6.0
POWER LOSS (W)
4.0
L = XEL5030
BIAS = VOUT
FCM
90
POWER LOSS (W)
80
12.0VIN to 3.3VOUT Efficiency
95
4.5
EFFICIENCY
55
100
1MHz, L = 0.47µH
1.5MHz, L = 0.3µH 5.5
2MHz, L = 0.2µH 5.0
L = XEL4030
95 FCM
90
85
6.0
EFFICIENCY (%)
100
TA = 25°C, unless otherwise noted.
0
BIAS = FLOAT
BIAS = VOUT1
6
8
10
12
14
INPUT VOLTAGE (V)
16
18
8652S G12
Rev. B
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5
LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
BIAS = FLOAT
BIAS = VOUT1
450
400
VIN1 = VIN2
VOUT1 = 3.3V, VOUT2 = 1.0V
IN REGULATION
SYNC = 0V
6
8
10
12
14
INPUT VOLTAGE (V)
350
30
28
300
250
200
EXTERNAL COMPENSATION
INTERNAL COMPENSATION
150
100
16
24
22
20
18
14
0
–55
18
26
16
50
–25
5
35
65
95
TEMPERATURE (°C)
125
12
155
19
36
28
18
32
26
17
30% DC
CURRENT LIMIT (A)
20
18
SWITCH RESISTANCE (mΩ)
40
22
16
15
14
13
20
16
12
12
11
4
12
–55
10
–55
0
–55
125
155
–25
5
35
65
95
TEMPERATURE (°C)
8652S G16
155
74
MINIMUM OFF-TIME (ns)
30
20
10
FCM, 1A LOAD
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8652S G19
6
5
35
65
95
TEMPERATURE (°C)
72
70
68
66
64
62
60
56
–55
125
155
fSW = 2MHz
VOUT = 3.4V
1200
1000
FCM
800
600
400
BURST
200
58
0
–55
–25
Dropout Voltage
1400
DROPOUT VOLTAGE (mV)
FCM, 4A LOAD
40
BOTTOM FET
TOP FET
LT8652 G18
Minimum Off-Time
76
50
MINIMUM ON-TIME (ns)
125
8
8652S G17
Minimum On-Time
60
1
24
14
5
35
65
95
TEMPERATURE (°C)
0.8
28
16
–25
0.4
0.6
DUTY CYCLE
Switch Resistance
Bottom FET Current Limit
24
0.2
8652S G14
20
30
0
8652S G13
Top FET Current Limit
CURRENT LIMIT (A)
32
VIN1 = VIN2 = 12V
VOUT1 = 3.3V, VOUT2 = 1.0V
VBIAS = VOUT1
SYNC = 0V
BOTH CHANNELS IN REGULATION
8652S G13
32
Top FET Current Limit
No Load Supply Current
500
CURRENT LIMIT (A)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
INPUT CURRENT (µA)
INPUT CURRENT (µA)
No Load Supply Current with
External Compensation
TA = 25°C, unless otherwise noted.
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8652S G20
0
0
1
2
3
4 5 6 7 8 9 10 11 12
LOAD CURRENT (A)
LT8652 G21
Rev. B
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LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
RT = 41.2kΩ
VIN1 = 12V
VOUT = 1V
SYNC = 0V
RT = 20kΩ
L = 0.2µH
2.25
1.10
1.05
1.00
0.95
0.90
0.85
2.00
1.75
0.6
FB VOLTAGE (V)
1.15
0.8
1.50
1.25
1.00
0.75
–25
5
35
65
95
TEMPERATURE (°C)
125
0
155
0
1
2
3
LOAD CURRENT (A)
8652S G22
1.9
0.81
0.80
0.79
1.8
0.78
1.7
0.77
1.6
–55
0.76
–55
5
35
65
95
TEMPERATURE (°C)
125
155
PG Low Thresholds
EN RISING
EN FALLING
–25
5
35
65
95
TEMPERATURE (°C)
155
6.5
6.0
5.5
5.0
–7.0
–7.5
–8.0
5
35
65
95
TEMPERATURE (°C)
125
155
SS1 = SS2 = 0V, FCM
2.6
2.4
1.10
0.80
0.50
0.20
–0.10
–0.40
FB RISING
FB FALLING
125
–25
1.40
2.2
5
35
65
95
TEMPERATURE (°C)
FB RISING
FB FALLING
4.5
Temperature Monitor Pin
TEMP PIN VOLTAGE (V)
INPUT VOLTAGE (V)
–6.5
–25
7.0
1.70
2.8
–8.5
7.5
8652S G27
VIN1 = VIN2
–4.5
–9.0
–55
125
8.0
Minimum Input Voltage
–5.0
1.2
8.5
4.0
–55
3.0
–6.0
1.0
8652S G26
–4.0
–5.5
0.4
0.6
0.8
SS VOLTAGE (V)
PG High Thresholds
0.82
EN THRESHOLD (V)
SS PIN CURRENT (µA)
2.2
2.0
0.2
9.0
0.83
2.1
0
8652S G24
EN Pin Thresholds
VSS = 0.4V
–25
0
5
0.84
8652S G25
PG THRESHOLD OFFSET FROM VREF (%)
4
8652S G23
Soft-Start Current
2.3
EXTERNAL COMPENSATION
INTERNAL COMPENSATION
0.25
0.80
–55
2.4
0.4
0.2
0.50
PG THRESHOLD OFFSET FROM VREF (%)
SWITCHING FREQUENCY (MHz)
1.20
Soft-Start Tracking
Burst Frequency
2.50
SWITCHING FREQUENCY (MHz)
1.25
TA = 25°C, unless otherwise noted.
155
8652S G28
2.0
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8652S G29
–0.70
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
8652S G30
BELOW 5°C: 100kΩ RESISTOR FROM TEMP TO –4V
ABOVE 5°C: FLOAT TEMP
Rev. B
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7
LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Bias Pin Current
21.0
VBIAS = 5V
ILOAD = 3A EACH CHANNEL
fSW = 1MHz
20.0
19.5
19.0
18.5
18.0
VBIAS = 5V
ILOAD = 3A EACH CHANNEL
VIN = 8V
50
BIAS PIN CURRENT (mA)
20.5
BIAS PIN CURRENT (mA)
Bias Pin Current
60
40
30
20
10
6
8
10
12
14
INPUT VOLTAGE (V)
16
18
0
0
0.5
1
1.5
2
2.5
3
SWITCHING FREQUENCY (MHZ)
LT8652 G31
LT8652 G32
LT8652S Transient Response
Internal Compensation
LT8652S Transient Response
Internal Compensation
ILOAD
5A/DIV
ILOAD
5A/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
20µs/DIV
8652S G33
20µs/DIV
6A TO 12A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
500mA TO 6A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
LT8652S Transient Response
External Compensation
LT8652S Transient Response
External Compensation
ILOAD
5A/DIV
8652S G34
ILOAD
5A/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
20µs/DIV
8652S G35
6A TO 12A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
CC = 220pF, RC = 17.1kΩ
8
3.5
20µs/DIV
8652S G36
500mA TO 6A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
CC = 220pF, RC = 17.1kΩ
Rev. B
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LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Forced Continuous Mode (FCM)
IL
2A/DIV
Burst Mode Operation
IL
2A/DIV
VSW
5V/DIV
VSW
5V/DIV
2µs/DIV
8652S G37
2µs/DIV
12VIN TO 1VOUT AT 250mA
SYNC = FLOAT
fSW = 1.5MHz
8652S G38
12VIN TO 1VOUT AT 250mA
SYNC = 0V
CH1, CH2 and CLKOUT
Two-Phase Operation
Switch Rising Edge
VSW1
10V/DIV
VSW2
10V/DIV
CLKOUT
5V/DIV
VSW
2V/DIV
200ns/DIV
LT8652 G39
2ns/DIV
8652S G40
12VIN TO 1VOUT AT 12A
SYNC = FLOAT
fSW = 2MHz
VIN = 12V
IOUT = 6A
Start-Up Dropout Performance
Forced Continuous Mode
Start-Up Dropout Performance
Burst Mode Operation
VIN
1V/DIV
VIN
1V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
100ms/DIV
LT8652 G41
1Ω LOAD
(3.2A IN REGULATION)
100ms/DIV
LT8652 G42
1Ω LOAD
(3.2A IN REGULATION)
Rev. B
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9
LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
Case Temperature Rise
Single Channel
Case Temperature Rise
Single Channel
100
DC2523A DEMO BOARD
VOUT1 = VOUT2 = 1V
100 fSW = 1.5MHz
12VIN, LOAD2 = 0A
12VIN, LOAD2 = LOAD1
80
12VIN, LOAD2 = 8.5A
5VIN, LOAD2 = LOAD1
60
1.20
CH1 = 1A STANDBY, 12A PULSED
CH2 = 0A DC
CH1 = 1A STANDBY, 12A PULSED
CH2 = 8.5A DC
90
40
20
80
70
0.80
60
50
40
1
2
3
DC2523A DEMO BOARD
VIN1 = VIN2 = 12V
fSW = 1.5MHz
VOUT1 = VOUT2 = 1V
20
0
4 5 6 7 8 9 10 11 12
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
DUTY CYCLE OF 12A LOAD ()
8652S G43
160
5.0
IIMON ERROR (%)
IIMON (µA)
80
60
40
FCM
Burst Mode OPERATION
0
1
2
IIMON Error
90
12VIN TO 1VOUT
4.0 fSW = 2MHz
L = XEL4030-301MEB
3.0
120
0
3 4 5 6 7 8 9 10 11 12
OUTPUT CURRENT (A)
2.0
84
1.0
82
0
–1.0
1
2
3
76
74
–25
8
9
10
8652S G45
IIMON vs Other Channel Load
5
35
65
95
TEMPERATURE (°C)
125
CH1 AT 6A (VARY IOUT2)
CH2 AT 6A (VARY IOUT1)
72
IOUT = 6A
–5.0
–55
7
78
–3.0
–4.0
4 5 6
IOUT1 (A)
80
–2.0
155
70
0
1
2
3
4
5
6
7
8
OUTPUT CURRENT ON OTHER CHANNEL (A)
8652S G47
8652S G48
RT Programmed Switching
Frequency
IIMON Current Limit
160
12VIN TO 1VOUT
fSW = 2MHz
L = XEL4030-301MEB
8.8
RLOAD = 10mΩ, RIMON = 9.53k
140
RT PIN RESISTOR (kΩ)
IOUT (A)
0
12VIN TO 1VOUT
88 fSW = 2MHz
L = XEL4030-201MEB
86
8652S G46
9.0
0
1
IIMON (µA)
12VIN TO 1VOUT
140 fSW = 2MHz
L = XEL4030-201MEB
100
RIMON = 9.6kΩ
12VIN TO 1VOUT
FCM, fSW = 2MHz
L = XEL4030-301MEB
0.20
8652S G44
IIMON vs IO,
FCM and Burst Mode Operation
20
0.60
0.40
30
10
0
IIMON Current Limit
1.00
VOUT1 (V)
CASE TEMPERATURE RISE (°C)
CASE TEMPERATURE RISE (°C)
120
0
TA = 25°C, unless otherwise noted.
8.6
8.4
8.2
120
100
80
60
40
20
8.0
–55
–25
5
35
65
95
TEMPERATURE (°C)
125
155
0
0
8652S G49
10
0.5
1
1.5
2
2.5
SWITCHING FREQUENCY (MHz)
3
LT8652 G50
Rev. B
For more information www.analog.com
LT8652S
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Conducted EMI Performance
60
AMPLITUDE (dBµV/m)
50
40
30
20
10
0
FIXED FREQUENCY
SPREAD SPECTRUM MODE
–10
–20
0
3
6
9
12
15
18
FREQUENCY (MHz)
21
24
27
30
8652S G51
DC2523A DEMO BOARD
(WITH EMI FILTER INSTALLED)
14V INPUT TO 3.3V OUTPUT1 AT 8.5A AND 1.2V OUTPUT2 AT 8.5A, fSW = 2MHz
Radiated EMI Performance
(CISPR25 Radiated Emission Test with Class 5 Peak Limits)
60
AMPLITUDE (dBµV/m)
50
40
30
20
10
0
CLASS 5 PEAK LIMIT
SPREAD SPECTRUM MODE
FIXED FREQUENCY
–10
–20
0
100
200
300
400
500
600
FREQUENCY (MHz)
700
800
900
1000
8652S G52
DC2523A DEMO BOARD
(WITH EMI FILTER INSTALLED)
14V INPUT TO 3.3V OUTPUT1 AT 8.5A AND 1.2V OUTPUT2 AT 8.5A, fSW = 2MHz
Radiated EMI Performance
(CISPR22 Radiated Emission Test with Class B Peak Limits)
60
AMPLITUDE (dBµV/m)
50
40
30
20
10
0
CLASS B PEAK LIMIT
SPREAD SPECTRUM MODE
FIXED FREQUENCY
–10
–20
0
100
200
300
400
500
600
700
800
900 1000
FREQUENCY (MHz)
8652S G53
DC2523A DEMO BOARD
(WITH EMI FILTER INSTALLED)
14V INPUT TO 3.3V OUTPUT1 AT 8.5A AND 1.2V OUTPUT2 AT 8.5A, fSW = 2MHz
For more information www.analog.com
Rev. B
11
LT8652S
PIN FUNCTIONS
IMON2 (Pin 1): Channel 2 Average Output Current Monitor
Pin. A current proportional to the average output current
flows out of this pin. An error amplifier compares the voltage on this pin to 1.0V (typical) and regulates the average
current as required based on the external resistor value
from this pin to GND. Selecting the external resistor value
allows the user to control the maximum average output
current such that:
VIN2 (Pin 9, 10, 11): The VIN2 pins supply current to the
internal top side power switch of Channel 2. These pins
must be locally bypassed. Be sure to place the positive
terminal of the input capacitor as close as possible to the
VIN2 pins and the negative capacitor terminal as close as
possible to the GND pins. This input is capable of operating from a different supply than VIN1. VIN1 must be present to run channel 2.
RIMON = 78,000/ILIM
EN/UV (Pin 13): The LT8652S is shutdown when this
pin is low and active when this pin is high. The hysteretic threshold voltage is 0.82V going up and 0.80V going
down. Tie to VIN1 if shutdown feature is not used. An
external resistor divider from VIN1 can be used to program
a VIN threshold below which Channel 1 and Channel 2 of
the LT8652S will shut down. Do not float this pin. For
individual channel shutdown, pull that channel’s soft start
pin to GND.
If IMON2 pin functionality is not desired, tie this pin to
GND. See the Applications Information section for more
details.
SS2 (Pin 2): Channel 2 Output Tracking and Soft-Start
Pin. This pin allows user control of output voltage ramp
rate during start-up. A SS2 voltage below 0.6V forces
the LT8652S to regulate the FB2 pin to equal the SS2 pin
voltage. When SS2 is above 0.6V, the internal reference
resumes control of the error amplifier. An internal 2μA
pull-up current from VCC on this pin allows a capacitor
to program output voltage slew rate. This pin is pulled
to ground with a 200Ω MOSFET during shutdown and
fault conditions; use a series resistor if driving from a
low impedance output. This pin may be left floating if the
soft-start feature is not being used.
RT (Pin 3): A resistor is tied between RT and ground to
set the switching frequency.
VIN1 (Pins 5, 6, 7): The VIN1 pins supply current to the
LT8652S internal circuitry and to the internal top side
power switch of Channel 1. These pins must be locally
bypassed. Be sure to place the positive terminal of the
input capacitor as close as possible to the VIN1 pins and
the negative capacitor terminal as close as possible to the
GND pins. VIN1 must be greater than 3V for the LT8652S
to operate.
NC (Pin 8): No Connect. This pin is not connected to
internal circuitry. It is recommended that this be left floating or tied to GND.
12
TEMP (Pin 14): Temperature Output Pin. This pin outputs
a voltage proportional to junction temperature. The pin is
250mV for 25°C and has a slope of 11mV/°C. The output
of this pin is not valid during light output loads on both
channels while in Burst Mode operation. Put the LT8652S
in forced continuous mode for the TEMP output to be valid
across the entire output load range. See the Applications
Information section for more information.
PG2 (Pin 15): The PG2 pin is the open-drain output of an
internal comparator. PG2 remains low until the FB2 pin is
within ±7% of the final regulation voltage and there are no
fault conditions. PG2 is pulled low during VIN1 UVLO, VCC
UVLO, Thermal Shutdown or when the EN/UV pin is low.
PG1 (Pin 16): The PG1 pin is the open-drain output of an
internal comparator. PG1 remains low until the FB1 pin is
within ±7% of the final regulation voltage and there are no
fault conditions. PG1 is pulled low during VIN1 UVLO, VCC
UVLO, Thermal Shutdown or when the EN/UV pin is low.
Rev. B
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LT8652S
PIN FUNCTIONS
SYNC (Pin 17): External Clock Synchronization Input.
Ground this pin for low ripple Burst Mode operation at
low output loads. Apply a DC voltage of 2.8V or higher or
tie to VCC for forced continuous mode with spread spectrum modulation. Float the SYNC pin for forced continuous mode without spread spectrum modulation. When in
forced continuous mode, the IQ will increase to several
mA. Apply a clock source to the SYNC pin for synchronization to an external frequency. The LT8652S will be in
forced continuous mode when an external frequency is
applied.
CLKOUT (Pin 18): In forced continuous mode, the
CLKOUT pin provides a 50% duty cycle square wave 90
degrees out of phase with Channel 1. This allows synchronization with other regulators with up to four phases.
When an external clock is applied to the SYNC pin, the
CLKOUT pin will output a waveform with the same phase,
duty cycle and frequency as the SYNC waveform. In Burst
Mode operation, the CLKOUT pin will be grounded. Float
this pin if the CLKOUT function is not used.
BST2 (Pin 19): This pin is used to provide a drive voltage, higher than the input voltage, to the top side power
switch of Channel 2.
SW2 (Pins 20, 21, 22): The SW2 pins are the output
of the Channel 2 internal power switches. Tie these pins
together and connect them to the inductor. This node
should be kept small on the PCB for good performance.
SW1 (Pins 23, 24, 25): The SW1 pins are the output
of the Channel 1 internal power switches. Tie these pins
together and connect them to the inductor. This node
should be kept small on the PCB for good performance.
BST1 (Pin 26): This pin is used to provide a drive voltage,
higher than the input voltage, to the top side power switch
of Channel 1.
BIAS (Pin 27): The internal regulator will draw current
from BIAS instead of VIN1 when BIAS is tied to a voltage
higher than 3.1V. For output voltages of 3.3V and above,
this pin should be tied to VOUT. If this pin is tied to a supply other than VOUT, use a 1µF local bypass capacitor on
this pin. This pin should be grounded if the BIAS feature
is not being used.
VCC (Pin 28): Internal Regulator Bypass Pin. The internal power drivers and control circuits are powered from
this voltage. VCC current will be supplied from BIAS if
VBIAS > 3.1V, otherwise current will be drawn from VIN1.
Voltage on VCC will vary between 2.8V and 3.3V when
VBIAS is between 3.0V and 3.5V. Decouple this pin to
ground with at least a 1μF low ESR ceramic capacitor. Do
not load the VCC pin with external circuitry.
SS1 (Pin 29): Channel 1 Output Tracking and Soft-Start
Pin. This pin allows user control of output voltage ramp
rate during start-up. A SS1 voltage below 0.6V forces
the LT8652S to regulate the FB1 pin to equal the SS1 pin
voltage. When SS1 is above 0.6V, the tracking function
is disabled and the internal reference resumes control of
the error amplifier. An internal 2μA pull-up current from
VCC on this pin allows a capacitor to program output voltage slew rate. This pin is pulled to ground with a 200Ω
MOSFET during shutdown and fault conditions; use a
series resistor if driving from a low impedance output.
This pin may be left floating if the soft-start feature is not
being used.
IMON1 (Pin 30): Channel 1 Average Output Current
Monitor Pin. A current proportional to the average output
current flows out of this pin. An error amplifier compares
the voltage on this pin to 1.0V (typical) and regulates the
average current as required based on the external resistor
value from this pin to GND. Selecting the external resistor
value allows the user to control the maximum average
output current such that:
RIMON = 78,000/ILIM
If IMON1 pin functionality is not desired, tie this pin
to GND. See the Applications Information section for
more details.
Rev. B
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13
LT8652S
PIN FUNCTIONS
VC1 (Pin 31): Channel 1 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. Connect this pin to
VCC to use the default internal compensation. If internal
compensation is used, the Burst Mode quiescent current
is only 12.8µA for Channel 1. If external compensation is
used, the Burst Mode quiescent current is increased to
about 100µA for Channel 1.
FB1 (Pin 32): The LT8652S regulates the FB1 pin to
600mV referenced to SNSGND1. Connect the feedback
resistor divider tap to this pin.
SNSGND1 (Pin 33): The LT8652S regulates the FB1 pin
to 600mV referenced to SNSGND1. Connect the ground
pin of the output capacitor to this pin with a Kelvin line.
If SNSGND1 pin functionality is not desired, tie this pin
to GND.
SNSGND2 (Pin 34): The LT8652S regulates the FB2 pin
to 600mV referenced to SNSGND2. Connect the ground
pin of the output capacitor to this pin with a Kelvin line.
If SNSGND2 pin functionality is not desired, tie this pin
to GND.
14
FB2 (Pin 35): The LT8652S regulates the FB2 pin to
600mV referenced to SNSGND2. Connect the feedback
resistor divider tap to this pin.
VC2 (Pin 36): Channel 2 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. Connect this pin to
VCC to use the default internal compensation. If internal
compensation is used, the Burst Mode quiescent current
is only 12.8µA for Channel 2. If external compensation is
used, the Burst Mode quiescent current is increased to
about 100µA for Channel 2.
GND (Pins 4, 12, Exposed Pad Pins 37 to 42): LT8652S
System Ground. Connect these pins to the system ground
and the board ground plane. Place the negative terminal of
the input capacitors as close to the GND pins as possible.
The exposed pad must be soldered to the PCB in order to
lower the thermal resistance.
Rev. B
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LT8652S
BLOCK DIAGRAM
VIN1
C1
0.22µF
×2
CIN1
R5
EN/UV
R6
INTERNAL 0.6V REF
+
–
SHDN
–
+
C5
0.22µF
PG1
±7%
ERROR
AMP
BURST
DETECT
VOUT1
R1
R2
FB1
CSS1
OPT
TR/SS1
SHDN
TSD
VCC UVLO
VIN1 UVLO
BST1
C3
0.22µF
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
SW1
200mV
VOUT1
GND
2µA
VC1
L1
COUT1
–
+
SNSGND1
RC1
VCC
SLOPE COMP
TEMP (10mV/°C)
CPL1
BIAS
3.4V
REG
+
–
IMON1
RIMON1
+
–
VCC
1V
RT
SYNC
+
–
OSCILLATOR
RT
CLKOUT
CC1
VIN2
C2
0.22µF
×2
CIN2
INTERNAL 0.6V REF
–
+
VCC
SLOPE COMP
BST2
PG2
±7%
ERROR
AMP
VOUT2
CPL2
R3
R4
FB2
CSS2
OPT
TR/SS2
SHDN
TSD
VCC UVLO
VIN1 UVLO
SW2
VOUT2
COUT2
GND
2µA
200mV
L2
+
–
IMON2
+
–
VCC
RIMON2
1V
+
–
RC2
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
–
+
SNSGND2
VC2
BURST
DETECT
C4
0.22µF
GND
8652S BD
CC2
Rev. B
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15
LT8652S
OPERATION
Foreword
The LT8652S is a dual monolithic step-down regulator. The two channels are the same in terms of current
capability and power switch size. The following sections
describe the operation of Channel 1 and common circuits.
They will highlight Channel 2 differences and interactions
only when relevant. To simplify the application, both VIN1
and VIN2 are assumed to be connected to the same input
supply. However, note that VIN1 must be greater than 3.0V
for either channel to operate.
Operation
The LT8652S is a dual monolithic, constant frequency,
peak current mode step-down DC/DC converter. An oscillator, with frequency set using a resistor on the RT pin,
turns on the internal top power switch at the beginning of
each clock cycle. Current in the inductor then increases
until the top switch current comparator trips and turns off
the top power switch. The peak inductor current at which
the top switch turns off is controlled by the voltage on
the VC node. The error amplifier servos the VC node by
comparing the voltage on the VFB pin with an internal 0.6V
reference. When the load current increases it causes a
reduction in the feedback voltage relative to the reference
leading the error amplifier to raise the VC voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins or
inductor current falls to zero when not in forced continuous mode (FCM). If overload conditions result in more
than the bottom NMOS current limit flowing through the
bottom switch, the next clock cycle will be delayed until
switch current returns to a safe level.
The “S” in LT8652S refers to the second generation
Silent Switcher technology. This technology allows fast
switching edges for high efficiency at high switching frequencies, while simultaneously achieving good EMI/EMC
performance. This includes the integration of ceramic
capacitors into the package for VIN1, VIN2, VCC, BST1,
and BST2 (C1–C5 in the Block Diagram). These capacitors
keep all the fast AC current loops small which improves
EMI performance.
16
The output voltage is resistively divided externally to create a feedback voltage for the regulator. In high current
operation, a ground offset may be present between the
LT8652S local ground and ground at the load. To overcome this offset, SNSGND should have a Kelvin connection to the load ground, and the lowest potential node of
the resistor divider should be connected to SNSGND. The
internal error amplifier senses the difference between this
feedback voltage and a 0.6V SNSGND referenced voltage. This scheme overcomes any ground offsets between
local ground and remote output ground, resulting in a
more accurate output voltage. The LT8652S allows for
remote output ground deviations as much as ±300mV
with respect to local ground.
If the EN/UV pin is low, both channels are fully shut down
and the LT8652S draws 6µA from the input supply. When
the EN/UV pin is above 0.82V, both channels’ switching
regulators will become active. 16μA is supplied by VIN1
to common bias circuits for both channels.
Each channel can independently enter Burst Mode operation to optimize efficiency at light load. Between bursts,
all circuitry associated with controlling the output switch
is shut down, reducing the channel’s contribution to input
supply current. In a typical application, 17μA will be consumed from the input supply when regulating both channels with no load. Ground the SYNC pin for Burst Mode
operation, float it for forced continuous mode (FCM) or
apply a DC voltage higher than 2.8V to use FCM with
spread spectrum modulation (SSM). If a clock is applied
to the SYNC pin, both channels will synchronize to the
external clock frequency and operate in FCM. While in
FCM, the oscillator operates continuously and rising SW
transitions are aligned to the clock. During light loads,
the inductor current is allowed to go negative to maintain
the programmed switching frequency. Minimum current
limits for both power switches are enforced to prevent
large negative inductor current from flowing back to the
input. SSM dithers the switching frequency from the programmed value set by the RT pin up to 20% higher than
the programmed value to spread out the switching energy
in the frequency domain. The CLKOUT pin has no output
Rev. B
For more information www.analog.com
LT8652S
OPERATION
in Burst Mode operation, but outputs a square wave 90
degrees phase shifted from Channel 1 when in FCM. If a
clock is applied to the SYNC pin, the CLKOUT pin has the
same phase and duty cycle as the external clock.
When the current limit feature is used, a compensation
capacitor should not be placed in parallel with the chosen resistor. The output monitor and limit circuits may be
individually disabled by shorting IMON to GND.
To improve efficiency across all loads, supply current to
internal circuitry can be sourced from the BIAS pin when
biased at 3.3V or above. Otherwise, the internal circuitry
will draw current exclusively from VIN1. The BIAS pin
should be connected to the lowest VOUT programmed at
3.3V or above.
Comparators monitoring the FB pin voltage will pull the
corresponding PG pin low if the output voltage varies
more than ±7% (typical) from the regulation voltage or if
a fault condition is present.
The VC pin allows the loop compensation of the switching regulator to be optimized based on the programmed
switching frequency. Internal compensation can be
selected by connecting the VC pin to VCC, which simplifies
the application circuit. External compensation improves
the transient response at the expense of about 100µA
more quiescent current per channel.
The LT8652S provides a scaled replica of the average
Channel 1 and Channel 2 output current at the IMON1
and IMON2 pins respectively. The average current at each
of these pins will be 1/78,000th of the measured average
current plus a sampling offset. Further, the voltage at each
pin is continuously fed to independent current limit amplifiers that have a voltage reference at 1V. Thus, a programmable average current limit for the output current may be
obtained by placing a resistor of suitable value from IMON
to GND so as to produce 1V at the desired current limit.
The voltage present at the TEMP pin is proportional to
the average die temperature of the LT8652S. The TEMP
pin will be 250mV for a die temperature of 25°C and will
have a slope of 11mV/°C.
Tracking soft-start is implemented by providing constant
current via the SS/TR pin to an external soft-start capacitor to generate a voltage ramp. FB voltage is regulated to
the voltage at the SS pin until it exceeds 0.6V; FB is then
regulated to the reference 0.6V. When the SS pin is below
40mV, the corresponding switching regulator will stop
switching. The SS capacitor is reset during shutdown,
VIN1 undervoltage, or thermal shutdown.
Both channels are designed for output currents up to 12A,
but thermal considerations practically limit the output currents to 8.5A of continuous current from each channel
simultaneously. Channel 1 has a minimum VIN1 requirement of 3.0V, Channel 2 can operate with no minimum
VIN2 provided the minimum VIN1 has been satisfied.
Rev. B
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17
LT8652S
APPLICATIONS INFORMATION
Achieving Ultralow Quiescent Current
To enhance efficiency at light loads, the LT8652S operates in low ripple Burst Mode operation, which keeps the
output capacitor charged to the desired output voltage
while minimizing the input quiescent current and minimizing output voltage ripple. 16μA is supplied by VIN1
to common bias circuits. In Burst Mode operation, the
LT8652S delivers single small pulses of current to the
output capacitor followed by sleep periods where the output power is supplied by the output capacitor. While in
sleep mode, both channels consume a combined 16μA.
As the output load decreases, the frequency of single current pulses decreases (see Figure 1) and the percentage
of time the LT8652S is in sleep mode increases, resulting in much higher light load efficiency than for typical
converters. By maximizing the time between pulses, the
converter quiescent current approaches 16µA for a typical application when there is no output load. Therefore,
to optimize the quiescent current performance at light
loads, the current in the feedback resistor divider must
be minimized as it appears to the output as load current.
2.50
VIN1 = 12V
VOUT = 1V
SYNC = 0V
RT = 20kΩ
L = 0.2µH
SWITCHING FREQUENCY (MHz)
2.25
2.00
1.75
1.00
0.75
0.50
0.25
1
2
3
LOAD CURRENT (A)
4
5
8652S F01
Figure 1. Burst Frequency
While in Burst Mode operation, the current limit of the
top switch is approximately 3A resulting in output voltage
ripple shown in Figure 2. Increasing the output capacitance will decrease the output ripple proportionally. As
18
VSW
5V/DIV
2µs/DIV
8652S F02
12VIN TO 1VOUT AT 250mA
SYNC = 0V
Figure 2. Burst Mode Operation
For some applications, it is desirable to select forced
continuous mode (FCM) to maintain full switching frequency down to zero output load. See Forced Continuous
Mode section.
The output voltage is programmed with an external
resistor divider from the output to its SNSGND (R1–2 for
Channel 1, R3–4 for Channel 2). The resistive divider is
tapped by the FB pin. Choose the resistor values according to:
1.25
0
IL
2A/DIV
FB Resistor Network and Differential Output Sensing
1.50
0
load ramps upward from zero, the switching frequency
will increase, but only up to the switching frequency
programmed by the resistor at the RT pin as shown in
Figure 1. The output load at which the LT8652S reaches
the programmed frequency varies based on input voltage,
output voltage and inductor choice.
⎛V
⎞
R1= R2 ⎜ OUT1 – 1⎟
⎝ 0.6V ⎠
Reference designators refer to the Block Diagram.
1% resistors or better are recommended to maintain
output voltage accuracy. More precisely, the VOUT value
programmed in the previous equation is with respect to
SNSGND and thus is a differential quantity. For example, if
VOUT is programmed to 3V and VSNSGND is –0.1V, then the
output will be 2.9V with respect to ground at the LT8652S.
Rev. B
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LT8652S
APPLICATIONS INFORMATION
Differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. Figure 3 illustrates the potential
variations in the power and ground lines due to parasitic
elements. These variations are exacerbated in multiapplication systems with shared ground planes. Without
differential output sensing, these variations directly reflect
as an error in the regulated output voltage. The LT8652S’s
differential output sensing can correct for up to ±300mV
of variation in the output’s power and ground lines.
resistor divider. The current flowing in the divider acts as
a load current and will increase the no-load input current
to the converter which is approximately:
where 16µA is the quiescent current of both channels
and common circuitries, the second term is the current
in the feedback divider reflected to the input of Channel 1
operating at its light load efficiency η. For a 1.2V application with R1 = 1M and R2 = 1M, the feedback divider
draws 0.6µA. With VIN = 12V and h = 80%, this adds 75nA
to the 16µA quiescent current resulting in 16.075µA noload current from the 12V supply. Note that this equation
implies that the no-load current is a function of VIN; this is
plotted in the Typical Performance Characteristics section.
The LT8652S allows for seamless differential output sensing by sensing the resistively divided feedback voltage
differentially. This allows for differential sensing in the
full output range from 0.6V to 18V.
To avoid noise coupling into FB, the resistor divider should
be placed near the FB and SNSGND pins and physically
close to the LT8652S. The remote output and ground
traces should be routed together as a differential pair to
the remote output. These traces should be terminated as
close as physically possible to the remote output point
that is to be accurately regulated through remote differential sensing.
A similar calculation can be done to determine the input
current contribution from the Channel 2 feedback resistors. For a 3.3V application with R3 = 1M, R4 = 221k,
VIN = 12V, and η = 80%, this adds 0.9µA to the input current resulting in a total of 17µA with both channels on.
For a typical FB resistor of 1MΩ, a 4.7pF to 10pF phaselead capacitor should be connected from VOUT to FB.
If low input quiescent current and good light-load efficiency are desired, use large resistor values for the FB
VIN
SW
CIN
L
LT8652S
⎞ ⎛ 1⎞
⎛ V
⎞⎛ V
IQ = 16µA + ⎜ OUT1 ⎟ ⎜ OUT1 ⎟ ⎜ ⎟
⎝ R1+ R2 ⎠ ⎝ VIN1 ⎠ ⎝ η ⎠
VIN
TRACE PARASITICS
±VDROP(PWR)
ILOAD
COUT1
FB
RFB1
GND
SNSGND
RFB2
COUT2
ILOAD
TRACE PARASITICS
±VDROP(GND)
MISCELLANEOUS CURRENTS
IN SHARED GROUND PLANE
8652S F03
Figure 3. Differential Output Sensing Used to Correct Line Loss Variations
in a High Power Distributed System with a Shared Ground Plane
Rev. B
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19
LT8652S
APPLICATIONS INFORMATION
Setting the Switching Frequency
The LT8652S uses a constant frequency PWM architecture that can be programmed to switch from 300kHz to
3MHz by using a resistor tied from the RT pin to ground.
Table 1 shows the necessary RT value for a desired
switching frequency.
The RT resistor required for a desired switching frequency
can be calculated using:
RT =
43.5
fSW
– 1.8
where RT is in kΩ and fSW is the desired switching frequency in MHz.
The two channels of the LT8652S operate 180° out of
phase to avoid aligned switching edge noise and reduce
input current ripple.
Table 1. SW Frequency vs. RT Value
fSW (MHz)
RT (kΩ)
0.3
143
0.4
107
0.5
84.5
0.6
69.8
0.8
52.3
1.0
41.2
1.2
34.8
1.4
29.4
1.6
25.5
1.8
22.6
2.0
20.0
2.2
18.2
2.5
15.8
3.0
12.7
fSW (MAX ) =
(
VOUT + VSW (BOT )
t ON(MIN) VIN – VSW ( TOP ) + VSW (BOT )
)
where VIN is the typical input voltage, VOUT is the output
voltage, VSW(TOP) and VSW(BOT) are the internal switch
drops (~0.3V, ~0.1V, respectively at maximum load) and
tON(MIN) is the minimum top switch on-time of 45nS (see
the Electrical Characteristics). This equation shows that a
slower switching frequency is necessary to accommodate a
high VIN/VOUT ratio. Choose the switching frequency based
on which channel has the lower frequency constraint.
For transient operation, VIN may go as high as the absolute maximum rating of 18V regardless of the RT value,
however the LT8652S will reduce switching frequency
on each channel independently as necessary to maintain
control of inductor current to assure safe operation.
In Burst Mode operation, the LT8652S is capable of a
maximum duty cycle of greater than 99%, and the VIN to
VOUT dropout is limited by the RDS(ON) of the top switch.
In this mode the channel that enters dropout skips switch
cycles, resulting in a lower switching frequency. The
LT8652S in forced continuous mode will not skip cycles
to achieve a higher duty cycle. The part will maintain the
programmed switching frequency and the dropout voltage will be larger due to the smaller maximum duty cycle.
For applications that cannot allow deviation from the programmed switching frequency at low VIN/VOUT ratios, use
the following formula to set switching frequency:
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off
between efficiency, component size, and input voltage
range. The advantage of high frequency operation is that
smaller inductor and capacitor values may be used. The
disadvantages are lower efficiency and a smaller input
voltage range.
20
The highest switching frequency (fSW(MAX)) for a given
application can be calculated as follows:
VIN(MIN) =
VOUT + VSW (BOT )
1– fSW • t OFF (MIN)
– VSW (BOT ) + VSW ( TOP )
where VIN(MIN) is the minimum input voltage without
skipped cycles, VOUT is the output voltage, VSW(TOP) and
VSW(BOT) are the internal switch drops (~0.3V, ~0.1V,
respectively at maximum load), fSW is the switching
frequency (set by RT), and tOFF(MIN) is the minimum
switch off-time. Note that higher switching frequency will
increase the minimum input voltage below which cycles
will be dropped to achieve higher duty cycle.
Rev. B
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Note there is no minimum VIN2 voltage requirement as it
does not supply the internal common bias circuits, making the Channel 2 uniquely capable of operating from very
low input voltages as long as VIN1 has a supply of 3V or
greater.
Inductor Selection and Maximum Output Current
The LT8652S is designed to minimize solution size by
allowing the inductor to be chosen based on the output
load requirements of the application. During overload or
short-circuit conditions, the LT8652S safely tolerates
operation with a saturated inductor through the use of a
high speed peak-current mode architecture.
The LT8652S limits the peak switch current in order to
protect the switches and the system from overload faults.
The top switch current limit (ILIM) is at least 29A at low
duty cycles and decreases linearly to 19A at DC = 0.8.
The inductor value must then be sufficient to supply the
desired maximum output current (IOUT(MAX)), which is a
function of the switch current limit (ILIM) and the ripple
current.
∆IL =
VOUT1,2 + VSW (BOT )
3 • fSW
where fSW is the switching frequency in MHz, VOUT is
the output voltage, VSW(BOT) is the bottom switch drop
(~0.1V) and L is the inductor value in μH. To avoid overheating and poor efficiency, an inductor must be chosen
with an RMS current rating that is greater than the maximum expected output load of the application. In addition,
the saturation current (typically labeled ISAT) rating of the
inductor must be higher than the load current plus 1/2 of
in inductor ripple current:
1
IL (PEAK ) = ILOAD(MAX ) + ∆IL
2
where ∆IL is the inductor ripple current as calculated in
Equation 1 and ILOAD(MAX) is the maximum output load
for a given application.
As a quick example, an application requiring 7A output
should use an inductor with an RMS rating of greater than
7A and an ISAT of greater than 9.1A. During long duration
overload or short-circuit conditions, the inductor RMS rating requirement must be greater to avoid overheating of
the inductor. To keep the efficiency high, the series resistance (DCR) should be less than 3mΩ and the core material should be intended for high frequency applications.
∆IL
2
The peak-to-peak ripple current in the inductor can be
calculated as follows:
A good first choice for the inductor value is:
L 1,2 =
IOUT (MAX ) = ILIM –
⎞
VOUT ⎛
V
• ⎜ 1– OUT ⎟ (1)
L • fSW ⎜⎝ VIN(MAX) ⎟⎠
where fSW is the switching frequency of the LT8652S and
L is the value of the inductor. Therefore, the maximum
output current that the LT8652S will deliver depends on
the switch current limit, the inductor value, and the input
and output voltages.
Each channel has a secondary bottom switch current
limit. After the top switch has turned off, the bottom
switch carries the inductor current. If for any reason the
inductor current is too high, the bottom switch will remain
on, delaying the top switch turning on until the inductor
current returns to a safe level. This level is specified as
the bottom NMOS current limit and is independent of duty
cycle. Maximum output current in the application circuit is
limited to this valley current plus one half of the inductor
ripple current.
In most cases, current limit is enforced by the top switch.
The bottom switch limit controls the inductor current
when the minimum on-time condition is violated (high
input voltage, high frequency or saturated inductor).
The bottom switch current limit is designed to be equal
to the peak current limit to avoid any contribution to
maximum rated current of the LT8652S.
For more information about maximum output current and
discontinuous operation, see Analog Devices Application
Note 44.
Rev. B
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21
LT8652S
APPLICATIONS INFORMATION
Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5),
a minimum inductance is required to avoid sub-harmonic
oscillation. See Analog Devices Application Note 19.
Table 2. Inductor Manufacturers
VENDOR
URL
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Würth Elektronik
www.we-online.com
Vishay
www.vishay.com
Output Current Monitor and Limit
The LT8652 senses the average current through the bottom switch during the off state and outputs a scaled replica of this current (which corresponds to the regulator’s
load current) to the IMON pin. The average current at the
monitor pin is 1/78000th the measured average output
current plus a sampling offset inversely proportional to
the switch off-time:
I
1
IIMON = OUT +
0.078 tOFF
tOFF
where fSW is the programmed switching frequency measured in MHz, tOFF is the switch off-time measured in
microseconds, IOUT is the output current in amps, and
IIMON is in microamps.
The output current may be measured directly or converted to a voltage with an external resistor. The voltages
at the IMON pins are continuously fed to independent
current limit amplifiers that have a voltage reference of
1V (typical). A programmable average current limit for
either channels’ average output current may be obtained
by placing a resistor, RIMON, from the monitor pin to GND
according to the following equation:
22
78,000
ILIM
When active, the current limit amplifiers form a feedback
loop that controls the maximum average current produced by the LT8652S. In current limit the output voltage drops, resulting in frequency stretching to maintain a
decreased duty-cycle. This results in the sampling offset
term becoming negligible in current limit. When using
the current limit feature, a capacitor should not be placed
between GND and the monitor pin, otherwise loop stability
could be adversely effected. However, if high frequency
noise reduction is desired a capacitor may be placed in
parallel with RIMON if:
RIMON • CFILTER < 3.2μs
This will ensure the pole created by the filter capacitor
and RIMON will not affect the current limit feedback loop.
Do not use a RIMON greater than 80kΩ.
When operating in BURST mode (SYNC low), if the load
is low enough that the switching frequency starts to
decrease, then IMON will cease to monitor output current and will instead pull the IMON voltage to ground.
⎛ VOUT ⎞
⎜⎝ 1– V ⎟⎠
IN
=
fSW
RIMON =
where ILIM is the programmed current limit in amps and
RIMON is in ohms. It is recommended to set the programmed average current limit to allow for at least 10%
margin.
As previously described, the LT8652S senses the average
output current through the bottom FET during the off time.
As a result, it is recommended the LT8652S be operated
with an off time of greater than 150ns for best current
monitor accuracy. For many applications, this is of little
concern unless operating at or near regulator dropout
conditions (extremely high duty cycle operation).
Input Capacitor
Bypass the input of the LT8652S circuit with a ceramic
capacitor of X7R or X5R type placed as close as possible
to the VIN and GND pins. Y5V types have poor performance over temperature and applied voltage, and should
not be used. A 10μF or higher value ceramic capacitor is
adequate to bypass the LT8652S and will easily handle
the ripple current. Note that larger input capacitance is
required when a lower switching frequency is used. If
the input power source has high impedance, or there is
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LT8652S
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significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be
provided with a low performance electrolytic capacitor.
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT8652S to produce the DC output. In this role, it
determines the output ripple, thus low impedance at the
switching frequency is important. The second function
is to store energy in order to satisfy transient loads and
stabilize the LT8652S’s control loop. Ceramic capacitors
have very low equivalent series resistance (ESR) and
provide the best ripple performance. For good starting
values, see the Typical Applications section.
Use X5R or X7R types. This choice will provide low output ripple and good transient response. Transient performance can be improved with a higher value output capacitor and the addition of a feed forward capacitor placed
between VOUT and FB. Increasing the output capacitance
will also decrease the output voltage ripple. A lower value
of output capacitor can be used to save space and cost
but transient performance will suffer and may cause loop
instability. See the Typical Applications in this data sheet
for suggested capacitor values.
When choosing a capacitor, special attention should be
given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage
bias and temperature. A physically larger capacitor or one
with a higher voltage rating may be required.
tantalum or electrolytic capacitor at the output. Low noise
ceramic capacitors are also available.
Table 3. Ceramic Capacitor Manufacturers
MANUFACTURER
WEB
Taiyo Yuden
www.t-yuden.com
AVX
www.avxcorp.com
Murata
www.murata.com
TDK
www.tdk.com
Enable Pin
The LT8652S is in shutdown when the EN/UV pin is low
and active when the pin is high. The rising threshold of
the EN/UV comparator is 0.83V, with 30mV of hysteresis.
The EN/UV pins can be tied to VIN if the shutdown feature
is not used, or tied to a logic level if shutdown control
is required.
Adding a resistor divider from VIN to EN/UV programs
the LT8652S to operate only when VIN is above a desired
voltage (see the Block Diagram). Typically, this threshold,
VIN(EN), is used in situations where the input supply is
current limited or has a relatively high source resistance.
A switching regulator draws constant power from the
source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current limit or latch
low under low source voltage conditions. The VIN(EN)
threshold prevents the regulator from operating at source
voltages where the problems might occur. This threshold
can be adjusted by setting the values R5 and R6 such that
they satisfy the following equation:
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8652S due to their piezoelectric
nature. When in Burst Mode operation, the LT8652S’s
switching frequency depends on the load current, and
at very light loads the LT8652S can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since the LT8652S operates at a lower current limit during
Burst Mode operation, the noise is typically very quiet to a
casual ear. If this is unacceptable, use a high performance
⎛ R5 ⎞
VIN(EN) = ⎜
+ 1 • 0.8V
⎝ R6 ⎟⎠
where the corresponding channel will remain off until
VIN is above VIN(EN). Due to the comparator’s hysteresis,
switching will not stop until the input falls slightly below
VIN(EN).
When operating in Burst Mode operation for light load
currents, the current through the VIN(EN) resistor network
can easily be greater than the supply current consumed
by the LT8652S. Therefore, the VIN(EN) resistors should
be large to minimize their effect on efficiency at low loads.
Rev. B
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23
LT8652S
APPLICATIONS INFORMATION
An internal low dropout (LDO) regulator produces the 3.4V
supply from VIN1 that powers the drivers and the internal
bias circuitry. For this reason, VIN1 must be present and
valid to use either channel. The VCC can supply enough
current for the LT8652S’s circuitry and must be bypassed
to ground with a 1μF ceramic capacitor. Good bypassing is
necessary to supply the high transient currents required
by the power MOSFET gate drivers. To improve efficiency
the internal LDO can also draw current from the BIAS pin
when the BIAS pin is at 3.1V or higher. Typically the BIAS
pin can be tied to the lowest output or external supply
above 3.1V. If BIAS is connected to a supply other than
VOUT, be sure to bypass with a local ceramic capacitor. If
the BIAS pin is below 3.0V, the internal LDO will consume
current from VIN1.
Applications with high input voltage and high switching
frequency where the internal LDO pulls current from VIN1
will increase die temperature because of the higher power
dissipation across the LDO. Do not connect an external
load to the VCC pin.
Frequency Compensation
The LT8652S has VC pins which can be used to optimize
the loop compensation of each channel. If the VC pins are
shorted to VCC, then internal compensation is used. This
simplifies the circuit design and minimizes the quiescent
current, but since the internal compensation has to be
stable across the 300kHz to 3MHz range of switching
frequencies, the internal compensation will not be optimal, especially at high switching frequencies. If the best
transient response is desired, an external compensation
network can be connected to the VC pin, which usually
consists of a series resistor and capacitor (see RC and CC
in the Block Diagram).
Designing the compensation network is a bit complicated
and the best values depend on the application and in particular the type of output capacitor. A practical approach
is to start with one of the circuits in the data sheet that is
similar to your application and tune the compensation network to optimize the performance. LTspice® simulations
24
can help in this process. Stability should then be checked
across all operating conditions, including load current,
input voltage and temperature.
The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the
stability using a transient load.
Figure 4 shows an equivalent circuit for the LT8652S
control loop. The error amplifier is a transconductance
amplifier with finite output impedance. The power section,
consisting of the modulator, power switches, and inductor,
is modeled as a transconductance amplifier generating an
output current proportional to the voltage at the VC pin.
Note that the output capacitor integrates this current and
that the capacitor on the VC pin (CC) integrates the error
amplifier output current, resulting in two poles in the loop.
A zero is required and comes from a resistor RC in series
with CC. This simple model works well as long as the value
of the inductor is not too high and the loop crossover
frequency is much lower than the switching frequency. A
phase lead capacitor (CPL) across the feedback divider can
be used to improve the transient response and is required
to cancel the parasitic pole caused by the feedback node
to ground capacitance.
LT8652S
CURRENT MODE
POWER STAGE
OUTPUT
R1
Gm = 15S
VC
700k
RC
CC
gm = 1.4mS
FB
CF
+
–
VCC Regulator
CPL
C1
0.6V
R2
8652S F04
Figure 4. Model for Loop Response
Rev. B
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Figure 5a shows the transient response for the front page
application which uses internal compensation. Figure 5b
shows the improved transient response of the same
application when a 17.1k RC and 220pF CC compensation network is used. Use of an external compensation
network increases the quiescent current by about 50µA
per channel.
ILOAD
5A/DIV
VOUT
100mV/DIV
20µs/DIV
8652S F05a
6A TO 12A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
a)
Output Voltage Tracking and Soft-Start
The LT8652S allows the user to program its output voltage ramp rate with the SS pin. An internal 2μA current
pulls up the SS pin to VCC. Putting an external capacitor
on SS, enables soft-starting the output to prevent current
surge on the input supply. During the soft-start ramp, the
output voltage will proportionally track the SS pin voltage. For output tracking applications, SS can be externally
driven by another voltage source. From 0V to 0.04V, the
SS pin will stop the corresponding channel from switching, thus allowing the SS pin to be used as a shutdown
pin. From 0.04V to 0.6V, the SS voltage will override the
internal 0.6V reference input to the error amplifier, thus
regulating the FB pin voltage to that of SS pin (Figure 6).
When SS is sufficiently above 0.6V, tracking is disabled
and the feedback voltage will regulate to the internal reference voltage. The SS pin may be left floating if the function is not needed. Note that in both Burst Mode operation
and forced continuous mode (FCM), the LT8652S will not
discharge the output to regulate to a lower SS voltage.
An active pull-down circuit is connected to the SS pin
which will discharge the external soft-start capacitor in
the case of fault conditions and restart the ramp when the
faults are cleared. Fault conditions that clear the soft-start
capacitor are the EN/UV pin below 0.8V, VIN1 voltage falling too low, or thermal shutdown.
ILOAD
5A/DIV
VOUT
100mV/DIV
0.8
6A TO 12A TRANSIENT
12VIN TO 1VOUT
COUT = 340µF
FCM, fSW = 2MHz
CC = 220pF, RC = 17.1kΩ
b)
8652S F05b
0.6
FB VOLTAGE (V)
20µs/DIV
Figure 5. Transient Response
0.4
0.2
0
EXTERNAL COMPENSATION
INTERNAL COMPENSATION
0
0.2
0.4
0.6
0.8
SS VOLTAGE (V)
1.0
1.2
8652S F06
Figure 6. Soft Start Pin Tracking
Rev. B
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25
LT8652S
APPLICATIONS INFORMATION
Output Power Good
Paralleling
When the LT8652S’s output voltage is within the ±7%
window of the regulation point, which is a FB voltage in
the range of 0.56V to 0.64V (typical), the output voltage
is considered good and the open-drain PG pin goes high
impedance and is typically pulled high with an external
resistor. Otherwise, the internal pull-down device will pull
the PG pin low. To prevent glitching both the upper and
lower thresholds, include 0.25% of hysteresis.
To increase the possible output current, the two channels
can be connected in parallel to the same output. To do
this, the VC, SS, and FB pins of each channel are connected together, while each channel’s SW node is connected to the common output through its own inductor.
Figure 8 shows an application where the two channels of
one LT8652S regulator are combined to get one output
capable of 17A DC with 24A peak transients.
The PG pin is also actively pulled low during several fault
conditions: corresponding EN/UV pin below 0.8V, VCC
voltage falling too low, VIN1 under voltage or thermal
shutdown.
VIN1
3.6V
TO 18V
VIN1
VIN2
EN
22µF
5.11k
Sequencing
5.11k
Start-up sequencing and tracking can be configured in
several ways with the LT8652S. One channel can be
required to be valid before enabling the other channel to
sequence their start-up order. This can be done by connecting the PG pin of the first channel to the SS pin of
the second channel.
22nF
0.3µH
SW2
FB1
IMON1
665k
VOUT
1V
17A
10pF
FB2
IMON2
LT8652S
SS1
SS2
1M
SNSGND1
SNSGND2
VC1
PG1
PG2
VCC
27.4k
330µF
(×2)
1210
X5R
10k
1000pF
VC2
BIAS
CLKOUT
TEMP
RT
The channels can also be started at the same time where
the output voltages can track in a ratiometric fashion (see
Figure 7).
0.3µH
SW1
100k
GND SYNC
L1, L2: XEL4030-301ME
1µF
fSW = 1.5MHz
8652S F08
Figure 8. Two-Phase Application
SEQUENCED START-UP
EN/UV
RATIOMETRIC START-UP
VIN1
EN/UV
SS2
VIN1
SS1
PG1
VOUT1
PG2
VOUT2
SS2
VOUT1
2V/DIV
VOUT2
2V/DIV
VOUT1
2V/DIV
VOUT2
2V/DIV
PG1
2V/DIV
PG1
2V/DIV
PG2
2V/DIV
PG2
2V/DIV
2ms/DIV
2ms/DIV
Figure 7. Sequencing and Start-up Configurations
26
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8652S F07
Rev. B
LT8652S
APPLICATIONS INFORMATION
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below 0.4V (this can be ground or a logic low output).
To select forced continuous mode (FCM), float the SYNC
pin. To select FCM with Spread Spectrum Modulation
(SSM), tie the SYNC pin above 2.8V (SYNC can be tied to
VCC). To synchronize the LT8652S oscillator to an external
frequency connect a square wave (with 20% to 80% duty
cycle) to the SYNC pin. The square wave amplitude should
have valleys that are below 0.4V and peaks above 1.5V
(up to 6V). When synchronized to an external clock the
LT8652S will use FCM.
Channel 1 will synchronize its positive switch edge
transitions to the positive edge of the SYNC signal and
Channel 2 will synchronize to the negative edge of the
SYNC signal.
The LT8652S may be synchronized over a 300kHz to
3MHz range. The RT resistor should be chosen to set
the LT8652S switching frequency equal to or below the
lowest synchronization input. For example, if the synchronization signal will be 500kHz and higher, the RT should
be selected for nominal 500kHz.
The slope compensation is set by the RT value, while the
minimum slope compensation required to avoid subharmonic oscillations is established by the inductor size,
input voltage, and output voltage. Since the synchronization frequency will not change the slopes of the inductor
current waveform, if the inductor is large enough to avoid
subharmonic oscillations at the frequency set by RT, then
the slope compensation will be sufficient for all synchronization frequencies.
A synchronizing signal that incorporates spread spectrum
may reduce EMI. The duty cycle of the SYNC signal can
be used to set the relative phasing of the two channels
for minimizing input ripple.
Forced Continuous Mode
While in FCM, discontinuous mode operation is disabled
and the inductor current is allowed to go negative so that
the regulator can switch at the programmed frequency all
the way down to zero output current. This has the advantage of maintaining the programmed switching frequency
across the entire load range so that the switch harmonics
and EMI are consistent and predictable. The disadvantage
of FCM is that the light load efficiency will be low compared to Burst Mode operation.
At low input voltages when the part enters dropout, the
programmed switching frequency will be maintained
and off time skipping will not be allowed. This keeps the
switching frequency controlled, but the dropout voltage
will be higher than in Burst Mode operation due to maximum duty cycle constraints.
The negative inductor current is limited to a maximum of
about –4A, so the LT8652S can only sink a maximum of
about –2A. This prevents boosting an excessive amount
of current back from the output to the input. Additional
safety features include disabling FCM when the SS pin
voltage is below 1.8V during start-up to prevent discharging the output when starting up into a pre-biased output,
and a bottom FET current limit to prevent over charging
the output if the minimum on time is violated.
Spread Spectrum Modulation
Spread spectrum modulation (SSM) is activated by applying a DC voltage above 2.8V to the SYNC pin. SSM reduces
the EMI/EMC emissions by modulating the switching frequency between the value programmed by RT to approximately 20% higher than that value. The switching frequency is modulated linearly up and then linearly down at
a 7kHz rate. This is an analog function, so each switching
period will be different than the previous one. For example, when the LT8652S is programmed to 2MHz and the
SSM feature is enabled, the switching frequency will vary
from 2MHz to 2.4MHz at a 7kHz rate. When in SSM, the
part will also operate in forced continuous mode.
Forced continuous mode (FCM) is activated by either floating the SYNC pin, applying a DC voltage above 2.8V to the
SYNC pin, or applying an external clock to the SYNC pin.
Rev. B
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LT8652S
APPLICATIONS INFORMATION
Clock Output
The CLKOUT pin outputs a clock which can be used to
synchronous other regulators to the LT8652S. In Burst
Mode operation (SYNC pin low), the CLKOUT pin is
grounded. In forced continuous mode (SYNC pin float
or DC high), the CLKOUT pin outputs a 50% duty cycle
clock where the CLKOUT rising edge is 90 degrees phase
shifted relative to Channel 1. If this CLKOUT waveform is
applied to the SYNC pin of another LT8652S regulator,
then four-phase operation can be achieved. If an external
clock is applied to the SYNC pin of the LT8652S, then
the CLKOUT pin will output a waveform with the same
phasing and duty cycle as the SYNC pin clock. The low
and high levels of the CLKOUT pin are ground and VCC,
respectively. The edge rates will be slower if the CLKOUT
trace has extra capacitance.
Temperature Monitor Function
The TEMP pin will output a voltage proportional to die
temperature. The TEMP pin typically outputs 250mV for
25°C and has a slope of 11mV/°C. Without the aid of an
external circuitry, the TEMP pin output is valid from 20°C
to 150°C (200mV to 1.6V). Do not load the TEMP pin with
more than 100µA. To extend the TEMP pin output below
20°C, connect a resistor from the TEMP pin to a negative
voltage. The TEMP pin output is valid down to –35°C.
As a safeguard, the LT8652S has an additional thermal
shutdown set at a typical value of 165°C. If the thermal
shutdown is exceeded, both channels of the LT8652S will
be shutdown until the thermal overload event expires.
It should be noted that the TEMP pin voltage represents
the steady-state, average die temperature and should not
be used to guarantee that maximum junction temperatures are not exceeded. Instantaneous power along with
thermal gradients and time constants may cause portions
of the die to exceed maximum ratings. Be sure to calculate
die temperature rise for steady state (>1 Min) as well as
impulse conditions.
is beyond safe levels, switching of the top switch will be
delayed until such time as the inductor current falls to
safe levels. Fault condition of one channel will not affect
the operation of the other channel.
There is another situation to consider in systems where
the output will be held high when the input to the LT8652S
is absent. This may occur in battery charging applications or in battery-backup systems where a battery or
some other supply is ORed with Channel 1’s output. If
the VIN1 pin is allowed to float and the EN/UV pin is held
high (either by a logic signal or because it is tied to VIN1),
then the LT8652S’s internal circuitry will pull its quiescent current through its SW1 pin. This is acceptable if
the system can tolerate current draw in this state. If the
EN/UV pin is grounded, the SW1 pin current will drop
to near 6µA. However, if the VIN1 pin is grounded while
Channel 1 output is held high, regardless of EN/UV1, parasitic body diodes inside the LT8652S can pull current
from the output through the SW1 pin and the VIN1 pin,
damaging the IC.
VIN2 is not connected to the shared internal supply and
will not draw any current if left floating. If both VIN1 and
VIN2 are floating, regardless of EN/UV pin states, no load
will be present at the output of Channel 2. However, if the
VIN2 pin is grounded while Channel 2 output is held high,
parasitic body diodes inside the LT8652S can pull current
from the output through the SW2 pin and the VIN2 pin,
damaging the IC.
Figure 9 shows a connection of the VIN pins and EN/UV
pin that will allow the LT8652S to run only when the input
voltage is present and that protects against a shorted or
reversed input.
VIN1
Shorted and Reversed Input Protection
VIN2
LT8652S
EN/UV
8652S F09
The LT8652S will tolerate a shorted output. The bottom
switch current is monitored such that if inductor current
28
VIN1
Figure 9. Reverse VIN Protection
Rev. B
For more information www.analog.com
LT8652S
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 10 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT8652S’s VIN pins, GND pins, and
the input capacitors. The loop formed by the input capacitor should be as small as possible by placing the capacitor
adjacent to the VIN and GND pins. When using a physically
large input capacitor, the resulting loop may become too
large in which case using a small case/value capacitor
placed close to the VIN and GND pins plus a larger capacitor further away is preferred. These components, along
with the inductor and output capacitor, should be placed
RC2
CC2
on the same side of the circuit board and their connections should be made on that layer. Place a local, unbroken
ground plane under the application circuit on the layer
closest to the surface layer. The SW and BOOST nodes
should be as small as possible. Finally, keep the FB and
RT nodes small so that the ground traces will shield them
from the SW and BOOST nodes. The exposed pad acts
as a heat sink and is connected electrically to ground. To
keep thermal resistance low, extend the ground plane as
much as possible and add thermal vias under and near
the LT8652S to additional ground planes within the circuit
board and on the bottom side. See Figure 10 for example
PCB layout.
RC1
CC1
RT
CPL2
R4
R2
R3
R1
CPL1
COUT1
CIN1
L1
L2
CIN2
COUT2
8652S F10
Figure 10. Recommended Layout
Rev. B
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29
LT8652S
APPLICATIONS INFORMATION
High Temperature Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8652S. The exposed pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to large copper layers
below with thermal vias; these layers will spread heat
dissipated by the LT8652S. Placing additional vias can
reduce thermal resistance further. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. Power dissipation within the LT8652S can be estimated by calculating
the total power loss from an efficiency measurement and
subtracting the inductor loss. The die temperature is calculated by multiplying the LT8652S power dissipation by
the thermal resistance from junction to ambient.
The internal thermal shutdown protection of LT8652S will
stop switching and indicate a fault condition if junction
temperature exceeds 165°C. The fault condition will clear
and switching resume when the temperature drops back
below 160°C.
Temperature rise of the LT8652S is worst when operating
at high load, high VIN and high switching frequency. If
the case temperature is too high for a given application,
then either VIN, switching frequency or load current can
be decreased to reduce the temperature to an acceptable
level. Figure 11 shows examples case temperature vs VIN,
switching frequency and load.
The LT8652S’s internal power switches are capable of
safely delivering up to 12A of maximum output current.
However, due to thermal limits, the package can only handle 12A loads for short periods of time. Figure 12 shows
an example of how case temperature rise changes with
the duty cycle of a 1kHz pulsed 12A load.
100
DC2523A DEMO BOARD
VOUT1 = VOUT2 = 1V
100 fSW = 1.5MHz
DC2523A DEMO BOARD
VIN1 = VIN2 = 12V
fSW = 1.5MHz
VOUT1 = VOUT2 = 1V
90
CASE TEMPERATURE RISE (°C)
CASE TEMPERATURE RISE (°C)
120
80
60
40
20
80
70
60
50
40
30
20
10
0
0
1
2
3
0
4 5 6 7 8 9 10 11 12
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
DUTY CYCLE OF 12A LOAD ()
8652S F11
8652S F12
12VIN, LOAD2 = 0A
12VIN, LOAD2 = LOAD1
12VIN, LOAD2 = 8.5A
5VIN, LOAD2 = LOAD1
Figure 11. Case Temperature Rise
30
1
CH1 = 1A STANDBY, 12A PULSED
CH2 = 0A DC
CH1 = 1A STANDBY, 12A PULSED
CH2 = 8.5A DC
Figure 12. Case Temperature Rise vs 12A Pulsed Load
Rev. B
For more information www.analog.com
LT8652S
TYPICAL APPLICATIONS
1.2V, 3.3V, 2MHz Step-Down Converter with FCM and External Compensation
VIN1
3.0V TO 18V
10µF
0.2µH
VOUT1
1.2V
8.5A
220µF
1210
X5R
10pF
VIN2
VIN1
10µF
EN
BST1
BST2
SW1
SW2
0.6µH
1M
1M
LT8652S
FB1
15k
10nF
100k
VOUT2
3.3V
8.5A
10pF
FB2
1M
390pF
VIN2
3.6V TO 18V
221k
SNSGND1
SNSGND2
VC1
VC2
SS1
SS2
PG1
PG2
CLKOUT
BIAS
220µF
1210
X5R
8.25k
1000pF
10nF
100k
TEMP
IMON1
5.11k
IMON2
RT
VCC
20k
fSW = 2MHz
GND SYNC
5.11k
L1: XEL4030-201ME
L2: XEL5030-601ME
1µF
8652S TA02
Rev. B
For more information www.analog.com
31
LT8652S
TYPICAL APPLICATIONS
3.3V, 1V, 1.5MHz Step-Down Converter with Burst Mode Operation, CH1 6A Current Limit and Internal Compensation
VIN1
3.6V TO 18V
10µF
1µH
VOUT1
3.3V
5A
VCC
220µF
1210
X5R
10pF
VIN2
VIN1
10µF
EN
BST1
BST2
SW1
SW2
VC1
VC2
0.3µH
665k
FB1
FB2
221k
1M
SNSGND1
10nF
VOUT2
1V
8.5A
VCC
1M
LT8652S
VIN2
1.4V TO 18V
10pF
330µF
1210
X5R
SNSGND2
SS1
SS2
PG1
10nF
PG2
CLKOUT
TEMP
BIAS
IMON2
IMON1
13.0k
RT
VCC
27.4k
fSW = 1.5MHz
32
GND SYNC
5.11k
L1: XEL5030-102ME
L2: XEL4030-301ME
1µF
8652S TA03
Rev. B
For more information www.analog.com
LT8652S
TYPICAL APPLICATIONS
Two-Phase, 1V, 17A, 1.5MHz Step-Down Converter
VIN1
3.0V
TO 18V
VIN1
VIN2
EN
LT8652S
IMON1
IMON2
22µF
5.11k
FB1
FB2
22nF
SNSGND1
SNSGND2
BIAS
CLKOUT
TEMP
RT
VCC
27.4k
VC1
665k
PG2
GND SYNC
1µF
fSW = 1.5MHz
10pF
330µF
(×2 )
1210
X5R
1M
10k
VC2
PG1
VOUT
1V
17A
0.3µH
SW2
5.11k
SS1
SS2
0.3µH
SW1
1000pF
100k
L1, L2: XEL4030-301ME
8652S TA04
Four-Phase, 1V, 34A, 1.5MHz Step-Down Converter
VIN1
3.6V
TO 18V
0.3µH
VIN1
VIN2
EN
LT8652S
IMON1
IMON2
22µF
5.11k
SW1
22nF
BIAS
CLKOUT
TEMP
RT
VCC
27.4k
665k
FB1
FB2
5.11k
10pF
1M
SNSGND1
SNSGND2
SS1
SS2
VOUT
1V
34A
0.3µH
SW2
330µF
(×2)
1210
X5R
4.99k
VC1
VC2
1000pF
PG1
100k
PG2
GND SYNC
1µF
fSW = 1.5MHz
0.3µH
VIN1
VIN2
EN
LT8652S
IMON1
IMON2
22µF
5.11k
SW1
22nF
BIAS
CLKOUT
TEMP
RT
VCC
27.4k
330µF
(×2)
1210
X5R
FB1
FB2
5.11k
SS1
SS2
0.3µH
SW2
SNSGND1
SNSGND2
VC1
VC2
PG1
PG2
GND SYNC
L1, L2, L3, L4: XEL4030-301ME
8652S TA05
1µF
fSW = 1.5MHz
Rev. B
For more information www.analog.com
33
For more information www.analog.com
0.25 ±0.05
7.50 ±0.05
D
1.10
0.20
1.67
4.50 ±0.05
0.20
1.2500
1.2500
SUGGESTED PCB LAYOUT
TOP VIEW
0.7500
PACKAGE TOP VIEW
0.2500
aaa Z
2×
PACKAGE
OUTLINE
0.70 ±0.05
5
0.0000
0.2500
PIN 1
CORNER
0.7500
0.375
X
Y
E
2.7500
2.2500
1.7500
1.2500
0.7500
0.2500
0.2500
0.7500
1.2500
1.7500
2.2500
0.0000
aaa Z
2.7500
0.375
2×
// bbb Z
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
36b
eee M Z X Y
fff M Z
MIN
0.85
0.01
0.30
0.22
DETAIL B
H2
MOLD
CAP
DETAIL C
A1
36×
e/2
e
L
NOM
0.94
0.02
0.40
0.25
4.00
7.00
2.40
5.40
0.50
0.24 REF
0.70 REF
0.10
0.10
0.10
0.10
0.15
0.08
MAX
1.03
0.03
0.50
0.28
DIMENSIONS
DETAIL A
H1
DETAIL C
SUBSTRATE
NOTES
SUBSTRATE THK
MOLD CAP HT
DETAIL B
A
(Reference LTC DWG # 05-08-1525 Rev B)
ddd Z
Z
Z
34
19
e
0.375
E1
b
30
6
b
0.20
1.10
1.67
D1
e
0.40
0.20
13
36
DETAIL A
PACKAGE BOTTOM VIEW
18
31
7
12
1
4
SEE NOTES
PIN 1 NOTCH
0.25 × 45°
TRAY PIN 1
BEVEL
COMPONENT
PIN 1
PACKAGE IN TRAY LOADING ORIENTATION
LGA 36 1018 REV B
CORNER SUPPORT PAD CHAMFER IS OPTIONAL
7
LTXXXXXX
THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED
IN A MATRIX FORMAT. IT MAY HAVE OPTIONAL CORNER RADII
ON EACH SEGMENT
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
6
5
4
3. PRIMARY DATUM -Z- IS SEATING PLANE
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
ccc M Z X Y
ccc M Z X Y
LQFN Package
36-Lead (4mm × 7mm × 0.94mm)
LT8652S
PACKAGE DESCRIPTION
Rev. B
LT8652S
REVISION HISTORY
REV
DATE
DESCRIPTION
A
10/20
AEC-Q100 Qualified for Automotive Applications.
1
Added Pin Configuration notes.
2
Updated #W Order Information.
2
B
06/21
PAGE NUMBER
Updated Tape and Reel Order Information.
2
Clarified VIN1 current to 16µA in 5th paragraph.
16
Clarified typical application input supply current to 17µA in 6th paragraph.
16
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
35
LT8652S
TYPICAL APPLICATION
3.3V, 1V, 1.5MHz Two-Stage Step-Down Converter with Output Sequencing and CH2 10A Current Limit
VIN1
3.6V TO 18V
10µF
VIN1
CLKOUT
EN
TEMP
VIN2
BST1
10µF
BST2
1.0µH
VOUT1
3.3V
8.5A
VCC
220µF
1210
X5R
10pF
0.2µH
VC1
VC2
LT8652S
1M
VCC
665k
FB2
FB1
221k
1M
SNSGND2
SNSGND1
100k
VOUT2
1V
8.5A
SW2
SW1
PG1
PG2
SS1
SS2
10nF
10pF
330µF
1210
X5R
100k
10nF
BIAS
IMON1
5.11k
IMON2
RT
VCC
27.4k
GND SYNC
7.87k
L1: XEL5030-102ME
L2: XEL4030-301ME
1µF
fSW = 1.5MHz
8652S TA06
RELATED PARTS
PART
NUMBER
DESCRIPTION
COMMENTS
LT8642S
18V, 10A, 96% Efficiency, 3MHz Synchronous Silent Switcher 2 Step-Down VIN Min = 3V, VIN Max = 18V, VOUT Min = 0.6V, IQ = 2160µA,
ISD
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