LT8705A
80V VIN and VOUT
Synchronous 4-Switch BuckBoost DC/DC Controller
Features
Description
Single Inductor Allows VIN Above, Below, or Equal
to Regulated VOUT
nn V Range 2.8V (Need EXTV
IN
CC > 6.4V) to 80V
nn V
OUT Range: 1.3V to 80V
nn Quad N-Channel MOSFET Gate Drivers
nn Synchronous Rectification: Up to 98% Efficiency
nn Input and Output Current Monitor Pins
nn Synchronizable Fixed Frequency: 100kHz to 400kHz
nn Integrated Input Current, Input Voltage, Output Current and Output Voltage Feedback Loops
nn Improved Light Load Transition from DCM to FCM
nn Improved IMON_OUT, IMON_IN Offset When Cold
nn Clock Output Usable To Monitor Die Temperature
The LT®8705A is a high performance buck-boost switching regulator controller that operates from input voltages
above, below or equal to the output voltage. The part has
integrated input current, input voltage, output current
and output voltage feedback loops. With a wide 2.8V to
80V input and 1.3V to 80V output range, the LT8705A
is compatible with most solar, automotive, telecom and
battery-powered systems. The LT8705A is an improved pin
compatible version of the LT8705 and is recommended for
new designs. See LT8705A vs LT8705 in the Applications
Information section for more information.
nn
The LT8705A includes a MODE pin to select among Burst
Mode® operation, discontinuous or continuous conduction mode at light loads. Additional features include a
3.3V/12mA LDO, a synchronizable fixed operating frequency, and onboard gate drivers.
Applications
nn
nn
High Voltage Buck-Boost Converters
Input or Output Current Limited Converters
L, LT, LTC, LTM, Linear Technology, Burst Mode, µModule and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Typical Application
Telecom Voltage Stabilizer
M1
×2
+
22µH
4.7µF
×4
220µF
×2
M3
×2
M2
TO
DIODE
0.22µF
2Ω
×2
TG1 BOOST1 SW1 BG1 CSP
M4
1nF
10Ω
1nF
10Ω
CSN
CSPOUT
CSPIN
CSNOUT
4.7µF
SRVO_FBOUT
SRVO_IIN
SS
SRVO_IOUT
1µF
VC
CLKOUT
SYNC
IMON_OUT
4
90
3
2
85
80
1
VOUT = 48V
ILOAD = 2A
4Ω
TO
TO
BOOST1 BOOST2
POWER LOSS (W)
4.7µF
SRVO_FBIN
IMON_IN
4.7µF
10k
INTVCC
GATEVCC
LT8705A
RT
215k
5
FBOUT
SWEN
6
95
EXTVCC
SHDN
FBIN
20k
100
GND BG2 SW2 BOOST2 TG2
MODE
71.5k
Efficiency and Power Loss
392k
CSNIN
LDO33
VOUT
48V
220µF 5A
×2
0.22µF
VIN
100k
4.7µF
×6
TO
DIODE
10mΩ
2Ω
×2
+
EFFICIENCY (%)
VIN
36V TO
80V
30
40
50
60
VIN (V)
70
80
0
8705A TA01b
56.2k
1µF
220pF
3.3nF
202kHz
8705A TA01
8705af
For more information www.linear.com/LT8705A
1
LT8705A
Absolute Maximum Ratings
(Note 1)
VCSP-VCSN, VCSPIN-VCSNIN,
VCSPOUT-VCSNOUT...................................... –0.3V to 0.3V
SS, CLKOUT, CSP, CSN Voltage.................... –0.3V to 3V
VC Voltage (Note 2).................................... –0.3V to 2.2V
RT, LDO33, FBOUT Voltage........................... –0.3V to 5V
IMON_IN, IMON_OUT Voltage...................... –0.3V to 5V
SYNC Voltage............................................. –0.3V to 5.5V
INTVCC, GATEVCC Voltage............................. –0.3V to 7V
VBOOST1-VSW1, VBOOST2-VSW2...................... –0.3V to 7V
SWEN, MODE Voltage................................... –0.3V to 7V
SRVO_FBIN, SRVO_FBOUT Voltage............ –0.3V to 30V
SRVO_IIN, SRVO_IOUT Voltage.................. –0.3V to 30V
FBIN, SHDN Voltage.................................... –0.3V to 30V
CSNIN, CSPIN, CSPOUT, CSNOUT Voltage...–0.3V to 80V
VIN, EXTVCC Voltage................................... –0.3V to 80V
SW1, SW2 Voltage.......................................81V (Note 7)
BOOST1, BOOST2 Voltage.......................... –0.3V to 87V
BG1, BG2, TG1, TG2............................................ (Note 6)
Operating Junction Temperature Range
LT8705AE (Notes 3, 8)........................ –40°C to 125°C
LT8705AI (Notes 3, 8)......................... –40°C to 125°C
LT8705AH (Notes 3, 8)....................... –40°C to 150°C
LT8705AMP (Notes 3, 8).................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package........................................................ 300°C
Pin Configuration
INTVCC
1
38 VIN
CSNIN
TOP VIEW
MODE
2
37 CSPIN
IMON_IN
3
36 CSNIN
38 37 36 35 34 33 32
SHDN
4
CSPIN
VIN
INTVCC
SWEN
MODE
IMON_IN
TOP VIEW
SHDN 1
31 CSPOUT
CSN
5
CSN 2
30 CSNOUT
CSP
6
CSP 3
29 EXTVCC
LDO33
7
FBIN
8
FBOUT
9
28 SRVO_FBOUT
LDO33 4
27 SRVO_IOUT
FBIN 5
FBOUT 6
26 SRVO_IIN
39
GND
IMON_OUT 7
IMON_OUT 10
25 SRVO_FBIN
VC 8
24 NC
SS 9
23 BOOST1
CLKOUT 10
22 TG1
SYNC 11
21 SW1
VC 11
CLKOUT 13
SW2
TG2
BOOST2
BG2
GATEVCC
BG1
GND
30 EXTVCC
39
GND
28 BOOST1
26 TG1
SYNC 14
RT 15
24 SW1
GND 16
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
32 CSNOUT
SS 12
20 NC
RT 12
34 CSPOUT
BG1 17
22 SW2
GATEVCC 18
21 TG2
BG2 19
20 BOOST2
FE PACKAGE
VARIATION: FE38(31)
38-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
8705af
2
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LT8705A
Order Information
http://www.linear.com/product/LT8705A#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8705AEUHF#PBF
LT8705AEUHF#TRPBF
8705A
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LT8705AIUHF#PBF
LT8705AIUHF#TRPBF
8705A
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
LT8705AEFE#PBF
LT8705AEFE#TRPBF
LT8705AFE
38-Lead Plastic TSSOP
–40°C to 125°C
LT8705AIFE#PBF
LT8705AIFE#TRPBF
LT8705AFE
38-Lead Plastic TSSOP
–40°C to 125°C
LT8705AHFE#PBF
LT8705AHFE#TRPBF
LT8705AFE
38-Lead Plastic TSSOP
–40°C to 150°C
LT8705AMPFE#PBF
LT8705AMPFE#TRPBF
LT8705AFE
38-Lead Plastic TSSOP
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Supplies and Regulators
VIN Operating Voltage Range
EXTVCC = 0V
EXTVCC = 7.5V
VIN Quiescent Current
Not Switching, VEXTVCC = 0
VIN Quiescent Current in Shutdown
VSHDN = 0V
EXTVCC Switchover Voltage
IINTVCC = 20mA, VEXTVCC Rising
l
l
5.5
2.8
4.2
mA
l
6.15
0
1
µA
6.4
6.6
V
0.18
Maximum Current Draw from INTVCC and LDO33
Pins Combined. Regulated from VIN or EXTVCC (12V)
l
INTVCC = 5.25V
l
INTVCC = 4.5V
INTVCC Voltage
Regulated from VIN, IINTVCC = 20mA
Regulated from EXTVCC (12V), IINTVCC = 20mA
INTVCC Load Regulation
IINTVCC = 0mA to 50mA
INTVCC, GATEVCC Undervoltage Lockout
INTVCC Falling, GATEVCC Connected to INTVCC
INTVCC, GATEVCC Undervoltage Lockout Hysteresis
GATEVCC Connected to INTVCC
INTVCC Regulator Dropout Voltage
VIN-VINTVCC, IINTVCC = 20mA
LDO33 Pin Voltage
5mA from LDO33 Pin
LDO33 Pin Load Regulation
ILDO33 = 0.1mA to 5mA
LDO33 Pin Current Limit
LDO33 Pin Undervoltage Lockout
V
V
2.65
EXTVCC Switchover Hysteresis
INTVCC Current Limit
80
80
l
l
l
l
l
LDO33 Falling
V
90
28
127
42
165
55
mA
mA
6.15
6.15
6.35
6.35
6.55
6.55
V
V
–0.5
–1.5
%
4.65
4.85
V
4.45
3.23
160
mV
245
mV
3.295
3.35
V
–0.25
–1
%
12
17.25
22
mA
2.96
3.04
3.12
LDO33 Pin Undervoltage Lockout Hysteresis
35
V
mV
Switching Regulator Control
Maximum Current Sense Threshold (VCSP – VCSN)
Maximum Current Sense Threshold (VCSN – VCSP)
Boost Mode, Minimum M3 Switch Duty Cycle
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
l
l
102
100
117
117
132
134
mV
mV
Buck Mode, Minimum M2 Switch Duty Cycle
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
l
l
69
67
86
86
102
104
mV
mV
8705af
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3
LT8705A
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER
CONDITIONS
Gain from VC to Maximum Current Sense Voltage
(VCSP-VCSN) (A5 in the Block Diagram)
Boost Mode
Buck Mode
SHDN Input Voltage High
SHDN Rising to Enable the Device
MIN
TYP
MAX
150
–150
l
mV/V
mV/V
1.184 1.234 1.284
SHDN Input Voltage High Hysteresis
50
SHDN Input Voltage Low
Device Disabled, Low Quiescent Current
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
SHDN Pin Bias Current
l
l
VSHDN = 3V
VSHDN = 12V
SWEN Rising Threshold Voltage (Note 5)
0
11
l
0.35
0.3
V
V
1
22
µA
µA
22
MODE Pin Forced Continuous Mode Threshold
l
0.4
MODE Pin Burst Mode Range
l
1.0
MODE Pin Discontinuous Mode Threshold
l
Soft-Start Charging Current
VSS = 0.5V
Soft-Start Discharge Current
VSS = 0.5V
13
V
mV
1.156 1.206 1.256
SWEN Threshold Voltage Hysteresis (Note 5)
UNITS
V
mV
V
19
1.7
V
2.3
V
25
µA
9.5
µA
Voltage Regulator Loops (Refer to Block Diagram to Locate Amplifiers)
Regulation Voltage for FBOUT
VC = 1.2V (LT8705AE, LT8705AI)
VC = 1.2V (LT8705AH, LT8705AMP)
l
l
1.193 1.207 1.222
1.191 1.207 1.222
V
V
Regulation Voltage for FBIN
VC = 1.2V (LT8705AE, LT8705AI)
VC = 1.2V (LT8705AH, LT8705AMP)
l
l
1.184 1.205 1.226
1.182 1.205 1.226
V
V
Line Regulation for FBOUT and FBIN Error Amp Reference
Voltage
VIN = 12V to 80V; Not Switching
0.002 0.005
%/V
FBOUT Pin Bias Current
Current Out of Pin
15
nA
FBOUT Error Amp EA4 gm
315
µmho
FBOUT Error Amp EA4 Voltage Gain
220
V/V
10
nA
FBIN Error Amp EA3 gm
130
µmho
FBIN Error Amp EA3 Voltage Gain
90
V/V
FBIN Pin Bias Current
Current Out of Pin
SRVO_FBIN Activation Threshold (Note 5)
(VFBIN Falling) – (Regulation Voltage for FBIN),
VFBOUT = VIMON_IN = VIMON_OUT = 0V
SRVO_FBIN Activation Threshold Hysteresis (Note 5)
VFBOUT = VIMON_IN = VIMON_OUT = 0V
SRVO_FBOUT Activation Threshold (Note 5)
(VFBOUT Rising) – (Regulation Voltage for FBOUT),
VFBIN = 3V, VIMON_IN = VIMON_OUT = 0V
SRVO_FBOUT Activation Threshold Hysteresis (Note 5)
VFBIN = 3V, VIMON_IN = 0V, VIMON_OUT = 0V
SRVO_FBIN, SRVO_FBOUT Low Voltage (Note 5)
I = 100μA
l
110
330
mV
SRVO_FBIN, SRVO_FBOUT Leakage Current (Note 5)
VSRVO_FBIN = VSRVO_FBOUT = 2.5V
l
0
1
µA
l
1.187 1.208 1.229
V
0.002 0.005
%/V
56
72
89
33
–37
–29
mV
mV
–21
15
mV
mV
Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers)
Regulation Voltages for IMON_IN and IMON_OUT
VC = 1.2V
Line Regulation for IMON_IN and IMON_OUT Error Amp
Reference Voltage
VIN = 12V to 80V; Not Switching
CSPIN, CSNIN Bias Current
BOOST Capacitor Charge Control Block Not Active
ICSPIN + ICSNIN, VCSPIN = VCSNIN = 12V
31
µA
8705af
4
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LT8705A
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CSPIN, CSNIN Common Mode Operating Voltage Range
l
1.5
80
V
CSPIN, CSNIN Differential Operating Voltage Range
l
–100
100
mV
l
l
0.95
0.94
0.93
1.05
1.06
1.07
mmho
mmho
mmho
IMON_IN Maximum Output Current
l
100
IMON_IN Overvoltage Threshold
l
1.55
VCSPIN-CSNIN to IMON_IN Amplifier A7 gm
VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V
(All Grades)
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
1
1
1
µA
1.61
1.67
V
IMON_IN Error Amp EA2 gm
185
µmho
IMON_IN Error Amp EA2 Voltage Gain
130
V/V
45
4
µA
µA
CSPOUT, CSNOUT Bias Current
BOOST Capacitor Charge Control Block Not Active
ICSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 12V
ICSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 1.5V
CSPOUT, CSNOUT Common Mode Operating Voltage Range
l
0
80
V
CSPOUT, CSNOUT Differential Mode Operating Voltage
Range
l
–100
100
mV
l
l
0.95
0.94
0.93
1
1
1
1.05
1.085
1.095
mmho
mmho
mmho
l
l
0.65
0.55
0.5
1
1
1
1.35
1.6
1.65
mmho
mmho
mmho
IMON_OUT Maximum Output Current
l
100
IMON_OUT Overvoltage Threshold
l
1.55
VCSPOUT-CSNOUT to IMON_OUT Amplifier A6 gm
VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V
(All Grades)
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V
(All Grades)
(LT8705AE, LT8705AI)
(LT8705AH, LT8705AMP)
µA
1.61
1.67
V
IMON_OUT Error Amp EA1 gm
185
µmho
IMON_OUT Error Amp EA1 Voltage Gain
130
V/V
SRVO_IIN Activation Threshold (Note 5)
(VIMON_IN Rising) – (Regulation Voltage for
IMON_IN), VFBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V
SRVO_IIN Activation Threshold Hysteresis (Note 5)
VFBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V
SRVO_IOUT Activation Threshold (Note 5)
(VIMON_OUT Rising) – (Regulation Voltage for IMON_
OUT), VFBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V
SRVO_IOUT Activation Threshold Hysteresis (Note 5)
VFBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V
SRVO_IIN, SRVO_IOUT Low Voltage (Note 5)
I = 100μA
l
110
330
mV
SRVO_IIN, SRVO_IOUT Leakage Current (Note 5)
VSRVO_IIN = VSRVO_IOUT = 2.5V
l
0
1
µA
–60
–49
–37
22
–62
–51
mV
mV
–39
22
mV
mV
NMOS Gate Drivers
TG1, TG2 Rise Time
CLOAD = 3300pF (Note 4)
20
ns
TG1, TG2 Fall Time
CLOAD = 3300pF (Note 4)
20
ns
BG1, BG2 Rise Time
CLOAD = 3300pF (Note 4)
20
ns
BG1, BG2 Fall Time
CLOAD = 3300pF (Note 4)
20
ns
TG1 Off to BG1 On Delay
CLOAD = 3300pF Each Driver
100
ns
BG1 Off to TG1 On Delay
CLOAD = 3300pF Each Driver
80
ns
TG2 Off to BG2 On Delay
CLOAD = 3300pF Each Driver
100
ns
8705af
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5
LT8705A
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER
CONDITIONS
BG2 Off to TG2 On Delay
CLOAD = 3300pF Each Driver
MIN
TYP
80
MAX
UNITS
ns
Minimum On-Time for Main Switch in Boost Operation
(tON(M3,MIN))
Switch M3, CLOAD = 3300pF
265
ns
Minimum On-Time for Synchronous Switch in Buck
Operation (tON(M2,MIN))
Switch M2, CLOAD = 3300pF
260
ns
Minimum Off-Time for Main Switch in Steady-State Boost
Operation
Switch M3, CLOAD = 3300pF
245
ns
Minimum Off-Time for Synchronous Switch in
Steady-State Buck Operation
Switch M2, CLOAD = 3300pF
245
ns
Oscillator
Switch Frequency Range
SYNCing or Free Running
Switching Frequency, fOSC
RT = 365k
RT = 215k
RT = 124K
100
l
l
l
102
170
310
SYNC High Level for Synchronization
l
1.3
SYNC Low Level for Synchronization
l
SYNC Clock Pulse Duty Cycle
VSYNC = 0V to 2V
120
202
350
kHz
142
235
400
kHz
kHz
kHz
V
0.5
V
80
%
2.45
2.55
V
25
100
mV
20
Recommended Minimum SYNC Ratio fSYNC/fOSC
400
3/4
CLKOUT Output Voltage High
1mA Out of CLKOUT Pin
CLKOUT Output Voltage Low
1mA Into CLKOUT Pin
CLKOUT Duty Cycle
TJ = –40°C
TJ = 25°C
TJ = 125°C
CLKOUT Rise Time
2.3
22.7
44.1
77
%
%
%
CLOAD = 200pF
30
ns
CLKOUT Fall Time
CLOAD = 200pF
25
ns
CLKOUT Phase Delay
SYNC Rising to CLKOUT Rising, fOSC = 100kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not force voltage on the VC pin.
Note 3: The LT8705AE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8705AI is guaranteed over the full –40°C to 125°C junction temperature
range. The LT8705AH is guaranteed over the full –40°C to 150°C operating
junction temperature range. The LT8705AMP is guaranteed over the full
–55°C to 150°C operating junction temperature range. Operating lifetime is
derated at junction temperatures greater than 125°C.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
l
160
180
200
Deg
Note 5: This specification not applicable in the FE38 package.
Note 6: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 7: Negative voltages on the SW1 and SW2 pins are limited, in an
application, by the body diodes of the external NMOS devices, M2 and
M3, or parallel Schottky diodes when present. The SW1 and SW2 pins
are tolerant of these negative voltages in excess of one diode drop below
ground, guaranteed by design.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability.
8705af
6
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LT8705A
Typical Performance Characteristics
Efficiency vs Output Current
(Boost Region-Figure 15)
Efficiency vs Output Current
(Buck-Boost Region-Figure 15)
100
100
90
90
80
80
70
70
70
60
50
40
VIN = 36V
VOUT = 48V
BURST
FCM
DCM
20
10
1000
100
LOAD CURRENT (mA)
10
60
50
40
VIN = 48V
VOUT = 48V
BURST
FCM
DCM
30
20
10
0
10000
1000
100
LOAD CURRENT (mA)
10
VC = 1.2V
0
1.19
IMON_OUT
IMON_IN
FBOUT
FBIN
1.18
1.17
–55 –30 –5
VC = 1.2V
300
1.21
1.20
1.19
1.17
–45
BUCK REGION
40
20
0
20
40
60
80
M2 OR M3 DUTY CYCLE (%)
100
55
30
80
5
TEMPERATURE (°C)
–20
105
0
–40 –20
130
0
20 40 60 80
TEMPERATURE (°C)
120
120
100
100
80
80
60
60
40
40
BUCK REGION
20
20
BOOST REGION
0
0
–20
–20
–40
–40
–60
–60
–80
0.5
1.5
1
100 120
8705A G06
Maximum Inductor Current Sense
Voltage at Minimum Duty Cycle
2
–80
VC (V)
8705A G07
RT = 365k
50
8705A G08
120
BOOST REGION
100
CSP-CSN (mV)
CSN-CSP (mV)
100
60
150
Inductor Current Sense Voltage at
Minimum Duty Cycle
140
BOOST REGION
RT = 215k
200
8705A G05
Maximum Inductor Current Sense
Voltage vs Duty Cycle
80
250
100
8705A G04
120
RT = 124k
350
1.18
20 45 70 95 120 145
TEMPERATURE (°C)
10000
Oscillator Frequency
400
FREQUENCY (kHz)
1.20
1000
100
LOAD CURRENT (mA)
10
8705A G03
1.22
FBOUT VOLTAGE (V)
PIN VOLTAGE (V)
1.22
0
10
FBOUT Voltages (Five Parts)
1.23
1.21
VIN = 72V
VOUT = 48V
BURST
FCM
DCM
8705A G02
Feedback Voltages
1.23
50
40
20
10000
8705A G01
60
30
|CSP-CSN| (mV)
0
EFFICIENCY (%)
90
80
30
|CSP-CSN| (mV)
Efficiency vs Output Current
(Buck Region-Figure 15)
100
EFFICIENCY (%)
EFFICIENCY (%)
TA = 25°C unless otherwise specified.
80
BUCK REGION
60
40
20
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
8705A G09
8705af
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7
LT8705A
Typical Performance Characteristics
Minimum Inductor Current Sense
Voltage in Forced Continuous Mode
INTVCC Line Regulation
(EXTVCC = 0V)
0
7.0
6.5
BUCK REGION
–40
6.5
–60
–80
5.5
4.5
–120
0
20
40
60
4.0
100
80
M2 OR M3 DUTY CYCLE (%)
6
4
8
10
12 14
VIN (V)
16
3.5
MAXIMUM VC (V)
IIN (mA)
1.0
0.8
0.6
2.0
1.5
125°C
25°C
–40°C
0.5
0.2
0
0.2
0.4
0.6 0.8
SS (V)
1.0
1.2
0
1.4
5
15
25
35
45
VIN (V)
55
65
150
125
100
75
50
25
0
–25
–100
75
8705A G14
8705A G13
LDO33 Pin Regulation
(ILDO33 = 1mA)
CLKOUT Duty Cycle
–50
0
50
200
100
150
CSPIN-CSNIN (mV)
CSPOUT-CSNOUT (mV)
8705A G15
SHDN and SWEN Pin Thresholds
vs Temperature
3.5
100
12
175
1.0
0.4
0
GATEVCC CONNECTED TO INTVCC
2.5
1.2
10
IMON Output Currents
3.0
BUCK
REGION
1.4
8
EXTVCC (V)
200
IMON_OUT, IMON_IN (µA)
BOOST AND
BUCK-BOOST REGIONS
6
8705A G12
VIN Supply Current vs Voltage
(Not Switching)
TJ = 25°C
1.6
4
8705A G11
Maximum VC vs SS
1.8
5.5
20
18
8705A G10
2.0
EXTVCC FALLING
6.0
5.0
BOOST REGION
–100
EXTVCC RISING
INTVCC (V)
6.0
INTVCC (V)
–|CSP-CSN| (mV)
INTVCC Line Regulation
(VIN = 12V)
7.0
–20
–140
TA = 25°C unless otherwise specified.
1.30
60
LDO (V)
DUTY CYCLE (%)
3.0
40
2.0
20
0
–50 –25
2.5
0
25 50
75 100 125 150
TEMPERATURE (°C)
8705A G16
1.5
2.5
125°C
25°C
–40°C
3
3.5
4
4.5
5
5.5
6
INTVCC (V)
8705A G17
PIN THRESHOLD VOLTAGE (V)
1.28
80
1.26
1.24
1.22
RISING
1.20
1.18
FALLING
1.16
1.14
1.12
SHDN
SWEN
1.10
–55 –35 –15 5 25 45 65 85 105 125 145
TEMPERATURE (°C)
8705A G18
8705af
8
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LT8705A
Typical Performance Characteristics
SRVO_xx Pin Activation
Thresholds
Internal VIN UVLO
SHDN and MODE Pin Currents
3.0
16
MODE
14
125
VPIN-VREGULATION
VPIN APPROACHING VREGULATION (mV)
18
2.5
SHDN
12
VIN UVLO (V)
CURRENT INTO PIN (µA)
TA = 25°C unless otherwise specified.
10
8
6
4
2
2.0
1.5
1.0
0.5
0
–2
0
3
6
9
0
–40 –20
12 15 18 21 24 27 30
PIN VOLTAGE (V)
0
20 40 60 80
TEMPERATURE (°C)
75
50
FBIN
FBOUT
IMON_IN
IMON_OUT
25
0
–25
–50
–75
–50 –25
100 120
0
25 50 75 100 125 150
TEMPERATURE (°C)
8705A G20
8705A G19
SRVO_xx Pin Activation
Threshold Hysteresis
PIN ACTIVATION THRESHOLD HYSTERSIS (mV)
100
8705A G21
Forced Continuous Mode
(Figure 15)
Discontinuous Mode (Figure 15)
50
40
SW1
20V/DIV
SW1
50V/DIV
30
20
FBIN
FBOUT
IMON_IN
IMON_OUT
10
0
–50 –25
0
SW2
20V/DIV
SW2
50V/DIV
IL
2A/DIV
IL
2A/DIV
25 50
75 100 125 150
TEMPERATURE (°C)
VIN = 72V
VOUT = 48V
8705A G23
5µs/DIV
VIN = 36V
VOUT = 48V
5µs/DIV
8705A G24
8705A G22
Forced Continuous Mode
(Figure 14)
Forced Continuous Mode
(Figure 14)
SW1
20V/DIV
SW1
50V/DIV
SW2
20V/DIV
SW2
20V/DIV
IL
2A/DIV
IL
2A/DIV
VIN = 48V
VOUT = 48V
5µs/DIV
8705A G25
VIN = 72V
VOUT = 48V
5µs/DIV
8705A G26
8705af
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9
LT8705A
Typical Performance Characteristics
Burst Mode Operation (Figure 14)
TA = 25°C unless otherwise specified.
VOUT
500mV/DIV
VOUT
100mV/DIV
VOUT
100mV/DIV
IL
2A/DIV
IL
5A/DIV
IL
1A/DIV
VIN = 36V
VOUT = 48V
2ms/DIV
8705A G27
VIN = 72V
VOUT = 48V
8705A G28
5ms/DIV
Load Step (Figure 14)
VIN = 36V
500µs/DIV
VOUT = 48V
LOAD STEP = 1A TO 3A
8705A G29
Load Step (Figure 14)
VOUT
500mV/DIV
VOUT
500mV/DIV
IL
2A/DIV
IL
2A/DIV
VIN = 72V
500µs/DIV
VOUT = 48V
LOAD STEP = 1A TO 3A
8705A G30
VIN = 48V
500µs/DIV
VOUT = 48V
LOAD STEP = 1A TO 3A
Line Transient (Figure 14)
8705A G31
Line Transient (Figure 14)
VIN
36V TO 72V
VIN
72V TO 36V
VC
0.5V/DIV
VC
0.5V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IL
2A/DIV
IL
2A/DIV
2ms/DIV
Load Step (Figure 14)
Burst Mode Operation (Figure 14)
8705A G32
2ms/DIV
8705A G33
8705af
10
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LT8705A
Pin Functions
(QFN/TSSOP)
SHDN (Pin 1/Pin 4): Shutdown Pin. Tie high to enable
device. Ground to shut down and reduce quiescent current
to a minimum. Do not float this pin.
RT (Pin 12/Pin 15): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to
set the free-running frequency. Do not float this pin.
CSN (Pin 2/Pin 5): The (–) Input to the Inductor Current
Sense and Reverse-Current Detect Amplifier.
BG1, BG2 (Pins 14, 16/Pins 17, 19): Bottom Gate Drive.
Drives the gates of the bottom N-channel MOSFETs between
ground and GATEVCC.
CSP (Pin 3/Pin 6): The (+) Input to the Inductor Current
Sense and Reverse-Current Detect Amplifier. The VC pin
voltage and built-in offsets between CSP and CSN pins, in
conjunction with the RSENSE resistor value, set the current
trip threshold.
LDO33 (Pin 4/Pin 7): 3.3V Regulator Output. Bypass this
pin to ground with a minimum 0.1μF ceramic capacitor.
FBIN (Pin 5/Pin 8): Input Feedback Pin. This pin is connected to the input error amplifier input.
FBOUT (Pin 6/Pin 9): Output Feedback Pin. This pin
connects the error amplifier input to an external resistor
divider from the output.
IMON_OUT (Pin 7/Pin 10): Output Current Monitor Pin. The
current out of this pin is proportional to the output current.
See the Operation and Applications Information sections.
VC (Pin 8/Pin 11): Error Amplifier Output Pin. Tie external
compensation network to this pin.
SS (Pin 9/Pin 12): Soft-Start Pin. Place at least 100nF of
capacitance here. Upon start-up, this pin will be charged
by an internal resistor to 2.5V.
CLKOUT (Pin 10/Pin 13): Clock Output Pin. Use this pin
to synchronize one or more compatible switching regulator ICs to the LT8705A. CLKOUT toggles at the same
frequency as the internal oscillator or as the SYNC pin,
but is approximately 180° out of phase. CLKOUT may also
be used as a temperature monitor since the CLKOUT duty
cycle varies linearly with the part’s junction temperature.
The CLKOUT pin can drive capacitive loads up to 200pF.
SYNC (Pin 11/Pin 14): To synchronize the switching frequency to an outside clock, simply drive this pin with a
clock. The high voltage level of the clock needs to exceed
1.3V, and the low level should be less than 0.5V. Drive this
pin to less than 0.5V to revert to the internal free-running
clock. See the Applications Information section for more
information.
GATEVCC (Pin 15/Pin 18): Power Supply for Gate Drivers.
Must be connected to the INTVCC pin. Do not power from
any other supply. Locally bypass to GND.
BOOST1, BOOST2 (Pins 23, 17/Pins 28, 20): Boosted
Floating Driver Supply. The (+) terminal of the bootstrap
capacitor connects here. The BOOST1 pin swings from a
diode voltage below GATEVCC up to VIN + GATEVCC. The
BOOST2 pin swings from a diode voltage below GATEVCC
up to VOUT + GATEVCC
TG1, TG2 (Pins 22, 18/Pins 26, 21): Top Gate Drive. Drives
the top N-channel MOSFETs with voltage swings equal
to GATEVCC superimposed on the switch node voltages.
SW1, SW2 (Pins 21, 19/Pins 24, 22): Switch Nodes. The
(–) terminals of the bootstrap capacitors connect here.
SRVO_FBIN (Pin 25 QFN Only): Open-Drain Logic Output. This pin is pulled to ground when the input voltage
feedback loop is active.
SRVO_IIN (Pin 26 QFN Only): Open-Drain Logic Output.
The pin is pulled to ground when the input current loop
is active.
SRVO_IOUT (Pin 27 QFN Only): Open-Drain Logic Output. The pin is pulled to ground when the output current
feedback loop is active.
SRVO_FBOUT (Pin 28 QFN Only): Open-Drain Logic Output. This pin is pulled to ground when the output voltage
feedback loop is active.
EXTVCC (Pin 29/Pin 30): External VCC Input. When EXTVCC
exceeds 6.4V (typical), INTVCC will be powered from this
pin. When EXTVCC is lower than 6.22V (typical), INTVCC
will be powered from VIN.
CSNOUT (Pin 30/Pin 32): The (–) Input to the Output Current Monitor Amplifier. Connect this pin to VOUT when not
in use. See Applications Information section for proper
use of this pin.
8705af
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11
LT8705A
Pin Functions
(QFN/TSSOP)
CSPOUT (Pin 31/Pin 34): The (+) Input to the Output
Current Monitor Amplifier. This pin and the CSNOUT pin
measure the voltage across the sense resistor, RSENSE2,
to provide the output current signals. Connect this pin
to VOUT when not in use. See Applications Information
section for proper use of this pin.
CSNIN (Pin 32/Pin 36): The (–) Input to the Input Current
Monitor Amplifier. This pin and the CSPIN pin measure
the voltage across the sense resistor, RSENSE1, to provide
the input current signals. Connect this pin to VIN when not
in use. See Applications Information section for proper
use of this pin.
CSPIN (Pin 33/Pin 37): The (+) Input to the Input Current Monitor Amplifier. Connect this pin to VIN when not
in use. See Applications Information section for proper
use of this pin.
SWEN (Pin 36 QFN Only): Switch Enable Pin. Tie high
to enable switching. Ground to disable switching. Don’t
float this pin. This pin is internally tied to INTVCC in the
TSSOP package.
IMON_IN (Pin 38/Pin 3): Input Current Monitor Pin. The
current out of this pin is proportional to the input current.
See the Operation and Applications Information sections.
MODE (Pin 37/Pin 2): Mode Pin. The voltage applied to
this pin sets the operating mode of the controller. When
the applied voltage is less than 0.4V, the forced continuous current mode is active. When this pin is allowed to
float, Burst Mode operation is active. When the MODE pin
voltage is higher than 2.3V, discontinuous mode is active.
GND (Pin 13, Exposed Pad Pin 39/Pin 16, Exposed Pad
Pin 39): Ground. Tie directly to local ground plane.
VIN (Pin 34/Pin 38): Main Input Supply Pin. It must be
locally bypassed to ground.
INTVCC (Pin 35/Pin 1): Internal 6.35V Regulator Output.
Must be connected to the GATEVCC pin. INTVCC is powered
from EXTVCC when the EXTVCC voltage is higher than 6.4V,
otherwise INTVCC is powered from VIN . Bypass this pin to
ground with a minimum 4.7μF ceramic capacitor.
8705af
12
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LT8705A
Block Diagram
VIN
RSENSE1
RSENSE
CSN
SWEN
CSP
DB1
BOOST1
CSNIN
–
CSPIN
+
+
+
A7
M1
SW1
–
A5
CB1
TG1
A8
M2
BUCK
LOGIC
–
D1
(OPT)
GATEVCC
VIN
BG1
IMON_IN
GND
MODE
BOOST CAPACITOR
CHARGE CONTROL
BG2
CLKOUT
SYNC
OSC
RT
M3
SW2
BOOST
LOGIC
TG2
+
CB2
BOOST2
A9
–
DB2
2.5V
OT
OI_IN
OI_OUT
STARTUP
AND FAULT
LOGIC
SS
+
CSPOUT
–
CSNOUT
A6
FAULT_INT
RSENSE2
VOUT
IMON_OUT
–
UV_INTVCC
M4
D2
(OPT)
EA1
+
UV_LDO33
RSHDN1
UV_VIN
UV_GATEVCC
1.208V
+
SHDN
EA2
+
–
RSHDN2
VIN
IMON_IN
–
1.234V
+
EXTVCC
–
6.35V
LDO
REG
EA3
+
6.4V
EN
FBIN
EN 6.35V
LDO
REG
3.3V
LDO
REG
LDO
REG
VIN
INTVCC
1.205V
+
1.207V
–
INTERNAL
SUPPLY1
LDO33
RFBIN2
–
EA4
INTERNAL
SUPPLY2
FBOUT
VC
SRVO_IOUT
SRVO_IIN
SRVO_FBIN
RFBIN1
RFBOUT1
RFBOUT2
SRVO_FBOUT
8705A F01
Figure 1. Block Diagram
8705af
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13
LT8705A
Operation
Refer to the Block Diagram (Figure 1) when reading the
following sections about the operation of the LT8705A.
Main Control Loop
The LT8705A is a current mode controller that provides an
output voltage above, equal to or below the input voltage.
The LTC® proprietary topology and control architecture
employs a current-sensing resistor (RSENSE) in buck or
boost modes. The inductor current is controlled by the
voltage on the VC pin, which is the diode-AND of error
amplifiers EA1-EA4. In the simplest form, where the output
is regulated to a constant voltage, the FBOUT pin receives
the output voltage feedback signal, which is compared to
the internal reference voltage by EA4. Low output voltages
would create a higher VC voltage, and thus more current
would flow into the output. Conversely, higher output voltages would cause VC to drop, thus reducing the current
fed into the output.
The LT8705A contains four error amplifiers (EA1-EA4)
allowing it to regulate or limit the output current (EA1),
input current (EA2), input voltage (EA3) and/or output
voltage (EA4). In a typical application, the output voltage
might be regulated using EA4, while the remaining error
amplifiers are monitoring for excessive input or output
current or an input undervoltage condition. In other applications, such as a battery charger, the output current
regulator (EA1) can facilitate constant current charging
until a predetermined voltage is reached where the output
voltage (EA4) control would take over.
INTVCC/EXTVCC/GATEVCC/LDO33 Power
Power for the top and bottom MOSFET drivers, the LDO33
pin and most internal circuitry is derived from the INTVCC
pin. INTVCC is regulated to 6.35V (typical) from either the
VIN or EXTVCC pin. When the EXTVCC pin is left open or
tied to a voltage less than 6.22V (typical), an internal low
dropout regulator regulates INTVCC from VIN. If EXTVCC
is taken above 6.4V (typical), another low dropout regulator will instead regulate INTVCC from EXTVCC. Regulating
INTVCC from EXTVCC allows the power to be derived
from the lowest supply voltage (highest efficiency) such
as the LT8705A switching regulator output (see INTVCC
Regulators and EXTVCC Connection in the Applications
Information section for more details).
14
The GATEVCC pin directly powers the bottom MOSFET
drivers for switches M2 and M3. GATEVCC should always
be connected to INTVCC and should not be powered or
connected to any other source. Undervoltage lock outs
(UVLOs) monitoring INTVCC and GATEVCC disable the
switching regulator when the pins are below 4.65V (typical).
The LDO33 pin is available to provide power to external
components such as a microcontroller and/or to provide an
accurate bias voltage. Load current is limited to 17.25mA
(typical). As long as SHDN is high the LDO33 output is
linearly regulated from the INTVCC pin and is not affected
by the INTVCC or GATEVCC UVLOs or the SWEN pin voltage.
LDO33 will remain regulated as long as SHDN is high and
sufficient voltage is available on INTVCC (typically > 4.0V).
An undervoltage lockout, monitoring LDO33, will disable the
switching regulator when LDO33 is below 3.04V (typical).
Start-Up
Figure 2 illustrates the start-up sequence for the LT8705A.
The master shutdown pin for the chip is SHDN. When driven
below 0.35V (LT8705AE, LT8705AI) or 0.3V (LT8705AH,
LT8705AMP) the chip is disabled (chip off state) and quiescent current is minimal. Increasing the SHDN voltage
can increase quiescent current but will not enable the chip
until SHDN is driven above 1.234V (typical) after which
the INTVCC and LDO33 regulators are enabled (switcher
off state). External devices powered by the LDO33 pin can
become active at this time if enough voltage is available
on VIN or EXTVCC to raise INTVCC, and thus LDO33, to an
adequate voltage.
Starting up the switching regulator happens after SWEN
(switcher enable) is also driven above 1.206V (typical),
INTVCC and GATEVCC have risen above 4.81V (typical) and
the LDO33 pin has risen above 3.08V (typical) (initialize
state). The SWEN pin is not available in the TSSOP package. In this package the SWEN pin is internally connected
to INTVCC.
Start-Up: Soft-Start of Switch Current
In the initialize state, the SS (soft-start) pin is pulled low
to prepare for soft starting the regulator. If forced continuous mode is selected (MODE pin low), the part is put into
discontinuous mode during soft-start to prevent current
For more information www.linear.com/LT8705A
8705af
LT8705A
Operation
SHDN < 1.184V OR
VIN < 2.5V OR
TJUNCTION > 165°C
CHIP OFF
• SWITCHER OFF
• LDOs OFF
TYPICAL VALUES
TJUNCTION < 160°C
AND
SHDN > 1.234V AND VIN > 2.5V
AND
(SWEN* < 1.184V OR (INTVCC AND GATEVCC < 4.65V)
OR LDO33 < 3.04V)
TYPICAL VALUES
SWITCHER OFF
• SWITCHER DISABLED
• INTVCC AND LDO33 OUTPUTS
ENABLED
SHDN > 1.234V AND VIN > 2.5V
AND SWEN* > 1.206V AND
(INTVCC AND GATEVCC > 4.81V) AND
LDO33 > 3.075V
TYPICAL VALUES
INITIALIZE
• SS PULLED LOW
• FORCE DISCONTINOUS
MODE UNLESS Burst Mode
OPERATION SELECTED
FAULT
SS < 50mV
SOFT-START
• SS CHARGES UP
• SWITCHER ENABLED
FAULT DETECTED
FAULT
• SS CHARGES UP
• SWITCHER DISABLED
• CLKOUT DISABLED
SS > 1.6V AND
NO FAULT CONDITIONS
STILL DETECTED
NORMAL MODE
• NORMAL OPERATION
• WHEN SS > 1.6V ...
• CLKOUT ENABLED
• ENABLE FORCED
CONTINUOUS MODE
IF SELECTED
FAULT
FAULT
POST FAULT DELAY
• SS SLOWLY DISCHARGES
SS < 50mV
*SWEN IS CONNECTED TO INTVCC IN THE TSSOP PACKAGE
FAULT = OVERVOLTAGE (IMON_IN OR IMON_OUT > 1.61V TYP)
8705A F02
Figure 2. Start-Up and Fault Sequence
from being drawn out of the output and forced into the
input. After SS has been discharged to less than 50mV,
a soft-start of the switching regulator begins (soft-start
state). The soft-start circuitry provides for a gradual
ramp-up of the inductor current by gradually allowing the
VC voltage to rise (refer to VC vs SS Voltage in the Typical
Performance Characteristics). This prevents abrupt surges
of current from being drawn out of the input power supply.
An integrated 100k resistor pulls the SS pin to ≅2.5V. The
ramp rate of the SS pin voltage is set by this 100k resistor and the external capacitor connected to this pin. Once
SS gets to 1.6V, the CLKOUT pin is enabled, the part is
allowed to enter forced continuous mode (if MODE is low)
and an internal regulator pulls SS up quickly to ≅2.5V.
Typical values for the external soft-start capacitor range
from 100nF to 1μF. A minimum of 100nF is recommended.
Fault Conditions
The LT8705A activates a fault sequence under certain
operating conditions. If any of these conditions occur (see
Figure 2) the CLKOUT pin and internal switching activity
are disabled. At the same time, a timeout sequence commences where the SS pin is charged up to a minimum
of 1.6V (fault detected state). The SS pin will continue
8705af
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15
LT8705A
Operation
charging up to 2.5V and be held there in the case of a fault
event that persists. After the fault condition had ended and
SS is greater than 1.6V, SS will then slowly discharge to
50mV (post fault delay state). This timeout period relieves
the part and other downstream power components from
electrical and thermal stress for a minimum amount of
time as set by the voltage ramp rate on the SS pin. After
SS has discharged to < 50mV, the LT8705A will enter the
soft-start state and restart switching activity.
is turned on first. Inductor current is sensed by amplifier
A5 while switch M2 is on. A slope compensation ramp is
added to the sensed voltage which is then compared by A8
to a reference that is proportional to VC. After the sensed
inductor current falls below the reference, switch M2 is
turned off and switch M1 is turned on for the remainder
of the cycle. Switches M1 and M2 will alternate, behaving
like a typical synchronous buck regulator.
CLOCK
Power Switch Control
Figure 3 shows a simplified diagram of how the four power
switches are connected to the inductor, VIN, VOUT and
ground. Figure 4 shows the regions of operation for the
LT8705A as a function of VOUT -VIN or switch duty cycle
DC. The power switches are properly controlled so the
transfer between modes is continuous.
VIN
TG1
M1
L
M4
TG2
SW2
M2
M3
Figure 3. Simplified Diagram of the Output Switches
SWITCH
M3 DCMAX
VOUT -VIN
BOOST REGION
BUCK/BOOST REGION
BUCK REGION
M1 ON, M2 OFF
PWM M3, M4 SWITCHES
SWITCH
M3 DCMIN
SWITCH
M2 DCMIN
4-SWITCH PWM
M4 ON, M3 OFF
PWM M1, M2 SWITCHES
8705A F04
SWITCH
M2 DCMAX
Figure 4. Operating Regions vs VOUT-VIN
Power Switch Control: Buck Region (VIN >> VOUT)
When VIN is significantly higher than VOUT, the part will
run in the buck region. In this region switch M3 is always
off. Also, switch M4 is always on unless reverse current is
detected while in Burst Mode operation or discontinuous
mode. At the start of every cycle, synchronous switch M2
16
ON
SWITCH M4
IL
8705A F05
Figure 5. Buck Region (VIN >> VOUT)
The part will continue operating in the buck region over a
range of switch M2 duty cycles. The duty cycle of switch M2
in the buck region is given by:
8705A F03
OFF
SWITCH M3
BG2
RSENSE
0
SWITCH M2
VOUT
SW1
BG1
SWITCH M1
V
DC(M2,BUCK) = 1– OUT •100%
VIN
As VIN and VOUT get closer to each other, the duty cycle
decreases until the minimum duty cycle of the converter
in buck mode reaches DC(ABSMIN,M2,BUCK). If the duty
cycle becomes lower than DC(ABSMIN,M2,BUCK) the part
will move to the buck-boost region.
DC(ABSMIN,M2,BUCK) ≅ tON(M2,MIN) • f • 100%
where:
tON(M2,MIN) is the minimum on-time for the synchronous
switch in buck operation (260ns typical, see Electrical
Characteristics).
f is the switching frequency
When VIN is much higher than VOUT the duty cycle of
switch M2 will increase, causing the M2 switch off-time
to decrease. The M2 switch off-time should be kept above
245ns (typical, see Electrical Characteristics) to maintain
steady-state operation, avoid duty cycle jitter, increased
output ripple and reduction in maximum output current.
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8705af
LT8705A
Operation
Power Switch Control: Buck-Boost (VIN ≅ VOUT)
Power Switch Control: Boost Region (VIN 1.6V
DCM TO FCM
TRANSITION OCCURS
O
IL
10A/DIV
10µs/DIV
8705A F08b
(8b)
Figure 8. LT8705 and LT8705A Inductor Current During DCM to
FCM Transition
The operating conditions for Figures 8a and 8b were intentionally set to maximize undershoot, including having VC
at the lowest possible voltage at the time of the transition.
The second main improvement effects the IMON_IN and
IMON_OUT currents, typically when operating below
–25°C, when the respective VCSPIN – VCSNIN or VCSPOUT –
VCSNOUT voltages are very close to 0mV. Using the LT8705
under these conditions, the IMON_OUT or IMON_IN output
current can increase, above the expected amount, by a few
μA. The increased current, above the expected amount,
diminishes as VCSPIN – VCSNIN or VCSPOUT – VCSNOUT
increases and is typically gone when VCSPIN – VCSNIN or
VCSPOUT – VCSNOUT becomes 5mV or greater. The LT8705A
has been improved to eliminate the additional output current under those conditions.
• Lower VOUT – VIN during the DCM to FCM transition
20
8705A F08a
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8705af
LT8705A
Applications Information
Operating Frequency Selection
The LT8705A uses a constant frequency architecture
between 100kHz and 400kHz. The frequency can be set
using the internal oscillator or can be synchronized to an
external clock source. Selection of the switching frequency
is a trade-off between efficiency and component size.
Low frequency operation increases efficiency by reducing
MOSFET switching losses, but requires more inductance
and/or capacitance to maintain low output ripple voltage.
For high power applications, consider operating at lower
frequencies to minimize MOSFET heating from switching
losses. The switching frequency can be set by placing an
appropriate resistor from the RT pin to ground and tying
the SYNC pin low. The frequency can also be synchronized
to an external clock source driven into the SYNC pin. The
following sections provide more details.
Internal Oscillator
The operating frequency of the LT8705A can be set using
the internal free-running oscillator. When the SYNC pin
is driven low ( VIN
COUT • VIN • f
V
VOUT • 1– OUT
VIN
∆V(BUCK,CAP) ≅
V for VOUT < VIN
2
8 •L • f •COUT
The maximum output ripple due to the voltage drop across
the ESR is approximately:
∆V(BOOST,ESR) ≅
VOUT(MAX) •IOUT(MAX)
VIN(MIN)
•ESR
As with CIN, multiple capacitors placed in parallel may
be needed to meet the ESR and RMS current handling
requirements.
Schottky Diode (D1, D2) Selection
The Schottky diodes, D1 and D2, shown in Figure 1, conduct during the dead time between the conduction of the
power MOSFET switches. They are intended to prevent
the body diodes of synchronous switches M2 and M4
from turning on and storing charge. For example, D2
significantly reduces reverse-recovery current between
switch M4 turn-off and switch M3 turn-on, which improves
converter efficiency, reduces switch M3 power dissipation
and reduces noise in the inductor current sense resistor
(RSENSE) when M3 turns on. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
For applications with high input or output voltages (typically >40V) avoid Schottky diodes with excessive reverseleakage currents particularly at high temperatures. Some
ultralow VF diodes will trade off increased high temperature
leakage current for reduced forward voltage. Diode D1
can have a reverse voltage up to VIN and D2 can have
a reverse voltage up to VOUT. The combination of high
reverse voltage and current can lead to self heating of the
diode. Besides reducing efficiency, this can increase leakage current which increases temperatures even further.
Choose packages with lower thermal resistance (θJA) to
minimize self heating of the diodes.
Topside MOSFET Driver Supply (CB1, DB1, CB2, DB2)
The top MOSFET drivers (TG1 and TG2) are driven digitally
between their respective SW and BOOST pin voltages.
The BOOST voltages are biased from floating bootstrap
capacitors CB1 and CB2, which are normally recharged
through external silicon diodes DB1 and DB2 when the
respective top MOSFET is turned off. The capacitors are
charged to about 6.3V (about equal to GATEVCC) forcing the
VBOOST1-SW1 and VBOOST2-SW2 voltages to be about 6.3V.
The boost capacitors CB1 and CB2 need to store about 100
times the gate charge required by the top switches M1 and
M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R
dielectric capacitor is adequate. The bypass capacitance
from GATEVCC to GND should be at least ten times the
CB1 or CB2 capacitance.
Boost Capacitor Charge Control Block: When the LT8705A
operates exclusively in the buck or boost region, one of
the top MOSFETs, M1 or M4, can be constantly on. This
prevents the respective bootstrap capacitor, CB1 or CB2,
from being recharged through the silicon diode, DB1 or
DB2. The Boost Capacitor Charge Control block (see Figure 1) keeps the appropriate BOOST pin charged in these
cases. When the M1 switch is always on (boost region),
8705af
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LT8705A
Applications Information
current is automatically drawn from the CSPOUT and/or
BOOST2 pins to charge the BOOST1 capacitor as needed.
When the M4 switch is always on (buck region) current
is drawn from the CSNIN and/or BOOST1 pins to charge
the BOOST2 capacitor. Because of this function, CSPIN
and CSNIN should be connected to a potential close
to VIN. Tie both pins to VIN if they are not being used.
Also, CSPOUT and CSNOUT should always be tied to a
potential close to VOUT, or be tied directly to VOUT if not
being used.
Boost Diodes DB1 and DB2: Although Schottky diodes
have the benefit of low forward voltage drops, they can
exhibit high reverse current leakage and have the potential
for thermal runaway under high voltage and temperature
conditions. Silicon diodes are thus recommended for
diodes DB1 and DB2. Make sure that DB1 and DB2 have
reverse breakdown voltage ratings higher than VIN(MAX)
and VOUT(MAX) and have less than 1mA of reverse leakage
current at the maximum operating junction temperature.
Make sure that the reverse leakage current at high operating temperatures and voltages won’t cause thermal
runaway of the diode.
In some cases it is recommended that up to 5Ω of resistance is placed in series with DB1 and DB2. The resistors
reduce surge currents in the diodes and can reduce ringing at the SW and BOOST pins of the IC. Since SW pin
ringing is highly dependent on PCB layout, SW pin edge
rates and the type of diodes used, careful measurements
directly at the SW pins of the IC are recommended. If
required, a single resistor can be placed between GATEVCC and the common anodes of DB1 and DB2 (as in the
front page application) or by placing separate resistors
between the cathodes of each diode and the respective
BOOST pins. Excessive resistance in series with DB1
and DB2 can reduce the BOOST-SW capacitor voltage
when the M2 or M3 on-times are very short and should
be avoided.
Output Voltage
The LT8705A output voltage is set by an external feedback
resistive divider carefully placed across the output capacitor. The resultant feedback signal (FBOUT) is compared
with the internal precision voltage reference (typically
1.207V) by the error amplifier EA4. The output voltage is
given by the equation:
R
VOUT = 1.207V • 1+ FBOUT1
RFBOUT2
where RFBOUT1 and RFBOUT2 are shown in Figure 1.
Input Voltage Regulation or Undervoltage Lockout
By connecting a resistor divider between VIN, FBIN and
GND, the FBIN pin provides a means to regulate the input
voltage or to create an undervoltage lockout function.
Referring to error amplifier EA3 in the Block Diagram,
when FBIN is lower than the 1.205V reference VC is pulled
low. For example, if VIN is provided by a relatively high
impedance source (i.e., a solar panel) and the current draw
pulls VIN below a preset limit, VC will be reduced, thus
reducing current draw from the input supply and limiting
the voltage drop. Note that using this function in forced
continuous mode (MODE pin low) can result in current
being drawn from the output and forced into the input.
If this behavior is not desired then use discontinuous or
Burst Mode operation.
To set the minimum or regulated input voltage use:
R
VIN(MIN) = 1.205V • 1+ FBIN1
RFBIN2
where RFBIN1 and RFBIN2 are shown in Figure 1. Make
sure to select RFBIN1 and RFBIN2 such that FBIN doesn’t
exceed 30V (absolute maximum rating) under maximum
VIN conditions.
This same technique can be used to create an undervoltage lockout if the LT8705A is NOT in forced continuous
mode. When in Burst Mode operation or discontinuous
mode, forcing VC low will stop all switching activity. Note
that this does not reset the soft-start function, therefore
resumption of switching activity will not be accompanied
by a soft-start.
8705af
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LT8705A
Applications Information
Input/Output Current Monitoring and Limiting
to the Boost Capacitor Charge Control block (also see
Figure 1) and can draw current in certain conditions. In
addition, all four of the current sense pins can draw bias
current under normal operating conditions. As such, do
not place resistors in series with any of the CSxIN or
CSxOUT pins.
The LT8705A has independent input and output current
monitor circuits that can be used to monitor and/or limit
the respective currents. The current monitor circuits work
as shown in Figures 11 and 12.
As described in the Topside MOSFET Driver Supply section, the CSNIN and CSPOUT pins are also connected
RSENSE1
FROM DC
POWER SUPPLY
TO REMAINDER
OF SYSTEM
INPUT
CURRENT
CSPIN
LT8705A
+
gm = 1m
A7
–
FAULT
CONTROL
CSNIN
Ω–
TO BOOST CAPACITOR
CHARGE CONTROL BLOCK
+
1.61V 1.208V
EA2
–
VC
+
IMON_IN
RIMON_IN
CIMON_IN
8705A F11
Figure 11. Input Current Monitor and Limit
RSENSE2
FROM
CONTROLLER
VOUT
TO SYSTEM VOUT
OUTPUT
CURRENT
CSPOUT CSNOUT
TO BOOST CAPACITOR
CHARGE CONTROL BLOCK
+
gm = 1m
LT8705A
Ω–
A8
–
FAULT
CONTROL
+
1.61V 1.208V
EA1
–
+
IMON_OUT
RIMON_OUT
VC
CIMON_OUT
8705A F12A
Figure 12. Output Current Monitor and Limit
8705af
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LT8705A
Applications Information
Also, because of their use with the Boost Capacitor
Charge Control block, tie the CSPIN and CSNIN pins
to VIN and tie the IMON_IN pin to ground when the input
current sensing is not in use. Similarly, the CSPOUT and
CSNOUT pins should be tied to VOUT and IMON_OUT
should be grounded when not in use.
The remaining discussion refers to the input current monitor circuit. All discussion and equations are applicable to
the output current monitor circuit, substituting pin and
device names as appropriate.
Current Monitoring: For input current monitoring, current
flowing through RSENSE1 develops a voltage across
CSPIN and CSNIN which is multiplied by 1mA/V (typical),
converting it to a current that is forced out of the IMON_IN
pin and into resistor RIMON_IN (Note: Negative CSPIN to
CSNIN voltages are not multiplied and no current flows
out of IMON_IN in that case). The resulting IMON_IN voltage is then proportional to the input current according to:
A
VIMON_IN =IRSENSE1 • RSENSE1 •1m •RIMON_IN
V
For accurate current monitoring, the CSPIN and CSNIN
voltages should be kept above 1.5V (CSPOUT and CSNOUT
pins should be kept above 0V). Also, the differential
voltage VCSPIN-CSNIN should be kept below 100mV due
to the limited amount of current that can be driven out of
IMON_IN. Finally, the IMON_IN voltage must be filtered
with capacitor CIMON_IN because the input current often
has ripple and discontinuities depending on the LT8705A’s
region of operation. CIMON_IN should be chosen by the
equation:
100
F
CIMON_IN >
f •RIMON_IN
where f is the switching frequency, to achieve adequate
filtering. Additional capacitance, bringing the CIMON_IN
total to 0.1μF to 1μF, may be necessary to maintain loop
stability if the IMON_IN pin is used in a constant-current
regulation loop.
Current Limiting: As shown in Figure 11, IMON_IN voltages
exceeding 1.208V (typical) cause the VC voltage to reduce,
thus limiting the inductor and input currents. RIMON_IN can
be selected for a desired input current limit using:
1.208V
RIMON_IN =
Ω
IRSENSE(LIMIT) •1m A • RSENSE1
V
For example, if RSENSE1 is chosen to be 12.5mΩ and the
desired input current limit is 4A then:
RIMON_IN =
1.208V
= 24.2kΩ
A
4A •1m •12.5mΩ
V
Review the Electrical Characteristics and the IMON Output
Currents graph in the Typical Performance Characteristics
section to understand the operational limits of the IMON_
OUT and IMON_IN currents.
Overcurrent Fault: If IMON_IN exceeds 1.61V (typical), a
fault will occur and switching activity will stop (see Fault
Conditions earlier in the data sheet). The fault current is
determined by:
1.61V
IRSENSE1(FAULT) =
•IRSENSE1(LIMIT) A
1.208V
For example, an input current limit set to 4A would have
a fault current limit of 5.3A.
Output Overvoltage
If the output voltage is higher than the value set by the
FBOUT resistor divider, the LT8705A will respond according
to the mode and region of operation. In forced continuous
mode, the LT8705A will sink current into the input (see
the Reverse Current Limit discussion in the Applications
Information section for more information). In discontinuous mode and Burst Mode operation, switching will stop
and the output will be allowed to remain high.
8705af
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LT8705A
Applications Information
INTVCC Regulators and EXTVCC Connection
The LT8705A features two PNP LDOs (low dropout regulators) that regulate the 6.35V (typical) INTVCC pin from
either the VIN or EXTVCC supply pin. INTVCC powers the
MOSFET gate drivers via the required GATEVCC connection and also powers the LDO33 pin regulator and much
of the LT8705A’s internal control circuitry. The INTVCC
LDO selection is determined automatically by the EXTVCC
pin voltage. When EXTVCC is lower than 6.22V (typical),
INTVCC is regulated from the VIN LDO. After EXTVCC rises
above 6.4V (typical), INTVCC is regulated by the EXTVCC
LDO instead.
Overcurrent protection circuitry typically limits the
maximum current draw from either LDO to 127mA. When
GATEVCC and INTVCC are below 4.65V, during start-up or
during an overload condition, the typical current limit is
reduced to 42mA. The INTVCC pin must be bypassed to
ground with a minimum 4.7μF ceramic capacitor placed
as close as possible to the INTVCC and GND pins. An additional ceramic capacitor should be placed as close as
possible to the GATEVCC and GND pins to provide good
bypassing to supply the high transient current required by
the MOSFET gate drivers. 1μF to 4.7μF is recommended.
Power dissipated in the INTVCC LDOs must be minimized
to improve efficiency and prevent overheating of the
LT8705A. Since LDO power dissipation is proportional
to the input voltage and VIN can be as high as 80V in
some applications, the EXTVCC pin is available to regulate
INTVCC from a lower input voltage. The EXTVCC pin is connected to VOUT in many applications since VOUT is often
regulated to a much lower voltage than the maximum VIN.
During start-up, power for the MOSFET drivers, control
circuits and the LDO33 pin is derived from VIN until VOUT/
EXTVCC rises above 6.4V, after which the power is derived
from VOUT/EXTVCC. This works well, for example, in a case
where VOUT is regulated to 12V and the maximum VIN
voltage is 40V. EXTVCC can be floated or grounded when
not in use or can also be connected to an external power
supply if available.
The maximum current drawn through the INTVCC LDO
occurs under the following conditions:
1. Large (capacitive) MOSFETs are being driven at high
frequencies.
2. VIN and/or VOUT is high, thus requiring more charge to
turn the MOSFET gates on and off.
3. The LDO33 pin output current is high.
4. In some applications, LDO current draw is maximum
when the part is operating in the buck-boost region
where VIN is close to VOUT since all four MOSFETs are
switching.
To check for overheating find the operating conditions that
consume the most power in the LT8705A (PLT8705A). This
will often be under the same conditions just listed that
maximize LDO current. Under these conditions monitor
the CLKOUT pin duty cycle to measure the approximate die
temperature. See the Junction Temperature Measurement
section for more information.
Powering INTVCC from VOUT/EXTVCC can also provide
enough gate drive when VIN drops as low as 2.8V. This
allows the part to operate with a reduced input voltage
after the output gets into regulation.
The following list summarizes the three possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from VIN through the internal 6.35V
regulator at the cost of a small efficiency penalty.
2. EXTVCC connected directly to VOUT (VOUT > 6.4V). This
is the normal connection for the regulator and usually
provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available greater than 6.4V (typical) it may be
used to power EXTVCC.
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Applications Information
Loop Compensation
Table 1. Voltage Lockout Conditions
The loop stability is affected by a number of factors including the inductor value, output capacitance, load current,
VIN, VOUT and the VC resistor and capacitors. The LT8705A
uses internal transconductance error amplifiers driving VC
to help compensate the control loop. For most applications
a 3.3nF series capacitor at VC is a good value. The parallel
capacitor (from VC to GND) is typically 1/10th the value
of the series capacitor to filter high frequency noise. A
larger VC series capacitor value may be necessary if the
output capacitance is reduced. A good starting value for
the VC series resistor is 20k. Lower resistance will improve
stability but will slow the loop response. Use a trim pot
instead of a fixed resistor for initial bench evaluation to
determine the optimum value.
LDO33 Pin Regulator
The LT8705A includes a low dropout regulator (LDO) to
regulate the LDO33 pin to 3.3V. This pin can be used to
power external circuitry such as a microcontroller or other
desired peripherals. The input supply for the LDO33 pin
regulator is INTVCC. Therefore INTVCC must have sufficient
voltage, typically >4.0V, to properly regulate LDO33. The
LDO33 and INTVCC regulators are enabled by the SHDN pin
and are not affected by SWEN. The LDO33 pin regulator
has overcurrent protection circuitry that typically limits
the output current to 17.25mA. An undervoltage lockout
monitoring LDO disables switching activity when LDO33
falls below 3.04V (typical). LDO33 should be bypassed
locally with 0.1µF or more.
Voltage Lockouts
The LT8705A contains several voltage detectors to make
sure the chip is under proper operating conditions. Table 1
summarizes the pins that are monitored and also indicates
the state that the LT8705A will enter if an under or overvoltage condition is detected.
The conditions are listed in order of priority from top
to bottom. If multiple over/undervoltage conditions are
detected, the chip will enter the state listed highest on
the table.
PIN
APPROXIMATE
VOLTAGE
CHIP STATE
CONDITION (FIGURE 2)
VIN
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