LTC1099
High Speed 8-Bit A/D
Converter with Built-In
Sample-and-Hold
DESCRIPTIO
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FEATURES
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The LTC®1099 is a high speed microprocessor compatible
8-bit analog-to-digital converter (A/D). An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the
full Nyquist limit. With a conversion rate of 2.5µs, this
allows 156kHz 5VP-P input signals or slew rates as high as
2.5V/µs, to be digitized without the need for an external
S/H.
Built-In Sample-and-Hold
No Missing Codes
No User Trims Required
All Timing Inputs Edge Sensitive for Easy Processor
Interface
Fast Conversion Time: 2.5µs
Latched Three-State Outputs
Single 5V Operation
No External Clock
Overflow Output Allows Cascading
TC Input Allows User Adjustable Conversion Time
0.3" Wide 20-Pin PDIP
Two modes of operation, Read (RD) mode and Write-Read
(WR-RD) mode, allow easy interface with processors. All
timing is internal and edge sensitive which eliminates the
need for external pulse shaping circuits. The Stand-Alone
(SA) mode is convenient for those applications not involving a processor.
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KEY SPECIFICATIO S
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Data outputs are latched with three-state control to allow
easy interface to a processor data bus or I/O port. An
overflow output (OFL) is provided to allow cascading for
higher resolution.
Resolution: 8-Bits
Conversion Time: 2.5µs (RD Mode)
2.5µs (WR/RD Mode)
Slew Rate Limit (Internal S/H): 2.5V/µs
Low Power: 75mW Max
Total Unadjusted Error
LTC1099: ±1 LSB
LTC1099A: ±0.75 LSB
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Infinite Hold Time Sample-and-Hold (TACQ = 240ns)
7
VIN
SAMPLE
HOLD
10k
12
20
REF+
VCC
LTC1099
MODE
DB7
DB6
DB5
VIN
DB4
6
WR/RDY DB3
DB2
8
DB1
RD
DB0
13
CS
1
GND
10
14
17
16
15
14
5
4
3
2
1
2
3
4
5
6
7
8
REF –
11
10k
Signal-to-Noise Ratio (SNR) vs Input Frequency
15V
REF +
B1
B2
B3
B4
B5
B6
B7
B8
REF –
15
– 36
20
2.5k
V+
IO
18
2
+
AM6012
7
LT1022
IO
3
19
–
6
VOUT
4
V–
17
SIGNAL-TO-NOISE RATIO, SNR (dB)
5V
– 40
– 42
– 44
– 46
– 48
– 50
– 52
–15V
1099 TA01
TA = 25°C
TC = 2.5µs
– 38
1
10
INPUT FREQUENCY (kHz)
100
1099 G08
1
LTC1099
W W
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ABSOLUTE
AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) to GND Voltage ...................... 12V
Analog and Reference Inputs... – 0.3V to (VCC + 0.3V)
Digital Inputs .........................................– 0.3V to 12V
Digital Outputs ........................ – 0.3V to (VCC + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1099C/LTC1099AC ............................ 0°C to 70°C
LTC1099I/LTC1099AI ..........................–40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
VIN
1
20 VCC
DB0
2
19 TC
DB1
3
18 OFL
DB2
4
17 DB7
ORDER PART
NUMBER
TOP VIEW
LTC1099CN
LTC1099ACN
LTC1099AIN
VIN 1
20 VCC
DB0 2
19 TC
DB1 3
18 OFL
DB2 4
17 DB7
DB3 5
16 DB6
WR/RDY 6
15 DB5
MODE 7
14 DB4
DB3
5
16 DB6
WR/RDY
6
15 DB5
MODE
7
14 DB4
RD
8
13 CS
RD 8
13 CS
INT
9
12 REF+
INT 9
12 REF+
GND 10
–
GND 10
11 REF–
11 REF
LTC1099CSW
SW PACKAGE
20-LEAD PLASTIC SO
N PACKAGE
20-LEAD PDIP
TJMAX = 150°C, θJA = 130°C/W
TJMAX = 150°C, θJA = 100°C/W
Consult factory for parts specified with wider operating temperature ranges.
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CONVERTER CHARACTERISTICS The ● denotes the+ specifications
which apply over the full operating
–
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, REF = 5V, REF = 0V and TA = TMIN to TMAX unless otherwise
noted.
PARAMETER
CONDITIONS
LTC1099AI/LTC1099I
MIN
TYP
MAX
LTC1099AC/LTC1099C
MIN
TYP
MAX
UNITS
±0.75
±1
±0.75
±1
LSB
LSB
Accuracy
Total Unadjusted Error
LTC1099A
LTC1099
(Note 3)
●
●
Minimum Resolution (No Missing Codes)
●
8
8
Bits
●
1
6
2
4.5
kΩ
Reference Input
Input Resistance
3.2
3.2
REF + Input Voltage Range
(Note 4)
●
REF –
VCC
REF –
VCC
V
REF – Input Voltage Range
(Note 4)
●
GND
REF +
GND
REF +
V
●
GND
VCC
GND
VCC
V
±3
µA
Analog Input
Input Voltage Range
Input Leakage Current
Input Capacitance
CS = VCC , VIN = VCC , GND
±3
●
60
60
pF
Acquisition Time
240
240
ns
Aperture Time
110
110
ns
Tracking Rate
2.5
2.5
V/µs
Sample-and-Hold
2
LTC1099
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted.
LTC1099AI/LTC1099I
MIN
TYP
MAX
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
All Digital Inputs, VCC = 5.25V
●
VIL
Low Level Input Voltage
All Digital Inputs, VCC = 4.75V
●
IIH
High Level Input Current
VIH = 5V; CS, RD, Mode
VIH = 5V; WR
●
●
VIL = 0V; All Digital Inputs
●
IIL
Low Level Input Current
VOH
High Level Output Voltage DB0-DB7, OFL, INT; VCC = 4.75V
IOUT = 360µA
IOUT =10µA
VOL
●
2.0
2.4
LTC1099AC/LTC1099C
MIN
TYP
MAX
UNITS
2.0
V
0.8
0.0001
0.8
V
0.0001
0.0005
1
3
0.0005
1
3
µA
µA
–0.0001
–1
–0.0001
–1
µA
4.0
4.7
Low Level Output Voltage DB0-DB7, OFL, INT, RDY; VCC = 4.75V
●
IOUT =1.6mA
2.4
4.0
4.7
0.4
V
V
0.4
V
IOZ
Hi-Z Output Leakage
DB0-DB7, RDY; VOUT = 5V
DB0-DB7, RDY; VOUT = 0V
●
●
0.1
–0.1
3
–3
0.1
–0.1
3
–3
µA
µA
ISOURCE
Output Source Current
DB0-DB7, OFL, INT; VOUT = 0V
●
–11
–6
–11
–7
mA
ISINK
Output Sink Current
DB0-DB7, OFL, INT, RDY; VOUT = 5V
●
14
7
14
9
mA
ICC
Supply Current
CS = WR = RD = VCC
●
11
20
11
15
mA
AC CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. VCC = 5V, REF+ = 5V, REF– = 0V and TA = TMIN to TMAX unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC1099AI/LTC1099I
MIN
TYP
MAX
LTC1099AC/LTC1099C
MIN
TYP
MAX
2.2
2.2
UNITS
RD Mode (Figure 2) Pin 7 = GND
t CRD
Conversion Time
TA = 25°C
2.5
●
2.8
2.5
5.0
2.8
µs
3.75
µs
t RDY
Delay From CS↓ to RDY↓
CL = 100pF
70
70
ns
t ACC0
Delay From RD↓ to Output Data Valid
CL = 100pF
tCRD + 35
tCRD + 35
ns
t INTH
Delay From RD↑ to INT↑
CL = 100pF
70
70
ns
t 1H, t 0H
Delay From RD↑ to Hi-Z State on Outputs
Test Circuit Figure 1
70
70
ns
tP
Delay Time Between Conversions
700
700
ns
t ACC2
Delay Time From RD↓ to Output Data Valid
70
70
ns
WR/RD Mode (Figures 3 and 4) Pin 7 = VCC
t CWR
Conversion Time
TA = 25°C
2.2
2.5
●
2.8
5.0
2.2
2.5
2.8
3.75
µs
µs
t ACC0
Delay Time From WR↓ to Output Data Valid CL = 100pF
tCWR + 40
tCWR + 40
ns
t ACC2
Delay From RD↓ to Output Data Valid
t INTH
Delay From RD↑ to INT↑
CL = 100pF
70
70
ns
CL = 100pF
70
70
ns
t IHWR
Delay From WR↓ to INT↑
CL = 100pF
240
240
ns
t 1H, t0H
Delay From RD↑ to Hi-Z State on Outputs
Test Circuit Figure 1
70
70
ns
tP
Delay Time Between Conversions
700
700
ns
t WR
Minimum WR Pulse Width
55
55
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltages are with respect to GND (Pin 10) unless otherwise
noted.
Note 3: Total unadjusted error includes offset, gain, linearity and hold step
errors.
Note 4: Reference input voltage range is guaranteed but is not tested.
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LTC1099
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Temperature
20
1.0
4
TA = 25°C
TC = 2.5µs
18
LINEARITY ERROR (LBS)
3
14
12
10
8
6
2
1
4
0.7
0.6
0.5
0.4
0.3
0.1
25
– 25
0
50
75 100
AMBIENT TEMPERATURE, TA (°C)
0
0
125
0
1099 G01
Total Error vs Reference Voltage
TA = 25°C
TC = 2.5µs
Accuracy vs Conversion Time
CONVERSION TIME (µs)
2
1
0
RESISTOR BETWEEN
PIN 19 AND VCC
RESISTOR BETWEEN
PIN 19 AND GND
1.0
0.1
5
4
1
3
2
REFERENCE VOLTAGE, VREF (V)
100
RESISTANCE (kΩ)
10
1000
TA = 25°C
0.8
0.6
0.4
0.2
0
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5
CONVERSION TIME (µs)
1099 G05
1099 G04
1.6
4.0
1.4
3.5
1.2
3.0
1.0
2.5
0.8
2.0
1.5
125
1099 G07
– 36
SIGNAL-TO-NOISE RATIO, SNR (dB)
4.5
CONVERSION TIME (µs)
1.8
0.6
50
100
–50 –25
25
75
0
AMBIENT TEMPERATURE, TA (°C)
1099 G06
Signal-to-Noise Ratio (SNR) vs
Input Frequency
Conversion Time vs Temperature
CONVERSION TIME/CONVERSION TIME AT 25°C
1.0
TA = 25°C
10
5
1099 G03
Conversion Time vs REXT
100
3
1
3
4
2
REFERENCE VOLTAGE, VREF (V)
1099 G02
4
0
0
5
4
1
3
2
REFERENCE VOLTAGE, VREF (V)
TOTAL UNADJUSTED ERROR (LBS)
0
– 50
TOTAL ERROR (LSB)
0.8
0.2
2
4
TA = 25°C
TC = 2.5µs
0.9
16
VOS ERROR (LSB)
SUPPLY CURRENT, ICC (mA)
Linearity Error vs Reference
Voltage
VOS Error vs Reference Voltage
TA = 25°C
TC = 2.5µs
– 38
– 40
– 42
– 44
– 46
– 48
– 50
– 52
1
10
INPUT FREQUENCY (kHz)
100
1099 G08
LTC1099
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PIN FUNCTIONS
VIN (Pin 1): Analog Input.
DB0 to DB3 (Pins 2 to 5): Data Outputs. DB0 = LSB.
INT (Pin 9): Output that goes low when the conversion in
process is complete and goes high after data is read.
GND (Pin 10): Ground Connection.
WR/RDY (Pin 6): WR/RDY is an input when M0DE = VCC.
Falling edge of WR switches internal S/H to hold then
starts conversion. WR/RDY is an open drain output (active
pull-down) when M0DE = GND. RDY goes low at start of
conversion and pull-down is turned off when conversion
is complete. Resistive pull-up is usually used in this mode.
REF + (Pin 12): High Reference Potential. VREF = Full Scale
= (REF +) – (REF –).
MODE (Pin 7): WR-RD when MODE = VCC. RD when
M0DE = GND. No internal pull-down.
DB4 to DB7 (Pins 14 to 17): Data Outputs. DB7 = MSB.
RD (Pin 8): A Low on RD with CS Low Activates ThreeState Outputs. With MODE = GND and CS low, the falling
edge of RD switches internal S/H to hold and starts
conversion.
REF – (Pin 11): Low Reference Potential (Analog Ground).
CS (Pin 13): Chip Select. When high, data outputs are high
impedance and all inputs are ignored.
OFL (Pin 18): Overflow Output. Goes low when VIN > VREF.
TC (Pin 19): User Adjustable Conversion Time.
VCC (Pin 20): Positive Supply. 4.75V ≤ VCC ≤ 5.25V.
TEST CIRCUITS
t1H
tr = 20ns, CL = 10pF
tr
VCC
VCC
90%
50%
RD
GND
10%
RD
t1H
DATA
OUT
CS
CL
V0H
1k
90%
DATA OUT
GND
t0H
tr = 20ns, CL = 10pF
VCC
tr
VCC
VCC
1k
RD
GND
DATA
OUT
CS
90%
50%
RD
10%
t0H
CL
VCC
DATA OUT
V0L
10%
1099 F01
Figure 1. Three-State Test Circuit
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LTC1099
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TI I G DIAGRA S
CS
tP
RD
tRDY
WR/RDY
tCRD
tINTH
INT
tACC0
DB0-DB7
t1H, t0H
NEW DATA
OLD DATA
tACC2
1099 F02
Figure 2. RD Mode (Pin 7 Is GND)
CS
CS
WR/RDY
WR/RDY
tP
tCWR
t CWR
RD
tP
RD
tINTH
t INTH
INT
INT
t ACC2
t1H, t0H
DB0-DB7
t 1H, t 0H
OLD DATA
DB0-DB7
tACC2
t ACC0
1099 F03A
Figure 3a. WR-RD Mode (Pin 7 Is HIGH and tRD > tCWR)
Figure 3b. WR-RD Mode (Pin 7 Is HIGH and tRD< tCWR)
CS (GND)
RD (GND)
WR/RDY
tIHWR
tP
INT
tCWR
DB0-DB7
OLD DATA
tACC0
NEW DATA
1099 F04
Figure 4. WR-RD Mode (Pin 7 Is HIGH) Standalone Operation
6
NEW DATA
1099 F03B
LTC1099
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FUNCTIONAL DESCRIPTIO
Figure 5 shows the functional block diagram for the
LTC1099 2-step flash ADC. It consists of two 4-bit flash
converters, a 4-bit DAC and a differencing circuit. The
conversion process proceeds as follows:
VREF
B7
MS
4-BIT
FLASH
VIN
1. At the start of the conversion, the on-board sampleand-hold switches from the sample to the hold mode.
This is a true sample-and-hold with an acquisition time
of 240ns, an aperture time of 110ns and a tracking rate
of 2.5V/µs.
2. The held input voltage is converted by the 4-bit MSFlash ADC. This generates the upper or most significant
4-bits of the 8-bit output.
3. A 4-bit approximation, from the DAC output, is subtracted from the held input voltage.
4. The LS-Flash ADC converts the difference between the
held input voltage and the DAC approximation. This
generates the lower or least significant (LS) 4-bits of
the 8-bit output. The LS-Flash reference is one sixteenth of the MS-Flash reference. This effectively multiplies the difference by 16.
5. Upon the completion of the LS 4-bit flash the eight
output latches are updated simultaneously. At the same
time, the sample-and-hold is switched from the hold
mode to the acquire mode in preparation for the next
conversion.
The advantage of this approach is the reduction in the
amount of hardware required. A full flash converter requires 255 comparators while this approach requires only
31. The price paid for this reduction in hardware is an
increase in conversion time. A full flash converter requires
only one comparison cycle while this approach requires
two comparison cycles, hence 2-step flash.
This architecture is further simplified in the LTC1099 by
reusing the MS-Flash hardware to do the LS-Flash. This
reduces the number of comparators from 31 to 16. This is
possible because the MS and LS conversions are done at
different times.
To take the simple block diagram of Figure 5 and reconfigure
it to reuse the MS-Flash to do the LS-Flash is conceptually
simple, but from a hardware point of view is not practical.
A new six input switched capacitor comparator is used to
B6
B5
B4
4-BIT
DAC
+
∑
–
REMAINDER
VREF/16
B3
LS
4-BIT
FLASH
B2
B1
B0
1099 F05
Figure 5. 8-Bit 2-Step Semiflash A/D
accomplish this function in a simple, although not straight
forward,␣ manner.
Figure 6 shows the six input switched capacitor comparator. Intuitively, the comparator is easy to understand by
noting that the common connection between the two input
capacitors, C1 and C2, acts like a virtual ground. In
operational amplifier circuits, current is summed at the
virtual ground node. Input voltage is converted to current
by the input resistors. In the switched capacitor comparator, input voltage is converted to charge by the input
capacitors and these charges are summed at the virtual
ground node.
A major advantage of this technique is that the switch-on
impedance has no affect on accuracy as long as sufficient
time exists to fully charge and discharge the capacitors.
During the first time period the T+ and TZ switches are
closed. This forces the common node between C1 and C2
to an arbitrary bias voltage. Since the capacitors subtract
out this voltage, it may be considered, for the sake of this
discussion, to be exactly zero (i.e., virtual ground). Note
7
LTC1099
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FUNCTIONAL DESCRIPTIO
T+
T–1
T–2
(+)
TZ
TZ
VIN
MS TAP
DAC
0.5 LSB
0V
LS TAP
(–)
C1
(–)
VIRTUAL
GROUND
(+)
(–)
C2
C1 = C2
(–)
HOLD
TZ
SAMPLE
SAMPLE
T+
T–1
T–2
STROBE
1099 F06
Figure 6. Six Input Switched Capacitor Comparator
also that variations in the bias voltage with time and
temperature will also be rejected. In this state, C1 charges
to VIN. When TZ opens, VIN is held on C1.
The next step is the first comparison — the MS-Flash. TZ
and T+ are opened and T–1 is closed. The equation for each
comparator is:
VIN + 0.5LSB – MSTAP = 0V
There are 16 identical comparators each tied to the tap on
a 16 resistor ladder. The MS tap voltages vary from VREF
to 0V in 16 equal steps of VREF/16.
Notice that capacitor C2 adds 0.5LSB to VIN. This offsets
the converter transfer function by 0.5LSB, equally distributing the 1LSB quantization error to ±0.5LSB.
The outputs of the 16 comparators are temporarily latched
and drive the 4-bit DAC directly without need of decoding.
8
This holds the DAC output constant for the next step — the
LS conversion. The LS conversion is started when T–1 is
opened and T–2 is closed. Capacitor C1 subtracts the 4-bit
DAC approximation from VIN and inputs the difference
charge to the virtual ground node. The equation for each
comparator is:
VIN + 0.5LSB – VDAC – LSTAP = 0V
The 4-bit DAC approximation is input to all 16 comparators. The LS tap voltages are converted to charge by
capacitor C2. LS taps vary from VREF/16V to 0V in 16 equal
steps of VREF/256. The comparators look at the net charge
on the virtual ground node to perform the LS-Flash conversion. When this conversion is complete, the four LSBs
along with the four MSBs are transferred to the output
latches. In this way, all eight outputs will change
simultaneously.
LTC1099
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DIGITAL I TERFACE
The digital interface to the LTC1099 entails either controlling the conversion timing or reading data. There are two
basic modes for controlling and reading the A/D — the
Write-Read(WR-RD) mode and the Read (RD) mode.
WR-RD Mode (Pin 7 = High)
In the WR-RD mode, a conversion sequence starts on the
falling edge of WR with CS low (Figures 3a and 3b). This
is an edge-sensitive control function. The width of the WR
input is not important. All timing functions are internal to
the A/D.
The first thing to happen after the falling edge of WR is the
internal S/H is switched to hold. This typically takes 110ns
after WR falls and is the aperture time of the S/H.
Next, the A/D conversion takes place. The conversion time
is internally set at 2.5µs, but is user adjustable (see
Adjusting the Conversion Time). The end of conversion is
signaled by the high to low transition of INT. The S/H is
switched back to the acquire state as soon as the conversion is complete.
After the conversion is complete, the 8-bit result is available on the three-state outputs. The outputs are active with
RD and CS low. Output data is latched and, if no new
conversion is initiated, is available indefinitely as long as
the power is not turned off.
The WR-RD mode is also used for stand-alone operation.
By tying CS and RD low the data outputs will be continuously active (Figure 4). The falling edge of WR starts the
conversion sequence and when done new data will appear
on the outputs. All outputs will be updated simultaneously.
In stand-alone operation, the outputs will never be in a
high impedance state.
RD Mode (Pin 7 = Low)
In the RD mode, a conversion sequence is initiated by the
falling edge of RD when CS is low (Figure 2). The S/H is
switched to the hold state 110ns after the falling edge of
RD. It is switched back to the acquire state at the end of
conversion.
When RD goes low, with CS low, the result of the previous
conversion is output. This data stays there until the
ongoing conversion is complete (INT goes low). At this
time the outputs are updated with new data.
As long as CS and RD stay low long enough, the receiving
device will get the right data. Remember, the receiving
device reads data in on the rising edge of RD. The RDY
output facilitates making RD long enough.
In the RD mode, the WR input becomes the RDY output.
On the falling edge of RD, the RDY goes low. It is an open
drain output to allow a wired OR function so it requires a
pull-up resistor. At the end of conversion, the active pulldown is released and RDY goes high.
The RDY output is designed to interface to the Ready In
(RDYIN) function on many popular processors. RDYIN
allows these processors to work with slow memory by
stretching the RD strobe coming from the processor. RD
will remain low as long as RDY is low. In the case of the
LTC1099, RDY stays low until the conversion is complete
and new data is available on the outputs. This greatly
simplifies the programmers task. Each time data is required from the A/D a simple read is executed. The
hardware interface makes sure the RD strobe is long
enough.
Adjusting the Conversion Time
The conversion time of the LTC1099 is internally set at
2.5µs. If desired, it can be adjusted by forcing a voltage on
Pin 19. With Pin 19 left open, the conversion time runs
2.5µs. A convenient way to force the voltage is with the
circuit shown in Figure 7. To preset the conversion time to
a fixed amount, a resistor may be tied from Pin 19 to VCC
or GND. Tying it to VCC slows down the conversion and
tying it to GND will speed it up (see Typical Performance
Characteristics).
5V
1
20
2
19
10k
1099 F07
Figure 7. Adjusting the Conversion Time
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LTC1099
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ANALOG INTERFACE
The inclusion of a high quality sample-and-hold (S/H)
simplifies the analog interface to the LTC1099. All of the
error terms normally associated with an S/H (hold step,
offset, gain and droop errors) are included in the error
specifications for the A/D. This makes it easy for the
designer since all the error terms need not be taken into
account individually.
S/H Timing
A falling edge on the RD or WR input switches the S/H from
acquire to hold and starts the conversion. The aperture
time is the delay from the falling edge to the actual instant
when the S/H switches to hold. It is typically 110ns.
As soon as a conversion is complete (2.5µs typ), the S/H
switches back to the sample mode. Even though the
acquisition time is only 240ns, a new conversion cannot
be started for (700ns typ) after a conversion is completed.
Analog Input
The input to the A/D looks like a 60pF capacitor in series
with 550Ω (Figure 8).
550Ω
VIN
TO A/D
60pF
1099 F08
Figure 8. Equivalent Input Circuit
With this high input capacitance care must be taken when
driving the inputs from a source amplifier. When the input
switch closes, an instantaneous capacitive load is applied
to the amplifier output. This acts like an impulse into the
amplifier and if it has poor phase margin the resulting
ringing can cause a considerable loss of accuracy. If the
amplifier is too slow the resulting settling tail will also
cause a loss of accuracy. The amplifier should also have
low open circuit output impedance. The LT1006 is an
10
excellent amplifier in this regard. It also works with a single
supply which fits nicely with the LTC1099.
Reference Inputs
Sixteen equal valued resistors are internally connected
between REF + and REF –. Each resistor is nominally 200Ω
giving a total resistance of 3.2k between the reference
terminals. When VIN equals REF +, the output code will be
all ones. When VIN equals REF –, the output code will be all
zeros.
Although it is most common to connect REF+ to a 5V
reference and REF – to ground, any voltages can be used.
The only restrictions are REF+ >REF – and REF+ and REF –
must be within the supply rails. As the reference voltage is
reduced the A/D will eventually lose accuracy. Accuracy is
quite good for references down to 1V.
Even though the reference drives a resistive ladder, a lot of
capacitive switching is taking place internally. For this
reason, driving the reference has the same characteristics
as driving VIN. A fast low impedance source is necessary.
The reference has the additional problem of presenting a
DC load to the driving source. This requires the DC as well
as the AC source impedance to be low.
Good Grounding
As with any precise analog system care must be taken to
follow good grounding practices when using the LTC1099.
The most noise free environment is obtained by using a
ground plane with GND (Pin 10) and REF – (Pin 11) tied to
it. Bypass capacitors from REF+ (Pin 12) and VCC (Pin 20)
with short leads are also required to prevent spurious
switching noise from affecting the conversion accuracy.
If a ground plane is not practical, single point grounding
techniques should be used. Ground for the A/D should not
be mixed in with other noisy grounds.
LTC1099
U
U
ANALOG INTERFACE
APPLICATIONS
Note that since this is only a two quadrant multiplier, a
carrier component (the input to the LTC1099) will appear
in the output spectrum. Figure 11 shows the frequency
spectrum of a 42.5kHz sine wave multiplied by a 5kHz sine
wave. The depth of modulation is about 30dB. Figure 12
shows a 42.375kHz sine wave multiplied by a 30.875kHz
sine wave. Note that at these higher frequencies, the depth
of modulation is still about 30dB. The carrier feed-through
is seen in Figure 12.
Analog Multiplier
The schematic Figure 9 shows the LTC1099 configured
with a DAC to form a two quadrant analog multiplier. An
input waveform is applied to the LTC1099 where it is
digitized at a 300kHz rate. The digitized signal is fed to the
DAC in “flow-through” mode where another signal is input
to the DAC reference input. In this way, the two analog
signals are multiplied to produce a double sideband amplitude modulated output. Figure 10 shows a 3kHz sine wave
multiplied by a 100Hz triangle.
(VIN1) 0V TO 5V
ANALOG
INPUT
1
N/C
2
3MHz
OSC
3
OUT
14
4
13
5
12
÷ 10 = 300kHz 6
11
7
5
10
8
6
9
7
8
1
CLK
2
74LS90
3
4
5V
4
DB0-DB3
CS AND RD LOW
5V
N/C
N/C
9
10
= DIGITAL GROUND
DB2
DB7
DB3
DB6
WR/RDY DB5
MODE
DB4
17
16
15
14
13
RD
CS
INT
REF +
12
GND
REF –
11
CS
2
18
DB1
12V
8
24
VCC
BYTE 1/ 23
WR1 BYTE 2
3
22
WR2
GND
4
21
XFER
DI5
5
20
DI6
DI4
6
19
DI7
DI3
7
18
DI8
DI2
8
17
DI9
DI1
9
16
DI10
DI0
10
15
DI11
VREF
11
14
IOUT2
RFB
12
13
IOUT1
4
10µF DB4-DB7
4.7µF
0.01µF
5VREF
LT1019-5
OUT
15VIN
MP1208 DAC
5V
19
DB0
8
1
20
LTC1099
= ANALOG GROUND
(VIN2) +10V TO –10V
ANALOG
INPUT MICROLINEAR
10pF
IN
TRIM
GND
10µF
50k
OFFSET NULL
15V
1
+
5
15V
LT1056
–
–15V
25k
AGND
Figure 9
VIN1 ≅ 0V TO 5V
TRIANGLE INTO LTC1099
~100Hz
VIN2 ≅ ±4.8V SINE
INTO DAC ~ 3kHz
1099 F10
Figure 10
11
LTC1099
U
U
ANALOG INTERFACE
10dBV/DIV
0
–70
32.5
34.5
36.5
38.5
40.5
37500Hz
42.5
44.5
42500Hz
46.5
48.5
50.5
47500Hz
52.5
1099 F11
Figure 11. Two Quadrant Multiplier Output Spectrum with 0V to
4.5V at 42.5kHz into LTC1099 and ±2V at 5kHz into DAC
10dBV/DIV
0
–70
5
15
11500Hz
25
35
45
30875Hz 42375Hz
55
65
75
73250Hz
85
95
105
1099 F12
Figure 12. Two Quadrant Multiplier Output Spectrum with 0V to
4.5V at 42.375kHz into LTC1099 and ±2V at 30.875kHz into DAC
12
LTC1099
U
TYPICAL APPLICATIONS
TMS320C25 Interface Using RD Mode
5V
(A10, B11, H2, L6)
(K1)
A0
(K2)
A1
(L3)
A2
(J11)
IS
(K3)
A3
(B1, K11, L2)
VSS
74AS138
VCC
5V
TMS320C25
D4
D5
D6
D7
D0
D1
D2
READY
(B8)
(6)
D3
STRB
(H10)
MSC
(C10)
(4)
(3)
(5)
A
VCC
B
Y0
C
Y1
G2A
Y2
G2B
Y3
G1
Y4
Y7
Y5
GND
Y6
(D1)
(C2)
(C1)
(B2)
LTC1099
ANALOG
INPUT
VOLTAGE
(F1)
(E2)
(E1)
(D2)
(1)
VIN
VCC
DB0
TC
DB1
OFL
DB2
DB7
DB3
DB6
WR/RDY
DB5
MODE
DB4
RD
CS
INT
REF+
GND
+
C1
–
REF
C2
5V
+
C1
(2)
C2
10k
1/2 74AS00
C1 = 4.7µF TANTALUM
C2 = 0.1µF CERAMIC
5V
1099 TA03
TMS320C25 Assembly Code for RD Mode Interface to LTC1099
0001 0000
0002 0032
AORG
0003 0032 CE01
DINT
0004 0033 C800
LDPK
0005 0034 8064 LOOP
IN
0006 0035 CB13
RPTK
0007 0036 5500
NOP
0008 0037 FF80
B
>32
Disable Interrupts
>00
Data Page Pointer Is 0
100,PAO Input 1099 Data to Address 100
12
Repeat Next Instruction 12 Times
Don’t Convert Again Too Soon
LOOP Go for Another Conversion
13
LTC1099
U
TYPICAL APPLICATIONS
TMS320C25 Interface Using WR/RD Mode
5V
(A10, B11, H2, L6)
(K1)
A0
(K2)
A1
(L3)
A2
(J11)
IS
(K3)
A3
VSS
74F138
VCC
5V
TMS320C25
D0
(F1)
ANALOG
INPUT
VOLTAGE
(E2)
D1
D2
D3
(E1)
(D2)
5V
READY
(B8)
MSC
(C10)
R/ W
(H11)
STRB
A
VCC
B
Y0
C
Y1
G2A
Y2
G2B
Y3
G1
Y4
Y7
Y5
GND
Y6
C5
0.1µF
+
C6
LTC1099
VIN
VCC
DB0
TC
DB1
OFL
DB2
DB7
D7(B2)
DB3
DB6
D6(C1)
WR/RDY
DB5
D5(C2)
MODE
DB4
D4(D1)
RD
CS
INT
REF+
GND
REF–
5V
+
C3
C4
5V
+
C1
C2
(H10)
74F00
IN1
VCC
5V
IN1
IN4
C8
0.1µF
OUT1
IN4
IN2
OUT4
1N2
IN3
OUT2
GND
IN3
OUT3
C1, C3, C6 = 4.7µF TANTALUM
C2, C4, C5, C7, C8 = 0.1µF CERAMIC
TMS320C25 Assembly Code for WR/RD Mode Interface to
LTC1099
0001 0032
AORG
0002 0032 CE01
DINT
0003 0033 C800
LDPK
>32
Disable Interrupts
>0
Data Page Pointer Is 0
0004 0034 E064 LOOP OUT >64.PAO Start LTC1099 Conversion
14
0005 0035 CB20
RPTK
0006 0036 5500
NOP
0007 0037 8064
IN
0008 0038 FF80
B
>12
Wait for Conversion to Finish
>64.PAO Read LTC1099 Data; Store in >64
LOOP Do Again
1099 TA04
C7
LTC1099
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N Package
20-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.040*
(26.416)
MAX
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
0.020
(0.508)
MIN
+0.035
0.325 –0.015
8.255
+0.889
–0.381
0.045 – 0.065
(1.143 – 1.651)
)
0.065
(1.651)
TYP
0.005
(0.127)
MIN
0.125
(3.175)
MIN
0.100
(2.54)
BSC
0.018 ± 0.003
(0.457 ± 0.076)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N20 1098
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
20
19
18
17
16
15
14
13
12
11
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029 × 45°
(0.254 – 0.737)
1
2
3
4
5
6
7
8
9
10
0.093 – 0.104
(2.362 – 2.642)
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.356 – 0.482)
TYP
0.004 – 0.012
(0.102 – 0.305)
S20 (WIDE) 1098
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1099
U
TYPICAL APPLICATIO S
Cascading for 9-Bit Resolution
CS
13
WR
8
CS
LTC1099
WR/RDY
VCC
VIN
20
5V
1
VIN
RD
6
B0
2
B1
3
µP B2
BUS
B3
4
B4
14
B5
15
B6
16
B7
17
5
RD
DB0
MODE
DB1
VREF +
7
5V
12
5V
DB2
4.7µF
DB3
DB4
DB5
VREF –
11
4.7µF
DB6
DB7
1k
B8
OFL
18
OFL
GND
10
5k
13
8
6
LTC1099
CS
VCC
WR/RDY
VIN
4
5
14
15
16
17
18
5V
1k
1
RD
2
3
20
MODE
DB0
VREF +
7
5V
12
DB1
DB2
4.7µF
DB3
DB4
VREF –
11
DB5
DB6
DB7
GND
10
OFL
1099 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1274/LTC1277
12-Bit, 100ksps Parallel/2-Byte ADC
5V or ± 5V, 10mW with 1µA Shutdown
LTC1279
12-Bit, 600ksps Parallel ADC
5V, 60mW, 70dB SINAD
LTC1406
8-Bit, 20Msps Parallel ADC
5V, 150mW, 48.5dB SINAD
LTC1409
12-Bit, 800ksps Parallel ADC
±5V, 80mW, 72.5dB SINAD
LTC1419
14-Bit, 800ksps Parallel ADC
±5V, 150mW, 81.5dB SINAD
16
Linear Technology Corporation
sn1099 1099fas LT/TP 1100 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1989
