LTC1159IS-5#PBF

LTC1159 LTC1159-3.3/LTC1159-5 High Efficiency Synchronous Step-Down Switching Regulators U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1159 series is a family of synchronous step-down switching regulator controllers featuring automatic Burst ModeTM operation to maintain high efficiencies at low output currents. These devices drive external complementary power MOSFETs at switching frequencies up to 250kHz using a constant off-time current-mode architecture. Operation from 4V to 40V Input Voltage Ultrahigh Efficiency: Up to 95% 20µA Supply Current in Shutdown High Efficiency Maintained Over Wide Current Range Current Mode Operation for Excellent Line and Load Transient Response Very Low Dropout Operation: 100% Duty Cycle Short-Circuit Protection Synchronous FET Switching for High Efficiency Adaptive Non-Overlap Gate Drives Available in SSOP and SO Packages A separate pin and on-board switch allow the MOSFET driver power to be derived from the regulated output voltage providing significant efficiency improvement when operating at high input voltages. The constant off-time current-mode architecture maintains constant ripple current in the inductor and provides excellent line and load transient response. The output current level is user programmable via an external current sense resistor. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Step-Down and Inverting Regulators Notebook and Palmtop Computers Portable Instruments Battery-Operated Digital Devices Industrial Power Distribution Avionics Systems Telecom Power Supplies The LTC1159 automatically switches to power saving Burst Mode operation when load current drops below approximately 15% of maximum current. Standby current is only 300µA while still regulating the output and shutdown current is a low 20µA. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO VIN + 1N4148 VIN CAP P-GATE Si9435DY CIN 100µF 100V LTC1159-5 Efficiency 100 0.15µF FIGURE 1 CIRCUIT VCC 3.3µF VIN = 10V 0.1µF P-DRIVE VCC EXTVCC LTC1159-5 90 D1 MBRS140T3 L* 33µH RSENSE 1 0.05Ω 2 3 SHDN1 0V = NORMAL >2V = SHUTDOWN SHDN2 ITH 3300pF 1k CT CT 300pF S-GND 4 VOUT 5V/2A SENSE + SENSE – 0.01µF + N-GATE Si9410DY EFFICIENCY (%) + VIN = 20V 80 70 COUT 220µF P-GND LTC1159 • F01 *COILTRONICS CTX33-4-MP 60 0.02 0.2 LOAD CURRENT (A) 2 LTC1159 • TA01 Figure 1. High Efficiency Step-Down Regulator 1 LTC1159 LTC1159-3.3/LTC1159-5 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (Pin 2) ..................... – 15V to 60V VCC Output Current (Pin 3) .................................. 50mA Continuous Pin Currents (Any Pin) ...................... 50mA Sense Voltages ......................................... – 0.3V to 13V Shutdown Voltages ................................................... 7V EXTVCC Input Voltage ............................................. 15V Junction Temperature (Note 2) ............................ 125°C Operating Temperature Range LTC1159C .............................................. 0°C to 70°C LTC1159I ........................................... – 40°C to 85°C Extended Commercial Temperature Range ............................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW P-GATE 1 20 CAP VIN 2 19 SHDN2 VCC 3 18 EXTVCC P-DRIVE 4 17 PGND P-DRIVE 5 16 N-GATE VCC 6 15 PGND VCC 7 14 SGND CT 8 13 SHDN1 ITH 9 12 VFB SENSE – 10 ORDER PART NUMBER LTC1159CG LTC1159CG-3.3 LTC1159CG-5 P-GATE 1 16 CAP VIN 2 15 SHDN2 VCC 3 14 EXTVCC P-DRIVE 4 13 N-GATE VCC 5 12 PGND CT 6 11 SGND ITH 7 10 VFB (SHDN1)* SENSE – 8 9 N PACKAGE 16-LEAD PDIP 11 SENSE + ORDER PART NUMBER TOP VIEW LTC1159CN LTC1159CN-3.3 LTC1159CN-5 LTC1159CS LTC1159CS-3.3 LTC1159CS-5 LTC1159IS LTC1159IS-3.3 LTC1159IS-5 SENSE + S PACKAGE 16-LEAD PLASTIC SO *FIXED OUTPUT VERSIONS G PACKAGE 20-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 80°C/ W (N) TJMAX = 125°C, θJA = 110°C/ W (S) TJMAX = 125°C, θJA = 135°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSHDN1 = 0V (Note 3), unless otherwise noted. SYMBOL PARAMETER VFB Feedback Voltage (LTC1159 Only) ● IFB Feedback Current (LTC1159 Only) ● VOUT Regulated Output Voltage LTC1159-3.3 LTC1159-5 VIN = 9V ILOAD = 700mA ILOAD = 700mA Output Voltage Line Regulation VIN = 9V to 40V Output Voltage Load Regulation LTC1159-3.3 LTC1159-5 5mA < ILOAD < 2A 5mA < ILOAD < 2A Burst Mode Output Ripple ILOAD = 0A 50 mVP-P VIN = 12V, EXTVCC = 5V VIN = 40V, EXTVCC = 5V 200 300 µA µA VIN = 12V, VSHDN2 = 2V VIN = 40V, VSHDN2 = 2V 15 25 µA µA EXTVCC = 5V, Sleep Mode 250 µA ∆VOUT IIN VIN Pin Current (Note 4) Normal Mode Shutdown IEXTVCC 2 EXTVCC Pin Current (Note 4) CONDITIONS ● ● ● ● MIN TYP MAX 1.21 1.25 1.29 UNITS V µA 0.2 3.23 4.90 3.33 5.05 3.43 5.20 V V – 40 0 40 mV 40 60 65 100 mV mV LTC1159 LTC1159-3.3/LTC1159-5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSHDN1 = 0V (Note 3), unless otherwise noted. SYMBOL PARAMETER VCC Internal Regulator Voltage VIN = 12V to 40V, EXTVCC = 0V, ICC = 10mA VIN – VCC VCC Dropout Voltage VIN = 4V, EXTVCC = Open, ICC = 10mA VEXT – VCC EXTVCC Switch Drop VP-GATE – VIN P-Gate to Source Voltage (Off) VSENSE + – VSENSE – Current Sense Threshold Voltage LTC1159 LTC1159-3.3 LTC1159-5 CONDITIONS MIN ● 4.25 VIN = 12V, EXTVCC = 5V, ISWITCH = 10mA VIN = 12V VIN = 40V TYP MAX UNITS 4.5 4.75 V 300 400 mV 250 350 mV – 0.2 – 0.2 0 0 V V VSENSE – = 5V, VFB = 1.32V (Forced) VSENSE – = 5V, VFB = 1.15V (Forced) ● 130 25 150 170 mV mV VSENSE – = 3.4V (Forced) VSENSE – = 3.1V (Forced) ● 130 25 150 170 mV mV VSENSE – = 5.2V (Forced) VSENSE – = 4.7V (Forced) ● 130 25 150 170 mV mV VSNDN1 SHDN1 Threshold LTC1159CG, LTC1159-3.3, LTC1159-5 0.5 0.8 2 V VSHDN2 SHDN2 Threshold 0.8 1.4 2 V ISHDN2 Shutdown 2 Input Current VSHDN2 = 5V 12 20 µA ICT CT Pin Discharge Current VOUT in Regulation VOUT = 0V 50 70 2 90 10 µA µA tOFF Off-Time (Note 5) CT = 390pF, ILOAD = 700mA, VIN = 10V 4 5 6 µs tr, tf Driver Output Transition Times CL = 3000pF (Pins P-Drive and N-Gate), VIN = 6V 100 200 ns MIN TYP MAX UNITS 1.2 1.25 1.3 V 3.17 4.85 3.30 5.05 3.43 5.25 V V – 40°C ≤ TA ≤ 85°C (Note 6) SYMBOL PARAMETER VFB Feedback Voltage (LTC1159 Only) VOUT Regulated Output Voltage LTC1159-3.3 LTC1159-5 IIN VIN Pin Current (Note 4) Normal Shutdown CONDITIONS VIN = 9V ILOAD = 700mA ILOAD = 700mA VIN = 12V, EXTVCC = 5V VIN = 40V, EXTVCC = 5V 200 300 µA µA VIN = 12V, VSHDN2 = 2V VIN = 40V, VSHDN2 = 2V 15 25 µA µA IEXTVCC EXTVCC Pin Current (Note 4) EXTVCC = 5V, Sleep Mode 250 µA VCC Internal Regulator Voltage VIN = 12V to 40V, EXTVCC = 0V, ICC = 10mA 4.5 V VSENSE + – VSENSE – Current Sense Threshold Voltage Low Threshold (Forced) High Threshold (Forced) VSHDN2 SHDN2 Threshold tOFF Off-Time (Note 5) CT = 390pF, ILOAD = 700mA, VIN = 10V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1159CG, LTC1159CG-3.3, LTC1159CG-5: TJ = TA + (PD • 135°C/W) LTC1159CN, LTC1159CN-3.3, LTC1159CN-5: TJ = TA + (PD • 80°C/W) LTC1159CS, LTC1159CS-3.3, LTC1159CS-5: TJ = TA + (PD • 110°C/W) 125 25 150 175 mV mV 0.8 1.4 2 V 3.5 5 6.5 µs Note 3: On LTC1159 versions which have a SHDN1 pin, it must be at ground potential for testing. Note 4: The LTC1159 VIN and EXTVCC current measurements exclude MOSFET driver currents. When VCC power is derived from the output via EXTVCC, the input current increases by (IGATECHG • Duty Cycle)/(Efficiency). See Typical Performance Characteristics and Applications Information. Note 5: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%. 3 LTC1159 LTC1159-3.3/LTC1159-5 ELECTRICAL CHARACTERISTICS Note 6: The LTC1159C, LTC1159C-3.3, and LTC1159C-5 are not tested and not quality assurance sampled at – 40°C and 85°C. These specifications are guaranteed by design and/or correlation. The LTC1159I, LTC1159I-3.3 and LTC1159I-5 are guaranteed and tested over the – 40°C to 85°C operating temperature range. Note 7: The logic-level power MOSFETs shown in Figure 1 are rated for VDS(MAX) = 30V. For operation at VIN > 30V, use standard threshold MOSFETs with EXTVCC powered from a 12V supply. See Applications Information. U W TYPICAL PERFOR A CE CHARACTERISTICS Line Regulation Efficiency vs Input Voltage 100 60 FIGURE 1 CIRCUIT ILOAD = 1A Load Regulation 20 FIGURE 1 CIRCUIT ILOAD = 1A 40 0 20 –20 FIGURE 1 CIRCUIT VIN = 24V NOTE 6 90 0 ∆VOUT (mV) ∆VOUT (mV) EFFICIENCY (%) 95 NOTE 6 –40 –20 –60 –40 –80 85 –100 –60 80 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 0 40 5 10 15 20 25 30 INPUT VOLTAGE (V) 0 40 0.5 1.0 1.5 2.0 LOAD CURRENT (A) EXTVCC Pin Current Operating Frequency vs (VIN – VOUT) VIN Pin Current 500 2.0 FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT 2.5 LTC1159 • TPC03 LT1159 • TPC02 LTC1159 • TPC01 10 35 VOUT = 5V T = 0°C SUPPLY CURRENT (µA) EXTVCC CURRENT (mA) ILOAD = 1A 6 NOTE 6 4 ILOAD = 100mA 300 NORMAL 0 0 5 10 1.5 T = 25°C T = 70°C 1.0 0.5 VSHDN2 = 2V ILOAD = 0 15 20 25 30 INPUT VOLTAGE (V) 35 40 LTC1159 • TPC04 4 NOTE 6 200 100 2 0 NORMALIZED FREQUENCY 400 8 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 LTC1159 • TPC05 0 0 5 15 20 10 (VIN – VOUT) VOLTAGE (V) 25 LTC1159 • TPC06 LTC1159 LTC1159-3.3/LTC1159-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Threshold Voltage Off-Time vs VOUT 160 500 70 140 60 120 400 300 200 SENSE VOLTAGE (mV) 80 OFF-TIME (µs) EXTVCC – VCC (mV) EXTVCC Switch Drop 600 50 40 30 20 100 LTC1159-5 10 MAXIMUM THRESHOLD 100 80 60 40 MINIMUM THRESHOLD 20 LTC1159-3.3 0 0 5 10 15 SWITCH CURRENT (mA) 20 0 0 1 3 4 2 OUTPUT VOLTAGE (V) LTC1159 • TPC07 5 LTC1159 • TPC08 0 0 20 60 40 TEMPERATURE (°C) 80 100 LTC1159 • TPC09 U U U PI FU CTIO S SGND: Small-Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT. SENSE+: The (+) Input for the Current Comparator. A builtin offset between the SENSE+ and SENSE – pins, in conjunction with RSENSE, sets the current trip threshold. PGND: Driver Power Grounds. Connect to source of Nchannel MOSFET and the (–) terminal of CIN. N-Gate: High Current Drive for the Bottom N-Channel MOSFET. The N-Gate pin swings from ground to VCC. VCC: Outputs of internal 4.5V linear regulator, EXTVCC switch, and supply inputs for driver and control circuits. The driver and control circuits are powered from the higher of the 4.5V regulator or EXTVCC voltage. Must be closely decoupled to power ground. P-Gate: Level-Shifted Gate Drive Signal for the Top P-Channel MOSFET. The voltage swing at the P-gate pin is from VIN to VIN – VCC. CT: External capacitor CT from this pin to ground sets the operating frequency. (The frequency is also dependent on the ratio VOUT/VIN.) CAP: Charge Compensation Pin. A capacitor to VCC provides charge required by the P-gate level-shift capacitor during supply transitions. The charge compensation capacitor must be larger than the gate drive capacitor. VIN: Main Supply Input Pin. ITH: Gain Amplifier Decoupling Point. The current comparator threshold increases with the ITH pin voltage. VFB: For the LTC1159 adjustable version, the VFB pin receives the feedback voltage from an external resistive divider used to set the output voltage. SENSE–: Connects to internal resistive divider which sets the output voltage in fixed output versions. The SENSE– pin is also the (–) input of the current comparator. P-Drive: High Current Gate Drive for the Top P-Channel MOSFET. The P-drive pin(s) swing(s) from VCC to ground. SHDN1: This pin shuts down the control circuitry only (VCC is not affected). Taking SHDN1 pin high turns off the control circuitry and holds both MOSFETs off. This pin must be at ground potential for normal operation. SHDN2: Master Shutdown Pin. Taking SHDN2 high shuts down VCC and all control circuitry. 5 LTC1159 LTC1159-3.3/LTC1159-5 W FU CTIO AL DIAGRA Internal divider broken at VFB for adjustable versions. U U VIN SHDN2 EXTVCC VCC P-GATE CAP LOW DROPOUT 4.5V REGULATOR VCC LOW DROP SWITCH 550k P-DRIVE 550k N-GATE SENSE + SENSE – PGND – V + R Q – S C + + 25mV TO 150mV + VTH1 – VOS T 13k – VTH2 100k 1.25V OFF-TIME CONTROL SENSE – CT SGND REFERENCE VFB LTC1159 • FD SHDN1 ITH (Refer to Functional Diagram) The LTC1159 uses a current mode, constant off-time architecture to synchronously switch an external pair of complementary power MOSFETs. Operating frequency is set by an external capacitor at the CT pin. The output voltage is sensed either by an internal voltage divider connected to the SENSE – pin (LTC1159-3.3 and LTC1159-5) or an external divider returned to the VFB pin (LTC1159). A voltage comparator V, and a gain block G, compare the divided output voltage with a reference voltage of 1.25V. To optimize efficiency, the LTC1159 automatically switches between two modes of operation, burst and continuous. A low dropout 4.5V regulator provides the operating voltage VCC for the MOSFET drivers and control circuitry during start-up. During normal operation, the LTC1159 family powers the drivers and control from the output via the EXTVCC pin to improve efficiency. The N-GATE pin is referenced to ground and drives the N-channel MOSFET gate directly. The P-channel gate drive must be referenced to the main supply input VIN, which is accomplished by 6 G + S U OPERATIO – SLEEP level-shifting the P-drive signal via an internal 550k resistor and external capacitor. During the switch “ON” cycle in continuous mode, current comparator C monitors the voltage between the SENSE+ and SENSE– pins connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the P-gate output is switched to VIN, turning off the P-channel MOSFET. The timing capacitor CT is now allowed to discharge at a rate determined by the off-time controller. The discharge current is made proportional to the output voltage to model the inductor current, which decays at a rate which is also proportional to the output voltage. While the timing capacitor is discharging, the N-gate output is high, turning on the N-channel MOSFET. When the voltage on CT has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the N-gate output to go low (turning off the N-channel MOSFET) and the Pgate output to also go low (turning the P-channel MOSFET back on). The cycle then repeats. As the load current LTC1159 LTC1159-3.3/LTC1159-5 U OPERATIO (Refer to Functional Diagram) increases, the output voltage decreases slightly. This causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal SLEEP line to go low and the N-channel MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode, much of the circuitry is turned off, dropping the supply current from several milliamps (with the MOSFETs switching) to 300µA. When the output capacitor has discharged by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset is incorporated in the gain stage. To prevent both the external MOSFETs from being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the N-gate output can go high, the P-drive output must also be high. Likewise, the P-drive output is prevented from going low when the N-gate output is high. U W U U APPLICATIO S I FOR ATIO The LTC1159 Compared to the LTC1148/LTC1149 Families The LTC1159 family is closest in operation to the LTC1149 and shares much of the applications information. In addition to reduced quiescent and shutdown currents, the LTC1159 adds an internal switch which allows the driver and control sections to be powered from an external source for higher efficiency. This change affects Power MOSFET Selection, EXTVCC Pin Connection, Important Information About LTC1159 Adjustable Applications, and Efficiency Considerations found in this section. The basic LTC1159 application circuit shown in Figure 1 is limited to a maximum input voltage of 30V due to MOSFET breakdown. If the application does not require greater than 18V operation, then the LTC1148 or LTC1148HV should be used. For higher input voltages where quiescent and shutdown current are not critical, the LTC1149 may be a better choice since it is set up to drive standard threshold MOSFETs. RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1159 current comparator has a threshold range that extends from a minimum of 0.025V/RSENSE to a maximum of 0.15V/RSENSE. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current IMAX equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, IRIPPLE(P-P) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 0.025V/RSENSE (see CT and L Selection for Operating Frequency). Solving for RSENSE and allowing a margin for variations in the LTC1159 and external component values yields: RSENSE = 100 mΩ IMAX A graph for selecting RSENSE versus maximum output current is given in Figure 2. The LTC1159 series works well with values of RSENSE from 0.02Ω to 0.2Ω. The load current below which Burst Mode operation commences, IBURST, and the peak short-circuit current, ISC(PK), both track IMAX. Once RSENSE has been chosen, IBURST and ISC(PK) can be predicted from the following equations: 7 LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO 1400 0.20 VOUT = 5V 0.18 1200 CT CAPACITANCE (pF) 0.16 RSENSE (Ω) 0.14 0.12 0.10 0.08 0.06 0.04 1000 800 VIN = 48V 600 VIN = 24V 400 200 VIN = 12V 0.02 0 0 0 1 3 4 2 MAXIMUM OUTPUT CURRENT (A) 5 0 50 150 100 FREQUENCY (kHz) Once the frequency has been set by CT, the inductor L must be chosen to provide no more than 0.025V/RSENSE of peak-to-peak inductor ripple current. This results in a minimum required inductor value of: ISC(PK) = 150mV RSENSE The LTC1159 automatically extends tOFF during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current ISC(AVG) to be reduced to approximately IMAX. L and CT Selection for Operating Frequency The LTC1159 uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. The value of CT is calculated from the desired continuous mode operating frequency, f: ) –5 V CT = 7.8 • 10 1 – OUT VIN f ) A graph for selecting CT versus frequency including the effects of input voltage is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency is given by: 8 ) 1 1 – VOUT tOFF VIN Figure 3. Timing Capacitor Selection where tOFF = 1.3 • 104 • CT IBURST ≈ 15mV RSENSE f= 250 LTC1159 • F03 LTC1159 • F02 Figure 2. RSENSE vs Maximum Output Current 200 ) LMIN = 5.1 • 105 • RSENSE • CT • VREG As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too small an inductor is used, the LTC1159 may not enter Burst Mode operation and efficiency will be severely degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As inductance increases, core losses go down but copper (I2R) losses will increase. Ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in Kool Mµ is a registered trademark of Magnetics, Inc. LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO inductor ripple current and consequent output voltage ripple which can cause Burst Mode operation to be falsely triggered in the LTC1159. Do not allow the core to saturate! The MOSFET dissipations at maximum output current are given by: Molypermalloy (from Magnetics, Inc.) is a low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new surface mount designs available from Coiltronics do not increase the height significantly. P-Ch PD = Power MOSFET Selection Two external power MOSFETs must be selected for use with the LTC1159: a P-channel MOSFET for the main switch and an N-channel MOSFET for the synchronous switch. The peak-to-peak drive levels are set by the VCC voltage on the LTC1159. This voltage is typically 4.5V during start-up and 5V to 7V during normal operation (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1159 family applications. The only exception is applications in which EXTVCC is powered from an external supply greater than 8V, in which standard threshold MOSFETs (VGS(TH) < 4V) may be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1159 is operating in continuous mode, the duty cycle for the P-channel MOSFET is given by: V P-Ch Duty Cycle = OUT VIN V –V N-Ch Duty Cycle = IN OUT VIN VOUT (I )2 (1 + ∂P) RDS(ON) + VIN MAX k(VIN)2 (IMAX) (CRSS) (f) V –V N-Ch PD = IN OUT (IMAX)2 (1 + ∂N) RDS(ON) VIN where ∂ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the P-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The N-channel MOSFET losses are the greatest at high input voltage or during a short circuit when the N-channel duty cycle is nearly 100%. The term (1 + ∂) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but ∂ = 0.007/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET electrical characteristics. The constant k = 5 can be used for the LTC1159 to estimate the relative contributions of the two terms in the P-channel dissipation equation. The Schottky diode D1 shown in Figure 1 only conducts during the dead time between the conduction of the two power MOSFETs. D1 prevents the body diode of the N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D1 is omitted). Therefore, D1 should be selected for a forward voltage of less than 0.6V when conducting IMAX. 9 LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: [V (V – V )]1/2 I CIN Required IRMS ≈ MAX OUT IN OUT VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IMAX/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. An additional 0.1µF ceramic capacitor may also be required on VIN for high frequency decoupling. The selection of COUT is driven by the required effective series resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1159: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. Manufacturers such as Nichicon, Chemicon, and Sprague should be considered for high performance capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR for its size at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For example, 10 if 200µF/10V is called for in an application requiring 3mm height, two AVX 100µF/10V (P/N TPSD107K010) could be used. Consult the manufacturer for other specific recommendations. At low supply voltages, a minimum value of COUT is suggested to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is too small, the output ripple at low frequencies will be large enough to trip the voltage comparator. This causes the Burst Mode operation to be activated when the LTC1159 would normally be in continuous operation. The effect is most pronounced with low values of RSENSE and can be improved by operating at higher frequencies with lower values of L. The output remains in regulation at all times. 1000 L = 50µH RSENSE = 0.02Ω 800 COUT (µF) CIN and COUT Selection L = 25µH RSENSE = 0.02Ω 600 400 L = 50µH RSENSE = 0.05Ω 200 0 0 1 3 4 2 (VIN – VOUT) VOLTAGE (V) 5 LTC1159 • TPC04 Figure 4. Minimum Suggested COUT Load Transient Response Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT until the regulator loop adapts to the current change and returns VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing which would indicate a stability problem. The ITH external components shown in the Figure 1 circuit will provide adequate compensation for most applications. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Line Transient Response The LTC1159 has better than 60dB line rejection and is generally impervious to large positive or negative line voltage transients. However, one rarely occurring condition can cause the output voltage to overshoot if the proper precautions are not observed. This condition is a negative VIN transition of several volts followed within 100µs by a positive transition of greater than 0.5V/µs slew rate. The reason this condition rarely occurs is because it takes tens of amps to slew the regulator input capacitor at this rate! The solution is to add a diode between the cap and VIN pins of the LTC1159 as shown in several of the typical application circuits. If you think your system could have this problem, add the diode. Note that in surface mount applications it can be combined with the P-gate diode by using a low cost common cathode dual diode. EXTVCC Pin Connection The LTC1159 contains an internal PNP switch connected between the EXTVCC and VCC pins. The switch closes and supplies the VCC power whenever the EXTVCC pin is higher in voltage than the 4.5V internal regulator. This allows the MOSFET driver and control power to be derived from the output during normal operation and from the internal regulator when the output is out of regulation (start-up, short circuit). Significant efficiency gains can be realized by powering VCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other low voltage regulators, additional circuitry is required to derive VCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC Left Open. This will cause VCC to be powered only from the internal 4.5V regulator resulting in reduced MOSFET gate drive levels and an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected Directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage which has been boosted to greater than 4.5V. This can be done either with the inductive boost winding shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics and generally provides the highest efficiency at the expense of a slightly higher parts count. VIN VIN + + BAT85 CIN VIN P-GATE L 1:1 P-CH P-DRIVE 1 • LTC1159-3.3 N-GATE P-GND P-GATE + 1µF • CIN VIN RSENSE 4 N-CH RSENSE L VOUT P-DRIVE 2 3 P-CH + COUT VOUT LTC1159-3.3 LTC1159 • F05a Figure 5a. Inductive Boost Circuit for EXTVCC BAT85 + COUT P-GND EXTVCC EXTVCC VN2222LL N-CH N-GATE BAT85 + 0.22µF BAT85 LTC1159 • F05b 1µF Figure 5b. Capacitive Charge Pump for EXTVCC 11 LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO 4. EXTVCC Connected to an External Supply. If an external supply is available in the 5V to 12V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. There are no restrictions on the EXTVCC voltage relative to VIN. EXTVCC may be higher than VIN providing EXTVCC does not exceed the 15V absolute maximum rating. In LTC1159N and LTC1159S applications with VOUT > 5.5V, the VCC pin may self-power through the SENSE pins when SHDN2 is taken high, preventing shutdown. In these applications, a pull-down must be added to the SENSE– pin as shown in Figure 6. This pull-down effectively takes the place of the SHDN1 pin, ensuring complete shutdown. Note: For versions in which both the SHDN1 and SHDN2 pins are available (LTC1159G and all fixed output versions), the two pins are simply connected to each other and driven together to guarantee complete shutdown. The Figure 6 circuit cannot be used to regulate a VOUT which is greater than the maximum voltage allowed on the LTC1159 SENSE pins (13V). In applications with VOUT > 13V, RSENSE must be moved to the ground side of the output capacitor and load. This operates the current sense comparator at 0V common mode, increasing the off-time approximately 40% and requiring the use of a smaller timing capacitor CT. When driving standard threshold MOSFETs, the external supply must always be present during operation to prevent MOSFET failure due to insufficient gate drive. The LTC1149 family should also be considered for applications which require the use of standard threshold MOSFETs. Important Information About LTC1159 Adjustable Applications When an output voltage other than 3.3V or 5V is required, the LTC1159 adjustable version is used with an external resistive divider from VOUT to the VFB pin (Figure 6). The regulated voltage is determined by: ) Inverting Regular Applications ) VOUT = 1 + R2 1.25V R1 The LTC1159 can also be used to obtain negative output voltages from positive inputs. In these inverting applications, the current sense resistor connects to ground while the LTC1159 and N-channel MOSFET connections, which would normally go to ground, instead ride on the negative output. This allows the negative output voltage to be set by The VFB pin is extremely sensitive to pickup from the inductor switching node. Care should be taken to isolate the feedback network from the inductor, and the 100pF capacitor should be connected between the VFB and SGND pins next to the package. VIN CAP 0.15µF + 1µF 3300pF 1k + 1N4148 VIN P-GATE LTC1159 P-DRIVE VCC N-GATE ITH PGND CT EXTVCC CT 390pF Si4401DY 0.1µF VCC VFB 100µF 50V 100µH 5M 1 RSENSE 0.039Ω 2 Si4840DY 1N5819 R2 215k R1 24.9k 100pF SGND 100Ω SENSE + 0V = NORMAL >3V = SHUTDOWN SHDN2 SENSE – 0.01µF VN2222LL 100Ω ( ) LTC1159 • F06 VOUT = 1 + R2 1.25 R1 VALUES SHOWN FOR VOUT = 12V/2.5A Figure 6. High Efficiency Adjustable Regulator with 5.5V < VOUT < 13V 12 VOUT 4 3 + 150µF 16V OS-CON LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO the same process as in conventional applications, using either the internal divider (LTC1159-3.3, LTC1159-5) or an external divider with the adjustable version. Figure 15 in the Typical Applications shows a synchronous 12V to –12V converter that can supply up to 1A with better than 85% efficiency. By grounding the EXTVCC pin in the Figure 15 circuit, the entire 12V output voltage is placed across the driver and control circuits since the LTC1159 ground pins are at –12V. During start-up or short-circuit conditions, operating power is supplied by the internal 4.5V regulator. The shutdown signal is level-shifted to the negative output rail by Q3, and Q4 ensures that Q1 and Q2 remain off during the entire shutdown sequence. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100 – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1159 circuits: 1) LTC1159 VIN current, 2) LTC1159 VCC current, 3) I2R losses and 4) P-channel transition losses. 1. LTC1159 VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (< 1%) loss which increases with VIN. 2. LTC1159 VCC current is the sum of the MOSFET driver and control circuit currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VCC to ground. The resulting dQ/dt is a current out of VCC which is typically much larger than the control circuit current. In continuous mode, IGATECHG ≈ f (QP + QN), where QP and QN are the gate charges of the two MOSFETs. By powering EXTVCC from an output-derived source, the additional VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For example in a 20V to 5V application, 10mA of VCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode all of the output current flows through L and RSENSE, but is “chopped” between the P-channel and N-channel MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω, and RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I2R losses cause the efficiency to roll-off at high output currents. 4. Transition losses apply only to the P-channel MOSFET, and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss ≈ 5(VIN)2(IMAX)(CRSS)(f) Other losses including CIN and COUT ESR dissipative losses, Schottky conduction losses during dead time, and inductor core losses, generally account for less than 2% total additional loss. Auxiliary Windings—Suppressing Burst Mode Operation The LTC1159 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. Burst Mode operation can be suppressed at low output currents with a simple external network that cancels the 0.025V minimum current comparator threshold. This technique is also useful for eliminating audible noise from 13 LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the SENSE – pin to subtract from the built-in 0.025V offset. An example of this technique is shown in Figure 7. Two 100Ω resistors are inserted in series with the leads from the sense resistor. With the addition of R3, a current is generated through R1 causing an offset of: VOFFSET = VOUT ) ) R1 R1 + R3 1 RSENSE 9 SENSE – 8 Board Layout Checklist 2 4 3 SENSE + R2 100Ω + COUT R1 100Ω 1000pF RSENSE ≈ 75 mΩ IMAX To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across the SENSE – and SENSE + pins. L LTC1159 If VOFFSET > 0.025V, the minimum threshold will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be reduced: LTC1159 • F07 R3 When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1159. These items are also illustrated graphically in the layout diagram of Figure 8. Check the following in your layout: Figure 7. Suppressing Burst Mode Operation + BOLD LINES INDICATE HIGH CURRENT PATHS + CIN 1N4148 P-CHANNEL VIN 0.15µF D1 1µF N-CHANNEL – + 2 0.1 µF 3 4 5 6 7 CT 3300pF 8 P-GATE CAP VIN SHDN2 VCC EXTVCC P-DRIVE N-GATE VCC PGND CT SGND ITH SENSE – VFB (SHDN1) SENSE + 16 15 SHUTDOWN 14 L 13 OUTPUT DIVIDER REQUIRED WITH ADJUSTABLE VERSION ONLY 5V EXTVCC CONNECTION 12 11 10 – 100pF R1 9 3 + 1 COUT 1 VOUT RSENSE 2 R2 1k 1000pF 4 LTC1159 • F08 Figure 8. LTC1159 Layout Diagram (N and S Packages) 14 + LTC1159 LTC1159-3.3/LTC1159-5 U W U U APPLICATIO S I FOR ATIO 1) Are the signal and power grounds segregated? The LTC1159 signal ground must connect separately to the (–) plate of COUT. The other ground pin(s) should return to the source of the N-channel MOSFET, anode of the Schottky diode and (–) plate of CIN, which should have as short lead lengths as possible. 2) Does the LTC1159 SENSE– pin connect to a point close to RSENSE and the (+) plate of COUT? In adjustable applications, the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. 3) Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The differential decoupling capacitor between the two SENSE pins should be as close as possible to the LTC1159. Up to 100Ω may be placed in series with each sense lead to help decouple the SENSE pins. However, when these resistors are used, the capacitor should be no larger than 1000pF. 4) Does the (+) plate of CIN connect to the source of the P-channel MOSFET as closely as possible? An additional 0.1µF ceramic capacitor between VIN and power ground may be required in some applications. 5) Is the VCC decoupling capacitor connected closely between the VCC pins of the LTC1159 and power ground? This capacitor carries the MOSFET driver peak currents. 6) In adjustable versions, the feedback pin is very sensitive to pickup from the switch node. Care must be taken to isolate VFB from possible capacitive coupling of the inductor switch signal. 7) Is the SHDN1 pin actively pulled to ground during normal operation? SHDN1 is a high impedance pin and must not be allowed to float. Troubleshooting Hints Since efficiency is critical to LTC1159 applications it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the CT pin . In continuous mode (ILOAD > IBURST) the voltage should be a sawtooth with a 0.9VP-P swing. This voltage should never dip below 2V as shown in Figure 9a. When the load current is low (ILOAD < IBURST), Burst Mode operation should occur with the CT waveform periodically falling to ground as shown in Figure 9b. If the CT pin is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist. 3.3V 0V (a) CONTINUOUS MODE OPERATION 3.3V 0V (b) Burst Mode OPERATION LTC1159 • F09 Figure 9. CT Pin 6 Waveforms 15 LTC1159 LTC1159-3.3/LTC1159-5 U TYPICAL APPLICATIO S VIN 8V TO 20V 5V 1N4148 + 1N4148 IRF7205 1 0.15µF 2 0.1µF 3 4 5 + 3.3µF 6 1000pF 7 0.047µF 8 2k P-GATE CAP VIN SHDN2 VCC EXTVCC L* 15µH 16 15 ITH VFB SENSE – SENSE + VOUT 2.5V/5A 4 3 14 + IRF7201 P-DRIVE N-GATE LTC1159 12 VCC PGND SGND 1µF WIMA RSENSE** 1 0.02Ω 2 SHUTDOWN 13 CT 47µF 25V × 2 OS-CON IRF7201 330µF 6.3V × 3 AVX MBRS330 11 10 10k 1% 100pF 10k 1% 9 10k 100Ω 100Ω 1000pF LTC1159 • F10 *MAGNETICS 77120-A7 CORE, 16T 18GA. WIRE **KRL SL-1-R020J Figure 10. High Efficiency 8V to 20V Input 2.5/5A Output Regulator VIN 4V TO 20V 1N4148 + 1N4148 Si9435DY 1 0.15µF 0.1µF 2 3 4 + 1µF 270pF CAP VIN SHDN2 VCC EXTVCC 6 11 8 ITH SHDN1 SENSE – RSENSE** 1 0.04Ω 2 3 14 P-DRIVE N-GATE LTC1159-3.3 12 VCC PGND SGND L* 20µH 15 13 CT 0.1µF 16 5 7 3300pF P-GATE 47µF 25V OS-CON 10 VN2222LL BAT85 0.22µF BAT85 BAT85 Si9410DY MBRS130LT3 VOUT 3.3V/2.5A 4 + 330µF 6.3V × 2 AVX + 1µF SHUTDOWN 9 SENSE + 1k 0.01µF LTC1159 • F11 *COILTRONICS CTX20-4 **KRL SL-1/2-R040J Figure 11. 5:1 Input Range (4V to 20V) High Efficiency 3.3V/2.5A Regulator 16 LTC1159 LTC1159-3.3/LTC1159-5 U TYPICAL APPLICATIO S VIN 15V TO 40V 12V + 0.33µF MPSA06 0.1µF 1N4148 1200µF 50V × 2 LXF 1N4148 SMP40P06 HEAT SINK 1µF WIMA MPSA56 1 2 0.15µF 3 P-GATE CAP VIN SHDN2 VCC EXTVCC 16 L* 22µH 15 14 + 13 P-DRIVE N-GATE LTC1159-5 5 12 VCC PGND 7 + 10µF 750pF 0.047µF 8 CT SGND ITH SHDN1 SENSE – VOUT 5V/10A 4 3 1N4148 4 6 RSENSE** 1 0.01Ω 2 MBR350 MTP75N05HD MPSA56 220µF 10V × 3 OS-CON 11 10 SHUTDOWN 100Ω 9 SENSE + 470Ω 1000pF 100Ω LTC1159 • F12 *HURRICANE LAB HL-KK122T/BB **DALE LVR-3-0.01 18k Figure 12. High Current, High Efficiency 15V to 40V Input 5V/10A Output Regulator VIN 15V TO 40V 1N4148 + 1N4148 Si4401DY L* 50µH 5M 1 0.15µF 0.1µF 2 3 P-GATE CAP VIN SHDN2 VCC EXTVCC 16 15 6 390pF 7 3300pF 8 CT SGND ITH VFB SENSE – SENSE + VOUT 12V/5A 4 14 13 P-DRIVE N-GATE LTC1159 5 12 VCC PGND 3.3µF 1µF WIMA RSENSE** 1 0.02Ω 2 3 4 + 100µF 63V × 2 SXC Si4840DY MBR350 + 150µF 16V × 2 OS-CON 11 10 100pF 10.5k 1% 90.9k 1% 9 470Ω 1000pF 100Ω 100Ω LTC1159 • F13 VN2222LL 0V = NORMAL >3V = SHUTDOWN *COILTRONICS CTX50-5-KM **IRC LO-3-0.02 ±5% Figure 13. High Efficiency 15V to 40V Input 12V/5A Output Regulator 17 LTC1159 LTC1159-3.3/LTC1159-5 U TYPICAL APPLICATIO S VIN 5.5V TO 24V BAS16 + BAS16 Si9435DY 47µF 25V × 2 OS-CON Si9435DY 1µF WIMA T* 0.22µF 2 3 CAP VIN SHDN2 VCC EXTVCC 16 • 15 0V = NORMAL >2V = SHUTDOWN 14 • 4 13 P-DRIVE N-GATE LTC1159 5 12 VCC PGND + 2.2µF 6 1000pF 7 2200pF 8 CT SGND ITH VFB SENSE – 5V OUTPUT • Si9410DY + Si9410DY MBRS140T3 1µF BAS16 100k 220µF 10V × 2 AVX 11 10 56pF 24.9k 1% 0.01µF 1k 102k 1% 9 SENSE + 124k 1% 1k 100Ω + 0.33µF P-GATE + 1 220µF 10V × 4 AVX 3 1 1000pF 100Ω 2 BAS16 RSENSE** 0.02Ω 3.3V OUTPUT 4 BAS16 LTC1159 • F14 + *HURRICANE LAB HL-8700 **KRL SL-1-R020J 10µF Figure 14. 17W Dual Output High Efficiency 5V and 3.3V Regulator U PACKAGE DESCRIPTIO G Package 20-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 5.20 – 5.38** (.205 – .212) 1.73 – 1.99 (.068 – .078) 7.07 – 7.33* (.278 – .289) 20 19 18 17 16 15 14 13 12 11 0° – 8° .13 – .22 (.005 – .009) .55 – .95 (.022 – .037) .65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 18 7.65 – 7.90 (.301 – .311) .25 – .38 (.010 – .015) .05 – .21 (.002 – .008) 1 2 3 4 5 6 7 8 9 10 G20 SSOP 0501 LTC1159 LTC1159-3.3/LTC1159-5 U PACKAGE DESCRIPTIO N Package 16-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.020 (0.508) MIN 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 0.045 – 0.065 (1.143 – 1.651) ) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) N16 1098 S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) TYP 8 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 7 0.050 (1.270) BSC S16 1098 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1159 LTC1159-3.3/LTC1159-5 U TYPICAL APPLICATIO VIN = 12V Q1 Si9435 1N4148 0.1µF + 330µF 35V NICHICON 0.15µF 0.1µF 3 4 1N5818 5 6 7 5V OR 3.3V CT 390pF Q3 TP0610L SHUTDOWN 6800pF 8 CAP VIN SHDN2 EXTVCC LTC1159 P-DRIVE N-GATE VCC 3.3µF VCC CT PGND SGND VFB (SHDN1) ITH SENSE – SENSE + Q2 Si9410 16 MBRS140 15 L* 100µH 14 13 12 11 OUTPUT –12V/1A 10 200pF 10.5k Q4 2N7002 90.5k 9 1k 1000pF + 2 P-GATE + 1 150µF 16V × 2 OS-CON 20k 100Ω 510k 100Ω 3 1 5.1V 1N5993 2 RSENSE** 0.05Ω 4 1159 F15 *DALE TJ4-100-1µ **IRC LR2512-01-R050-J Figure 15. High Efficiency 12V to –12V 1A Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1628 2-Phase, Dual Step-Down Controller VIN ≤ 36V, Minimum CIN, Current Mode LTC1702 550kHz Dual, 2-Phase Step-Down Controller Minimum CIN, No Sense Resistor Required, VIN ≤ 7V LTC1735 Synchronous Step-Down Controller 3.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, Synchronizable LTC1773 550kHz Synchronous Step-Down Controller 2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN, Synchronizable to 750kHz, MS10 LTC1778 No RSENSETM Step-Down Controller No Sense Resistor Required, tON(MIN) ≤ 100ns, Current Mode, GN16 LTC1876 Triple Output, 2-Phase Controller Two, 2-Phase Step-Down Controllers and Step-Up DC/DC Converter in One IC No RSENSE is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation 1159fa LT/TP 0801 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 1994