LTC1198-1ACS8#TRPBF

LTC1196/LTC1198 8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options FEATURES n n n n n n n n n n n n DESCRIPTION High Sampling Rates: 1MHz (LTC1196) 750kHz (LTC1198) Low Cost Single Supply 3V and 5V Specifications Low Power: 10mW at 3V Supply 50mW at 5V Supply Auto-Shutdown: 1nA Typical (LTC1198) ±1/2LSB Total Unadjusted Error over Temperature 3-Wire Serial I/O 1V to 5V Input Span Range (LTC1196) Converts 1MHz Inputs to 7 Effective Bits Differential Inputs (LTC1196) 2-Channel MUX (LTC1198) SO-8 Plastic Package n n n The 3-wire serial I/O, SO-8 packages, 3V operation and extremely high sample rate-to-power ratio make these ADCs an ideal choice for compact, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans below 1V full scale (LTC1196) allow direct connection to signal sources in many applications, eliminating the need for gain stages. APPLICATIONS n The LTC®1196/LTC1198 are 600ns, 8-bit A/D converters with sampling rates up to 1MHz. They are offered in 8-pin SO packages and operate on 3V to 6V supplies. Power dissipation is only 10mW with a 3V supply or 50mW with a 5V supply. The LTC1198 automatically powers down to a typical supply current of 1nA whenever it is not performing conversions. These 8-bit switched-capacitor successive approximation ADCs include sample-andholds. The LTC1196 has a differential analog input; the LTC1198 offers a software selectable 2-channel MUX. High Speed Data Acquisition Disk Drives Portable or Compact Instrumentation Low Power or Battery-Operated Systems The A-grade devices are specified with total unadjusted error of ±1/2LSB maximum over temperature. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Single 5V Supply, 1Msps, 8-Bit Sampling ADC 2 ANALOG INPUT 0V TO 5V RANGE 3 4 CS +IN –IN GND VCC LTC1196 CLK DOUT VREF 8 7 6 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP, OR SHIFT REGISTERS 5 1196/98 TA01 50 VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) 7 6 44 VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 5 S/(N + D) (dB) 1 8 5V EFFECTIVE NUMBER OF BITS (ENOBs) 1μF Effective Bits and S/(N + D) vs Input Frequency 4 3 2 1 TA = 25°C 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 11968 TA01b 119698fb 1 LTC1196/LTC1198 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND .................................... 7V Voltage Analog Reference ....................... –0.3V to VCC + 0.3V Digital Inputs ......................................... –0.3V to 7V Digital Outputs ........................... –0.3V to VCC + 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1196-1AC, LTC1198-1AC, LTC1196-1BC, LTC1198-1BC, LTC1196-2AC, LTC1198-2AC, LTC1196-2BC, LTC1198-2BC ................. 0°C to 70°C Storage Temperature Range.................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ................ 300°C PIN CONFIGURATION LTC1196 LTC1198 TOP VIEW CS 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 VREF TOP VIEW CS/ 1 SHUTDOWN CH0 2 8 VCC (VREF) 7 CLK CH1 3 6 DOUT GND 4 5 DIN S8 PACKAGE 8-LEAD PLASTIC SO S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W TJMAX = 150°C, θJA = 175°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1196-1ACS8#PBF LTC1196-1ACS8#TRPBF 11961A 8-Lead Plastic SO 0°C to 70°C LTC1196-1BCS8#PBF LTC1196-1BCS8#TRPBF 11961B 8-Lead Plastic SO 0°C to 70°C LTC1196-2ACS8#PBF LTC1196-2ACS8#TRPBF 11962A 8-Lead Plastic SO 0°C to 70°C LTC1196-2BCS8#PBF LTC1196-2BCS8#TRPBF 11962B 8-Lead Plastic SO 0°C to 70°C LTC1198-1ACS8#PBF LTC1198-1ACS8#TRPBF 11981A 8-Lead Plastic SO 0°C to 70°C LTC1198-1BCS8#PBF LTC1198-1BCS8#TRPBF 11981B 8-Lead Plastic SO 0°C to 70°C LTC1198-2ACS8#PBF LTC1198-2ACS8#TRPBF 11982A 8-Lead Plastic SO 0°C to 70°C LTC1198-2BCS8#PBF LTC1198-2BCS8#TRPBF 11982B 8-Lead Plastic SO 0°C to 70°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 119698fb 2 LTC1196/LTC1198 RECOMMENDED OPERATING CONDITIONS The l denotes the specifications which apply over SYMBOL PARAMETER LTC1196-1 LTC1198-1 TYP VCC Supply Voltage the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS MIN LTC1196-2 LTC1198-2 TYP MAX MAX MIN 2.7 6 2.7 6 0.01 0.01 14.4 12.0 0.01 0.01 12.0 9.6 UNITS V VCC = 5V Operation fCLK Clock Frequency tCYC Total Cycle Time l LTC1196 LTC1198 MHz MHz 12 16 12 16 CLK CLK tSMPL Analog Input Sampling Time 2.5 2.5 CLK thCS Hold Time CS LOW After Last CLK↑ 10 13 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) 20 26 ns thDI Hold Time DIN After CLK↑ LTC1198 20 26 ns tsuDI Setup Time DIN Stable Before CLK↑ LTC1198 20 26 ns tWHCLK CLK HIGH Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWLCLK CLK LOW Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWHCS CS HIGH Time Between Data Transfer Cycles 25 32 ns tWLCS CS LOW Time During Data Transfer 11 15 11 15 CLK CLK LTC1196 LTC1198 CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. PARAMETER CONDITIONS l No Missing Codes Resolution LTC1196-1A/LTC1196-2A LTC1198-1A/LTC1198-2A LTC1196-1B/LTC1196-2B LTC1198-1B/LTC1198-2B MIN MIN TYP MAX 8 TYP MAX 8 UNITS Bits l ±1/2 ±1 LSB l ±1/2 ±1 LSB Full-Scale Error l ±1/2 ±1 LSB Total Unadjusted Error (Note 4) l ±1/2 ±1 LSB ±1 μA Offset Error Linearity Error (Note 3) LTC1196, VREF = 5.000V LTC1198, VCC = 5.000V Analog and REF Input Range LTC1196 Analog Input Leakage Current (Note 5) –0.05V to VCC + 0.05V l ±1 V DIGITAL AND DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VCC = 5.25V l VIL Low Level Input Voltage VCC = 4.75V l TYP MAX 2.0 UNITS V 0.8 V IIH High Level Input Current VIN = VCC l 2.5 μA IIL Low Level Input Current VIN = 0V l –2.5 μA VOH High Level Output Voltage VCC = 4.75V, IO = 10μA VCC = 4.75V, IO = 360μA l l 4.5 2.4 4.74 4.71 V V 119698fb 3 LTC1196/LTC1198 DIGITAL AND DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA l l IOZ Hi-Z Output Leakage CS = HIGH ISOURCE Output Source Current VOUT = 0V MIN TYP MAX UNITS 0.4 V ±3 μA –25 mA ISINK Output Sink Current VOUT = VCC IREF Reference Current, LTC1196 CS = VCC fSMPL = fSMPL(MAX) l l 0.001 0.5 45 3 1 mA μA mA ICC Supply Current CS = VCC, LTC1198 (Shutdown) CS = VCC, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 l l l 0.001 7 11 3 15 20 μA mA mA DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. MAX MIN LTC1198 TYP CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion 500kHz/1MHz Input Signal 47/45 47/45 dB THD Total Harmonic Distortion 500kHz/1MHz Input Signal 49/47 49/47 dB Peak Harmonic or Spurious Noise 500kHz/1MHz Input Signal 55/48 55/48 dB Intermodulation Distortion fIN1 = 499.37kHz fIN2 = 502.446kHz 51 51 dB IMD MIN LTC1196 TYP SYMBOL PARAMETER MAX UNITS Full-Power Bandwidth 8 8 MHz Full Linear Bandwidth [S/(N + D) > 44dB 1 1 MHz AC CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER tCONV Conversion Time (See Figures 1, 2) CONDITIONS MIN LTC1196-1 LTC1198-1 TYP LTC1196 LTC1196 LTC1198 LTC1198 tdDO Delay Time, CLK↑ to DOUT Data Valid CLOAD = 20pF tDIS Delay Time CS↑ to DOUT Hi-Z ten Delay Time, CLK↓ to DOUT Enabled thDO l l MIN 600 710 l fSMPL(MAX) Maximum Sampling Frequency MAX LTC1196-2 LTC1198-2 TYP 1.20 1.00 0.90 0.75 MAX UNITS 710 900 ns ns 1.00 0.80 0.75 0.60 MHz MHz MHz MHz 55 64 73 68 78 94 ns ns l 70 120 88 150 ns CLOAD = 20pF l 30 50 43 63 ns Time Output Data Remains Valid After CLK↑ CLOAD = 20pF l tf DOUT Fall Time CLOAD = 20pF l tr DOUT Rise CLOAD = 20pF l CIN Input Capacitance Analog Input On Channel Analog Input Off Channel Digital Input l 30 45 30 55 ns 5 15 10 20 ns 5 15 10 20 ns 30 5 5 30 5 5 pF pF pF 119698fb 4 LTC1196/LTC1198 RECOMMENDED OPERATING CONDITIONS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V operation. SYMBOL PARAMETER fCLK Clock Frequency tCYC Total Cycle Time CONDITIONS MIN l LTC1196 LTC1198 LTC1196-1 LTC1198-1 TYP 0.01 0.01 MAX MIN 5.4 4.6 0.01 0.01 LTC1196-2 LTC1198-2 TYP MAX UNITS 4 3 MHz MHz 12 16 12 16 CLK CLK tSMPL Analog Input Sampling Time 2.5 2.5 CLK thCS Hold Time CS LOW After Last CLK↑ 20 40 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Figures 1, 2) 40 78 ns thDI Hold Time DIN After CLK↑ LTC1198 40 78 ns tsuDI Setup Time DIN Stable Before CLK↑ LTC1198 40 78 ns tWHCLK CLK HIGH Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWLCLK CLK LOW Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWHCS CS HIGH Time Between Data Transfer Cycles 50 96 ns tWLCS CS LOW Time During Data Transfer 11 15 11 15 CLK CLK LTC1196 LTC1198 CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. PARAMETER CONDITIONS LTC1196-1A/LTC1196-2A LTC1198-1A/LTC1198-2A LTC1196-1B/LTC1196-2B LTC1198-1B/LTC1198-2B MIN MIN TYP MAX TYP MAX UNITS No Missing Codes Resolution l Offset Error l ±1/2 ±1 LSB l ±1/2 ±1 LSB l ±1/2 ±1 LSB l ±1/2 ±1 LSB Linearity Error (Note 3) Full-Scale Error Total Unadjusted Error (Note 4) LTC1196, VREF = 2.5.000V LTC1198, VCC = 2.700V Analog and REF Input Range LTC1196 Analog Input Leakage Current (Note 5) 8 8 Bits –0.05V to VCC + 0.05V l ±1 V ±1 μA DIGITAL AND DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 3.6V l MIN TYP MAX VIL Low Level Input Voltage VCC = 2.7V l 2.5 μA –2.5 μA 1.9 UNITS V 0.45 V IIH High Level Input Current VIN = VCC l IIL Low Level Input Current VIN = 0V l VOH High Level Output Voltage VCC = 2.7V, IO = 10μA VCC = 2.7V, IO = 360μA l l VOL Low Level Output Voltage VCC = 2.7V, IO = 400μA l 0.3 V CS = HIGH l ±3 μA IOZ Hi-Z Output Leakage 2.3 2.1 2.60 2.45 V V 119698fb 5 LTC1196/LTC1198 DIGITAL AND DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS ISOURCE Output Source Current VOUT = 0V ISINK Output Sink Current VOUT = VCC MIN IREF Reference Current, LTC1196 CS = VCC fSMPL = fSMPL(MAX) l l ICC Supply Current CS = VCC = 3.3V, LTC1198 (Shutdown) CS = VCC = 3.3V, LTC1196 fSMPL = fSMPL(MAX), LTC1196/LTC1198 l l l TYP MAX UNITS –10 mA 15 mA 0.001 0.25 3.0 0.5 μA mA 0.001 1.5 2.0 3.0 4.5 6.0 μA mA mA DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion 190kHz/380kHz Input Signal THD IMD MIN LTC1196 TYP MAX MIN 47/45 LTC1198 TYP MAX 47/45 UNITS dB Total Harmonic Distortion 190kHz/380kHz Input Signal 49/47 49/47 dB Peak Harmonic or Spurious Noise 190kHz/380kHz Input Signal 53/46 53/46 dB Intermodulation Distortion fIN1 = 189.37kHz fIN2 = 192.446kHz 51 51 dB 5 5 MHz 0.5 0.5 MHz Full-Power Bandwidth Full Linear Bandwidth [S/(N + D) > 44dB AC CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL PARAMETER tCONV Conversion Time (See Figures 1, 2) CONDITIONS MIN LTC1196-1 LTC1198-1 TYP tdDO Delay Time, CLK↑ to DOUT Data Valid tDIS Delay Time CS↑ to DOUT Hi-Z ten Delay Time, CLK↓ to DOUT Enabled LTC1196 LTC1196 LTC1198 LTC1198 CLOAD = 20pF l l MIN 1.58 1.85 l fSMPL(MAX) Maximum Sampling Frequency MAX LTC1196-2 LTC1198-2 TYP 450 383 337 287 MAX UNITS 2.13 2.84 μs μs 333 250 250 187 kHz kHz kHz kHz 100 150 180 130 200 250 ns ns l 110 220 120 250 ns CLOAD = 20pF l 80 130 100 200 ns l thDO Time Output Data Remains Valid After CLK↑ CLOAD = 20pF l tf DOUT Fall Time CLOAD = 20pF l 10 30 15 40 ns tr DOUT Rise CLOAD = 20pF l 10 30 15 40 ns CIN Input Capacitance Analog Input On Channel Analog Input Off Channel Digital Input Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute 45 90 30 5 5 45 120 ns 30 5 5 pF pF pF Maximum Rating condition for extended periods may affect device reliability and lifetime. 119698fb 6 LTC1196/LTC1198 ELECTRICAL CHARACTERISTICS Note 4: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. Note 5: Channel leakage current is measured after the channel selection. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Clock Rate 9 14 TA = 25°C CS = 0V VREF = VCC 3 VCC = 2.7V 2 10 ACTIVE MODE CS = 0V 8 LTC1196 LTC1198 6 4 2 1 0.000002 0 0 2 4 6 8 10 12 FREQUENCY (MHz) 14 16 SUPPLY CURRENT (mA) 6 4 LT1196 VCC = 5V LTC1198 0 2.5 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) CS = 0V SUPPLY CURRENT (mA) 8 7 VCC = 5V 6 5 4 3 2 VCC = 2.7V 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G04 LT1198 VCC = 5V 0.1 LT1198 VCC = 2.7V 0.01 5.5 6.0 TA = 25°C 0.001 100 1k 1.6 1.4 1M 10k 100k SAMPLE RATE (Hz) 1196/98 G03 Offset vs Reference Voltage MAGNITUDE OF OFFSET (LSB = 1 s VREF) 256 Supply Current vs Temperature 9 LT1196 VCC = 2.7V 1196/98 G02 1196/98 G01 10 1 SHUTDOWN MODE CS = VCC Offset vs Supply Voltage TA = 25°C VCC = 5V fCLK = 12MHz 1.2 1.0 0.8 0.6 0.4 0.2 0.5 0.4 MAGNITUDE OF OFFSET (LSB) 7 5 10 TA = 25°C 12 VCC = 5V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 Supply Current vs Sample Rate 0.3 TA = 25°C VREF = VCC fCLK = 3MHz 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G05 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 1196/98 G06 119698fb 7 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Linearity Error vs Reference Voltage 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 0.2 –0.3 0.1 –0.4 2.5 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 5.5 17 6.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 –0.2 –0.3 –0.5 6.0 18 7 14 12 70 60 50 40 30 20 10 5 25 45 65 85 105 125 TEMPERATURE (°C) 1196/98 G13 VIN +IN 10 –IN 8 RSOURCE– 6 4 2 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 3.0 5.5 0 6.0 1 1196/98 G11 ADC Noise vs Referenced and Supply Voltage 80 TA = 25°C VCC = VREF = 5V 16 9 0.30 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G09 Maximum Clock Frequency vs Source Resistance 11 0.35 0 1196/98 G08 13 1196/98 G10 VCC = 5V VREF = 5V 0 –55 –35 –15 –0.1 TA = 25°C VREF = VCC 5 2.5 PEAK-TO-PEAK ADC NOISE (LSB) MINIMUM CLOCK FREQUENCY (kHz) 90 3.0 15 Minimum Clock Rate for 0.1LSB* Error 100 0 CLOCK FREQUENCY (MHz) MAXIMUM CLOCK FREQUENCY (MHz) MAGNITUDE OF GAIN ERROR (LSB) 19 TA = 25°C 0.4 fCLK = 3MHz VREF = VCC 0.3 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0.1 Maximum Clock Frequency vs Supply Voltage 0.5 3.0 0.2 –0.4 Gain vs Supply Voltage 2.5 0.3 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 1196/98 G07 TA = 25°C VCC = 5V fCLK = 12MHz 0.4 MAGNITUDE OF GAIN ERROR (LSB) LINEARITY ERROR (LSB) 0.8 Supply Current vs Sample Rate 0.5 TA = 25°C 0.4 VREF = VCC f = 3MHz 0.3 CLK TA = 25°C VCC = 5V fCLK = 12MHz 0.9 LINEARITY ERROR (LSB) Linearity Error vs Supply Voltage 0.5 1k 10 10k 100 SOURCE RESISTANCE (Ω) 100k 1196/98 G12 Sample-and-Hold Acquisition Time vs Source Resistance 10000 TA = 25°C VCC = VREF = 5V TA = 25°C VREF = VCC S&H ACQUISITION TIME (ns) 1.0 0.25 0.20 0.15 0.10 RSOURCE+ VIN 1000 +IN –IN 0.05 0 2.5 100 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.5 6.0 1196/98 G14 1 100 10 1k SOURCE RESISTANCE (Ω) 10k 1196/98 G15 *AS THE FREQUENCY IS DECREASED FROM 12MHz, MINIMUM CLOCK FREQUENCY (ΔERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED. 119698fb 8 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage 1.9 DOUT Delay Time vs Supply Voltage TA = 25°C 1.5 1.3 1.1 0.9 100 80 60 40 0.5 2.5 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 3.0 5.5 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) Input Channel Leakage Current vs Temperature 40 ON CHANNEL 1 OFF CHANNEL 0.1 0 0 32 64 96 128 160 192 224 256 CODE 0.5 –0.5 0 96 128 160 192 224 256 CODE 1196/98 G22 64 96 128 160 192 224 256 CODE 1196/98 G21 Effective Bits and S/(N + D) vs Input Frequency 8 VCC = 2.7V VREF = 2.5V fCLK = 3MHz EFFECTIVE NUMBER OF BITS (ENOBs) DIFFERENTIAL NONLINEARITY ERROR (LSB) –0.5 32 0 50 VREF = VCC = 2.7V fSMPL = 383kHz (LTC1196) fSMPL = 287kHz (LTC1198) 7 6 VREF = VCC = 5V fSMPL = 1MHz (LTC1196) fSMPL = 750kHz (LTC1198) 5 4 3 2 1 TA = 25°C 0 –0.5 0 32 64 96 128 160 192 224 256 CODE 1196/98 G23 44 S/(N + D) (dB) 0 VCC = 5V VREF = 5V fCLK = 12MHz 0 Differential Nonlinearity vs Code at 2.7V VCC = 2.7V VREF = 2.5V fCLK = 3MHz 64 0.5 1196/98 G20 Integral Nonlinearity vs Code at 2.7V 32 1196/98 G18 Differential Nonlinearity vs Code at 5V VCC = 5V VREF = 5V fCLK = 12MHz 1196/98 G19 0 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 6.0 –0.5 0.01 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0.5 5.5 DIFFERENTIAL NONLINEARITY ERROR (LSB) 10 INTEGRAL NONLINEARITY ERROR (LSB) VCC = 5V VREF = 5V 100 LEAKAGE CURRENT (nA) 60 Integral Nonlinearity vs Code at 5V 0.5 1000 VCC = 5V 80 1196/98 G17 1196/98 G16 INTEGRAL NONLINEARITY ERROR (LSB) 100 20 0 2.5 6.0 VCC = 2.7V 120 20 0.7 VREF = VCC 140 DOUT DELAY TIME, tdDO (ns) DOUT DELAY TIME, tdDO (ns) LOGIC THRESHOLD (V) TA = 25°C VREF = VCC 120 1.7 DOUT Delay Time vs Temperature 160 140 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1196/98 G24 119698fb 9 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS 4096 Point FFT Plot at 5V –20 –40 –50 –60 –70 –20 –30 –40 –50 –60 –70 –30 –40 –50 –60 –70 –80 –90 –90 –90 300 200 FREQUENCY (kHz) 400 –100 500 0 50 150 100 FREQUENCY (kHz) –20 –30 –40 –50 –60 –60 –70 –70 10k 100k RIPPLE FREQUENCY (Hz) 1k 1M 10k 100k RIPPLE FREQUENCY (Hz) Intermodulation Distortion at 2.7V –40 –50 –60 –70 1M –20 –30 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 50 150 100 FREQUENCY (kHz) 200 250 1196/98 G31 fIN = 200kHz fIN = 500kHz 40 35 30 VCC = 5V 25 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 REFERENCE VOLTAGE (V) 1196/98 G30 S/(N + D) vs Input Level VCC = 5V f1 = 200kHz f2 = 210kHz fSMPL = 750kHz –10 MAGNITUDE (dB) –30 500 fIN = 100kHz Intermodulation Distortion at 5V 0 VCC = 2.7V f1 = 100kHz f2 = 110kHz fSMPL = 420kHz –20 45 1196/98 G29 1196/98 G28 –10 400 - –50 300 200 FREQUENCY (kHz) 50 SIGNAL TO NOISE PLUS DISTORTION (dB) –20 FEEDTHROUGH (dB) TA = 25°C = 10mV) V (V –10 f CC = RIPPLE CLK 5MHz –40 100 S/(N + D) vs Reference Voltage and Input Frequency 0 TA = 25°C = 20mV) V (V –10 f CC = RIPPLE CLK 12MHz –30 0 1196/98 G27 Power Supply Feedthrough vs Ripple Frequency 0 0 –100 1196/98 G26 Power Supply Feedthrough vs Ripple Frequency 1k 200 0 100 300 200 FREQUENCY (kHz) 400 1196/98 G32 50 SIGNAL TO NOISE-PLUS-DISTORTION (dB) 100 1196/98 G25 FEEDTHROUGH (dB) –20 –80 0 VCC = 5V fIN = 455kHz WITH 20kHz AM fSMPL = 1MHz –10 –80 –100 MAGNITUDE (dB) 0 VCC = 2.7V fIN = 29kHz fSMPL = 340kHz –10 MAGNITUDE (dB) –30 MAGNITUDE (dB) 0 VCC = 5V fIN = 29kHz fSMPL = 882kHz MAGNITUDE (dB) 0 –10 FFT Output of 455kHz AM Signal Digitized at 1Msps 4096 Point FFT Plot at 2.7V 40 VREF = VCC = 5V fIN = 500kHz fSMPL = 1MHz 30 20 10 0 –40 –35 –30 –25 –20 –15 –10 INPUT LEVEL (dB) –5 0 1196/98 G33 119698fb 10 LTC1196/LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Output Amplitude vs Input Frequency Spurious-Free Dynamic Range vs Frequency 70 SPURIOUS-FREE DYNAMIC RANGE (dB) PEAK-TO-PEAK OUTPUT (%) 100 80 VREF = VCC = 5V 60 VREF = VCC = 2.7V 40 20 0 50 100k 10k 1M INPUT FREQUENCY (Hz) VCC = 3V fCLK = 5MHz 40 30 20 10 0 1k VCC = 5V fCLK = 12MHz 60 TA = 25°C 1k 10M 10k 100k 1M 10M FREQUENCY (Hz) 1196/98 G35 1196/98 G34 PIN FUNCTIONS LTC1196 LTC1198 CS (Pin 1): Chip Select Input. A logic LOW on this input enables the LTC1196. A logic HIGH on this input disables the LTC1196. CS/SHUTDOWN (Pin 1): Chip Select Input. A logic LOW on this input enables the LTC1198. A logic HIGH on this input disables the LTC1198 and disconnects the power to THE LTC1198. IN+ (Pin 2): Analog Input. This input must be free of noise with respect to GND. IN– (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. CHO (Pin 2): Analog Input. This input must be free of noise with respect to GND. CH1 (Pin 3): Analog Input. This input must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. VCC (VREF) (Pin 8): Power Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. 119698fb 11 LTC1196/LTC1198 BLOCK DIAGRAM CS (CS/SHUTDOWN) CLK VCC (VCC/VREF) BIAS AND SHUTDOWN CIRCUIT IN+ (CH0) CSMPL SERIAL PORT DOUT – IN– (CH1) + SAR HIGH SPEED COMPARATOR CAPACITIVE DAC 1196/98 BD PIN NAMES IN PARENTHESES REFER TO THE LTC1198 GND VREF (DIN) TEST CIRCUITS On and Off Channel Leakage Current Load Circuit for tdDO, tr and tf 5V 1.4V ION A 3k ON CHANNEL DOUT IOFF TEST POINT 100pF A • • • • POLARITY OFF CHANNEL 1196/98 TC02 1196/98 TC01 Voltage Waveform for DOUT Rise and Fall Times, tr , tf Voltage Waveform for DOUT Delay Time, tdDO , thDO VOH DOUT CLK VOL tr VIH tdDO thDO tf 1196/98 TC04 VOH DOUT VOL 1196/98 TC03 119698fb 12 LTC1196/LTC1198 TEST CIRCUITS Load Circuit for tdis and ten Voltage Waveforms for tdis TEST POINT VIH CS VCC tdis WAVEFORM 2, ten 3k DOUT DOUT WAVEFORM 1 (SEE NOTE 1) tdis WAVEFORM 1 20pF 90% tdis 1196/98 TC05 DOUT WAVEFORM 2 (SEE NOTE 2) 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1196/98 TC06 Voltage Waveforms for ten LTC1196 CS CLK 2 1 3 4 B7 DOUT VOL 1196/98 TC07 ten Voltage Waveforms for ten LTC1198 CS DIN CLK START 1 2 3 5 4 6 7 B7 DOUT VOL ten 1196/98 TC08 119698fb 13 LTC1196/LTC1198 APPLICATIONS INFORMATION OVERVIEW can convert either channel with respect to ground or the difference between the two. It also automatically powers down when not performing conversion, drawing only leakage current. The LTC1196/LTC1198 are 600ns sampling 8-bit A/D converters packaged in tiny 8-pin SO packages and operating on 3V to 6V supplies. The ADCs draw only 10mW from a 3V supply or 50mW from a 5V supply. SERIAL INTERFACE Both the LTC1196 and the LTC1198 contain an 8-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see the Block Diagram). The on-chip sample-andholds have full-accuracy input bandwidths of 1MHz. Although they share the same basic design, the LTC1196 and LTC1198 differ in some respects. The LTC1196 has a differential input and has an external reference input pin. It can measure signals floating on a DC common mode voltage and can operate with reduced spans below 1V. The LTC1198 has a 2-channel input multiplexer and The LTC1196/LTC1198 will interface via three or four wires to ASICs, PLDs, microprocessors, DSPs, or shift registers (see Operating Sequence in Figures 1 and 2). To run at their fastest conversion rates (600ns), they must be clocked at 14.4MHz. HC logic families and any high speed ASIC or PLD will easily interface to the ADCs at that speed (see Data Transfer and Typical Application sections). Full speed operation from a 3V supply can still be achieved with 3V ASICs, PLDs or HC logic circuits. tCYC (12 CLKs) CS tsuCS tdDO DOUT B0 B7 NULL BITS Hi-Z B6 B5 B4 B3 B2 B1 B0* tCYC (8.5 CLKs) tSMPL NULL BITS Hi-Z tSMPL *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196/98 F01 Figure 1. LTC1196 Operating Sequence tCYC (16 CLKs) CS POWER DOWN tsuCS CLK ODD/ SIGN START DUMMY DIN DON’T CARE SGL/ DIFF DOUT DUMMY tdDO NULL BITS HI-Z tSMPL (2.5 CLKs) B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z tCONV (8.5 CLKs) *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196/98 F02 Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0) 119698fb 14 LTC1196/LTC1198 APPLICATIONS INFORMATION Connection to a microprocessor or a DSP serial port is quite simple (see the Data Transfer section). It requires no additional hardware, but the speed will be limited by the clock rate of the microprocessor or the DSP which limits the conversion time of the LTC1196/LTC1198. two null bits and the conversion result are output on the DOUT line. At the end of the data exchange CS should be brought HIGH. This resets the LTC1198 in preparation for the next data exchange. Data Transfer The LTC1196 requires no DIN word. It is permanently configured to have a single differential input. The conversion result is output on the DOUT line in an MSB-first sequence, followed by zeros indefinitely if clocks are continuously applied with CS LOW. Data transfer differs slightly between the LTC1196 and the LTC1198. The LTC1196 interfaces over three lines: CS, CLK and DOUT . A falling CS initiates data transfer as depicted by the LTC1196 Operating Sequence in Figure 1. After CS falls, the first CLK pulse enables DOUT . After two null bits, the A/D conversion result is output on the DOUT line. Bringing CS HIGH resets the LTC1196 for the next data exchange. Input Data Word The LTC1198 clocks data into the DIN input on the rising edge of the clock. The input data word is defined as follows: The LTC1198 can transfer data with three or four wires. The additional input, DIN, is used to select the 2-channel MUX configuration. The data transfer between the LTC1198 and the digital systems can be broken into two sections: Input Data Word and A/D Conversion Result. First, each bit of the input data word is captured on the rising CLK edge by the LTC1198. Second, each bit of the A/D conversion result on the DOUT line is updated on the rising CLK edge by the LTC1198. This bit should be captured on the next rising CLK edge by the digital systems (see the A/D Conversion Result section). Data transfer is initiated by a falling chip select (CS) signal as depicted by the LTC1198 Operating Sequence in Figure 2. After CS falls, the LTC1198 looks for a START bit. After the START bit is received, the 4-bit input word is shifted into the DIN input. The first two bits of the input word configure the LTC1198. The last two bits of the input word allow the ADC to acquire the input voltage by 2.5 clocks before the conversion starts. After the conversion starts, START SGL/ DIFF ODD/ SIGN MUX ADDRESS DUMMY DUMMY DUMMY BITS 119698 AI02 START Bit The first logical one clocked into the DIN input after CS goes LOW is the START bit. The START bit initiates the data transfer. The LTC1198 will ignore all leading zeros which precede this logical one. After the START bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. Multiplexer (MUX) Address The two bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. CS LTC1198 Channel Selection DIN1 DIN2 DOUT1 DOUT2 SINGLE-ENDED MUX MODE SHIFT MUX ADDRESS IN DIFFERENTIAL MUX MODE 2 NULL BITS SHIFT A/D CONVERSION RESULT OUT MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + – + + – GND – – 1196/98 AI03 1196/98 AI01 119698fb 15 LTC1196/LTC1198 APPLICATIONS INFORMATION Dummy Bits Unipolar Transfer Curve The last two bits of the input word following the MUX address are dummy bits. Either bit can be a logical one or a logical zero. These two bits allow the ADC 2.5 clocks to acquire the input signal after the channel selection. The LTC1196/LTC1198 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures. A/D Conversion Result Both the LTC1196 and the LTC1198 have the A/D conversion result appear on the DOUT line after two null bits (see the operating sequences in Figures 1 and 2). Data on the DOUT line is updated on the rising edge of the CLK line. The DOUT data should also be captured on the rising CLK edge by the digital systems. Data on the DOUT line remains valid for a minimum time of thDO (30ns at 5V) to allow the capture to occur (see Figure 3). INPUT VOLTAGE INPUT VOLTAGE (VREF = 5.000V) 11111111 11111110 • • • 00000001 00000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.9805V 4.9609V • • • 0.0195V 0V Unipolar Transfer Curve 11111111 11111110 • • • 00000001 00000000 VIH CLK OUTPUT CODE 1196/98 AI05 Unipolar Output Code VIN 0V tdDO 1LSB thDO Operation with DIN and DOUT Tied Together VOH DOUT VREF – VREF – VREF 2LSB 1LSB 1196/98 AI04 VOL 1196/98 TC03 Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO The LTC1198 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the digital systems. Data is transmitted in both directions on a single wire. The pin of the digital systems connected to this data line should be configurable as either an input or an output. The LTC1198 will take control of the data line and drive it LOW on the fifth falling CLK edge after the START bit is received (see Figure 4). Therefore, the port line of the digital systems must be switched to an input before this happens to avoid a conflict. DUMMY BITS LATCHED BY LTC1198 CS 1 2 3 4 ODD/SIGN DUMMY 5 CLK DATA (DIN/DOUT) START SGL/DIFF THE DIGITAL SYSTEM CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1198 THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER 5TH RISING CLK AND BEFORE THE 5TH FALLING CLK LTC1198 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO THE DIGITAL SYSTEM LTC1198 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK 1196/98 F04 Figure 4. LTC1198 Operation with DIN and DOUT Tied Together 119698fb 16 LTC1196/LTC1198 APPLICATIONS INFORMATION REDUCING POWER CONSUMPTION The LTC1196/LTC1198 can sample at up to a 1MHz rate, drawing only 50mW from a 5V supply. Power consumption can be reduced in two ways. Using a 3V supply lowers the power consumption on both devices by a factor of five, to 10mW. The LTC1198 can reduce power even further because it shuts down whenever it is not converting. Figure 5 shows the supply current versus sample rate for the LTC1196 and LTC1198 on 3V and 5V. To achieve such a low power consumption, especially for the LTC1198, several things must be taken into consideration. DIN and CLK with CS = HIGH; they can continue to run without drawing current. Minimize CS LOW Time (LTC1198) In systems that have significant time between conversions, lowest power drain will occur with the minimum CS LOW time. Bringing CS LOW, transferring data as quickly as possible, then bringing it back HIGH will result in the lowest current drain. This minimizes the amount of time the device draws power. OPERATING ON OTHER THAN 5V SUPPLIES SUPPLY CURRENT (mA) 10 1 0.1 LT1196 VCC = 2.87V LT1198 VCC = 5V Input Logic Levels LT1198 VCC = 2.87V 0.01 0.001 100 The LTC1196/LTC1198 operate from single 2.7V to 6V supplies. To operate the LTC1196/LTC1198 on other than 5V supplies, a few things must be kept in mind. LT1198 VCC = 5V 1k 10k 100k SAMPLE RATE (Hz) 1M 1196/98 F05 Figure 5. Supply Current vs Sample Rate for LTC1196/LTC1198 Operating on 5V and 2.7V Supplies Shutdown (LTC1198) Figure 2 shows the operating sequence of the LTC1198. The converter draws power when the CS pin is LOW and powers itself down when that pin is HIGH. For lowest power consumption in shutdown, the CS pin should be driven with CMOS levels (0V to VCC) so that the CS input buffer of the converter will not draw current. When the CS pin is HIGH (= supply voltage), the LTC1198 is in shutdown mode and draws only leakage current. The status of the DIN and CLK input has no effect on the supply current during this time. There is no need to stop The input logic levels of CS, CLK and DIN are made to meet TTL on 5V supply. When the supply voltage varies, the input logic levels also change (see the Digital Input Logic Threshold vs Supply Voltage curve in the Typical Performance Characteristics section). For these two ADCs to sample and convert correctly, the digital inputs have to be in the logical LOW and HIGH relative to the operating supply voltage. If achieving micropower consumption is desirable on the LTC1198, the digital inputs must go rail-to-rail between supply voltage and ground (see the Reducing Power Consumption section). Clock Frequency The maximum recommended clock frequency is 14.4MHz at 25°C for the LTC1196/LTC1198 running off a 5V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the Maximum Clock Rate vs Supply Voltage curve in the Typical Performance Characteristics section). If the supply is reduced, the clock rate must also be reduced. At 3V, the devices are specified with a 5.4MHz clock at 25°C. 119698fb 17 LTC1196/LTC1198 APPLICATIONS INFORMATION Mixed Supplies BOARD LAYOUT CONSIDERATIONS It is possible to have a digital system running off a 5V supply and communicate with the LTC1196/LTC1198 operating on a 3V supply. Achieving this reduces the outputs of DOUT from the ADCs to toggle the equivalent input of the digital system. The CS, CLK and DIN inputs of the ADCs will take 5V signals from the digital system without causing any problem (see the Digital Input Logic Threshold vs Supply Voltage curve in the Typical Performance Characteristics section). With the LTC1196 operating on a 3V supply, the output of DOUT only goes between 0V and 3V. This signal easily meets TTL levels (see Figure 6). 3V 4.7μF MPU (e.g., 8051) DIFFERENTIAL INPUTS COMMON MODE RANGE 0V TO 3V CS VCC P1.4 +IN CLK P1.3 LTC1196 –IN DOUT GND VREF Grounding and Bypassing The LTC1196/LTC1198 are easy to use if some care is taken. They should be used with an analog ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 1μF tantalum with leads as short as possible. If the power supply is clean, the LTC1196/LTC1198 can also operate with smaller 0.1μF surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single-point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. 5V SAMPLE-AND-HOLD P1.2 3V 1196/98 F06 Figure 6. Interfacing a 3V Powered LTC1196 to a 5V System Both the LTC1196 and the LTC1198 provide a built-in sample-and-hold (S&H) function to acquire the input signal. The S&H acquires the input signal from “+” input during tSMPL as shown in Figures 1 and 2. The S&H of the LTC1198 can sample input signals in either single-ended or differential mode (see Figure 7). SAM PLE H O LD + INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV CLK DIN START SGL/DIFF ODD/SIGN DUMMY DUMMY DON’T CARE B7 DOUT 1ST BIT TEST: – INPUT MUST SETTLE DURING THIS TIME + INPUT – INPUT 1196/98 F07 Figure 7. LTC1198 “+” and “–” Input Settling Windows 119698fb 18 LTC1196/LTC1198 APPLICATIONS INFORMATION Single-Ended Inputs “+” Input Settling The sample-and-hold of the LTC1198 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins as the bit preceding the first dummy bit is shifted in and continues until the falling CLK edge after the second dummy bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. The input capacitor of the LTC1196 is switched onto “+” input at the end of the conversion and samples the input signal until the conversion begins (see Figure 1). The input capacitor of the LTC1198 is switched onto “+” input during the sample phase (tSMPL, see Figure 7). The sample phase is 2.5 CLK cycles before conversion starts. The voltage on the “+” input must settle completely within tSMPL for the LTC1196/LTC1198. Minimizing RSOURCE+ will improve the input settling time. If a large “+” input source resistance must be used, the sample time can be increased by allowing more time between conversions for the LTC1196 or by using a slower CLK frequency for the LTC1198. Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 8.5 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input, this error would be: VERROR(MAX) = VPEAK • 2 • π • f(–) • 8.5/fCLK where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. VERROR is proportional to f(–) and inversely proportional to fCLK. For a 60Hz signal on the “–” input to generate a 1/4LSB error (5mV) with the converter running at CLK = 12MHz, its peak value would have to be 18.7V. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1196/LTC1198 have one capacitive switching input current spike per conversion. These current spikes settle quickly and do not cause a problem. However, if source resistances larger than 100Ω are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. “–” Input Settling At the end of the tSMPL, the input capacitor switches to the “–” input and conversion starts (see Figures 1 and 7). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settle completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– will improve settling time. If a large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figures 1 and 7). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. To achieve the full sampling rate, the analog input should be driven with a low impedance source ( 7) LTC1198-1 PDISS PDISS (Shutdown) 15μW 9μW Max fSMPL 750kHz 287kHz Min tCONV 600ns 1.6μs INL (Max) Typical ENOBs 0.5LSB 0.5LSB 7.9 at 300kHz 7.9 at 100kHz 1MHz 500kHz Linear Input Bandwidth (ENOBs > 7) TYPICAL APPLICATIONS PLD Interface Using the Altera EPM5064 The Altera EPM5064 has been chosen to demonstrate the interface between the LTC1196 and a PLD. The EPM5064 is programmed to be a 12-bit counter and an equivalent 74HC595 8-bit shift register, as shown in Figure 12. The circuit works as follows: bringing ENA HIGH makes the CS output HIGH and the EN input LOW to reset the LTC1196 and disable the shift register. Bringing ENA LOW, the CS output goes HIGH for one CLK cycle with every 12 CLK cycles. The inverted signal, EN, of the CS output makes the 8-bit data available on the B0-B7 lines. Figures 13 and 14 show the interconnection between the LTC1196 and EPM5064 and the timing diagram of the signals between these two devices. The CLK frequency in this circuit can run up to fCLK(MAX) of the LTC1196. VCC CLK 1μF 3, 14, 25, 36 8-BIT SHIFT REGISTER 33 DATA DATA 1 CLK CLK B0-B7 B0-B7 EN CLK 12-BIT CONVERTER ENA ENA + – 2 3 4 CS VCC +IN CLK –IN GND LTC1196 DOUT VREF 8 23 7 34 6 35 ENA EPM5064 CLK DATA 5 B0 CS CS 1196/98 F12 Figure 12. An Equivalent Circuit of the EPM5064 B7 RESERVE PINS OF EPM5064: 2, 4-8,15-20, 22, 24, 26-30 9-13, 21, 31, 32, 43 1 37 38 39 40 41 42 44 1196/98 F13 Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD 119698fb 23 LTC1196/LTC1198 TYPICAL APPLICATIONS DATA CLK CS B7 B6 B5 B4 B3 B2 B1 B0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 TIME (ns) 1196/98 F14 Figure 14. The Timing Diagram Interfacing the LTC1198 to the TMS320C25 DSP Figure 15 illustrates the interface between the LTC1198 8-bit data acquisition system and the TMS320C25 digital signal processor (DSP). The interface, which is optimized for speed of transfer and minimum processor supervision, can complete a conversion and shift the data in 4μs with fCLK = 5MHz. The cycle time, 4μs, of each conversion is limited by maximum clock frequency of the serial port of the TMS320C25 which is 5MHz. The supply voltage for 5MHz CLK CLKX CLK CH0 CH1 CLKR FSR TMS320C25 FSX LTC1198 CS DX DIN DR DOUT 1196/98 F15 Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP the LTC1198 in Figure 15 can be 2.7V to 6V with fCLK = 5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See the Recommended Operating Conditions table in the Electrical Characteristics section for limits over temperature. Hardware Description The circuit works as follows: the LTC1198 clock line controls the A/D conversion rate and the data shift rate. Data is transferred in a synchronous format over DIN and DOUT . The serial port of the TMS320C25 is compatible with that of the LTC1198. The data shift clock lines (CLKR, CLKX) are inputs only. The data shift clock comes from an external source. Inverting the shift clock is necessary because the LTC1198 and the TMS320C25 clock the input data on opposite edges. The schematic of Figure 15 is fed by an external clock source. The signal is fed into the CLK pin of the LTC1198 directly. The signal is inverted with a 74HC04 and then applied to the data shift clock lines (CLKR, CLKX). The framing pulse of the TMS320C25 is fed directly to the CS of the LTC1198. DX and DR are tied directly to DIN and DOUT, respectively. 119698fb 24 LTC1196/LTC1198 TYPICAL APPLICATIONS The timing diagram of Figure 16 was obtained from the circuit of Figure 15. The CLK was 5MHz for the timing diagram and the TMS320C25 clock rate was 40MHz. Figure 17 shows the timing diagram with the LTC1198 running off a 2.7V supply and 5MHz CLK. VERTICAL: 5V/DIV CS CLK DIN DOUT 1196/98 F16 NULL BITS MSB (B7) LSB (B0) HORIZONTAL: 1500ns/DIV Figure 16. Scope Trace the LTC1198 Running Off 5V Supply in the Circuit of Figure 15 VERTICAL: 5V/DIV CS Software Description The software configures and controls the serial port of the TMS320C25. The code first sets up the interrupt and reset vectors. On reset the TMS320C25 starts executing code at the label INIT. Upon completion of a 16-bit data transfer, an interrupt is generated and the DSP will begin executing code at the label RINT. In the beginning, the code initializes registers in the TMS320C25 that will be used in the transfer routine. The interrupts are temporarily disabled. The data memory page pointer register is set to zero. The auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal. This is the data memory location where the data from the LTC1198 will be stored. The interrupt mask register (IMR) is configured to recognize the RINT interrupt, which is generated after receiving the last of 16 bits on the serial port. This interrupt is still disabled at this time. The transmit framing synchronization pin (FSX) is configured to be an output. The F0 bit of the status register ST1, is initialized to zero which sets up the serial port to operate in the 16-bit mode. Next, the code in TXRX routine starts to transmit and receive data. The DIN word is loaded into the ACC and shifted left eight times so that it appears as in Figure 18. This DIN word configures the LTC1198 for CH0 with respect to CH1. The DIN word is then put in the transmit register and the RINT interrupt is enabled. The NOP is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles. All clocking and CS functions are performed by the hardware. CLK DIN DOUT NULL BITS MSB (B7) LSB (B0) 1196/98 F17 HORIZONTAL: 500ns/DIV Figure 17. Scope Trace the LTC1198 Running Off 1.7V Supply in the Circuit of Figure 15 B15 0 1 START 0 S/D 0 O/S 0 1 DUMMY DUMMY 0 B8 0 L1196/98 F18 Figure 18. DIN Word in ACC of TMS20C25 for the Circuit in Figure 15 119698fb 25 LTC1196/LTC1198 TYPICAL APPLICATIONS Once RINT is generated the code begins execution at the label RINT. This code stores the DOUT word from the LTC1198 in the ACC and then stores it in location 200 hex. The data appears in location 200 hex right-justified as shown in Figure 19. The code is set up to continually loop, so at this point the code jumps to label TXRX and repeats from here. LABEL INIT TXRX RINT MNEMONIC LSB MSB X X X X X X X X 7 6 5 4 DOUT FROM LTC1198 STORED IN TMS320C25 RAM 3 2 1 0 > 200 L1196/98 F19 Figure 19. Memory Map for the Circuit in Figure 15 COMMENTS AORG B 0 INIT ON RESET CODE EXECUTION STARTS AT 0 BRANCH TO INITIALIZATION ROUTINE AORG B >26 RINT ADDRESS TO RINT INTERRUPT VECTOR BRANCH TO RINT SERVICE ROUTINE AORG DINT LDPK LARP LRLK LACK SACL STXM FORT >32 MAIN PROGRAM STARTS HERE DISABLE INTERRUPTS SET DATA MEMORY PAGE POINTER TO 0 SET AUXILIARY REGISTER POINTER TO 1 SET AUXILIARY REGISTER 1 TO >200 LOAD IMR CONFIG WORD INTO ACC STORE IMR CONFIG WORD INTO IMR CONFIGURE FSX AS AN OUTPUT SET SERIAL PORT TO 16-BIT MODE LACK SFSM RPTK SFL SACL EINT >44 RPTK NOP 2 MINIMIZE THE CONVERSION CYCLE TIME TO BE 20 CLOCK CYCLES ZALS SACL B END >0 *, 0 TXRX STORE LTC1198 DOUT WORD IN ACC STORE ACC IN LOCATION >200 BRANCH TO TRANSMIT RECEIVE ROUTINE >0 >1 AR1, >200 >10 >4 0 7 >1 LOAD LTC1198 DIN WORD INTO ACC FSX PULSES GENERATED ON XSR LOAD REPEAT NEXT INSTRUCTION 8 TIMES SHIFTS DIN WORD TO RIGHT POSITION PUT DIN WORD IN TRANSMIT REGISTER ENABLE INTERRUPT (DISABLE ON RINT) Figure 20. TMS320C25 Code for the Circuit in Figure 15 119698fb 26 LTC1196/LTC1198 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN 7 6 5 .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 2 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC SO8 0303 119698fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC1196/LTC1198 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADCs 3V, 15mW, Unipolar Inputs, MSOP Package LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADCs 3V, 15mW, Bipolar Inputs, MSOP Package ADCs LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD LCT1414 14-Bit, 2.2Msps Parallel ADC ±5V Supply, ±2.5V Span, 78dB SINAD LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD LTC1604 16-Bit, 333ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD LTC1609 16-Bit, 250ksps Serial ADC 5V, Configurable Bipolar/Unipolar Inputs LTC1864/LTC1865 16-Bit, 250ksps Serial ADCs 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package LTC2355-12/ LTC2355-14 12-Bit, 3.5Msps Serial ADCs 3.3V Supply, 0V to 2.5V Span, MSOP Package LTC2356-12/LTC2356-14 12-/14-Bit, 3.5Msps Serial ADCs 3.3V Supply, ±1.25V Span, MSOP Package DACs LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift References SoftSpan is a trademark of Linear Technology Corporation. 119698fb 28 Linear Technology Corporation LT 0609 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1993