LTC1279
12-Bit, 600ksps Sampling
A/D Converter with Shutdown
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DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
■
Single Supply 5V or ±5V Operation
Sample Rate: 600ksps
70dB S/(N + D) and 74dB THD at Nyquist
Power Dissipation: 60mW Typ
Power Shutdown with Instant Wake-Up
Internal Reference Can Be Overdriven Externally
Internal Synchronized Clock; No Clock Required
High Impedance Analog Input
Input Range: 0V to 5V or ±2.5V
New Flexible, Friendly Parallel Interface Eases
Connections to DSPs and FIFOs
24-Pin SO Wide Package
The LTC®1279 is a 1.4µs, 600ksps, sampling 12-bit A/D
converter which draws only 60mW from a single 5V or
±5V supplies. This easy-to-use device comes complete
with a 160ns sample-and-hold, a precision reference and
an internally trimmed clock. Unipolar and bipolar conversion modes add to the flexibility of the ADC. The low
power dissipation is reduced even more, drawing only
8.5mW in power shutdown mode. Instant wake-up from
power shutdown allows the converter to be powered
down even during brief inactive periods.
The LTC1279 converts 0V to 5V unipolar inputs from a
single 5V supply and ±2.5V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1LSB INL and
±1LSB DNL. Outstanding guaranteed AC performance
includes 70dB S/(N + D) and 78dB THD at the input
frequency of 100kHz over temperature.
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APPLICATI
■
■
■
■
■
S
High Speed Data Acquisition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
The internal clock is trimmed for 1.4µs conversion time.
The clock automatically synchronizes to each sample
command, eliminating problems with asynchronous clock
noise found in competitive devices. A separate conversion
start input and a data-ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATI
Single 5V Supply, 600kHz, 12-Bit Sampling A/D Converter
+
23
22
21
20
19
18
17
10µF
0.1µF
µP CONTROL
LINES
CONVERSION-START INPUT
POWER SHUTDOWN INPUT
16
15
EFFECTIVE NUMBER OF BITS
+
10µF
5V
24
12
74
11
68
10
9
56
50
8
7
6
5
4
3
14
2
13
1
0
10k
LTC1279 • TA01
62
NYQUIST
FREQUENCY
SIGNAL/(NOISE + DISTORTION) (dB)
2.42V
REFERENCE
OUTPUT
LTC1279
ANALOG INPUT 1 A
AVDD
(0V TO 5V) 2 IN
VREF
VSS
3
AGND
BUSY
0.1µF
4
D11(MSB)
CS
5
D10
RD
6
D9
CONVST
7
D8
SHDN
8
D7
DVDD
9
12-BIT
D6
D0
PARALLEL
10
D5
D1
BUS
11
D4
D2
12
DGND
D3
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
fSAMPLE = 600kHz
100k
1M
FREQUENCY (Hz)
5M
1279 G03
1
LTC1279
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PACKAGE/ORDER I FOR ATIO
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AVDD = DVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................ 7V
Negative Supply Voltage (VSS)
Bipolar Operation Only ......................... – 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation............... VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)
Unipolar Operation ............................... – 0.3V to 12V
Bipolar Operation.......................... VSS – 0.3V to 12V
Digital Output Voltage
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation..................... – 0.3V to VDD + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1279C............................................... 0°C to 70°C
LTC1279I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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CO VERTER CHARACTERISTICS
PARAMETER
TOP VIEW
AIN
1
24 AVDD
VREF
2
23 VSS
AGND
3
22 BUSY
D11(MSB)
4
21 CS
D10
5
20 RD
D9
6
19 CONVST
D8
7
18 SHDN
D7
8
17 DVDD
D6
9
16 D0
D5 10
15 D1
D4 11
14 D2
DGND 12
13 D3
LTC1279CSW
LTC1279ISW
TJMAX = 110°C, θJA = 130°C/W
*Consult factory for plastic DIP package.
Consult factory for Military grade parts.
With Internal Reference (Notes 5, 6)
Resolution (No Missing Codes)
MIN
●
(Note 7)
Differential Linearity Error
Bipolar Offset Error
ORDER
PART NUMBER*
SW PACKAGE
24-LEAD PLASTIC SO WIDE
CONDITIONS
Integral Linearity Error
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AXI U
TYP
12
Bits
LSB
●
±1
LSB
●
±4
±6
LSB
LSB
●
±6
±8
LSB
LSB
Gain Error
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A ALOG I PUT
±10
●
±15
LSB
±45
ppm/°C
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.95V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar)
●
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
2
UNITS
±1
Unipolar Offset Error
IOUT(REF) = 0
MAX
●
(Note 8)
Gain Error Tempco
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ABSOLUTE
MIN
TYP
MAX
0 to 5
±2.5
V
V
±1
25
5
UNITS
µA
pF
pF
LTC1279
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DY A IC ACCURACY
(Notes 5, 10)
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
100kHz Input Signal
300kHz Input Signal
●
THD
Total Harmonic Distortion
First 5 Harmonics
100kHz Input Signal
300kHz Input Signal
●
– 82
– 74
– 78
dB
dB
Peak Harmonic or Spurious Noise
100kHz Input Signal
300kHz Input Signal
●
– 82
– 80
– 78
dB
dB
Intermodulation Distortion
fIN1 = 94.189kHz, fIN2 = 97.705kHz
2nd Order Terms
3rd Order Terms
– 81
– 78
dB
dB
fIN1 = 299.26kHz, fIN2 = 305.12kHz
2nd Order Terms
3rd Order Terms
– 77
– 74
dB
dB
IMD
MIN
TYP
70
72
70
Full Power Bandwidth
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
MAX
UNITS
dB
dB
5
MHz
500
kHz
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I TER AL REFERE CE CHARACTERISTICS (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.400
2.420
2.440
V
VREF Output Tempco
IOUT = 0
±10
±45
ppm/°C
VREF Line Regulation
4.95V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.95V
0.01
0.01
VREF Load Regulation
– 5mA ≤ IOUT ≤ 800µA
2
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.95V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
●
LSB/V
LSB/V
LSB/mA
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DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5)
VOL
Low Level Output Voltage
MIN
VDD = 4.95V
IO = – 10µA
IO = – 200µA
●
VDD = 4.95V
IO = 160µA
IO = 1.6mA
●
TYP
MAX
2.4
UNITS
V
0.8
V
±10
µA
5
pF
4.9
V
V
4.0
0.05
0.10
0.4
V
V
±10
µA
IOZ
High-Z Output Leakage D11 to D0
VOUT = 0V to VDD, CS High
●
COZ
High-Z Output Capacitance D11 to D0
CS High (Note 9 )
●
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
15
pF
3
LTC1279
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POWER REQUIRE E TS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
VDD
Positive Supply Voltage (Notes 11, 12)
Unipolar
Bipolar
4.95
4.75
5.25
5.25
V
V
VSS
Negative Supply Voltage (Note 11, 12)
Bipolar Only
– 2.45
– 5.25
V
IDD
Positive Supply Current
fSAMPLE = 600ksps
SHDN = 0V
●
●
12
1.7
24
3
mA
mA
ISS
Negative Supply Current
fSAMPLE = 600ksps, VSS = – 5V
●
0.12
0.30
mA
PD
Power Dissipation
fSAMPLE = 600ksps
SHDN = 0V
●
60
8.5
120
15
mW
mW
TYP
MAX
●
TYP
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TI I G CHARACTERISTICS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
tSAMPLE(MIN)
Minimum Throughput Time
(Acquisition Time Plus Conversion Time)
●
tCONV
Conversion Time
●
tACQ
Acquisition Time
t1
CS↓ to RD↓ Setup Time
(Notes 9, 11)
●
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Notes 9, 11)
●
20
ns
t3
SHDN↑ to CONVST↓ Wake-Up Time
(Note 11)
t4
CONVST Low Time
(Notes 11, 13)
●
t5
CONVST↓ to BUSY↓ Delay
CL = 100pF
Commercial
Industrial
●
●
CL = 20pF
●
20
●
– 20
MIN
600
µs
1.6
µs
ns
350
ns
40
ns
50
t7
Wait Time RD↓ After BUSY↑
Mode 2, (See Figure 14) (Note 9)
t8
Data Access Time After RD↓
CL = 20pF (Note 9)
Commercial
Industrial
●
●
CL = 100pF
Commercial
Industrial
●
●
(3k and 10pF Connected as Shown in
Test Circuits)
Commercial
Industrial
●
●
10
10
10
Bus Relinquish Time
1.66
160
Data Ready Before BUSY↑
t9
kHz
1.4
t6
UNITS
110
130
140
40
ns
ns
ns
ns
ns
35
90
110
120
ns
ns
ns
50
125
150
170
ns
ns
ns
30
75
85
90
ns
ns
ns
t10
RD Low Time
(Note 9)
●
t8
ns
t11
CONVST High Time
(Notes 9, 13)
●
40
ns
t12
Aperture Delay of Sample-and-Hold
Jitter < 50ps
4
12
ns
LTC1279
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TI I G CHARACTERISTICS
(Note 5)
The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When the analog input voltage is taken below VSS (ground for
unipolar mode) or above VDD, it will be clamped by internal diodes. This
product can handle input currents greater than 80mA below VSS (ground
for unipolar mode) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.
Note 5: AVDD = DVDD = VDD = 5V, (VSS = – 5V for bipolar mode), fSAMPLE =
600kHz, tr = tf = 5ns unless otherwise specified.
Note 6: Linearity, offset and full scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 1/2LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: The AC test is for bipolar mode. The signal-to-noise plus
distortion ratio is about 1dB lower for unipolar mode, so the typical
S/(N + D) at 100kHz in unipolar mode is 71dB.
Note 11: Recommended operating conditions.
Note 12: AIN must not exceed VDD or fall below VSS by more than 50mV for
specified accuracy. Therefore the minimum supply voltage for the unipolar
mode is 4.95V. The minimum for the bipolar mode is 4.75V, – 2.45V.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small errors.
For best performance ensure that CONVST returns high either within 120ns
after conversion start (i.e., before the first bit decision) or after BUSY rises
(i.e., after the last bit test). See mode 1a and 1b (Figures 12 and 13) timing
diagrams.
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
0.5
0
–0.5
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
1279 G01
1.0
fSAMPLE = 600kHz
EFFECTIVE NUMBER OF BITS
DIFFERENTIAL NONLINEARITY ERROR (LSB)
fSAMPLE = 600kHz
0.5
0
–0.5
12
74
11
68
10
9
62
NYQUIST
FREQUENCY
56
50
8
7
6
5
4
3
2
1
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
1279 G02
0
10k
SIGNAL/(NOISE + DISTORTION) (dB)
INTEGRAL NONLINEARITY ERROR (LSB)
1.0
–1.0
ENOBs and S/(N + D) vs
Input Frequency
Differential Nonlinearity vs
Output Code
fSAMPLE = 600kHz
100k
1M
FREQUENCY (Hz)
5M
1279 G03
5
LTC1279
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
60
70
VIN = –20dB
50
40
30
20
VIN = –60dB
10
60
50
40
30
20
10
fSAMPLE = 600kHz
0
10k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
VIN = 0dB
70
100k
1M
INPUT FREQUENCY (Hz)
fSAMPLE = 600kHz
0
10k
10M
100k
1M
INPUT FREQUENCY (Hz)
0
fSAMPLE = 600kHz
–30
–40
–50
–60
–70
–70
100k
INPUT FREQUENCY (Hz)
1M
–40
–50
–60
(2fa – fb)
–80 (fb – fa)
–70
(3fb)
(fa + 2fb)
(2fb – fa) (fa + fb)(2fa + fb)
(2fa)
–90
–80
(2fb)
(3fa)
TA = 25°C
1500
1000
500
–100
–90
2M
2000
ACQUISITION TIME (ns)
–60
3RD HARMONIC
Acquisition Time vs
Source Impedance
–30
–50
THD
–90
1279 G06
fSAMPLE = 600kHz
fa = 94.189kHz
fb = 97.705kHz
–20
–20
–40
2ND HARMONIC
–80
2500
(fa) (fb)
–10
AMPLITUDE (dB)
–110
–100
10k
100k
INPUT FREQUENCY (Hz)
1M
–120
2M
0
50
100
150
200
FREQUENCY (kHz)
250
1279 G07
10
15
Reference Voltage vs
Load Current
2.435
AMPLITUDE OF
POWER SUPPLY FEEDTHROUGH (dB)
0
9
6
3
100
125
1279 G10
10k
1279 G09
Power Supply Feedthrough vs
Ripple Frequency
12
100
1k
SOURCE RESISTANCE (Ω)
1279 G08
Supply Current vs Temperature
fSAMPLE = 600kHz
0
50
0
75
25
–55 –25
TEMPERATURE (°C)
0
300
fSAMPLE = 600kHz
2.430
–20
–40
VSS(VRIPPLE = 10mV)
–60
DGND(VRIPPLE = 100mV)
–80
–100
–120
AVDD(VRIPPLE = 1mV)
1k
10k
100k
RIPPLE FREQUENCY (Hz)
REFERENCE VOLTAGE (V)
SPURIOUS-FREE DYNAMIC RANGE (dB)
0
SUPPLY CURRENT, IDD (mA)
–20
Intermodulation Distortion Plot
–30
fSAMPLE = 600kHz
–10
1279 G05
Peak Harmonic or Spurious
Noise vs Input Frequency
–10
0
–100
10k
10M
1279 G04
6
Distortion vs Input Frequency
80
SIGNAL-TO-NOISE RATIO (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
80
2.425
2.420
2.415
2.410
2.405
2.400
2.395
1M
1279 G11
2.390
–8 –7 –6 –5 –4 –3 –2 –1
LOAD CURRENT (mA)
0
1
2
1279 G12
LTC1279
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PI FU CTIO S
AIN (Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V
(Bipolar).
conversion. The LTC1279 responds to CONVST signal
only if the signal applied to CS is a logic low.
VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
RD (Pin 20): READ Input. A logic low signal applied to
this pin enables the output data drivers when the signal
applied to the CS pin is a logic low.
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DVDD (Pin 17 ): Digital Power Supply, 5V. Tie to AVDD pin.
CS (Pin 21): The CHIP SELECT input must be a logic low
for the ADC to recognize the signals applied to the
CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is a logic low during a conversion.
SHDN (Pin 18): Power Shutdown. The LTC1279 powers down when SHDN is low.
VSS (Pin 23): Negative Supply. – 5V will select bipolar
operation. Bypass to AGND with 0.1µF ceramic. Tie to
analog ground to select unipolar operation.
CONVST (Pin 19): Conversion Start Input. It is active
low. The falling edge of the CONVST signal initiates a
AVDD (Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
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FU CTIO AL BLOCK DIAGRA
CSAMPLE
AVDD
AIN
ZEROING
SWITCH
DVDD
2.42V REF
VSS
(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)
VREF
COMPARATOR
12-BIT CAPACITIVE DAC
12
12
AGND
SUCCESSIVE APPROXIMATION
REGISTER
DGND
•
•
•
OUTPUT LATCHES
D11
D0
1279 BD
INTERNAL
CLOCK
CONTROL LOGIC
SHDN CONVST
RD
CS
BUSY
7
LTC1279
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
3k
3k
DBN
3k
DBN
DBN
DBN
CL
DGND
10pF
DGND
DGND
DGND
B) VOL TO HIGH-Z
A) VOH TO HIGH-Z
B) HIGH-Z TO VOL (t8)
AND VOH TO VOL (t6)
A) HIGH-Z TO VOH (t8)
AND VOL TO VOH (t6)
10pF
3k
CL
1279 TC02
1279 TC01
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TI I G DIAGRA S
CS to CONVST Setup Timing
CS to RD Setup Timing
CS
SHDN to CONVST Wake-Up Timing
CS
SHDN
t1
t2
RD
t3
CONVST
CONVST
1279 TD02
1279 TD01
1279 TD03
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APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1279 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
SAMPLE
SAMPLE
SI
CSAMPLE
–
AIN
COMPARATOR
HOLD
+
CDAC
DAC
VDAC
S
A
R
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
Figure 1. AIN Input
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 160ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the summing junction. This input charge is successively com-
8
12-BIT
LATCH
1279 F01
LTC1279
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APPLICATIONS INFORMATION
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1279 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an
FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figures 2a
and 2b show typical LTC1279 FFT plots.
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 600kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 300kHz as shown in Figure 2b.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
0
fSAMPLE = 600kHz
fIN = 97.705kHz
–10
–20
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 600kHz the LTC1279 maintains very good ENOBs up
to the Nyquist input frequency of 300kHz. Refer to Figure 3.
–30
AMPLITUDE (dB)
Signal-to-Noise Ratio
–40
–50
–60
–70
11
–100
10
–110
–120
0
50
100
150
200
FREQUENCY (kHz)
250
300
1279 F02a
Figure 2a. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 100kHz Input Frequency
EFFECTIVE NUMBER OF BITS
12
–90
9
74
68
62
NYQUIST
FREQUENCY
56
50
8
7
6
5
4
3
2
0
1
fSAMPLE = 600kHz
fIN = 292.822kHz
–10
–20
0
10k
AMPLITUDE (dB)
–30
SIGNAL/(NOISE + DISTORTION) (dB)
–80
fSAMPLE = 600kHz
100k
1M
FREQUENCY (Hz)
5M
1279 G03
–40
–50
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs
Input Frequency
–60
–70
–80
–90
Total Harmonic Distortion
–100
–110
–120
0
50
100
150
200
FREQUENCY (kHz)
250
300
1279 F02
Figure 2b. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 300kHz Input Frequency
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
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√V22 + V32 + V42 ... + VN2
V1
Figure 5 shows the IMD performance at a 100kHz input.
0
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input frequency is shown in Figure 4. The LTC1279 has good
distortion performance up to the Nyquist frequency and
beyond.
(fa) (fb)
–10
–20
–40
–50
–60
(2fa – fb)
–80 (fb – fa)
–70
(3fb)
(fa + 2fb)
(2fb – fa) (fa + fb)(2fa + fb)
(2fa)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
–90
0
–10
(2fb)
(3fa)
–100
fSAMPLE = 600kHz
–110
–120
–20
–30
0
50
100
150
200
FREQUENCY (kHz)
250
–40
300
1279 G08
Figure 5. Intermodulation Distortion Plot
–50
–60
–70
–80
Peak Harmonic or Spurious Noise
2ND HARMONIC
THD
3RD HARMONIC
–90
–100
10k
100k
INPUT FREQUENCY (Hz)
1M
2M
1279 G06
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of
the 2nd order IMD products can be expressed by the
following formula:
IMD (fa ± fb) = 20log
10
fSAMPLE = 600kHz
fa = 94.189kHz
fb = 97.705kHz
–30
AMPLITUDE (dB)
THD = 20log
Amplitude at (fa ± fb)
Amplitude at fa
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1279 has been designed to optimize input bandwidth,
allowing ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise
floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond
Nyquist.
Driving the Analog Input
The LTC1279’s analog input is easy to drive. It draws only
one small current spike while charging the sample-andhold capacitor at the end of conversion. During conversion
the analog input draws no current. The only requirement
is that the amplifier driving the analog input must settle
after the small current spike before the next conversion
starts. Any op amp that settles in 160ns to small current
transients will allow maximum speed operation. If slower
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Internal Reference
The LTC1279 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at pin 2 to provide up to 800µA current to an
external load.
For minimum code transition noise, the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
The VREF pin can be driven with a DAC or other means to
provide input span adjustment in bipolar mode. The VREF
pin must be driven to at least 2.45V to prevent conflict with
the internal reference. The reference should be driven to
no more than 4.8V to keep the input span within the ±5V
supplies.
Figure 6 shows an LT1006 op amp driving the VREF pin. (In
the unipolar mode, the input span is already 0V to 5V with
the internal reference so driving the reference is not
recommended, since the input span will exceed the supply
and codes will be lost at the full scale.) Figure 7 shows a
typical reference, the LT1019A-2.5 connected to the
LTC1279. This will provide an improved drift (equal to the
LT1019A-2.5’s maximum of 5ppm/°C) and a ±2.582V full
scale.
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
Figure 8a shows the ideal input/output characteristics for
the LTC1279. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, ... FS – 1.5LSB). The output code is naturally
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
8b shows the input/output transfer characteristics for the
bipolar mode in two’s complement format.
1LSB = FS = 5V
4096 4096
111...111
111...110
111...101
OUTPUT CODE
op amps are used, more settling time can be provided by
increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the
LT ®1360, LT1220, LT1223 and LT1224 op amps.
111...100
UNIPOLAR
ZERO
000...011
INPUT RANGE
±1.033 × VREF(OUT)
000...010
5V
000...001
000...000
+
VREF(OUT) ≥ 2.45V
LT1006
0V
AIN
VREF LTC1279
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
1279 F08a
–
3Ω
AGND
Figure 8a. LTC1279 Unipolar Transfer Characteristics
10µF
–5V
1279 F06
Figure 6. Driving the VREF with the LT1006 Op Amp
011...111
BIPOLAR
ZERO
INPUT RANGE
±2.58V
(= ±1.033 × VREF)
OUTPUT CODE
011...110
5V
5V
AIN
VIN
GND
000...000
111...111
111...110
VREF LTC1279
VOUT
LT1019A-2.5
000...001
3Ω
AGND
100...001
–5V
1279 F07
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1279 with the LT1019A-2.5
FS = 5V
1LSB = FS/4096
100...000
10µF
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
1279 F08b
Figure 8b. LTC1279 Bipolar Transfer Characteristics
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Unipolar Offset and Full-Scale Error Adjustments
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. For zero offset
error apply 0.61mV (i.e., 0.5LSB) at the input and adjust
the offset trim until the LTC1279 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error apply an analog input of 4.99817V (i.e.,
FS – 1.5LSB or last code transition) at the input and adjust
R5 until the LTC1279 output code flickers between 1111
1111 1110 and 1111 1111 1111.
+
R2
10k
AIN
–
R4
100k
LTC1279
R5
4.3k
FULL-SCALE
ADJUST
5V
R3
R8
100k R7
100k
20k
R6
200Ω
OFFSET
ADJUST
–5V
1279 F09c
Figure 9c. LTC1279 Bipolar Offset and Full-Scale Adjust Circuit
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset of the op amp
driving the analog input of the LTC1279 while the input
voltage is 0.5LSB below ground. This is done by applying
an input voltage of – 0.61mV (– 0.5LSB) to the input in
Figure 9c and adjusting the R8 until the ADC output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full scale adjustment, an input voltage of 2.49817V
(FS – 1.5LSBs) is applied to the input and R5 is adjusted
until the output code flickers between 0111 1111 1110
and 0111 1111 1111.
+
V1
AIN
A1
–
LTC1279
R4
100Ω
R2
10k
R3
10k
AGND
FULL-SCALE
ADJUST
1279 F09a
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
Figure 9a. Full-Scale Adjust Circuit
R1
10k
10k
BOARD LAYOUT AND BYPASSING
+
R2
10k
5V
R9
20Ω
AIN
–
R4
100k
LTC1279
R5
4.3k
FULL-SCALE
ADJUST
R3
100k R7
100k
R6
400Ω
5V
R8
10k
OFFSET
ADJUST
1279 F09b
Figure 9b. LTC1279 Unipolar Offset and Full-Scale Adjust Circuit
12
R1
10k
Bipolar Offset and Full-Scale Error Adjustments
R1
50Ω
ANALOG
INPUT
0V TO 5V
ANALOG
INPUT
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1279, a printed circuit board is
required. The printed circuit board’s layout should ensure
that digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to run
any digital trace alongside an analog signal trace or
underneath the ADC. The analog input should be screened
by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the AVDD and VREF pins as shown in
Figure 10. For the bipolar mode, a 0.1µF ceramic provides
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1
+
–
DIGITAL
SYSTEM
LTC1279
AIN
AGND
ANALOG
INPUT
CIRCUITRY
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APPLICATI
3
10µF
VREF
AVDD
DVDD
DGND
2
24
17
12
0.1µF
10µF
0.1µF
GROUND CONNECTION
TO DIGITAL CIRCUITRY
1279 F10
ANALOG GROUND PLANE
Figure 10. Power Supply Grounding Practice
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Input signal traces to AIN (pin 1) and signal return traces
from AGND (pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between the signal source
and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC
appears as an error voltage in series with the input signal,
attention should be paid to reducing the ground circuit
impedances as much as possible.
A single point analog ground, separate from the logic
system ground, should be established with an analog
ground plane at pin 3 (AGND) or as close as possible to the
ADC. Pin 12 (DGND) and all other analog grounds should
be connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to isolate the ADC data bus.
DIGITAL INTERFACE
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.4µs. No external adjustments are required, and
with the typical acquisition time of 160ns, throughput
performance of 600ksps is assured.
Power Shutdown
The LTC1279 provides a power shutdown feature that
saves power when the ADC is in inactive periods. To power
down the ADC, pin 18 (SHDN) needs to be driven low.
When in power shutdown mode, the LTC1279 will not start
a conversion even though the CONVST goes low. All the
power is off except the Internal Reference which is still
active and provides 2.42V output voltage to the other
circuitry. In this mode the ADC draws 8.5mW instead of
60mW (for minimum power, the logic inputs must be
within 600mV of the supply rails). The wake-up time from
the power shutdown to active state is 350ns.
13
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Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic “0” for CONVST will start a conversion after the ADC
has been selected (i.e., CS is low). Once initiated, it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.
Figures 12 through 16 show several different modes of
operation. In modes 1a and 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.
In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVST and RD are tied together. The MPU
starts conversion and reads the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).
In Slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode, the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the previous conversion result. After the conversion is complete,
the processor can read the new result (which will initiate
another conversion).
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
RD
BUSY
CS
D
Q
CONVERSION
START (RISING
EDGE TRIGGER)
FLIP
FLOP
CONVST
SHDN
CLEAR
1279 F11
Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN
tCONV
CS = RD = 0
t4
SAMPLE N + 1
SAMPLE N
CONVST
t5
BUSY
t6
DATA
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST =
14
1279 F12
)
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t11
CS = RD = 0
tCONV
SAMPLE N
SAMPLE N + 1
t5
t5
CONVST
BUSY
t6
DATA (N – 1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
1279 F13
Figure 13. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled.(CONVST =
)
t11
CS = 0
tCONV
t4
SAMPLE N + 1
SAMPLE N
CONVST
t5
BUSY
t7
t9
t10
RD
t8
DATA N
DB11 TO DB0
DATA
DATA (N + 1)
DB11 TO DB0
1279 F14
Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD
tCONV
CS = 0
SAMPLE N
SAMPLE N + 1
RD = CONVST
t5
t9
BUSY
t8
t6
DATA (N – 1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11-DB0
1279 F15
Figure 15. Slow Memory Mode
tCONV
CS = 0
SAMPLE N
SAMPLE N + 1
RD = CONVST
t5
t9
BUSY
t8
DATA
DATA N
DB11 TO DB0
DATA (N – 1)
DB11 TO DB0
1279 F16
Figure 16. ROM Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1279
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
24-Lead Plastic SOL
24
23
22
21
0.598 – 0.614
(15.190 – 15.600)
(NOTE 2)
20 19 18 17 16
15
14
13
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
1
0.005
(0.127)
RAD MIN
0.291 – 0.299
(7.391 – 7.595)
(NOTE 2)
0.010 – 0.029 × 45°
(0.254 – 0.737)
2
3
4
5
6
7
8
9
10
11
12
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
RELATED PARTS
SOL24 0392
(12 Bit)
PART NUMBER
DESCRIPTION
COMMENTS
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Single 5V, Sampling 7572 Upgrade
LTC1273/ LTC1275/ LTC1276
12-Bit, 300ksps Sampling A/D Converters with Reference
Complete with Clock, Reference
LTC1274/ LTC1277
12-Bit, 10mW, 100ksps A/D Converters with 1µA Shutdown
Complete with Clock, Reference
LTC1278
12-Bit, 500ksps Sampling A/D Converter with Shutdown
70dB SINAD at Nyquist, Low Power
LTC1282
3V, 140ksps 12-Bit Sampling A/D Converter with Reference
3V or ±3V ADC with Reference, Clock
LTC1409
12-Bit, 800ksps Sampling A/D Converter with Shutdown
Fast, Complete Low Power ADC
LTC1410
12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
Fast, Complete, Wideband ADC
16
Linear Technology Corporation
LT/GP 0495 10K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1995
工商网监
湘ICP备2023018690号
