LTC1326/LTC1326-2.5
Micropower Precision
Triple Supply Monitors
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FEATURES
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■
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■
■
■
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DESCRIPTIO
Simultaneously Monitors Three Supplies
LTC1326: 5V, 3.3V and ADJ
LTC1326-2.5: 2.5V, 3.3V and ADJ
Guaranteed Threshold Accuracy: ±0.75%
Low Supply Current: 20µA
Internal Reset Time Delay: 200ms
Manual Push-Button Reset Input
Active Low and Active High Reset Outputs
Active Low “Soft” Reset Output
Power Supply Glitch Immunity
Guaranteed RESET for VCC3 ≥ 1V or VCC5 ≥ 1V
or VCC25 ≥ 1V
8-Pin SO and MSOP Packages
■
■
The RST output is guaranteed to be in the correct state for
VCC3, VCC5 or VCC25 down to 1V. The LTC1326/LTC1326-2.5
can be configured to monitor one, two or three inputs,
depending on system requirements.
Desktop Computers
Notebook Computers
Intelligent Instruments
Portable Battery-Powered Equipment
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 4843302.
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■
Tight 0.75% threshold accuracy and glitch immunity
ensure reliable reset operation without false triggering.
The 20µA typical supply current makes the LTC1326/
LTC1326-2.5 ideal for power-conscious systems.
A manual push-button reset input provides the ability to
generate a very narrow “soft” reset pulse (100µs typ) or a
200ms reset pulse equivalent to a power-on reset. Both
SRST and RST outputs are open-drain and can be OR-tied
with other reset sources.
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APPLICATIO S
■
The LTC®1326/LTC1326-2.5 are triple supply monitors
intended for systems with multiple supply voltages. They
provide micropower operation, small size and high accuracy supply monitoring.
TYPICAL APPLICATIO
RST Output Voltage vs Supply Voltage (LTC1326-2.5)
3.5
SYSTEM
LOGIC
0.1µF
VCC25 VCC3 VCCA
LTC1326-2.5
VCC25 = VCCA = VCC3
4.7k PULL-UP FROM RST TO VCC3
TA = 25°C
3.0
RST OUTPUT VOLTAGE (V)
2.5V
3.3V
VCORE
DC/DC
CONVERTER
2.5
2.0
1.5
1.0
0.5
RST
PBR
PUSH-BUTTON
RESET
GND
0
SRST
0
0.5
1.0
1.5 2.0
VCC3 (V)
2.5
3.0
3.5
1326/2.5 TA02
1326/2.5 TA01
132625fc
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LTC1326/LTC1326-2.5
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AXI U
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ABSOLUTE
RATI GS
(Notes 1, 2)
Terminal Voltage
VCC3, VCC5, VCC25, VCCA ......................... – 0.5V to 7V
RST, SRST ............................................ – 0.5V to 7V
RST ...................................... – 0.5V to (VCC3 + 0.3V)
PBR .......................................................... – 7V to 7V
Operating Temperature Range
LTC1326C/LTC1326C-2.5 ....................... 0°C to 70°C
LTC1326I/LTC1326I-2.5 ..................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
VCC3
VCC5
VCCA
GND
1
2
3
4
8
7
6
5
PBR
SRST
RST
RST
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 250°C/W
ORDER PART NUMBER
VCC3 1
8 PBR
VCC5 2
7 SRST
VCCA 3
6 RST
GND 4
5 RST
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 150°C/W
MS8 PART NUMBER
ORDER PART NUMBER
S8 PART NUMBER
LTBA
LTUH
LTC1326CS8
LTC1326IS8
1326
1326I
LTC1326CMS8
LTC1326IMS8
TOP VIEW
TOP VIEW
VCC3
VCC25
VCCA
GND
1
2
3
4
8
7
6
5
PBR
SRST
RST
RST
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 250°C/W
VCC3 1
8 PBR
VCC25 2
7 SRST
VCCA 3
6 RST
GND 4
5 RST
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 150°C/W
ORDER PART NUMBER
MS8 PART NUMBER
ORDER PART NUMBER
S8 PART NUMBER
LTC1326CMS8-2.5
LTC1326IMS8-2.5
LTEK
LTUJ
LTC1326CS8-2.5
LTC1326IS8-2.5
132625
326I25
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult factory for parts specified with wider operating temperature ranges.
132625fc
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LTC1326/LTC1326-2.5
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5),
VCCA = VCC3, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VRT3
Reset Threshold VCC3
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
3.094
3.052
3.118
3.118
3.135
3.143
V
V
VRT5
Reset Threshold VCC5 (LTC1326)
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
4.687
4.625
4.725
4.725
4.750
4.762
V
V
VRT25
Reset Threshold VCC25 (LTC1326-2.5)
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
2.344
2.312
2.363
2.363
2.375
2.381
V
V
VRTA
Reset Threshold VCCA
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
0.992
0.980
1.000
1.000
1.007
1.007
V
V
VCC
VCC3 Operating Voltage
RST in Correct Logic State
●
1
7
V
IVCC3
VCC3 Supply Current
PBR = VCC3
●
20
40
µA
IVCC5
VCC5 Input Current (LTC1326)
VCC5 = 5V
●
4
10
µA
IVCC25
VCC25 Input Current (LTC1326-2.5)
VCC25 = 2.5V
●
2.8
7
µA
IVCCA
VCCA Input Current
VCCA = 1V
●
–15
0
15
nA
tRST
Reset Pulse Width
RST Low with 10kΩ Pull-Up to VCC3
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
140
140
200
200
280
300
ms
ms
●
50
100
200
µs
tSRST
Soft Reset Pulse Width
SRST Low with 10kΩ Pull-Up to VCC3
tUV
VCC Undervoltage Detect to RST
VCC25, VCC3 or VCCA Less Than Reset
Threshold VRT by More Than 1%
IPBR
PBR Pull-Up Current
PBR = 0V
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
µs
13
●
●
3
3
7
7
10
15
µA
µA
0.8
V
VIL
PBR, RST Input Low Voltage
●
VIH
PBR, RST Input High Voltage
●
2
V
tPW
PBR Min Pulse Width
●
40
ns
tDB
PBR Debounce
Deassertion of PBR Input to SRST
Output (PBR Pulse Width = 1µs)
tPB
PBR Assertion Time for Transition
from Soft to Hard Reset Mode
PBR Held Less Than VIL
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
ISINK = 5mA
VOL
RST Output Voltage Low
●
1.4
1.4
20
35
ms
2.0
2.0
2.8
3.0
s
s
●
0.15
0.4
V
ISINK = 100µA,
0°C ≤ TA ≤ 70°C
VCC3 = 1V, VCC5 = 0V
VCC3 = 0V, VCC5 = 1V
VCC3 = 1V, VCC5 = 1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
ISINK = 100µA,
–40°C ≤ TA ≤ 85°C
VCC3 = 1.1V, VCC5 = 0V
VCC3 = 0V, VCC5 = 1.1V
VCC3 = 1.1V, VCC5 = 1.1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
ISINK = 100µA,
0°C ≤ TA ≤ 70°C
VCC3 = 1V, VCC25 = 0V
VCC3 = 0V, VCC25 = 1V
VCC3 = 1V, VCC25 = 1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
ISINK = 100µA,
–40°C ≤ TA ≤ 85°C
VCC3 = 1.1V, VCC25 = 0V
VCC3 = 0V, VCC25 = 1.1V
VCC3 = 1.1V, VCC25 = 1.1V
●
●
●
0.05
0.05
0.05
0.4
0.4
0.4
V
V
V
SRST Output Voltage Low
ISINK = 2.5mA
●
0.15
0.4
V
RST Output Voltage Low
ISINK = 2.5mA
●
0.15
0.4
V
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LTC1326/LTC1326-2.5
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTC1326 Only VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25°C unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOH
RST Output Voltage High (Note 3)
ISOURCE = 1µA
●
VCC3 – 1
V
SRST Output Voltage High (Note 3)
ISOURCE = 1µA
●
VCC3 – 1
V
RST Output Voltage High
ISOURCE = 600µA
●
VCC3 – 1
V
tPHL
Prop Delay RST to RST
High Input to Low Output
CRST = 20pF
25
ns
tPLH
Prop Delay RST to RST
Low Input to High Output
CRST = 20pF
45
ns
VOVR
VCC5 Reset Override Voltage
Override VCC5 Ability to Assert RST (Note 4)
VCC3 ±0.025
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
MIN
TYP
MAX
UNITS
Note 3: The output pins SRST and RST have weak internal pull-ups to
VCC3 of 6µA typ. However, external pull-up resistors may be used when
faster rise times are required.
Note 4: The VCC5 reset override voltage is valid for an operating range less
than approximately 4.15V. Above this point the override is turned off and
the VCC5 pin functions normally.
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TYPICAL PERFOR A CE CHARACTERISTICS
IVCC5 vs Temperature
(LTC1326)
IVCC25 vs Temperature
(LTC1326-2.5)
5.0
3.00
24
4.8
2.95
23
4.6
2.90
22
4.4
2.85
21
4.2
20
19
IVCC25 (µA)
25
IVCC5 (µA)
IVCC3 (µA)
IVCC3 vs Temperature
4.0
3.8
2.80
2.75
2.70
18
3.6
2.65
17
3.4
2.60
16
3.2
2.55
15
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
3.0
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
80
100
1326/2.5 G01
80
100
1326/2.5 G02
2.50
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
80
100
1326/2.5 G03
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LTC1326/LTC1326-2.5
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC5 Transient Immunity
(LTC1326)
VCCA Input Current vs Input Voltage
50
TRANSIENT DURATION (µs)
2
INPUT CURRENT (nA)
45
RESET OCCURS
ABOVE CURVE
TA = 25°C
45
1
0
–1
–2
–3
0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2
INPUT VOLTAGE (V)
40
35
30
25
20
15
10
25
20
15
10
0
0.001
0.01
0.1
1
VCC5 RESET COMPARATOR OVERDRIVE (V)
0
0.01
0.1
1
0.001
VCC25 RESET COMPARATOR OVERDRIVE (V)
1326/2.5 G05
1326/2.5 G06
VCC5 Threshold Voltage
vs Temperature (LTC1326)
VCC3 Transient Immunity
40
4.750
40
RESET OCCURS
ABOVE CURVE
TA = 25°C
RESET OCCURS
ABOVE CURVE
TA = 25°C
35
TRANSIENT DURATION (µs)
TRANSIENT DURATION (µs)
30
5
VCCA Transient Immunity
30
25
20
15
10
30
25
20
15
10
5
5
0
0.01
0.1
1
0.001
VCCA RESET COMPARATOR OVERDRIVE (V)
0
0.01
0.1
1
0.001
VCC3 RESET COMPARATOR OVERDRIVE (V)
1326/2.5 G07
4.735
4.730
4.725
4.720
4.715
4.710
4.705
4.700
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
2.365
2.360
2.355
100
1.005
3.130
3.125
3.120
3.115
3.110
3.105
3.100
– 60 – 40 – 20
0
20
40
60
80
100
TEMPERATURE (°C)
1326/2.5 G10
100
VCCA Threshold Voltage
vs Temperature
VCCA THRESHOLD VOLTAGE, VRTA (V)
VCC3 THRESHOLD VOLTAGE, VRT3 (V)
2.370
80
1326/2.5 G09
3.135
80
4.740
VCC3 Threshold Voltage
vs Temperature
2.375
2.350
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
4.745
1326/2.5 G08
VCC25 Threshold Voltage
vs Temperature (LTC1326-2.5)
VCC25 THRESHOLD VOLTAGE, VRT25 (V)
35
RESET OCCURS
ABOVE CURVE
TA = 25°C
5
1326/2.5 G04
35
40
TRANSIENT DURATION (µs)
TA = 25°C
VCC5 THRESHOLD VOLTAGE, VRT5 (V)
3
VCC25 Transient Immunity
(LTC1326-2.5)
1326/2.5 G11
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
80
100
1326/2.5 G12
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LTC1326/LTC1326-2.5
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TYPICAL PERFOR A CE CHARACTERISTICS
Reset Pulse Width
vs Temperature
SOFT RESET PULSE WIDTH, tSRST (µs)
220
215
210
205
200
195
190
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
80
100
PBR ASSERTION TIME TO RESET, tPB (SEC)
112.5
225
RESET PULSE WIDTH, tRST (ms)
PBR Assertion Time to Reset
vs Temperature
“Soft” Reset Pulse Width
vs Temperature
110.0
107.5
105.0
102.5
100.0
97.5
95.0
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
1326/2.5 G13
80
100
1326/2.5 G14
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
– 60 – 40 – 20 0 20 40 60
TEMPERATURE (°C)
80
100
1326/2.5 G15
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PIN FUNCTIONS
VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor.
VCC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate
drive for the RST output FET when the voltage on VCC3 is
less than the voltage on VCC5. If unused, it can be tied to
VCC3 (see Dual and Single Supply Monitor Operation in
the Applications Information section).
VCC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
gate drive for RST output FET when the voltage on VCC3
is less than the voltage on VCC25. If unused, it can be tied
to VCC3.
VCCA (Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused, it can
be tied to either VCC3 or VCC25.
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to VCC3, buffered complement of RST.
An external pull-down on the RST pin will drive this pin
high.
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to VCC3. Can be pulled up
greater than VCC3 when interfacing to 5V logic. Asserted
for 100µs after PBR is held low for less than 2 seconds
and released.
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to VCC3. Can be pulled up greater than
VCC3 when interfacing to 5V logic. When asserted for less
than 2 seconds, outputs a soft reset 100µs pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
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LTC1326/LTC1326-2.5
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BLOCK DIAGRA S
LTC1326
VCC3
VCC3
6µA
7µA
7
SRST
6
RST
5
RST
SOFT RESET
PBR
TIMER
PBR 8
–
RESET
4.15V
TO POWER
DETECT
+
–
VCC5 2
+
25mV
–
VCC3
–
25mV
VCC3
INTERNAL
+
+
VCC3 1
VCC3
VCC3
6µA
–
200ms
RESET
GENERATOR
+
POWER
DETECT/
GATE DRIVE
–
VCCA 3
VCC5
+
GND 4
VCC3
REF
1326 BD
LTC1326-2.5
VCC3
VCC3
6µA
7µA
PBR
TIMER
PBR 8
SRST
6
RST
5
RST
RESET
TO POWER
DETECT
VCC25 2
7
SOFT RESET
VCC3
VCC3
6µA
–
VCC3
INTERNAL
200ms
RESET
GENERATOR
+
POWER
DETECT/
GATE DRIVE
VCC3 1
VCC25
–
VCC3
+
–
VCCA 3
+
GND 4
REF
1326-2.5 BD
132625fc
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LTC1326/LTC1326-2.5
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TI I G DIAGRA S
VCC Monitor Timing
VCCX
Push-Button Reset Function Timing
PBR
VRTX
t < tPB
tRST
tPB
tRST
tDB
RST
RST
tSRST
1326/2.5 TD01
SRST
1326/2.5 TD02
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APPLICATIO S I FOR ATIO
Operation
The LTC1326/LTC1326-2.5 are micropower, high accuracy triple supply monitoring circuits. The parts have two
basic functions: generation of a reset when power supplies are out of range, and generation of reset or a “soft”
reset when the PBR pin is pulled low.
The three internal precision voltage comparators have
response times that are typically 13µs. This slow response time helps prevent mistriggering due to transients on each of the VCC inputs. The part’s ability to
suppress transients can be improved by bypassing each
of the VCC inputs with a 0.1µF capacitor to ground.
Supply Monitoring
Push-Button Reset
All three VCC inputs must be above predetermined
thresholds for 200ms before the reset output is released.
The parts will assert reset during power-up, power-down
and brownout conditions on any one or more of the VCC
inputs.
The parts provide a push-button reset input pin. The PBR
input has an internal pull-up current source to VCC3. If the
PBR pin is not used it can be left floating.
On power-up, either the VCC5 or VCC3 pin on the LTC1326,
or the VCC25 or VCC3 pin on the LTC1326-2.5, can power
the drive circuits for the RST pin. This ensures that RST
will be low when VCC5, VCC25 or VCC3 reaches 1V. As long
as any one of the VCC inputs is below its predetermined
threshold, RST will stay a logic low. Once all of the VCC
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. The RST pin
outputs the inverted state of what is seen on RST pin.
RST is reasserted whenever any one of the VCC inputs
drops below its predetermined threshold and remains
asserted until 200ms after all of the VCC inputs are above
their thresholds.
On power-down, once any of the VCC inputs drop below
its threshold, RST is held at a logic low. A logic low of 0.4V
is guaranteed until VCC3 and VCC5 on the LTC1326 or VCC3
and VCC25 on the LTC1326-2.5 drop below 1V.
When the PBR is pulled low for less than tPB (≈ 2 sec), a
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The pushbutton circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undisturbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than tPB (≈ 2 sec),
a standard reset is generated on the RST and RST pins.
Once the 2 second period has elapsed, a reset signal is
produced by the push-button logic, thereby clearing the
reset counter. Once the button is released, the reset
counter begins counting the reset period (200ms nominal). Consequently, the reset outputs remain asserted for
approximately 200ms after the button is released.
132625fc
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LTC1326/LTC1326-2.5
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APPLICATIO S I FOR ATIO
During a supply induced reset condition, the ability of the
PBR pin to force a soft reset condition on the SRST pin
is disabled. In other words SRST will remain high. If the
PBR pin is held low, both during and after a supply
induced reset (low RST), the RST pin will remain low until
200ms after the PBR goes high.
Power Detect/Gate Drive
The LTC1326/LTC1326-2.5 for the most part are powered
internally from the VCC3 pin. The exception is at the gate
drive of the output FET on the RST pin. On the input to this
FET is power detection circuitry used to detect and drive
the gate from either the 3.3V input pin (VCC3) or the 5V
input pin (VCC5) on the LTC1326 or the 2.5V input pin
(VCC25) on the LTC1326-2.5. The gate drive is derived
from the pin with the highest potential. This ensures the
part pulls the RST pin low as soon as either input pin is
≥ 1V.
appropriate range. The LTC1326 handles this situation as
shown in Figure 2. Above 1V and below VRT3, RST is held
low. From VRT3 to approximately 4.15V, the LTC1326
assumes 3.3V supply monitoring and RST is deasserted.
Above approximately 4.15V, the LTC1326 operates as a 5V
monitor. In most systems, the 5V supply will pass through
the 3.1V to 4.15V region in
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