LTC1403CMSE#PBF

LTC1403/LTC1403A Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown Features Description 2.8Msps Conversion Rate nn Low Power Dissipation: 14mW nn 3V Single Supply Operation nn –40°C to 125°C Guaranteed Operation nn 2.5V Internal Bandgap Reference can be Overdriven nn 3-Wire Serial Interface nn Sleep (10µW) Shutdown Mode nn Nap (3mW) Shutdown Mode nn 80dB Common Mode Rejection nn 0V to 2.5V Unipolar Input Range nn Tiny 10-Lead MS Package The LTC®1403/LTC1403A are 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MS package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low power and tiny package makes the LTC1403/LTC1403A suitable for high speed, portable applications. nn The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. Applications The devices convert 0V to 2.5V unipolar inputs differentially. The absolute voltage swing for +AIN and –AIN extends from ground to the supply voltage. Automotive Communications nn Data Acquisition Systems nn Uninterrupted Power Supplies nn Multiphase Motor Control nn Multiplexed Data Acquisition The serial interface sends out the conversion results during the 16 clock cycles following CONV↑ for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. nn nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LinearView and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Block Diagram AIN+ 1 + 14-BIT ADC S&H AIN– 2 –44 VDD – –50 THREESTATE SERIAL OUTPUT PORT SDO 8 14 3 VREF 2.5V REFERENCE 10F 4 GND 5 6 10 CONV 9 SCK TIMING LOGIC 11 EXPOSED PAD 1403A TA01 THD, 2nd, SFDR, 3rd (dB) 7 LTC1403A 2nd, 3rd and SFDR vs Input Frequency 3V 14-BIT LATCH 10µF –56 –62 THD 2nd, SFDR –68 –74 –80 3rd –86 –92 –98 –104 0.1 1 10 FREQUENCY (MHz) 100 1403A TA02 1403fc For more information www.linear.com/LTC1403 1 LTC1403/LTC1403A Absolute Maximum Ratings Pin Configuration (Note 1, 2,) TOP VIEW Supply Voltage (VDD)...................................................4V Analog Input Voltage (Note 3).................................... –0.3V to (VDD + 0.3V) Digital Input Voltage..................... –0.3V to (VDD + 0.3V) Digital Output Voltage................... –0.3V to (VDD + 0.3V) Power Dissipation................................................100mW Operation Temperature Range LTC1403C/LTC1403AC.............................. 0°C to 70°C LTC1403I/LTC1403AI............................–40°C to 85°C LTC1403H/LTC1403AH....................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C Order Information AIN+ AIN– VREF GND GND 1 2 3 4 5 11 GND 10 9 8 7 6 CONV SCK SDO VDD GND MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, qJA = 40°C/W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC1403#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1403CMSE#PBF LTC1403CMSE#TRPBF LTBDN 10-Lead Plastic MSOP 0°C to 70°C LTC1403IMSE#PBF LTC1403IMSE#TRPBF LTBDP 10-Lead Plastic MSOP –40°C to 85°C LTC1403HMSE#PBF LTC1403HMSE#TRPBF LTBDP 10-Lead Plastic MSOP –40°C to 125°C LTC1403ACMSE#PBF LTC1403ACMSE#TRPBF LTADF 10-Lead Plastic MSOP 0°C to 70°C LTC1403AIMSE#PBF LTC1403AIMSE#TRPBF LTAFD 10-Lead Plastic MSOP –40°C to 85°C LTC1403AHMSE#PBF LTC1403AHMSE#TRPBF LTAFD 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 1403fc For more information www.linear.com/LTC1403 LTC1403/LTC1403A Converter Characteristics l denotes the specifications which apply over the full operating The temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3V LTC1403 PARAMETER CONDITIONS MIN LTC1403H TYP MAX MIN LTC1403A TYP MAX MIN l 12 (Notes 4, 5, 18) l –2 ±0.25 2 –2 ±0.25 2 –4 Offset Error (Notes 4, 18) l –10 ±1 10 –20 ±2 20 Gain Error (Note 4, 18) l –30 ±5 30 –40 ±5 40 Gain Tempco Internal Reference (Note 4) External Reference Resolution (No Missing Codes) Integral Linearity Error 12 LTC1403AH TYP MAX MIN 14 ±15 ±1 TYP MAX UNITS 14 ±0.5 4 –4 –20 ±2 20 –60 ±10 60 ±15 ±1 Bits ±0.5 4 LSB –30 ±2 30 LSB –80 ±10 80 LSB ±15 ±1 ±15 ±1 ppm/°C ppm/°C Analog Input l denotes the specifications which apply over the full operating temperature range, otherwise The specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS VIN Analog Differential Input Range (Notes 3, 9) 2.7V ≤ VDD ≤ 3.3V VCM Analog Common Mode + Differential Input Range (Note 10) IIN Analog Input Leakage Current CIN Analog Input Capacitance tACQ Sample-and-Hold Acquisition Time MIN TYP MAX UNITS 0 to 2.5 V 0 to VDD V l 1 l µA 13 (Note 6) tAP Sample-and-Hold Aperture Delay Time tJITTER Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio pF 39 l fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V ns 1 ns 0.3 ps –60 –15 dB dB Dynamic Accuracy l denotes the specifications which apply over the full operating temperature range, The otherwise specifications are at TA = 25°C. VDD = 3V LTC1403/LTC1403H SYMBOL PARAMETER CONDITIONS SINAD Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 1.4MHz Input Signal 1.4MHz Input Signal (H Grade) 100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V 750kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V THD l l MIN TYP 68 67 70.5 70.5 70.5 72 MAX 72 LTC1403A/LTC1403AH MIN TYP 70 69 73.5 73.5 73.0 76.3 MAX UNITS dB dB dB dB 76.3 dB Total Harmonic Distortion 100kHz First 5 Harmonics 1.4MHz First 5 Harmonics SFDR Spurious Free Dynamic Range 100kHz Input Signal 1.4MHz Input Signal –87 –83 –90 –86 dB dB IMD Intermodulation Distortion 1.25V to 2.5V 1.25MHz into AIN+, 0V to 1.25V, 1.2MHz into AIN– –82 –82 dB Code-to-Code Transition Noise VREF = 2.5V (Note 18) 0.25 1 LSBRMS Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) 50 50 MHz Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz l –87 –83 –76 –90 –86 –78 dB dB 1403fc For more information www.linear.com/LTC1403 3 LTC1403/LTC1403A Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 MIN VREF Output Tempco TYP MAX UNITS 2.5 V 15 ppm//°C VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 µV/V VREF Output Resistance Load Current = 0.5mA 0.2 Ω 2 ms VREF Settling Time Digital Inputs and Digital Outputs l denotes the specifications which apply over the full The operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.3V l VIL Low Level Input Voltage VDD = 2.7V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 3V, IOUT = –200µA VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA VDD = 2.7V, IOUT = 1.6mA l VOUT = 0V to VDD l IOZ Hi-Z Output Leakage DOUT COZ Hi-Z Output Capacitance DOUT ISOURCE Output Short-Circuit Source Current ISINK Output Short-Circuit Sink Current MIN l TYP MAX 2.4 2.5 UNITS V 5 pF 2.9 V 0.05 0.10 0.4 V V ±10 µA 1 pF VOUT = 0V, VDD = 3V 20 mA VOUT = VDD = 3V 15 mA Power Requirements l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. (Note 17) SYMBOL VDD PARAMETER Supply Voltage CONDITIONS IDD Positive Supply Voltage PD Power Dissipation Active Mode Active Mode (LTC1403H, LTC1403AH) Nap Mode Nap Mode (LTC1403H, LTC1403AH) Sleep Mode (LTC1403, LTC1403H) Sleep Mode (LTC1403A, LTC1403AH) Active Mode with SCK in Fixed State (Hi or Lo) 4 MIN 2.7 l l l l TYP MAX 3.6 4.7 5.2 1.1 1.2 2 2 12 7 8 1.5 1.8 15 10 UNITS V mA mA mA mA µA µA mW 1403fc For more information www.linear.com/LTC1403 LTC1403/LTC1403A Timing Characteristics l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency per Channel (Conversion Rate) CONDITIONS l MIN 2.8 TYP MAX UNITS MHz 357 ns 10000 ns tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) tSCK Clock Period (Notes 16) tCONV Conversion Time (Note 6) 17 t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) t9 SCK to Hi-Z at SDO (Notes 6, 12) t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-scale specifications are measured for a singleended AIN+ input with AIN– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN–. Note 9: The absolute voltage at AIN+ and AIN– must be within this range. l l 19.8 18 2 SCLK cycles 8 ns 6 ns ns 2 ms Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read without an arbitrarily long clock. Note 17: VDD = 3V, fSAMPLE = 2.8Msps. Note 18: The LTC1403A is measured and specified with 14-bit Resolution (1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit Resolution (1LSB = 610µV). 1403fc For more information www.linear.com/LTC1403 5 LTC1403/LTC1403A Typical Performance Characteristics THD, 2nd and 3rd vs Input Frequency 11.5 71 11.0 68 10.5 65 10.0 62 9.5 59 9.0 56 8.5 53 8.0 0.1 104 –50 98 THD –56 –74 3rd –80 62 –92 56 –98 50 1 10 FREQUENCY (MHz) 0 SNR (dB) 65 62 59 56 53 1 10 FREQUENCY (MHz) –30 –40 –40 –50 –60 –70 –80 –60 –70 –80 –90 –100 –100 –110 –110 700k 1.05M FREQUENCY (Hz) –120 1.4M –50 –60 –70 –80 –90 –100 1.0 4 0.8 3 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 1.4M 1403A G07 700k 1.05M FREQUENCY (Hz) –1.0 1.4M 2 1 0 –1 –2 –3 –0.8 –110 350k Integral Linearity vs Output Code INTEGRAL LINEARITY (LSB) DIFFERENTIAL LINEARITY (LSB) –40 0 1403A G06 Differential Linearity vs Output Code –30 MAGNITUDE (dB) –50 –90 350k 2.8Msps 1403A G05 2.8Msps 700k 1.05M FREQUENCY (Hz) 0 –10 –20 0 100 1.3MHz Sine Wave 4096 Point FFT Plot –30 –120 100 –20 1 10 FREQUENCY (MHz) 1403A G03 2.8Msps 1403A G04 350k 44 0.1 –20 1.4MHz Input Summed with 1.56MHz Input IMD 4096 Point FFT Plot 6 100 MAGNITUDE (dB) MAGNITUDE (dB) 68 0 68 –86 –10 71 –120 74 98kHz Sine Wave 4096 Point FFT Plot 74 0 80 1403A G02 SNR vs Input Frequency –10 86 –68 1403A G01 50 0.1 92 2nd –62 –104 0.1 50 100 1 10 FREQUENCY (MHz) SFDR vs Input Frequency –44 SFDR (dB) 74 THD, 2nd, 3rd (dB) 12.0 SINAD (dB) ENOBs (BITS) ENOBs and SINAD vs Input Frequency TA = 25°C, VDD = 3V (LTC1403A) 0 4096 8192 12288 OUTPUT CODE 16383 1403A G08 –4 0 4096 8192 12288 OUTPUT CODE 16383 1403A G09 1403fc For more information www.linear.com/LTC1403 LTC1403/LTC1403A Typical Performance Characteristics Differential and Integral Linearity vs Conversion Rate 5 4 79 MAX INL 2 EXTERNAL VREF = 3.3V fIN~fS/3 78 77 MAX DNL 1 S/(N+D) LINEARITY (LSB) SINAD vs Conversion Rate 80 18 CLOCKS PER CONVERSION 3 0 –1 MIN DNL –2 –3 EXTERNAL VREF = 3.3V fIN~fS/40 76 75 74 73 72 INTERNAL V REF = 2.5V fIN~fS/40 71 INTERNAL VREF = 2.5V fIN~fS/3 70 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 CONVERSION RATE (Msps) MIN INL –4 –5 TA = 25°C, VDD = 3V (LTC1403A) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 CONVERSION RATE (Msps) 1403A G10 1403A G11 TA = 25°C, VDD = 3V (LTC1403 and LTC1403A) 12 2.5VP-P Power Bandwidth CMRR vs Frequency PSRR vs Frequency –25 0 6 –30 –20 –35 –40 –12 –18 PSRR (dB) –40 –6 CMRR (dB) AMPLITUDE (dB) 0 –60 –55 –80 –24 –60 –100 –30 –36 1M 10M 100M FREQUENCY (Hz) –65 –120 100 1G –45 –50 1k 10k 100k 1M FREQUENCY (Hz) 1403A G12 10M –70 100M 1 10 100 1k 10k FREQUENCY (Hz) VDD Supply Current vs Conversion Rate Reference Voltage vs VDD 2.4902 2.4902 2.4900 2.4900 2.4898 2.4898 1M 1403A G14 1403A G13 Reference Voltage vs Load Current 100k 6.0 2.4896 VDD SUPPLY CURRENT (mA) VREF (V) VREF (V) 5.5 2.4896 2.4894 2.4894 2.4892 2.4892 2.4890 2.4890 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 1403A G15 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 1403A G16 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 CONVERSION RATE (Msps) 1403A G17 1403fc For more information www.linear.com/LTC1403 7 LTC1403/LTC1403A Pin Functions AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN– with a 0V to 2.5V differential swing and a 0V to VDD common mode swing. solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. AIN– (Pin 2): Inverting Analog Input. AIN– operates fully differentially with respect to AIN+ with a –2.5V to 0V differential swing and a 0V to VDD common mode swing. SDO (Pin 8): Three-State Serial Data Output. Each of output data words represents the difference between AIN+ and AIN– analog inputs at the start of the previous conversion. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference between 2.55V and VDD. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (≤3V) and 3V CMOS levels. One or more pulses wake from sleep. GND (Pins 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK in fixed high or fixed low state start Nap mode. Four or more pulses with SCK in fixed high or fixed low state start Sleep mode. VDD (Pin 7): 3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a Block Diagram 7 LTC1403A AIN+ 1 + AIN– 2 – 3V VDD 14-BIT ADC S&H THREESTATE SERIAL OUTPUT PORT 14-BIT LATCH 10µF 8 SDO 10 CONV 9 SCK 14 3 VREF 2.5V REFERENCE 10µF 4 GND 5 8 6 TIMING LOGIC 11 EXPOSED PAD 1403A BD 1403fc For more information www.linear.com/LTC1403 LTC1403/LTC1403A Timing Diagram LTC1403 Timing Diagram t2 t3 16 17 t7 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD t8 t8 t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z SDO SAMPLE D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X HOLD t9 Hi-Z X 1403A TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. LTC1403A Timing Diagram t2 t3 16 17 1 t7 t1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD t8 SDO Hi-Z SAMPLE t8 t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 HOLD t9 D0 Hi-Z 1403A TD01b 14-BIT DATA WORD tCONV tTHROUGHPUT Nap Mode and Sleep Mode Waveforms SLK t1 t1 CONV NAP SLEEP t12 VREF 1403A TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK t8 t10 SDO VIH t9 VOH VOL 90% SDO 10% 1403A TD03 1403fc For more information www.linear.com/LTC1403 9 LTC1403/LTC1403A Applications Information Driving the Analog Input The differential analog inputs of the LTC1403/LTC1403A are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the AIN– input is grounded). Both differential analog inputs, AIN+ with AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1403/LTC1403A inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance ( 1403A Sine wave collection with Serial Port interface bvectors.asm buffered mode to avoid standard mode bug. s2k14ini.asm 2k buffer size. first element at 1024, last element at 1023, two middles at 2047 and 0000 unipolar mode negative edge BCLKR negative BFSR pulse -0 data shifted 1’ cable from counter to CONV at DUT 2’ cable from counter to CLK at DUT *************************************************************************** .width 160 .length 110 .title “sineb0 BSP in auto buffer mode” .mmregs .setsect “.text”, 0x500,0 ;Set address of executable .setsect “vectors”, 0x180,0 ;Set address of incoming 1403 data .setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing .setsect “result”, 0x1800,0 ;Set address of result for clearing .text ;.text marks start of code start: tim=#0fh prd=#0fh tcr = #10h tspc = #0h pmst = #01a0h sp = #0700h dp = #0 ar2 = #1800h ar3 = #0800h ar4 = #0h call sineinit sinepeek: call sineinit wait ; goto wait ;this label seems necessary ;Make sure /PWRDWN is low at J1-9 ;to turn off AC01 adc ; ; ; ; ; ; ; ; stop timer stop TDM serial port to AC01 set up iptr. Processor Mode STatus register init stack pointer. data page pointer to computed receive buffer. pointer to Buffered Serial Port receive buffer reset record counter ; Double clutch the initialization to insure a proper ; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. ----------------Buffered Receive Interrupt Routine ------------------ breceive: ifr = #10h ; clear interrupt flags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return _ enable ; --------------mask and shift input data ---------------------------bufull: b = *ar3+ 1)|((Format & 2)