LTC1403-1/LTC1403A-1
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
FEATURES
n
n
n
n
n
n
n
n
n
n
DESCRIPTION
2.8Msps Conversion Rate
Low Power Dissipation: 14mW
3V Single Supply Operation
2.5V Internal Bandgap Reference Can Be Overdriven
3-Wire Serial Interface
Sleep (10µW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection
±1.25V Bipolar Input Range
Tiny 10-Lead MSE Package
The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps
serial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MSE package. A Sleep shutdown feature lowers power
consumption to 10µW. The combination of speed, low
power and tiny package makes the LTC1403-1/LTC1403A‑1
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs
differentially. The absolute voltage swing for AIN+ and
AIN– extends from ground to the supply voltage.
APPLICATIONS
Communications
Data Acquisition Systems
n Uninterrupted Power Supplies
n Multiphase Motor Control
n Multiplexed Data Acquisition
n
The serial interface sends out the conversion results during
the 16 clock cycles following CONV↑ for compatibility with
standard serial interfaces. If two additional clock cycles
for acquisition time are allowed after the data stream in
between conversions, the full sampling rate of 2.8Msps
can be achieved with a 50.4MHz clock.
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
BLOCK DIAGRAM
AIN+
1
+
14-BIT ADC
S&H
AIN–
2
–44
VDD
–
–50
THREESTATE
SERIAL
OUTPUT
PORT
–56
SDO
8
14
3
VREF
10
2.5V
REFERENCE
10µF
4
GND
5
11
EXPOSED PAD
–62
–68
–74
–80
THD
–86
SCK
14031 TA01a
3rd
2nd
–92
9
6
CONV
TIMING
LOGIC
THD, 2nd, 3rd (dB)
7
LTC1403A-1
THD, 2nd and 3rd vs Input
Frequency for Differential Input
Signals
3V
14-BIT LATCH
10µF
–98
–104
0.1
1
10
FREQUENCY (MHz)
100
14031 TA01b
14031fd
For more information www.linear.com/LTC1403-1
1
LTC1403-1/LTC1403A-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VDD) ..................................................4V
Analog Input Voltage
(Note 3) ....................................–0.3V to (VDD + 0.3V)
Digital Input Voltage .................. – 0.3V to (VDD + 0.3V)
Digital Output Voltage ...................– 0.3V to (VDD + 0.3V)
Power Dissipation................................................100mW
Operation Temperature Range
LTC1403C-1/LTC1403AC-1........................ 0°C to 70°C
LTC1403I-1/LTC1403AI-1......................– 40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
ORDER INFORMATION
TOP VIEW
AIN+
AIN–
VREF
GND
GND
1
2
3
4
5
11
10
9
8
7
6
CONV
SCK
SDO
VDD
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 40°C/ W
EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC1403-1#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1403CMSE-1#PBF
LTC1403CMSE-1#TRPBF
LTBGP
10-Lead Plastic MSOP
0°C to 70°C
LTC1403IMSE-1#PBF
LTC1403IMSE-1#TRPBF
LTBGQ
10-Lead Plastic MSOP
–40°C to 85°C
LTC1403ACMSE-1#PBF
LTC1403ACMSE-1#TRPBF
LTBGR
10-Lead Plastic MSOP
0°C to 70°C
LTC1403AIMSE-1#PBF
LTC1403AIMSE-1#TRPBF
LTBGS
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
The
l denotes the specifications which apply over the full operating
CONVERTER
CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3V
LTC1403-1
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
l
TYP
LTC1403A-1
MAX
12
MIN
TYP
MAX
UNITS
14
Bits
Integral Linearity Error
(Notes 4, 5, 18)
l
–2
±0.25
2
–4
±0.5
4
LSB
Offset Error
(Notes 4, 18)
l
–10
±1
10
–20
±2
20
LSB
Gain Error
(Note 4, 18)
l
–30
±5
30
–60
±10
60
LSB
Gain Tempco
Internal Reference (Note 4)
External Reference
±15
±1
±15
±1
ppm/°C
ppm/°C
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. VDD = 3V
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 8, 9)
VCM
Analog Common Mode + Differential
Input Range (Note 10)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
2.7V ≤ VDD ≤ 3.3V
MIN
l
TYP
MAX
UNITS
–1.25 to 1.25
V
0 to VDD
V
1
l
13
µA
pF
14031fd
2
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. VDD = 3V
SYMBOL PARAMETER
CONDITIONS
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
(Note 6)
TYP
MAX
UNITS
39
l
fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V
ns
1
ns
0.3
ps
–60
–15
dB
dB
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. VDD = 3V. Single-ended AIN+ signal drive with AIN– = 1.5V DC. Differential signal drive with
VCM = 1.5V at AIN+ and AIN–
LTC1403-1
Symbol
PARAMETER
CONDITIONS
SINAD
Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
100kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
750kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
THD
l
MIN
TYP
68
70.5
70.5
72
LTC1403A-1
MAX
MIN
TYP
70
73.5
73.5
76.3
dB
dB
dB
76.3
dB
72
–87
–83
–90
–86
MAX
UNITS
dB
dB
Total Harmonic
Distortion
100kHz First 5 Harmonics (Note 19)
1.4MHz First 5 Harmonics (Note 19)
SFDR
Spurious Free
Dynamic Range
100kHz Input Signal (Note 19)
1.4MHz Input Signal (Note 19)
–87
–83
–90
–86
dB
dB
IMD
Intermodulation
Distortion
0.625VP-P 1.4MHz Summed with 0.625VP-P
1.56MHz into AIN+ and Inverted into AIN–
–82
–82
dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 18)
0.25
1
LSBRMS
Full Power Bandwidth
VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15)
50
50
MHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB
5
5
MHz
l
–76
–78
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
MIN
TYP
MAX
UNITS
2.5
V
15
ppm/°C
VREF Line Regulation
VDD = 2.7V to 3.6V, VREF = 2.5V
600
µV/V
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
2
ms
VREF Settling Time
14031fd
For more information www.linear.com/LTC1403-1
3
LTC1403-1/LTC1403A-1
DIGITAL
INPUTS AND DIGITAL OUTPUTS
The
l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.3V
l
VIL
Low Level Input Voltage
VDD = 2.7V
l
0.6
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
µA
CIN
Digital Input Capacitance
(Note 20)
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200µA
l
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT = 160µA
VDD = 2.7V, IOUT = 1.6mA
l
VOUT = 0V to VDD
l
IOZ
Hi-Z Output Leakage DOUT
COZ
Hi-Z Output Capacitance DOUT
ISOURCE
Output Short-Circuit Source Current
ISINK
Output Short-Circuit Sink Current
MIN
TYP
MAX
UNITS
2.4
2.5
V
5
pF
2.9
V
0.05
0.10
0.4
V
V
±10
µA
1
pF
VOUT = 0V, VDD = 3V
20
mA
VOUT = VDD = 3V
15
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 17)
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Supply Voltage
IDD
Positive Supply Voltage
Active Mode
Nap Mode
Sleep Mode (LTC1403-1)
Sleep Mode (LTC1403A-1)
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
TYP
MAX
2.7
4.7
1.1
2
2
l
l
UNITS
3.6
V
7
1.5
15
10
mA
mA
µA
µA
12
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel
(Conversion Rate)
MIN
l
tTHROUGHPUT
Minimum Sampling Period (Conversion + Acquisition Period)
tSCK
Clock Period
(Note 16)
TYP
2.8
UNITS
MHz
l
l
MAX
19.8
357
ns
10000
ns
tCONV
Conversion Time
(Note 6)
17
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
18
ns
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
ns
t3
Nearest SCK Edge Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t7
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Data
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
SCLK cycles
ns
2
ms
14031fd
4
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and full-scale specifications are measured for a singleended AIN+ input with AIN– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between AIN+ and AIN–. Performance is specified with AIN– = 1.5V DC while
driving AIN+.
Note 9: The absolute voltage at AIN+ and AIN– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17: VDD = 3V, fSAMPLE = 2.8Msps.
Note 18: The LTC1403A-1 is measured and specified with 14-bit
Resolution (1LSB = 152µV) and the LTC1403-1 is measured and specified
with 12-bit Resolution (1LSB = 610µV).
Note 19: Full-scale sinewaves are fed into the noninverting input while the
inverting input is kept at 1.5V DC.
Note 20: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
14031fd
For more information www.linear.com/LTC1403-1
5
LTC1403-1/LTC1403A-1
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 3V. Single ended AIN+ signal drive
T
–
with AIN = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1)
THD, 2nd and 3rd vs Input
Frequency
SFDR vs Input Frequency
–44
104
11.5
71
–50
98
11.0
68
–56
92
–62
86
10.5
65
10.0
62
9.5
59
9.0
56
8.5
53
1
10
FREQUENCY (MHz)
THD
–74
3rd
–80
2nd
–86
56
50
1
10
FREQUENCY (MHz)
71
11.5
71
11.0
68
65
10.5
65
10.0
62
ENOBs (BITS)
68
9.5
59
56
9.0
56
53
8.5
53
100
8.0
0.1
–50
–56
–68
–74
–86
–98
98
92
MAGNITUDE (dB)
74
68
62
56
50
100
14031 G20
1
10
FREQUENCY (MHz)
100
14031 G19
1.3MHz Sine Wave 4096 Point
FFT Plot
0
–10
–10
–20
–20
–30
–40
–30
0
MAGNITUDE (dB)
104
80
3rd
2nd
–104
0.1
98kHz Sine Wave 4096 Point
FFT Plot
86
THD
–80
–92
50
100
1
10
FREQUENCY (MHz)
–62
14031 G18
SFDR vs Input Frequency for
Differential Input Signals
1
10
FREQUENCY (MHz)
–44
SINAD (dB)
SNR (dB)
74
14031 G04
SFDR (dB)
THD, 2nd and 3rd vs Input
Frequency for Differential Input
Signals
12.0
59
100
14031 G03
ENOBs and SINAD vs Input
Frequency for Differential Input
Signals
62
1
10
FREQUENCY (MHz)
14031 G02
SNR vs Input Frequency
44
0.1
44
0.1
100
74
1
10
FREQUENCY (MHz)
68
–98
14031 G01
50
0.1
74
–92
–104
0.1
50
100
80
62
THD, 2nd, 3rd (dB)
8.0
0.1
–68
SFDR (dB)
74
THD, 2nd, 3rd (dB)
12.0
SINAD (dB)
ENOBs (BITS)
ENOBs and SINAD
vs Input Frequency
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
350
700k
1.05M
FREQUENCY (Hz)
1.4M
14031 G05
0
350k
700k
1.05M
FREQUENCY (Hz)
1.4M
14031 G06
14031fd
6
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 3V. Single ended AIN+ signal drive
T
–
with AIN = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1)
1.4MHz Input Summed with
1.56MHz Input IMD 4096 Point FFT
Plot for Differential Input Signals
1.3MHz Sine Wave 4096 Point
FFT Plot for Differential Input
Signals
0
0
–10
–10
0
–10
–20
–20
–30
–30
–40
–30
–40
–40
–50
–60
–70
–80
MAGNITUDE (dB)
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
10.7MHz Sine Wave 4096 Point
FFT Plot for Differential Input
Signals
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0
200k 400k 600k 800k 1M
FREQUENCY (Hz)
1.2M 1.4M
0
350
700k
1.05M
FREQUENCY (Hz)
1.4M
14031 G07
0.4
0.2
0
–0.2
–0.4
–0.6
4
4
3
3
2
1
0
–1
–2
12288
8192
OUTPUT CODE
–4
16384
0
4096
12288
8192
OUTPUT CODE
16384
14031 G08
7
0
–1
–2
–4
0
4096
12288
8192
OUTPUT CODE
16384
14071 G23
SINAD vs Conversion Rate
78
18 CLOCKS PER CONVERSION
77
6
76
5
4
75
S/(N+D) (dB)
MAX INL
3
2
MAX DNL
1
0
74
73
72
71
MIN DNL
–1
EXTERNAL VREF = 3.3V fIN ~ fS/3
EXTERNAL VREF = 3.3V fIN ~ fS/40
INTERNAL VREF = 2.5V fIN ~ fS/3
INTERNAL VREF = 2.5V fIN ~ fS/40
70
–2
MIN INL
–3
–4
1
14071 G09
Differential and Integral Linearity
vs Conversion Rate
8
2
–3
–3
–0.8
1.4M
Integral Linearity vs Output Code
for Differential Input Signals
INTEGRAL LINEARITY (LSB)
INTEGRAL LINEARITY (LSB)
0.6
LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
0.8
4096
700k
1.05M
FREQUENCY (Hz)
14031 G22
Integral Linearity
vs Output Code
1.0
0
350
14031 G21
Differential Linearity
vs Output Code
–1.0
0
2
69
2.25 2.5 2.75 3 3.25 3.5 3.75
CONVERSION RATE (Msps)
4
68
2
2.25 2.5 2.75 3 3.25 3.5 3.75
CONVERSION RATE (Msps)
14031 G10
4
14031 G11
14031fd
For more information www.linear.com/LTC1403-1
7
LTC1403-1/LTC1403A-1
T
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 3V (LTC1403-1 and LTC1403A-1)
2.5VP-P Power Bandwidth
CMRR vs Frequency
12
PSRR vs Frequency
–25
0
6
–30
–20
–35
–40
–12
–18
PSRR (dB)
–40
–6
CMRR (dB)
AMPLITUDE (dB)
0
–60
–55
–80
–24
–60
–100
–30
–36
1M
10M
100M
FREQUENCY (Hz)
–65
–120
100
1G
–45
–50
1k
10M
10k
100k 1M
FREQUENCY (Hz)
14031 G12
–70
100M
1
10
100
1k
10k
FREQUENCY (Hz)
VDD Supply Current vs
Conversion Rate
Reference Voltage vs VDD
2.4902
2.4902
2.4900
2.4900
2.4898
2.4898
1M
14031 G14
14031 G13
Reference Voltage vs Load
Current
100k
6.0
VDD SUPPLY CURRENT (mA)
VREF (V)
VREF (V)
5.5
2.4896
2.4896
2.4894
2.4894
2.4892
2.4892
2.4890
2.4890
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
14031 G15
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
14031 G16
0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
CONVERSION RATE (Msps)
14031 G17
14031fd
8
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
PIN FUNCTIONS
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a –1.25V to
1.25V differential swing with respect to AIN– and a 0V to
VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates fully
differentially with respect to AIN+ with a 1.25V to –1.25V
differential swing with respect to AIN+ and a 0V to VDD
common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
Can be overdriven by an external reference between 2.55V
and VDD.
GND (Pins 4, 5, 6, Exposed Pad Pin 11): Ground. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND and to a
solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising
edge. Responds to TTL (≤3V) and 3V CMOS levels. One
or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input signal
and starts the conversion on the rising edge. Responds
to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
in fixed high or fixed low state start Nap mode. Four or
more pulses with SCK in fixed high or fixed low state start
Sleep mode.
14031fd
For more information www.linear.com/LTC1403-1
9
LTC1403-1/LTC1403A-1
BLOCK DIAGRAM
7
LTC1403A-1
AIN+
1
2
VDD
+
14-BIT ADC
S&H
AIN–
3V
–
THREESTATE
SERIAL
OUTPUT
PORT
14-BIT LATCH
10µF
8
SDO
10
CONV
9
SCK
14
3
VREF
2.5V
REFERENCE
10µF
4
GND
5
6
TIMING
LOGIC
11
EXPOSED PAD
14031 BD
14031fd
10
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
TIMING DIAGRAM
LTC1403-1 Timing Diagram
t2
t3
17
18
t7
t1
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18
1
SCK
t4
t5
CONV
t6
INTERNAL
S/H STATUS
tACQ
SAMPLE
HOLD
SAMPLE
t8
t8
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
Hi-Z
SDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X*
HOLD
t9
Hi-Z
X*
14031 TD01
14-BIT DATA WORD
tCONV
tTHROUGHPUT
*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
LTC1403A-1 Timing Diagram
t2
t3
17
18
t7
t1
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18
1
SCK
t4
t5
CONV
t6
INTERNAL
S/H STATUS
tACQ
SAMPLE
HOLD
SAMPLE
t8
t8
SDO
Hi-Z
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
HOLD
t9
D0
Hi-Z
14031 TD01b
14-BIT DATA WORD
tCONV
tTHROUGHPUT
Nap Mode and Sleep Mode Waveforms
SLK
t1
t1
CONV
NAP
SLEEP
t12
VREF
14031 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
t8
t10
SDO
VIH
t9
VOH
VOL
90%
SDO
For more information www.linear.com/LTC1403-1
10%
14031 TD03
14031fd
11
LTC1403-1/LTC1403A-1
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1403-1/LTC1403A‑1
are easy to drive. The inputs may be driven differentially or
as a single-ended input (i.e., the AIN– input is set to VCM).
Both differential analog inputs, AIN+ with AIN–, are sampled
at the same instant. Any unwanted signal that is common
to both inputs of each input pair will be reduced by the
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charging
the sample-and-hold capacitors at the end of conversion.
During conversion, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low, then the LTC1403-1/LTC1403A-1 inputs can
be driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifier must be used. The
main requirement is that the amplifier driving the analog
input(s) must settle after the small current spike before
the next conversion starts (settling time must be 39ns
for full throughput rate). Also keep in mind while choosing an input amplifier, the amount of noise and harmonic
distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements are
taken into consideration. First, to limit the magnitude of the
voltage spike seen by the amplifier from charging the sampling
capacitor, choose an amplifier that has a low output impedance ( 1403 bipolar Sine wave collection with Serial Port interface
bvectors.asm
buffered mode.
s2k14ini.asm
2k buffer size.
first element at 1024, last element at 1023, two middles at 2047 and 0000
bipolar mode
negative edge BCLKR
negative BFSR pulse
-0 data shifted
1’ cable from counter to CONV at DUT
2’ cable from counter to CLK at DUT
***************************************************************************
.width
160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”,
0x500,0
;Set address
.setsect “vectors”, 0x180,0
;Set address
.setsect “buffer”, 0x800,0
;Set address
.setsect “result”, 0x1800,0
;Set address
.text
;.text marks
start:
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
pmst = #01a0h
sp = #0700h
dp = #0
ar2 = #1800h
ar3 = #0800h
ar4 = #0h
call sineinit
sinepeek:
call sineinit
wait
;
goto
wait
of executable
of incoming 1403 data
of BSP buffer for clearing
of result for clearing
start of code
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
;
;
;
;
;
;
;
;
stop timer
stop TDM serial port to AC01
set up iptr. Processor Mode STatus register
init stack pointer.
data page
pointer to computed receive buffer.
pointer to Buffered Serial Port receive buffer
reset record counter
; Double clutch the initialization to insure a proper
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
————————Buffered Receive Interrupt Routine —————————
breceive:
ifr = #10h
; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull
; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
;
———————mask and shift input data ——————————————
bufull:
b = *ar3+ Vector Table for the ‘C54x DSKplus
10.Jul.96
BSP vectors and Debugger vectors
TDM vectors just return
***************************************************************************
The vectors in this table can be configured for processing external and
internal software interrupts. The DSKplus debugger uses four interrupt
vectors. These are RESET, TRAP2, INT2, and HPIINT.
* DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
All other vector locations are free to use. When programming always be sure
the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
reset
nmi
trap2
int0
int1
.title “Vector Table”
.mmregs
goto #80h
nop
nop
return_enable
nop
nop
nop
goto #88h
nop
nop
.space 52*16
return_enable
nop
nop
nop
return_enable
nop
;00; RESET
* DO NOT MODIFY IF USING DEBUGGER *
;04; non-maskable external interrupt
;08; trap2
* DO NOT MODIFY IF USING DEBUGGER *
;0C-3F: vectors for software interrupts 18-30
;40; external interrupt int0
;44; external interrupt int1
14031fd
For more information www.linear.com/LTC1403-1
19
LTC1403-1/LTC1403A-1
APPLICATIONS INFORMATION
int2
tint
brint
bxint
trint
txint
int3
hpiint
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
goto breceive
nop
nop
nop
goto bsend
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
return_enable
nop
nop
nop
dgoto #0e4h
nop
nop
.space 24*16
;48; external interrupt int2
;4C; internal timer interrupt
;50; BSP receive interrupt
;54; BSP transmit interrupt
;58; TDM receive interrupt
;5C; TDM transmit interrupt
;60; external interrupt int3
;64; HPIint
* DO NOT MODIFY IF USING DEBUGGER *
;68-7F; reserved area
**********************************************************************
*
(C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996
*
**********************************************************************
*
*
* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus *
*
for use with 1403 in buffered mode
*
*
BSPC and SPC are the same in the ‘C542
*
*
BSPCE and SPCE seem the same in the ‘C542
*
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON
.set 1
OFF
.set !ON
YES
.set 1
NO
.set !YES
BIT_8
.set 2
BIT_10
.set 1
BIT_12
.set 3
BIT_16
.set 0
GO
.set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
14031fd
20
For more information www.linear.com/LTC1403-1
LTC1403-1/LTC1403A-1
APPLICATIONS INFORMATION
*****************************************************************************************************
*LTC1403 timing from board with 10MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1403 board.
*
*Horizontal scale is 25ns/chr or 100ns period at BCLKR
*
*Timing measured at DSP pins. Jxx pin labels for jumper cable.
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~*
*BDR
Pin J1-26 _—_—_——_—> 1)|((Format & 2)
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