LTC1407-1/LTC1407A-1
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
3Msps Sampling ADC with Two Simultaneous
Differential Inputs
1.5Msps Throughput per Channel
Low Power Dissipation: 14mW (Typ)
3V Single Supply Operation
±1.25V Differential Input Range
Pin Compatible 0V to 2.5V Input Range Version
(LTC1407/LTC1407A)
2.5V Internal Bandgap Reference with External
Overdrive
3-Wire Serial Interface
Sleep (10μW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection at 100kHz
Tiny 10-Lead MS Package
The LTC®1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps
ADCs with two 1.5Msps simultaneously sampled differential inputs. The devices draw only 4.7mA from a single
3V supply and come in a tiny 10-lead MS package. A sleep
shutdown feature lowers power consumption to 10μW.
The combination of speed, low power and tiny package
makes the LTC1407-1/LTC1407A-1 suitable for high speed,
portable applications.
The LTC1407-1/LTC1407A-1 contain two separate differential inputs that are sampled simultaneously on the rising
edge of the CONV signal. These two sampled inputs are
then converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for CH0+, CH0–, CH1+
and CH1– extends from ground to the supply voltage.
APPLICATIONS
n
n
n
n
Telecommunications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
I & Q Demodulation
Industrial Radio
BLOCK DIAGRAM
The serial interface sends out the two conversion results in 32
clocks for compatibility with standard serial interfaces.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
10μF
3V
7
CH0+
1
+
CH0–
2
–
S&H
MUX
CH1+
4
+
S&H
CH1–
5
3
10μF
–
GND
11
VDD
LTC1407A-1
–44
–50
–56
THREESTATE
SERIAL
OUTPUT
PORT
SDO
8
10
CONV
9
SCK
TIMING
LOGIC
VREF
6
3Msps
14-BIT ADC
THD, 2nd and 3rd vs Input Frequency
for Differential Input Signals
14-BIT LATCH
n
14-BIT LATCH
n
THD, 2ND, 3RD (dB)
n
–62
–68
–74
THD
–80
–86
–92
–98
2.5V
REFERENCE
EXPOSED PAD
3RD
–104
0.1
2ND
1
FREQUENCY (MHz)
10
20
14071 TA01b
1407A1 BD
14071fb
1
LTC1407-1/LTC1407A-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (VDD) .................................................4V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................. –0.3V to (VDD + 0.3V)
Power Dissipation ...............................................100mW
Operation Temperature Range
LTC1407C-1/LTC1407AC-1 ...................... 0°C to 70°C
LTC1407I-1/LTC1407AI-1 .....................–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
CH0+
CH0–
VREF
CH1+
CH1–
1
2
3
4
5
10
9
8
7
6
11
CONV
SCK
SDO
VDD
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD IS GND (PIN 11), MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1407CMSE-1#PBF
LTC1407CMSE-1#TRPBF
LTBGT
10-Lead Plastic MSOP
0°C to 70°C
LTC1407IMSE-1#PBF
LTC1407IMSE-1#TRPBF
LTBGV
10-Lead Plastic MSOP
–40°C to 85°C
LTC1407ACMSE-1#PBF
LTC1407ACMSE-1#TRPBF
LTBGW
10-Lead Plastic MSOP
0°C to 70°C
LTC1407AIMSE-1#PBF
LTC1407AIMSE-1#TRPBF
LTBGX
10-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
PARAMETER
CONDITIONS
MIN
LTC1407-1
TYP MAX
MIN
LTC1407A-1
TYP MAX
l
12
Integral Linearity Error
(Notes 5, 17)
l
–2
±0.25
2
–4
±0.5
4
LSB
Offset Error
(Notes 4, 17)
l
–10
±1
10
–20
±2
20
LSB
–5
±0.5
5
–10
±1
10
LSB
l
–30
±5
30
–60
±10
60
LSB
±1
5
–10
±2
10
Resolution (No Missing Codes)
Offset Match from CH0 to CH1
(Note 17)
Gain Error
(Notes 4, 17)
Gain Match from CH0 to CH1
(Note 17)
Gain Tempco
Internal Reference (Note 4)
External Reference
–5
14
±15
±1
Bits
±15
±1
LSB
ppm/°C
ppm/°C
14071fb
2
LTC1407-1/LTC1407A-1
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 8, 9)
VCM
Analog Common Mode + Differential
Input Range (Note 10)
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
(Note 18)
tACQ
Sample-and-Hold Acquisition Time
(Note 6)
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
tSK
Sample-and-Hold Aperture Skew from CH0 to CH1
CMRR
Analog Input Common Mode Rejection Ratio
MIN
2.7V ≤ VDD ≤ 3.3V
TYP
MAX
UNITS
–1.25 to 1.25
V
0 to VDD
V
l
1
μA
13
pF
l
39
fIN = 1MHz, VIN = 0V to 3V
fIN = 100MHz, VIN = 0V to 3V
ns
1
ns
0.3
ps
200
ps
–60
–15
dB
dB
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V. Single-ended signal drive CH0+/CH1+ with
CHO–/CH1– = 1.5V DC. Differential signals drive both inputs of each channel with VCM = 1.5V DC.
SYMBOL PARAMETER
CONDITIONS
SINAD
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
100kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
750kHz Input Signal, External VREF = 3.3V,
VDD ≥ 3.3V (Note 19)
THD
Signal-to-Noise Plus
Distortion Ratio
MIN
l
68
LTC1407-1
TYP MAX
70.5
70.5
72.0
LTC1407A-1
MIN
TYP MAX
70
72.0
UNITS
73.5
73.5
76.3
dB
dB
dB
76.3
dB
Total Harmonic
Distortion
100kHz First 5 Harmonics (Note 19)
750kHz First 5 Harmonics (Note 19)
SFDR
Spurious Free
Dynamic Range
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
87
83
90
86
dB
dB
IMD
Intermodulation
Distortion
0.625VP-P 1.4MHz Summed with 0.625VP-P, 1.56MHz
into CH0+ and Inverted into CHO–. Also Applicable
to CH1+ and CH1–
–82
–82
dB
Code-to-Code
Transition Noise
VREF = 2.5V (Note 17)
0.25
1
LSBRMS
Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15)
50
50
MHz
Full Linear Bandwidth
5
5
MHz
S/(N + D) ≥ 68dB
l
–87
–83
–77
–90
–86
–80
dB
dB
14071fb
3
LTC1407-1/LTC1407A-1
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
TA = 25°C. VDD = 3V.
MIN
TYP
VREF Output Tempco
MAX
UNITS
2.5
V
15
ppm/°C
VREF Line Regulation
VDD = 2.7V to 3.6V, VREF = 2.5V
600
μV/V
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
2
ms
VREF Setting Time
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.3V
l
MIN
TYP
MAX
UNITS
VIL
Low Level Input Voltage
VDD = 2.7V
l
0.6
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
μA
CIN
Digital Input Capacitance
l
2.4
V
5
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200μA
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT = 160μA
VDD = 2.7V, IOUT = 1.6mA
l
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V to VDD
l
COZ
Hi-Z Output Capacitance DOUT
ISOURCE
Output Short-Circuit Source Current
ISINK
Output Short-Circuit Sink Current
2.5
pF
2.9
V
0.05
0.10
0.4
V
V
±10
μA
1
pF
VOUT = 0V, VDD = 3V
20
mA
VOUT = VDD = 3V
15
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
IDD
Supply Current
Active Mode, fSAMPLE = 1.5Msps
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
MIN
TYP
2.7
l
l
4.7
1.1
2.0
2.0
12
MAX
UNITS
3.6
V
7.0
1.5
15
10
mA
mA
μA
μA
mW
14071fb
4
LTC1407-1/LTC1407A-1
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
fSAMPLE(MAX)
Maximum Sampling Frequency per Channel
(Conversion Rate)
l
tTHROUGHPUT
Minimum Sampling Period (Conversion + Acquisition Period)
l
tSCK
Clock Period
(Note 16)
tCONV
Conversion Time
(Note 6)
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
t3
SCK Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t7
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+
or CH1+ input with CH0 – or CH1– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0+ and CH0– or CH1+ and CH1–. Performance is specified
with CHO– = 1.5V DC while driving CHO+ and with CH1– = 1.5V DC while
driving CH1+.
Note 9: The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
within this range.
CONDITIONS
MIN
l
TYP
MAX
1.5
MHz
19.6
32
UNITS
667
ns
10000
ns
34
SCLK cycles
ns
10000
2
ns
ms
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A-1 is measured and specified with 14-bit
Resolution (1LSB = 152μV) and the LTC1407-1 is measured and specified
with 12-bit Resolution (1LSB = 610μV).
Note 18: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19: Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.
14071fb
5
LTC1407-1/LTC1407A-1
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3V, TA = 25°C. Single-ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
74
11.5
71
11.0
68
10.5
65
10.0
62
9.5
59
9.0
56
8.5
53
1
10
FREQUENCY (MHz)
104
–50
98
–56
92
–62
86
–68
THD
–74
3RD
–80
2ND
56
50
1
10
FREQUENCY (MHz)
68
11.0
68
10.5
65
10.0
62
9.5
59
56
9.0
56
53
8.5
53
ENOBs (BITS)
71
100
8.0
0.1
50
100
1
10
FREQUENCY (MHz)
SNR (dB)
–50
–56
SINAD (dB)
11.5
59
–44
74
71
62
–62
–68
–74
SFDR vs Input Frequency for
Differential Input Signals
–86
98
92
MAGNITUDE (dB)
68
62
–104
0.1
–10
–20
–20
–30
–40
–30
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
50
–110
–110
44
0.1
–120
14071 G07
20
0
0
–10
–100
100
10
748kHz Sine Wave 4096 Point
FFT Plot
–100
1
10
FREQUENCY (MHz)
1
FREQUENCY (MHz)
14071 G06
–90
56
2ND
–98
MAGNITUDE (dB)
104
74
3RD
–92
98kHz Sine Wave 4096 Point
FFT Plot
80
THD
–80
14071 G05
14071 G04
86
100
THD, 2nd and 3rd
vs Input Frequency for
Differential Input Signals
12.0
65
1
10
FREQUENCY (MHz)
14071 G03
ENOBs and SINAD
vs Input Sinewave Frequency
for Differential Input Signals
SNR vs Input Frequency
SFDR (dB)
44
0.1
100
14071 G02
74
1
10
FREQUENCY (MHz)
68
–98
14071 G01
50
0.1
74
62
–86
–104
0.1
50
100
80
–92
THD, 2nd, 3rd (dB)
8.0
0.1
SFDR vs Input Frequency
–44
SFDR (dB)
12.0
THD, 2ND, 3RD (dB)
THD, 2nd and 3rd
vs Input Frequency
SINAD (dB)
ENOBs (BITS)
ENOBs and SINAD
vs Input Sinewave Frequency
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
14071 G08
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
14071 G09
14071fb
6
LTC1407-1/LTC1407A-1
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3V, TA = 25°C. Single-ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
1403kHz Input Summed with
1563kHz Input IMD 4096 Point FFT
Plot for Differential Input Signals
0
0
–10
–10
0
–10
–20
–20
–30
–30
–40
–30
–40
–40
–50
–60
–70
–80
MAGNITUDE (dB)
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
10.7MHz Sine Wave 4096 Point
FFT Plot for Differential Input
Signals
748kHz Sine Wave 4096 Point FFT
Plot for Differential Input Signals
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
0
185k
371k
556k
FREQUENCY (Hz)
3.2
0.6
2.4
2.4
–0.4
–0.6
INTEGRAL LINEARITY (LSB)
4.0
INTEGRAL LINEARITY (LSB)
DIFFERENTIAL LINEARITY (LSB)
4.0
–0.2
1.6
0.8
0
–0.8
–1.6
–2.4
0.8
0
–0.8
–1.6
–2.4
–3.2
–3.2
–1.0
–4.0
–4.0
4096
12288
8192
OUTPUT CODE
0
16384
4096
12288
8192
OUTPUT CODE
14071 G13
16384
0
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
3.2
3.2
0.6
2.4
2.4
0
–0.2
–0.4
–0.6
0.8
0
–0.8
–1.6
–2.4
–0.8
–3.2
–1.0
–4.0
0
4096
12288
8192
OUTPUT CODE
16384
14071 G16
INTEGRAL LINEARITY (LSB)
0.8
INTEGRAL LINEARITY (LSB)
4.0
1.6
16384
14071 G15
4.0
0.2
12288
8192
OUTPUT CODE
Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference
for Differential Input Signals
1.0
0.4
4096
14071 G14
Differential Linearity for CH1 with
Internal 2.5V Reference
DIFFERENTIAL LINEARITY (LSB)
1.6
–0.8
0
741k
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
3.2
0
371k
556k
FREQUENCY (Hz)
14071 G12
1.0
0.2
185k
Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference
for Differential Input Signals
0.8
0.4
0
14071 G11
14071 G10
Differential Linearity for CH0 with
Internal 2.5V Reference
741k
1.6
0.8
0
–0.8
–1.6
–2.4
–3.2
0
4096
12288
8192
OUTPUT CODE
16384
14071 G17
–4.0
0
4096
12288
8192
OUTPUT CODE
16384
14071 G18
14071fb
7
LTC1407-1/LTC1407A-1
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3V, TA = 25°C. Single ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1407A-1)
Differential and Integral Linearity
vs Conversion Rate
SINAD vs Conversion Rate
78
8
7
77
76
5
4
75
MAX INL
S/(N+D) (dB)
LINEARITY (LSB)
6
3
2
MAX DNL
1
0
–1
74
73
72
MIN DNL
71
MIN INL
70
–2
EXTERNAL VREF = 3.3V, fIN ~ fS/3
EXTERNAL VREF = 3.3V, fIN ~ fS/40
INTERNAL VREF = 2.5V, fIN ~ fS/3
INTERNAL VREF = 2.5V, fIN ~ fS/40
69
–3
68
–4
2
2.25 2.5 2.75 3 3.25 3.5 3.75
CONVERSION RATE (MSPS)
2
4
2.5
3
3.5
CONVERSION RATE (Msps)
14071 G20
14071 G19
VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1)
Full-Scale Signal Frequency
Response
CMRR vs Frequency
Crosstalk vs Frequency
0
12
6
–20
–30
–20
–40
–12
–18
CROSSTALK (dB)
–40
CMRR (dB)
AMPLITUDE (dB)
0
–6
–60
CH0
CH1
–80
–100
–36
1M
10M
100M
FREQUENCY (Hz)
1G
–120
100
1k
10k 100k
1M
FREQUENCY (Hz)
10M
CH1 TO CH0
CH0 TO CH1
100M
–90
100
1k
10k
100k
FREQUENCY (Hz)
14071 G22
14071 G21
1M
10M
14071 G23
PSSR vs Frequency
–25
16384
CH0 AND CH1
RISING
14336
–30
–35
12288
–40
10240
PSRR (dB)
OUTPUT CODE
–60
–80
Output Match with Simultaneous
Input Steps at CH0 and CH1
from 25Ω
CH0
CH1
8192
6144
–45
–50
–55
4096
–60
CH0 AND CH1
FALLING
2048
0
–50
–70
–24
–30
4
–65
–70
–5
0
5
15
10
TIME (ns)
20
25
14071 G24
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
14071 G25
14071fb
8
LTC1407-1/LTC1407A-1
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1)
Reference Voltage
vs Load Current
Reference Voltage vs VDD
2.4902
2.4900
2.4900
2.4898
2.4898
VREF (V)
VREF (V)
2.4902
2.4896
2.4896
2.4894
2.4894
2.4892
2.4892
2.4890
2.4890
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
14071 G26
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
14071 G27
PIN FUNCTIONS
CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates
fully differentially with respect to CH0–, with a –1.25V to
1.25V differential swing with respect to CH0– and a 0 to
VDD absolute input range.
CH0– (Pin 2): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+, with a 1.25V to –1.25V
differential swing with respect to CH0+ and a 0 to VDD
absolute input range.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Can be
overdriven by an external reference voltage ≥ 2.55V and
≤VDD.
CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates
fully differentially with respect to CH1–, with a –1.25V to
1.25V differential swing with respect to CH1– and a 0 to
VDD absolute input range.
CH1– (Pin 5): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+, with a 1.25V to –1.25V
differential swing with respect to CH1+ and a 0 to VDD
absolute input range.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these connections.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1μF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion. The output format
is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts sleep mode.
14071fb
9
LTC1407-1/LTC1407A-1
BLOCK DIAGRAM
3V
CH0+
1
+
S&H
CH0–
2
–
MUX
CH1+
4
+
S&H
CH1–
5
3
10μF
–
GND
11
LTC1407A-1
THREESTATE
SERIAL
OUTPUT
PORT
8
SDO
10
CONV
9
SCK
TIMING
LOGIC
VREF
6
3Msps
14-BIT ADC
VDD
14-BIT LATCH
7
14-BIT LATCH
10μF
2.5V
REFERENCE
EXPOSED PAD
1407A1 BD
14071fb
10
SDO
INTERNAL
S/H STATUS
CONV
SCK
SDO
INTERNAL
S/H STATUS
CONV
SCK
t6
t4
34
t6
t4
34
SAMPLE
33
SAMPLE
33
Hi-Z
t3
t8
2
3
D11
4
6
HOLD
7
1
Hi-Z
t3
2
t8
t2
3
D13
4
8
t1
9
10
11
12
13
14
15
D10
D9
D8
6
HOLD
7
8
t1
D6
D4
9
10
11
12-BIT DATA WORD
D5
D3
12
D2
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
X*
X*
17
19
t8
20
13
14
15
D3
D2
D1
t9
16
D0
17
19
22
HOLD
23
24
25
26
27
28
29
30
t8
20
D10
21
D9
22
D8
HOLD
23
D7
24
D6
D4
25
26
27
12-BIT DATA WORD
D5
D3
28
D2
29
D1
30
D0
D12
D11
D10
D9
D8
D6
14-BIT DATA WORD
D7
D5
D4
D3
D2
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D13
tTHROUGHPUT
tCONV
Hi-Z
18
21
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D11
tTHROUGHPUT
tCONV
Hi-Z
18
LTC1407A-1 Timing Diagram
D1
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
D7
t9
16
LTC1407-1 Timing Diagram
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
*BITS MARKED “X” AFTER D0 SHOULD BE IGNORED
1
t2
t5
31
t5
31
D1
X*
t8
32
t8
32
D0
X*
34
tACQ
34
Hi-Z
t9
SAMPLE
33
t7
Hi-Z
t9
SAMPLE
tACQ
t7
33
HOLD
HOLD
1407A1 TD01
1
14071 TD01
1
LTC1407-1/LTC1407A-1
TIMING DIAGRAMS
14071fb
11
LTC1407-1/LTC1407A-1
TIMING DIAGRAMS
Nap Mode Waveforms
SCK
t1
CONV
NAP
Sleep Mode Waveforms
SCK
t1
t1
CONV
NAP
SLEEP
t12
VREF
1407 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
VIH
t8
t10
SDO
t9
VOH
90%
SDO
10%
VOL
14071 TD03
14071fb
12
LTC1407-1/LTC1407A-1
APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1407-1/LTC1407A-1
are easy to drive. The inputs may be driven differentially or
as a single-ended input (i.e., the CH0– input is AC grounded
at VCC /2). All four analog inputs of both differential analog
input pairs, CH0+ with CH0– and CH1+ with CH1–, are
sampled at the same instant. Any unwanted signal that is
common to both inputs of each input pair will be reduced by
the common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charging
the sample-and-hold capacitors at the end of conversion.
During conversion, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low, then the LTC1407-1/LTC1407A-1 inputs can
be driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifier must be used. The
main requirement is that the amplifier driving the analog
input(s) must settle after the small current spike before
the next conversion starts (settling time must be 39ns for
full throughput rate). Also keep in mind, while choosing
an input amplifier, the amount of noise and harmonic
distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (
1407A Sine wave collection with Serial Port interface
bvectors.asm
both channels collected in sequence in the same 2k record.
s2k14ini.asm
Buffered mode 2k buffer size.
First element at 1024, last element at 1023, two middles at 2047 and 0000
bipolar mode
Works 16 or 64 clock frames.
negative edge BCLKR
negative BFSR pulse
-0 data shifted
***************************************************************************
.width
160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”,
0x500,0
;Set address
.setsect “vectors”, 0x180,0
;Set address
.setsect “buffer”, 0x800,0
;Set address
.setsect “result”, 0x1800,0
;Set address
.text
;.text marks
of executable
of incoming 1403 data
of BSP buffer for clearing
of result for clearing
start of code
start:
;this label seems necessary
;Make sure /PWRDWN is low at J1-9
;to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
pmst = #01a0h
sp = #0700h
dp = #0
ar2 = #1800h
ar3 = #0800h
ar4 = #0h
call sineinit
sinepeek:
call sineinit
wait
;
goto
;
;
;
;
;
;
;
;
stop timer
stop TDM serial port to AC01
set up iptr. Processor Mode STatus register
init stack pointer.
data page
pointer to computed receive buffer.
pointer to Buffered Serial Port receive buffer
reset record counter
; Double clutch the initialization to insure a proper
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait
———————— Buffered Receive Interrupt Routine —————————
breceive:
ifr = #10h
; clear interrupt flags
TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer
if (NTC) goto bufull
; if this still the first half get next half
bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))
return_enable
14071fb
19
LTC1407-1/LTC1407A-1
APPLICATIONS INFORMATION
;
——————— mask and shift input data ——————————————
bufull:
b = *ar3+ Vector Table for the ‘C54x DSKplus
10.Jul.96
BSP vectors and Debugger vectors
TDM vectors just return
***************************************************************************
The vectors in this table can be configured for processing external and
internal software interrupts. The DSKplus debugger uses four interrupt
vectors. These are RESET, TRAP2, INT2, and HPIINT.
* DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
All other vector locations are free to use. When programming always be sure
the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
14071fb
20
LTC1407-1/LTC1407A-1
APPLICATIONS INFORMATION
.title “Vector Table”
.mmregs
reset
nmi
trap2
int0
int1
int2
tint
brint
bxint
trint
txint
int3
hpiint
goto #80h
nop
nop
return_enable
nop
nop
nop
goto #88h
nop
nop
.space 52*16
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
nop
goto breceive
nop
nop
nop
goto bsend
nop
nop
nop
return_enable
nop
nop
nop
return_enable
nop
nop
return_enable
nop
nop
nop
dgoto #0e4h
nop
nop
;00; RESET
* DO NOT MODIFY IF USING DEBUGGER *
;04; non-maskable external interrupt
;08; trap2
* DO NOT MODIFY IF USING DEBUGGER *
;0C-3F: vectors for software interrupts 18-30
;40; external interrupt int0
;44; external interrupt int1
;48; external interrupt int2
;4C; internal timer interrupt
;50; BSP receive interrupt
;54; BSP transmit interrupt
;58; TDM receive interrupt
;5C; TDM transmit interrupt
;60; external interrupt int3
;64; HPIint
* DO NOT MODIFY IF USING DEBUGGER *
14071fb
21
LTC1407-1/LTC1407A-1
APPLICATIONS INFORMATION
.space 24*16
;68-7F; reserved area
**********************************************************************
*
(C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996
*
**********************************************************************
*
*
* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus *
*
for use with 1407 in buffered mode
*
*
BSPC and SPC are the same in the ‘C542
*
*
BSPCE and SPCE seem the same in the ‘C542
*
**********************************************************************
.title “Buffered Serial Port Initialization Routine”
ON
.set 1
OFF
.set !ON
YES
.set 1
NO
.set !YES
BIT_8
.set 2
BIT_10
.set 1
BIT_12
.set 3
BIT_16
.set 0
GO
.set 0x80
**********************************************************************
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
*******************************************************************************************
*LTC1407 timing from board with 10MHz crystal.
*
*10MHz, divided from 40MHz, forced to CLKIN by 1407 board.
*
*Horizontal scale is 25ns/chr or 100ns period at BCLKR
*
*Timing measured at DSP pins. Jxx pin labels for jumper cable.
*
*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/
~~~~~~~~~~~*
*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
~\_/~\_/~*
*BDR
Pin J1-26 _—_—_——_—> 1)|((Format & 2)
工商网监
湘ICP备2023018690号
